Guide for the VLSI chip design CAD tools at Penn State, CSE Department

K. Choi, 2014, kyusun@cse.psu.edu University Park

1. Introduction

The objective of this tutorial is to give you a quick overview to (1) setup the Cadence and Synopsys hspice tools for your account in IST
218 Lab, (2) use the schematic editor, (3) use the hspice tool, (3) use the chip layout editor - Cadence Virtuoso, and (4) use DRC,
Extract, LVS tools. This guide may be updated as needed during the semester, any user comments are welcome.

2. Set up the tool environment

Before you can start using design tools, there are a few configuration files needed in your working directory. These files determine the
environment in which tools run, and what libraries are to be included in your designs. The setup given below is for LINUX machines in
Lab 218. Some UNIX/LINUX commands will be included in this tutorial. Please be familiar with basic UNIX/LINUX commands to work
efficiently.

(Anyone outside of Penn State needing the setup files and scripts we use here, may request a copy of files to me by email:
kyusun@cse.psu.edu.edu I will supply the file copies for your reference for free with the basis of non-responsibility disclaimer.)

Step1.

Login to a machine in room 218 IST Building. Bring up a terminal window where you can type a UNIX command. Then type the
following:

% /home/faculty/kyusun/c411x/bin/class411setup

This setup needs to be done only once for this semester.

Now for the setup to take effect, you logout and login again.

Step 2.

Make your own class directory(folder) for CMPEN 411 class. I made:

% mkdir cmpen411

The “cmpen411” is the name of your class directory(folder). You can use any name you like. This directory will be containing all your
homework, project, exam, etc. design directories and files. „ls‟ or „ls –al‟ unix command will list your directory contents and you will
see the cmpen411 subdirectory.

Directory structure:
For the grading homework, projects, and exams, one must collect all files of each design project under one directory. Student will „tar‟
and „zip‟ the directory of their design project and turn-in for grading. Any missing files may cause the design project verification to fail.
So each design project must be stand-alone, self-contained, and independent of other projects. For example, the design project for
homework 2 may include homework 1 inverter design. In this case, the inverter design files must be physically copied into the
homework 2 directory; otherwise, the turned-in homework 2 project cannot be verified due to missing homework 1 inverter files.

Step3.

Change your current directory to cmpen411 by typing:

% cd cmpen411

Now you may create your design project directory. For a short tutorial presented in this guide, create hw0 directory. Again for the
purpose of the class homework, project, and exam, one needs to identify the project file with his/her name. Please add your last name
(up to 8 characters, all lower case) to your project directory name. That way, the zipped file will contain your last name and it will be
quickly indentified and separated from other student files. For example, I will add 'choi' to my directory name, so I will type :

% mkdir hw0choi

This directory (folder) and everything in it will be zipped and turned-in for the grading in subsequent homework projects.

You need to set up your directory for the CAD tool use once the directory has been created. So type:

% cd hw0choi

% runcds

This command needs to be done only once for each design project directory. (When you do homework 2 project later, you will need to
create hw2 directory, and you would need to 'cd' to that directory, and do 'runcds' once again for that directory.)

All of my design files will be in hw0choi directory from now on. When I stop working on the hw0 tutorial project today and want to return
to the project to continue tomorrow, I simply type:

% cd cmpen411/hw0choi

and resume. I will not type the 'runcds' again.

Now start the Cadence tool by typing the following:

% virtuoso &

Then the CIW (Command Interpreter Window) and the library manager should pop up.

Figure: CIW Window

Figure: CIW Window with proper starting, Library Manager pops up

Figure: Library manager

Figure: CIW Window with NOT proper starting, Library Manager does NOT pops up
If you see the Library Manager on your screen, your set up is proper. If you do NOT see the Library Manager and see the
„*WARNING*‟ message in CIW window, your set up is not proper, you can still use Cadence Virtuoso tool and do the work but you need
to see the lab-support staffs in room 111 IST Building to update your account. You need to also send email to:

helpdesk@cse.psu.edu

Step4. Optional – connecting to the Lab 218 IST machines from home

You can connect to the Lab 218 IST machines from home Windows PC and do the VLSI design work at home. You will need the
following programs:

VPN - http:// downloads.its.psu.edu

SSH - http:// downloads.its.psu.edu

Plus you will need one of the following X11 clients (program) running on your Windows PC:

Xming
Xmanager
Xwin32
Exceed from Hummingbird
cygwin ('XWin -multiwindow' command)

Once you have the above programs installed on your Windows PC, follow the steps below to connect to the Lab 218 IST machines:

1. Run VPN, set „ISP to CSE‟ (this step should be omitted if you are connecting from campus, or if you live on campus)

2. Run X11 client program (I run cygwin 'XWin Server')

3. Run ssh terminal, login to one of the following machines:

p218inst10 p218inst11 p218inst12 p218inst13 p218inst14

p218inst15 p218inst16 p218inst17 p218inst18 p218inst19
p218inst20 p218inst21 p218inst22 p218inst23 p218inst24
p218inst25 p218inst26 p218inst27 p218inst28 p218inst29
p218inst30 p218inst31 p218inst32 p218inst33
Double click on the ssh shell to start the ssh Terminal session.

Click on the „Settings‟ and be sure to check on the „Tunnel X11 connection‟ as shown below.
Once the ssh shell started, click on „Quick Connect‟ and type the followings, for example:

Host Name: p218inst10.cse.psu.edu

User Name: your_cse_user_id
Port Number: 22
Authentication Method: Password

Once you are logged-in, type „xclock &‟ to see if X11 is properly working. You will see a new clock on your screen. Otherwise X11 is
not working.

Once the X11 is working, you may resize you ssh Terminal and change fonts if you like. Then be sure to Save Settings and Save
Layout, these menu options are located under the File menu tap of the ssh shell window.

3. Working with Cadence tool - virtuoso

Using the Cadence tool, the overall VLSI chip design flow can be outlined as follows:

1. Schematic design and entry – transistors, symbols, input pins, output pins vdd component, and gnd component
2. Schematic check – check and save
3. Schematic spice netlist file creation
4. Hspice simulation of the netlist file from the schematic
5. Schematic symbol creation

6. Layout design and entry – pmos, nmos, ptap, NTAP, input pins, output pins, vdd! pin, and gnd! pin
7. Layout DRC (Design Rule Check)
8. Extraction of circuits from the layout including parasitic elements
9. Spice netlist file creation from the layout-extracted circuit
10. Hspice simulation of the spice netlist file from the layout-extracted circuit
11. LVS (Layout Versus Schematic) checking – consistency verification of the layout extracted circuit with the schematic

Following lists some tutorials, many others also exists:

http://webster.engr.pitt.edu/electrical/faculty-staff/levitan/1192/index.html

http://www.ee.virginia.edu/~mrs8n/cadence/tutorial1.html
http://www.ee.virginia.edu/~mrs8n/cadence/tutorial2.html

http://www.ee.siue.edu/~cdsadmin/tutorial.htm

You may also google to find what you want to know about the Cadence tool (or any error messages).

4. Schematic Design

We use latest Cadence tool, however the almost all of the older Cadence schematic and layout editing tool procedures are the same.
In this section, we will create our own library and generate a schematic of an inverter circuit.
Step1.

Create a library that will hold all you designs. My case, I named 'hw0choi' as my library. You must also use your last name as part of
your library name (in addition to the project folder name). For grading, everyone in class will submit their hw1 project library, grader
needs to distinguish your library for homework 1 over another student's.

In the Library Manager window,

a) Select File -> New -> Library
b) Enter the library name 'hw0yourlastname
c) Select the option 'Attach to an existing technology library'

Figure: Initial Library Manager

Figure: File menu of the Library Manager, to create a new Library

Figure: Enter a new library name

Figure: Select the new Library Technology option

d) Press OK. Then another window will pop up. Choose the library NCSU_Techlib_aim06 and press OK. Then, a library using the AIM
0.6um technology is created.

Figure: Select NCSU_Techlib_aim06 library option

Figure: a new library 'hw0choi' successfully created

Step2. Create a Schematic Cell View

Now create a new schematic view, an inverter. In the Library Manager window,
a) Select File -> New -> Cell View, schematic
b) Choose hw0choi (in my case) and enter the cell name inv in the pop-up window.

Figure: File menu of the Library Manager, to create a new Cell View
Figure: Select the new library and type the cell name

Then you may get another pop-up window for the Virtuoso Schematic Editor License selection. Select 'Always'.

Schematic editor will pop up next.

In the schematic editor, create instance of pmos4 and nmos4 from the AnalogLib library.
On the schematic editor, select Create -> Instance or use toolbar .
Choose library NCSU_Analog_Parts in the pop-up Component Browser window.
Choose pmos4 from the P_Transistors directory.
If the Component Browser does not appear or other error messages, click the Browse button in the Add Instance. Select the Library,
NCSU_Analog_Parts.
Place pmos4 transistor on the schematic sheet.

Then continue select the nmos4 transistor and place it on the schematic sheet.
Change the nmos transistor width to 2.7um. All the other parameters are left unchanged. One may note that the current inverter
design, we are using 2.7um width for nmos and 4.5um width for pmos. They are optimized for equal rise and fall time of the inverter.
Place the nmos transistor and start wiring.
Next, place the Ground (gnd symbol = 0V) and VDD (vdd symbol = 5V) to the inverter schematic. The gnd and vdd are under the
component directory of Supply_Nets . After placing the instances, press “ESC” to exit the placing mode.

On the schematic editor, select Create -> Instance or use toolbar .

Choose library NCSU_Analog_Parts in the pop-up Component Browser window.
Choose vdd from the Supply_Nets directory.

And place the vdd on the schematic.

Likewise, choose gnd from the Supply_Nets directory. And place the gnd on the schematic.
Next step is to add input and output pins to the inverter circuit.
Choose Create -> Pin menu or use toolbar . Choose appropriate name and direction.

Then place the pin on the input wire.

Likewise, do the output pin.

The completed schematic for the inverter needs to be checked and saved. Click the 'check and save' button.
Be sure that there are no errors in CIW. Correct any errors. You can find further instruction from “Help” option in CIW. There are many
detailed tutorials in this option.

Now create a netlist file from the drawn schematic and simulate the circuit.

5. Generate netlist from the schematic and simulate it with HSPICE

Select Launch -> ADE L, the Analog Design Environment window will pop up.
Then you may get another pop-up window for the Analog Design Environment License selection. Select 'Always'.

Figure: ADE Window

Select Setup -> Model files, add two models “ami06N” and “ami06P” from ncsu/models/hspice/public/publicModels/

Figure: Add models

Finished Model Library Setup:

Next, generate the netlist from the schematic. Select Simulation -> Netlist -> Create to generate the netlist.
Figure: Generated netlist window

Without any changes, Save the file as SCHinv.s using the File -> Save As menu. The SCHinv.s file contains the two transistors and
their circuit connections. One needs simulation signals and simulation command to do the Hspice simulation of the circuit. Now you
must create another file, SCHinv.hsp file with the following content:

VDD 5.0
CLK 5.0
RISE 0.1
FALL 0.1
ain 01010
..CL zout 0 10fF
You may use any text editor of your choice. One I use is „gedit‟ program. You can type:

% gedit SCHinv.hsp &

And select Create New File option if asked.

'VDD 5.0' specify the power supply voltage is 5V.

'CLK 5.0' specify the simulation time step: 5 nsec. logic low and 5 nsec. logic high
'RISE 0.1' specify the digital input signal to transition from logic low to logic high in 0.1 nsec.
'FALL 0.1' specify the digital input signal to transition from logic high to logic low in 0.1 nsec.
'ain 01010' specify the digital input signal 'ain' to go low, high, low, high, and low sequences
'..CL zout 0 10fF' specify the output signal 'zout' is connected with a load capacitance CL of 10 fF

To create the hspice file to simulate your design, I have made available for your use the „hsp50‟ command script. PWL (Piecewise
Linear Function) voltage source is assumed for signal sources. You may change the parameters above to experiment how the hspice
simulation can be designed. The last line „..CL zout 0 10fF‟ is an actual spice line which proceeds with two periods. This adds 10fF
capacitor at the „zout‟ node. This capacitor is NOT part of your schematic but it is inserted to the netlist file for more realistic circuit
simulation. Once the above 6 lines are typed, Save the file (saved as SCHinv.hsp).
Then hsp50 to generate the complete hspice file “SCHinv.sp”.

% hsp50 SCHinv

It will create “SCHinv.sp” file. Both “SCHinv.s” file and “SCHinv.hsp” file are combined into the “SCHinv.sp” file.

Now hspice simulate your schematic netlist using the following command:

% hspice SCHinv.sp

Be sure to read the hspice output, it must say it concluded and not aborted.

Once the hspice is successfully completed, you can see the input and output waveform. Type the following command to plot the
simulation output:

% wv SCHinv.tr0 &

Choose the SCHinv.tr0 from the Output View window of the SpiceCheck (sc) window and expand it. Then select “ain” and “zout”
signals, drag them to the WaveView window. You may explore other features of the WaveView program to measure the signal
parameters. Be sure that the inverter circuit is properly working.
Zoom in
Measure the gate delay
Measure output signal zout rise time:

Likewise one can measure gate delay time for signal zout changing from logic high to logic low. Also one can measure the signal fall
time. One can explore many other features of the WaveView program.

Important note:
Now we have many windows opened through the Cadence virtuoso. Once the schematic circuit has been simulated and verified its
operation, some of the windows are no longer needed and they can be closed. One of the window is ADE window, it is no longer
needed. However, the ADE window do not close normally on our system. Please do not close ADE window, just minimize it and
move on to your next tasks. If needed, additional ADE windows can be opened later. Just do not attempt to close any of the ADE
windows, it will cause virtuoso to lock up. And please do not attempt to quit virtuoso either with any of ADE windows open. You will
need to do proper virtuoso quitting procedure. Once you completed everything you need to accomplish with the virtuoso, then close all
of the virtuoso windows except ADE windows and CIW window. Then in your SSH Terminal session window, type 'ps -al' to list ALL
processes running on your linux computer system.

% ps -al

Form the processes list, identify the ADE processes. You need their process id numbers. If you see and ADE window process with the
id number, say 4567, then do the 'kill -9 4567' to quit the ADE window.

% kill -9 4567

Close all ADE windows this way. Once all the ADE windows are closed, you can normally quit the virtuoso from the CIW window.
6. Layout design of an inverter circuit

In this section, we will draw the layout view of the inverter. A layout describes the masks from which your design will be fabricated. The
layers in a layout describe the physical characteristics of the device and have more details than a schematic. Therefore, layout
verification of your design is critical. There are two types of layout design: Full-Custom and Automated. Full-custom layout is when the
user physically draws all of the layers for the individual transistor. This is a very tedious process, but it usually enables results in a
compacter design than the automated process. The automated process, on the other hand, is done by instantiating standard cells
(reusing basic blocks) and usually takes more area but it is much faster. We only introduce custom layout design here.
You should follow MOSIS SCMOS design rule for ON Semi/AIM 0.6µm:
http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html

We use the scalable rule under the SCN3M_SUBM technology code. The minimum size drawn transistor length is 0.6um, the lambda
(λ) is set to 0.3um. The inverter consists of three parts -- p-transistor, n-transistor, and connections.

6.1 Layout design with macro in the library

Step1.
Create a layout view for the inverter.
a) Select File -> New -> Cell View
b) Choose hw0choi (for my case), select the cell name inv, and select layout view.
c) Click OK. LSW and Layout Editor windows will pop up as shown below.
d) Next, Setting Display Parameters:
Select Options -> Display
Set the following options: (1) Pin names: On (2) Display levels: From: 0 To: 20
(3) Minor Spacing to 0.3, (4) Major Spacing to 2.4

Figure: Set display option

Step2.

Create a instance of pmos transistor.

1. Select Create -> instance. Then click on the Browse.. button. Wait for the Library Browser to pop up.
2. In the Library Browser, Choose NCSU_TechLib_ami06, select the cell name pmos, and select layout view.
3. Edit the pmos width parameter, then place the pmos transistor layout in the layout editor.
4. Do same for the nmos transistor.
Placing pmos layout to the layout editor window.

Scroll down the scroll bar to set the pmos transistor width parameter.
Set pmos width to 4.5um.

Place the pmos on the layout editor window.

Next, place the nmos to the layout editor window.

Scroll down the scroll bar to set the nmos transistor width parameter.
Set nmos width to 2.7um.
place the ntap to the layout editor window, ntap electrically connects nwell to vdd (5V).
Place ntap connected to pmos transistor.

Place more ntap.

place the ptap to the layout editor window, ptap electrically connects pwell to gnd (0V).
Place ptap connected or near to nmos transistor.
Do the DRC (Design Rule Check):
DRC is used to check that all process-specific design rules (such as spacing) have been met. There are process-specific design rules
that describe how close layers can be placed together and what the sizes of the areas can be. These rules are giving the minimum
requirement to avoid a catastrophic failure of your circuit due to fabrication faults. You can use the following MOSIS SCMOS design
rules as a guideline.

http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html

For this class, we use ON Semiconductor's 0.5um N-well process (C5N) to fabricate the chips. We use the scalable rule under the
SCN3M_SUBM technology code. The minimum size drawn transistor length is 0.6um, the lambda (λ) is set to 0.3um.

The design rules are different for different processes.

To do the DRC, in the layout editor, select Verify -> DRC

If your design has violated any design rules, DRC will reports the errors in the CIW. Errors are indicated by the markers (white color)
on the layout editor window. You may then proceed to correcting the errors according to the design rules. For huge layouts, the
marker might not be easily located. To find markers, choose Verify -> Markers -> Find in layout editor window. A pop-up menu will
appear. Select on the Zoom to Markers box. Click on the Apply button and Cadence will zoom in to the errors or warnings as
desired.
Finish the inverter layout design by adding vdd, gnd, input, output, etc.
First, do the metal wiring. Select the metal1 layer in LSW window.
Create -> Rectangle, or 'r' for short key.

Click on the places where the two corners should be.

Connect the pmos source to vdd.
Do touch up on nwell.
Connect the gates of pmos and nmos transistors using poly wire material.
Need to move the nmos transistor to line up the gate wire.
Finish connecting nmos and gnd wire using metal1 material.

Next, connect the drain terminal of pmos and the drain terminal of nmos transistors. Use the metal2 for the vertical wiring. To use
metal2, metal1 of the drain must be connected to the metal2. Use the via contact m2_m1 for this.
Connect the two transistor drains with metal2.
Now make an input signal connection, assume the signal come through metal1. We can use metal1 to poly contact.
Now make an output signal connection, assume the signal goes out through metal1. We can use metal1 to metal2 via contact.
Now we need to create four pins: ain, zout, vdd!, and gnd! pins.
Click on Create -> Pin.
To place the pin, first select the material metal1 from the LSW window. Then follow the instruction shown at the bottom of the layout
editor window.
Add zout pin.
Next, create vdd! and gnd! pins for the power supply.
Be sure to do the DRC.
Now the layout of the inverter must be verified. First we will extract the circuit from the layout. Then the extracted circuit will be
simulated with hspice for correct functioning and signal timing. Then we will verify the consistency of the layout circuit with the
schematic circuit using the LVS tool.
7. Generate netlist from the layout and simulate it with HSPICE

Step1.

Open the layout view of inverter, if not already opened.

Step2.

First, extract the circuit from the layout design:

Select Verify -> Extract

Click the Set Switches button.
Select Extract_parasitic_caps option. If you use capacitors or resistors, like in many analog applications, select Extract_cap and
Extract_resistor also.
Step 3

Once the circuit has been extracted from the layout, open the extracted file:

Go to the Library Manager window, select hw0chip (for my case) library -> select inv cell -> select extracted view. Double click on
the extracted view to open the extracted view in another layout editor window. You may want to take a detailed look at the extracted
view of your inverter layout design. You can also click on the materials to highlight all of the materials that are electrically connected.
There should be also some parasitic capacitors, extracted from the layout design. The simulation of the extracted circuit will be more
accurate than the schematic circuit for the signal timing, because the additional consideration of the wire length and the layout area
reflected into the parasitic capacitances.
For the simulation, we need a netlist, A netlist can be generated from the extracted circuit. Similar to Section 4,
select Launch -> ADE L from the extracted view window.
Figure: Generated netlist window, note the parasitic capacitors extracted.

Without any changes, Save the file as LAYinv.s using the File -> Save As menu. The LAYinv.s file contains the two transistors and
the parasitic capacitors. One needs simulation signals and simulation command to do the Hspice simulation of the circuit. Now you
must create another file, LAYinv.hsp file with the following content:
VDD 5.0
CLK 5.0
RISE 0.1
FALL 0.1
ain 01010
..CL zout 0 10fF

You may use any text editor of your choice. One I use is „gedit‟ program. You can type:

% gedit LAYinv.hsp &

And select Create New File option if asked.

'VDD 5.0' specify the power supply voltage is 5V.

'CLK 5.0' specify the simulation time step: 5 nsec. logic low and 5 nsec. logic high
'RISE 0.1' specify the digital input signal to transition from logic low to logic high in 0.1 nsec.
'FALL 0.1' specify the digital input signal to transition from logic high to logic low in 0.1 nsec.
'ain 01010' specify the digital input signal 'ain' to go low, high, low, high, and low sequences
'..CL zout 0 10fF' specify the output signal 'zout' is connected with a load capacitance CL of 10 fF

To create the hspice file to simulate your design, I have made available for your use the „hsp50‟ command script. PWL (Piecewise
Linear Function) voltage source is assumed for signal sources. You may change the parameters above to experiment how the hspice
simulation can be designed. The last line „..CL zout 0 10fF‟ is an actual spice line which proceeds with two periods. This adds 10fF
capacitor at the „zout‟ node. This capacitor is NOT part of your schematic but it is inserted to the netlist file for more realistic circuit
simulation. Once the above 6 lines are typed, Save the file (saved as LAYinv.hsp).

In my case, I just copied the previous SCHinv.hsp file to LAYinv.hsp file.

Then hsp50 to generate the complete hspice file “LAYinv.sp”.

% hsp50 LAYinv

It will create “LAYinv.sp” file. Both “LAYinv.s” file and “LAYinv.hsp” file are combined into the “LAYinv.sp” file.

Now hspice simulate your schematic netlist using the following command:

% hspice LAYinv.sp

Be sure to read the hspice output, it must say it concluded and not aborted.

Once the hspice is successfully completed, you can see the input and output waveform. Type the following command to plot the
simulation output:

% wv LAYinv.tr0 &

Choose the LAYinv.tr0 from the Output View window of the WaveView (wv) window and expand it. Then select “ain” and “zout”
signals, drag them to the WaveView window. You may explore other features of the WaveView program to measure the signal
parameters. Be sure that the inverter circuit is properly working.

The signal propagation time, rise time, fall time may be different from the schematic circuit.
8. LVS (Layout Versus Schematic)

The LVS check is to verify the consistence between the layout and the schematic. The layout should verified before the further
simulation. Now we have already obtained the schematic and extracted views of the inverter. We could do the LVS check with the
extracted view. Open the extracted view and choose Verify -> LVS, the following window will pop up.
LVS in progress ... wait
The output of the LVS report contains some useful information for your design. Especially when the LVS fails and the schematic and
the extracted circuits does NOT match, you may find useful clues from it.

Please try: first make a mistake in the layout of the inverter - make the nmos transistor drain not connected to zout by not drawing the
metal2 wire long enough. Extract the layout, and redo LVS.

After doing the LVS, click on Output and Error Display, observed the information. We could get six errors (actually they are all caused
by the disconnection mismatch). On the extracted view window, you can zoom-in to the problem place and find that the problem is
highlighted. Then, you can fix the problem.
9. Create symbol view

Step1. Create the symbol from the schematic

Open the schematic view of inverter, and choose “Create -> Cellview -> From Cellview”
Draw triangle and draw circle as shown below.

One can use a rectangle to represent an inverter but we can improve the readability by using the proper inverter symbol. Replace the
rectangle representation of the inverter with the new drawing. So, first select the rectangle and delete. Move the new drawing to the
middle of the red box. The red box is the boundary of the symbol. Follow the figures below to complete the inverter symbol.
Later, when you use the inverter again, you will see the diagram shown below.
10. Create NAND gate cell

Step1. Create a New CellView from the Library Manager.

Follow “File -> New -> Cellview”
Select the Library. If the selection tab is not shown, drag the right widow boundary to the right side to enlarge it.
Set the pmos transistor width to 4.5um.
Place two pmos transistors as shown below.
Then place the nmos transistors, width is set to 2.7um.
Finish wiring up the transistors, place power supply components vdd and gnd, and add the input and output pins to complete the circuit
schematic diagram. Do click on the Check and Save button. And be sure to check the CIW window, must see the 'no error' status.
The complete 2-input NAND gate circuit schematic is shown below.
Next, create the symbol view of the 2-input NAND gate. On the nand2 schematic editor window,
click Create -> Cellview -> From Cellview.
Delete the inner rectangle and replace it with a new symbol.
Next create the layout of the 2-input NAND gate. Click on the Library Manager window, File -> New -> Cellview.
Then add NTAP and PTAP to the wells.
Complete the 2-input NAND gate layout. Inputs are the two poly lines of the transistor gates. The inputs ain and bin are connected
with metal1 wires for easy access. Minimum two metal1 to poly contacts are used. The pmos and nmos transistor drains are
connected with metal2 wire, connected to the output pin zout. Again minimum two metal1 to metal2 contacts are used. Be sure to add
vdd! and gnd! pins also on the layout. Be sure to run the DRC and verify 'Total errors found: 0' status. Then extract the circuit from
the layout. And then do the LVS check. Once the nand2 passed with LVS, do create the netlist from the extraction and simulate.
Now the inverter and the 2-input NAND gates are completely designed and checked. We can design 2-input AND gate next, combining
the inverter and NAND gate.

11. Create AND gate cell

On the Library Manager window, click File -> New -> Cellview.
Finish wiring, with input and output pins. Do 'Check and Save', and be sure the 'no errors' status.
Just for the testing and analysis, an extra pin 'xout' is added

Once the 2-input AND gate schematic is complete and tested (with hspice simulation - function verification), we are ready to design the
layout. This time, we will generate the 2-input AND gate layout from the schematic since we have completed the 2-input NAND gate
layout and the inverter layout. On the Schematic Editor window, click Launch -> Layout XL. We will see the XL Editor for the
schematic (left) and XL Editor (right) for the layout. On the layout editor, the layout instance of 2-input NAND gate, the layout instance
of inverter, and the signal pins will be shown. We can reposition the two layouts and manually connect the signals, and place the pins
on the layout. The following sequence of figures will illustrate the layout design of the 2-input AND gate.
The XL Editor: left is the schematic editor and right is the layout editor. Click the 'Generate All From Source' button on the lower left
of the layout editor window.
Next, move the nand2 gate. The signal connection wires will follow the layout instance move as shown below.
Place the nand2 layout and inverter layout near each other and delete the area marker. The area marker
can be simply selected and deleted.
Then set the Display Option.
Move the inverter layout over to the left, overlapping the NAND gate layout, make the overall AND gate layout as small as possible
without any DRC error.
Connect the NAND gate output to inverter input. And move each of the signal pins to the designated location following the orange
string. The final placement of the pins should eliminate any trace of the orange indicator string.
Completed 2-input AND gate layout, composed of two subcells - NAND and inverter.
Do the DRC, and be sure to check no error.

Extract the circuit from the layout, next.

Extraction switch options selection:

Bring up the extracted view.

For the AND gate layout verification, we will do the LVS.
Be sure to wait for the completed 'match' message.
And for final AND gate layout verification and characterization, we will do the hspice simulation.
Save the file as 'LAYand2.s'
Update to be continued ...

Done.

Some old material on the next page to be continued ...

12.1 Smaller transistor layout

Step1.

Create a layout view for the inverter.

a) Select File -> New -> Cellview.
b) Choose mylib, select the cell name inv, and select layout view.

Figure 1 Create layout view

c) Click OK. LSW and Layout Editor windows will pop up as shown below.
d) Next, Setting Display Parameters:
Select Options -> Display.
Set the following options: (1) Pin names: On (2) Display levels: From: 0 To: 20

Figure 2 Set display

Step2.

Create a instance of pmos transistor.

1. Select Create->instance. Then click on the Browse.. button. Wait for the Library Browser to pop up.
2. In the Library Browser, Choose NCSU_TechLib_ami06, select the cell name pmos, and select layout view.
3. Place the pmos in the layout editor and get the following layout:

Figure 3 pmos instance

Step3.

Place a nmos as in step2.

Step4.

Draw the gnd next to the Nmos

1. Select the pselect layer from the LSW window; we will draw the pselect enclosing the substrate (connected to the gnd) contact for the
N transistor
2. Select the Create -> Rectangle
3. Draw the pselect on the cellview; it will have to enclose the contact p-active by at least 0.6.The pselect abuts directly to the nselect of
the N transistor, but they should not overlap.
4. Select the pactive layer from the LSW window
5. Draw the pactive island on the cellview to be 1.2 wide by 1.5 tall; it must be enclosed by the pselect by 0.6.
6. Add contacts in the center of the substrate-contact island.
Step5.

Draw the Vdd next to the nmos as in the previous step.

Step6.

1. Connect the source of p-transistor to the well-contact using the metal 1 layer.
2. Connect the source of n-transistor to the substrate-contact with the metal 1.
3. Add a contact to the gate (poly)

Figure 4 Layout of inverter

12.2 Generate layout layer by layer

Step1.

Same as step1 in 4.1

Step2.

Layout of P-transistor with L=0.6µm and W=1.5 µm.

Since we are using the Nwell process technology, the substrate will be p-substrate.
We will create a pmos transistor first. To do that we need an Nwell in which the pmos
transistor will be formed.

a) Draw the well

1．Select the n-well layer from the LSW window
2. Select the Create->Rectangle (or use hotkey R).
3. Draw the n-well on the cellview to be 7.2 wide by 7.2 tall.
b) Draw the p- select regions for the p transistor
1. Select the pselect layer from the LSW window; we will draw the pselect enclosing the transistor
2. Select the Create->Rectangle.
3. Draw the pselect on the cellview; 4.8 wide and 2.7 tall; its Left- and
Right-edges should be 0.6 away from well edges. The pselect should be placed within the n-well, even if the size should vary (you can
use the Edit->move or hotkey m command to move the layer) .

c) Draw Diffusions
1. Select the pactive layer from the LSW window; draw the active region of the p-device with size 1.5 X 3.6
2. Add a contact in the center of the well-contact island with the size 0.6 X 0.6
d) Similarly, draw the nmos transistor and connect them.
e) Draw the substrate-contact as in step 4 of 4.1.
f) Draw metal Connections as in step 6 of 4.1 and get the same layout as in figure 14.

Step3.
Draw the vdd and gnd as in section 5.1.

Step4.
Add Pins to the layout. Use metal 1 layer for the power supply pins: "vdd!" and "gnd!" Be sure to use the "!" in the power supply pin
names - it will match with pin names generated by the schematic components: vdd and gnd. This is important for the hspice simulation
and LVS checking later. Then add "in" and "out" pins, again on metal 1 layer if possible.

12.3 DRC rule check.

DRC is used to check that all process-specific design rules (such as spacing) have been met. There are process-specific design rules
that describe how close layers can be placed together and what the sizes of the areas can be. These rules are giving the minimum
requirement to avoid a catastrophic failure of your circuit due to fabrication faults. You can use the following MOSIS SCMOS design
rules as a guideline. The design rules are different for different processes.
In the layout editor, select Verify -> DRC

Figure 5 DRC
If your design has violated any design rules, DRC will reports the errors in the CIW.
Errors are indicated by the markers (white color) on the circuit. You may then proceed to correcting the errors according to the design
rules. For huge layouts, the marker might not be easily located. To find markers, choose Verify -> Markers -> Find in layout window.
A pop-up menu will appear. Select on the Zoom to Markers box.
Click on the Apply button and Cadence will zoom in to the errors or warnings as desired.

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