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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

A Noise-Power-Area Optimized Biosensing Front

End for Wireless Body Sensor Nodes and
Medical Implantable Devices
Hansraj Bhamra, Member, IEEE, John Lynch, Matthew Ward, and Pedro Irazoqui, Senior Member, IEEE

Abstract— In this paper, we present a noise, power, and area

efficient biosensing front-end application specified integrated
circuit (ASIC) for the next-generation wireless body sensor nodes
and implantable devices. We identify the key design parameter
tradeoffs in the biomedical recording systems and carry out a
thorough analysis and optimization to maximize them. Based on
our analysis and optimization of the front end, we propose a
design methodology for the recording channel that is applicable
to various biomedical applications. The ASIC is implemented in
a 0.18-µm CMOS process to validate our optimization method-
ology. The ASIC is reconfigurable to accommodate various
biopotentials with the high-pass and low-pass cutoff frequencies
being 0.5–300 Hz and 150 Hz–10 kHz, respectively. The low-
pass cutoff is provided by an ultralow power G m -C low-pass
filter, which also acts as an antialiasing filter for the switching-
optimized 10-b successive approximation register (SAR) analog-
to-digital converter (ADC). The analog front end (AFE) gain is
also programmable from 38 to 72 dB. A comprehensive power Fig. 1. WBSNs forming a WBAN.
management unit provides the power supply, multiple reference
voltages, and bias currents to the entire chip. The AFE and ADC
dissipate only 5.74 µW and 306 nW from the on-chip regulators,
respectively. The measured input-referred noise is 2.98 µVrms ,
resulting in the noise efficiency factor and power efficiency factor
equals 2.6 and 9.46, respectively. The active area of the AFE
is 0.0228 mm2 . We verify the chip functionality in a number of
in vivo and ex vivo biological experiments.
Index Terms— Analog front end (AFE), biopotentials, biosens-
ing acquisition, implantable devices, low noise, low power, wire-
less body sensor node (WBSN).

I. I NTRODUCTION Fig. 2. Design parameter tradeoffs in a biosensing AFE.

R ECENT advances in wireless body sensor nod-

es (WBSNs) and implantable system-on-chips (SoCs)
enable a huge paradigm shift in personalized healthcare and
effective treatment of various illnesses such as neural disor-
ders, cardiac diseases, glaucoma, and diabetes [1]–[4]. These
nodes utilize the ultralow power CMOS integrated circuit
Manuscript received January 9, 2017; revised April 21, 2017; accepted
May 28, 2017. This work was supported by the Defense Advanced Research
Projects Agency MTO under the auspices of Dr. J. Judy, Pacific Grant/Contract
N66001-11-1-4029. (Corresponding author: Hansraj Bhamra.)
H. Bhamra and J. Lynch are with the School of Electrical and Computer
Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail:
hansraj4u.iitd@gmail.com).
M. Ward is with the Weldon School of Biomedical Engineering, Purdue
University, West Lafayette, IN 47907 USA.
P. Irazoqui is with the School of Electrical and Computer Engineering,
Purdue University, West Lafayette, IN 47907 USA, and also with the Weldon
School of Biomedical Engineering, Purdue University, West Lafayette, IN
47907 USA.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2017.2714171
1063-8210 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
design techniques to acquire and process biopotential signals
in a wireless body area network (WBAN) and transmit the data
to the secure mobile devices in real time [4]–[6]. Fig. 1 shows
the architecture of a typical sensor node in a WBAN com-
prising a biosensing analog front end (AFE), an analog-to-
digital converter (ADC), a digital signal processing core,
a power management unit (PMU), and a wireless telemetry
section. The biopotential signals are captured from either
implanted or surface electrodes via a biosensing AFE, which
is one of the most critical circuit blocks in the WBSNs and
implantable SoCs.
Fig. 2 illustrates all the design tradeoffs (i.e., noise, power,
area, linearity, common-mode rejection ratio (CMRR), power-
supply-rejection-ratio (PSRR), offset rejection, and input
impedance) for a biosensing AFE. Thus, a thorough analysis
and design optimization of the AFE blocks is necessary to
capture the detailed information carried out by the biopotential
signals. In keeping with the resulting analysis and optimiza-
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
tion, the main design challenges of the AFE are due to the
following.
1) System Design Constraints of the Sensor Nodes:
This includes an optimum number of amplification
stages, power consumption, filter specifications, linear-
ity, CMRR, and PSRR. In recent studies, the application
of wireless power transfer in WBSNs demands a very
low peak power consumption of the entire SoC [5]–[8].
A voltage regulator (linear or switch capacitor) is often
employed as a part of PMU to mitigate the supply volt-
age fluctuations owing to unreliable and unpredictable
nature of the harvested energy. However, a finite amount
of ripple is still present in the supply voltage due to
the lack of a bypass off-chip capacitor [5]. Moreover,
the postamplification signal processing in the digital
domain [9], [10] injects switching noise into the AFE
that appears as a common-mode supply and substrate
noise. The interference from 50/60-Hz power lines also
appear as a common-mode noise. Therefore, the AFE
must have a high PSRR and CMRR, while limiting its
power consumption to less than 10 μW.
2) The Nature of Biopotential Signals: These signals are
characterized as a low-frequency and low-amplitude
signals [11]. The amplitude of such signals range from
tens of microvolts to a few millivolts and their frequency
spectrum spans from sub-1 Hz to a few kilohertz.
To ensure a clean signal acquisition, the AFE amplifier
must have a sufficiently low input-referred noise (IRN)
per unit bandwidth. Since the low frequencies are of
interest, the flicker or 1/ f noise of MOS transis-
tors is an immediate concern. In order to accommo-
date the upper end of the amplitude range (typically
1–5 mV), a sufficient dynamic range of the amplifier
is also required.
3) Reconfigurable AFE: In future, the sensor nodes in a
WBAN will capture the various biopotential signals,
with different amplitudes and bandwidths, simultane-
ously from the different parts of a human body. Accord-
ingly, a single AFE with reconfigurable parameters
settings, such as gain, bandwidth, bias current, and
sampling rate, is highly desirable. Also, the dependence
of peak signal amplitude on the type of electrode used
and interface environment necessitates a reconfigurable
gain stage. The amplifier linearity at very low bias
current is another important design parameter for the
ultralow power AFE.
4) Sensor Interface Between the AFE and Electrodes: The
electrode–tissue interface creates a dc offset voltage
(up to 200–300 mV), which must be filtered out by the
AFE in order to avoid the saturation of the first-stage
amplifier [11], [12]. Also, in order to reduce the sensi-
tivity to electrode impedance imbalance, the AFE should
present a very high-input impedance to the preceding
electrodes.
5) Chip Area: It must be as small as possible for the
body worn and implantable devices. It is popularly
known that the 1/ f noise of the MOS transistors is
inversely proportional to the occupied area, which makes
Fig. 3. Schematic of widely used capacitively coupled neural amplifier.
it extremely challenging to meet the area and noise
specifications simultaneously.
In order to address the above-mentioned challenges,
we present a fully integrated AFE for the WBSNs and
implantable SoCs, which follows a design methodology
and optimization to fulfill the requirements posed by a
number of design parameters. The rest of this paper is
organized as follows: Section II describes the perfor-
mance analysis of the recording amplifier channel and
prior work. Section III presents the system architecture.
Section IV details the circuit blocks. The chip measure-
ment results and biological data from the in vivo animal
and ex vivo human studies are presented in Section V.
Conclusions are drawn in Section VI.
II. P ERFORMANCE A NALYSIS AND P RIOR A RT
There are several biosensing amplifiers that have been
reported in [5], [9], and [13]–[31]. As depicted in Fig. 3, most
of these architectures are capacitively coupled to the recording
electrodes in order to reject the dc offset and to accommodate
the rail-to-rail input common-mode range. The amplifier is
configured to provide a bandpass frequency response, where
the high-pass (lower) and low-pass (upper) cutoff frequencies
are approximately given by the relation: fHP = 1/2π R f C f
and f LP = G m /2π A M C L (G m is the transconductance of
the operation transconductance amplifier (OTA), A M is the
amplifier’s mid-band gain, and C L is the load capacitance),
respectively. The mid-band closed-loop gain A M of the ampli-
fier is set by the ratio of input capacitor Cs to feedback
capacitor C f ( A M = C S /C f ). The capacitively coupled archi-
tectures are implemented in both single-stage [13]–[22] and
multistage configurations [5], [23]–[31]. The noise efficiency
factor (NEF) is often used to compare these works among each
other. The NEF is mainly focused on the tradeoff between IRN
and current consumption and is expressed as

2Itot
NEF = v ni,rms (1)
πUt 4kT BW
where Ut is the thermal voltage, k is the Boltzmann’s constant,
T is the absolute temperature, BW is the −3 dB bandwidth
of the amplifier, Itot is the total current, and v ni,rms is the
total input-referred voltage noise of the amplifier, which can
be approximated as [32]

4kT
v ni,rms ≈ . (2)
3C L A M
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BHAMRA et al.: NOISE-POWER-AREA OPTIMIZED BIOSENSING FRONT END FOR WBSN
Fig. 4. Block diagram of the implemented chip.
However, the power efficiency factor (PEF = NEF2 × VDD )
is a more relevant metric to address the noise-power tradeoff,
since it carries the VDD information which was overlooked
in the NEF expression. Targeting only NEF, several excellent
solutions neglected other important design parameters such as
active silicon area, linearity, optimum number of amplification
stages, and filter requirements.
In order for one to meet all of the design constraints,
the design and optimization of the AFE using only a single
stage is extremely difficult [13]–[22]. To mitigate the issues
associated with the single-stage design, studies in [23]–[31]
employ two stages of amplification. However, these works
often utilize a large load capacitor or a bandpass filter (BPF)
stage to restrict the noise bandwidth, which is highly area
inefficient. Also, a high-power buffer stage will be needed to
drive the ADC, when utilizing the above-mentioned designs
to build a biosensing AFE. Finally, a comprehensive PMU
and an ultralow power ADC with very small area is required
to provide a highly integrated solution for biopotential data
acquisition.
The goal for the presented biosensing front end is to
establish a methodology that can maximize all the perfor-
mance tradeoffs depicted in Fig. 2. In keeping with this
goal, the optimized number of stages, filtering requirement
for the subsequent ADC, programmability, and higher degree
of integration are needed to be considered for achieving a
satisfactory AFE performance.
III. S YSTEM A RCHITECTURE
The block diagram of our implemented chip is shown
in Fig. 4. The system consists of a micropower biosens-
ing AFE, a successive approximation register (SAR) ADC,
a process and voltage (PV) compensated clock oscillator [33],
and a PMU. The proposed reconfigurable biosensing AFE
comprises a low-noise amplifier (LNA), a programmable gain
amplifier (PGA) with seven steps of gain control, followed
by a third-order antialiasing G m -C low-pass filter (LPF).
The G m -C LPF provides a programmable f LP . A 10-b SAR
ADC with reconfigurable sampling rate is used to digitized
the biopotentials. Ultralow power operation and low area
occupation were the main design goals for the ADC. The
front end is fully differential to provide a good common-mode
3
and digital switching noise rejection. The PMU incorporates
1.4- and 1-V linear voltage regulators, a bias current generator,
and a sub-1 V and sub-1 μW bandgap reference (BGR) circuit.
The BGR is capable of providing multiple reference voltages
to the chip for the programmability and tuning purposes.
A. Front-End Design
A maximum noise-area-power efficiency can only be
achieved by optimally designing all three major compo-
nents (amplifier, LPF, and ADC) of the front end. First, it is
a well-established fact that in a multistage amplifier, the first
stage determines the overall noise performance of the system
as its noise contribution is significantly higher than the other
stages. Thus, the first-stage amplifier, LNA, must be designed
for very low noise at a very low bias current. We also consider
the AFE area along with the performance parameters shown
in Fig. 2 in designing and optimizing the system and the circuit
blocks, which were ignored in the previous works. Second,
a third-order G m -C LPF is designed to improve the area of the
recording AFE by eliminating the bulky load capacitors that
are used in the earlier designs to restrict the noise bandwidth
of the amplifier. Additionally, the programmable LPF also acts
as an antialiasing filter stage for various biopotentials, since it
is an interface between the two-stage biosensing amplifier and
the SAR ADC. This eliminates an additional RC-antialiasing
filter stage to improve the area of the AFE. Finally, the SAR
architecture is chosen for the ADC due to its low power and
small-area feature. The major sources of power dissipation in
a charge redistribution SAR ADC are capacitive digital-to-
analog converter (DAC), comparator, and SAR digital control
logic. We optimized the DAC switching sequence to lower
the DAC switching energy and the digital switching power
consumption associated with the SAR control logic. We use
the split capacitive DAC array to reduce the total capacitance,
and hence the active area of the ADC. The energy-efficient
two-stage dynamic comparator with improved linearity avoids
the need for a power and area consuming analog preamplifier.
Also, the need for a power and area consuming reference
buffer was obviated by using the 1.4-V regulated supply as
a reference voltage for the ADC.
B. Noise-Area-Power Optimization of the Amplifier
Fig. 5 shows the reconfigurable biosensing amplifier that
consists of an LNA and a PGA. The feedback resistors
in the LNA are implemented by the nMOS transistors
(MT 1 –MT 4 ), providing extremely high on-chip incremental
resistance (>1012 ) to synthesize a very low-frequency high-
pass cutoff ( f HP,LNA = 1/2π R f 1 C f 1 ). In order to restrict
the noise bandwidth of the pseudo resistors and to reduce the
area occupation, an intermediate BPF stage and the large load
capacitors (∼tens of picofarad) can be avoided by judicially
choosing the series and feedback capacitors of LNA and PGA,
C S1,2 and C f 1,2 to meet the criteria suggested by [32]
CL 2 f LP
 . (3)
CS 3 f HP
Since the noise contribution from the pseudo resistors is
made negligible by satisfying the inequality (3), the input-
referred voltage noise of the LNA v ni,LNA
2 can directly be
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 7. Simulation result for the input-referred rms voltage noise of the LNA
with respect to the input pair channel width for different channel lengths.
Fig. 5. Schematic of fully differential two-stage biosensing amplifier
comprises of LNA and PGA.
transistors will lower the thermal and 1/ f noise components,
respectively. Second, the input pair parasitic capacitance Cin1
should be minimized (i.e., input pair dimensions should be
kept small) to minimize the factor (C S1 + C f 1 + Cin1 )/C S1
in (4). If area is not an important design criteria then this factor
can easily be minimized by choosing large C S1 and C f 1 , such
that C S1 + C f 1  Cin1 . However, this is not a viable solution,
since we have included AFE area as an important design
criterion. The arguments listed above suggest that increasing
the dimensions of the input pair M1,2 beyond a certain
optimum value will make the ratio (C S1 + C f 1 + Cin1 )/C S1 a
Fig. 6. Schematic of fully differential FC OTA A1 for the biosensing LNA.
dominant factor in (4), which will adversely affect the v ni,LNA
2 .
Therefore, we need to evaluate the effect of input differential
written as a function of the input-referred voltage noise of pair M1,2 size on the v ni,LNA
2 . Also, in order to achieve a high
noise-area-power efficiency, we need to limit the values of
the OTA A1 , v ni,A1
2 , by the following relation:
capacitors C S1 and C f 1 , and input bias current I B .
(C S1 + C f 1 + Cin1 )2 Fig. 7 shows the simulated value of v ni,LNA 2 versus the
v ni,LNA
2 = v ni,A1
2
2
(4)
C S1 input transistors M1,2 width for the different channel lengths.
As seen from Fig. 7 that an optimum input transistor dimen-
where Cin1 is the input parasitic capacitance of the OTA A1 sions can be found for the given bias current I B and the ratio
(see Fig. 5). From this expression, it is clear that the noise from C S1/C f 1 . In this optimization example, we set the I B and
the OTA A1 is the most dominant component in the expression C S1/C f 1 to 0.5 μA and 10 pF/100 fF, respectively.
of v ni,LNA
2 . In addition, the factor (C S1 + C f 1 + Cin1 )/C S1 The AFE capacitors are implemented by the high
must be kept close to 1 to lower the v ni,LNA
2 . For the folded density (4 fF/μm2 ) but well matched metal–insulator–
cascade (FC) OTA A1 (Fig. 6) designed in this paper, the metal (MIM) capacitors. The MIM capacitors were placed
input-referred voltage noise, including both flicker (1/ f ) and over the active transistor area to minimize the overall size.
thermal noise components, can be approximated as The common-centroid and symmetrical layout techniques were
  utilized to minimize the mismatches in the differential path for
∼ 1 4kT 16 gm13,14 16 gm5,6
v n,
2
= + kT + kT an improved CMRR.
A1
gm1,2 κ 3 gm1,2 3 gm1,2
  
2 Kp Kn gm13,14 2 C. Optimum Number of Stages and Filtering Requirement
+ 2 +
COX f W1,2 L 1,2 W13 L 13 gm1,2 Two stages of signal amplification is required to efficiently
  
Kp gm5,6 2 control the gain without compromising the signal linearity
+ (5) and tracking speed, while providing sufficient dynamic range.
W5 L 5 gm1,2
Thus, the AFE comprises two gain stages: LNA and PGA.
where gmi is the transconductance of the i th transistor in A1 , The LNA is designed for a very low noise, whereas the PGA
k is the Boltzmann’s constant, κ is the inverse of subthreshold provides additional gain with a sufficient linearity and dynamic
slope, T is the absolute temperature, and K p and K n are the range. Having more than two stages of amplification would
1/ f noise coefficients. unnecessarily burden the AFE with additional power and area
Combining (3) and (4) suggests following conclusions for overhead. However, the AFE still requires one LPF stage that
the LNA design: first, maximizing the gm1,2 (i.e., increasing follows the LNA and PGA for the reasons explained in the
the W1,2 /L 1,2 or I B ), and the area (W1,2 × L 1,2 ) of the input following.
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BHAMRA et al.: NOISE-POWER-AREA OPTIMIZED BIOSENSING FRONT END FOR WBSN
First, the LPF sees both the amplification stages as a single
amplifier, relaxing the bandwidth criteria, and hence removing
the signal errors associated with the tracking speed of LNA.
Second, the in-built low-power buffers in the LPF discard
the need for extra power hungry buffer stages to drive a
subsequent ADC in the WBSN system. Third, the LPF stage
preceding the ADC acts as an antialiasing filter for the ADC
and can be employed with various ADC architectures. Finally,
the deployment of LPF following the amplifiers allows all
three stages (LNA, PGA, and LPF) in the AFE to be optimized
separately, which makes the design easier and modular. Since a
modular WBSN is designed to acquire a variety of biopotential
signals, a high filter rolloff (−60 dB/decade) along with a
reconfigurable low-pass cutoff frequency was chosen for the
LPF design. The cutoff frequency of the LPF is digitally recon-
figured by the PV clock oscillator [33] with programmable
clock frequencies.
The f HP and f LP of the AFE are determined by the
bandwidth of a given biopotential. For example, the bandwidth
of electromyogram (EMG), electroencephalogram (EEG), and
electrocardiogram (ECG) signals are 10 Hz–1 kHz, 1–150 Hz,
and 0.5–250 Hz, respectively, for most recording purposes.
Similarly, neural signals contain the information from less
than 1 Hz to 10 kHz. Accordingly, the cutoff frequencies
in the AFE signal chain are made reconfigurable. The f HP
can be tuned from 0.5 to 300 Hz by changing the bias
voltage (VTUNE ) of transistors MT 1 –MT 4 in the LNA (Fig. 5).
This tunability would also compensate for the variation in
f HP,LNA due to the pseudo-resistance sensitivity to the CMOS
process variations and provide a high uniformity in the first
stage f HP,LNA in a multinode and/or multichannel WBAN
scenario. The f LP of the AFE is reconfigured by programming
the cutoff frequency of G m –C LPF.
Details of design and optimization of the circuit blocks are
discussed in the following section.
IV. C IRCUIT B LOCKS
A. Biosensing LNA
The design of LNA (Fig. 5) is based on the optimization
methodology described in the previous section. Due to the
large amplitude range of the biopotential signals (tens of
microvolts to millivolts), the first stage cannot afford to have
a high output signal swing. To keep that in mind, a relatively
low gain of 38 dB (80 V/V) is set for the first stage LNA
by choosing C S1 = 9.6 pF and C f 1 = 120 fF, respectively.
The selection of these values for C S1 and C f 1 is carried
out to maximize all the design tradeoffs and to satisfy the
expression (3). The multiple reference voltages from the BGR
are multiplexed to generate the tune voltage VTUNE for LNA,
thereby providing tunability to f HP (0.5 to 300 Hz).
B. Energy-Efficient Low-Noise OTA
The selection of the OTA architecture for a low-noise and
energy-efficient LNA design should carefully be investigated.
The open-loop gain of the OTA must be very high to minimize
the gain error due to the capacitive feedback. The low-noise
neural amplifier presented in [13] and [18] utilizes the current
5
mirror OTA architecture. This topology requires a high bias
current to achieve satisfactory v ni,A1
2 and also has a lower
open-loop gain. A telescopic OTA has a large open-loop gain,
but the input and load devices cannot be optimized separately
for a noise-power tradeoff [21]. Similarly, a two-stage OTA
provides high gain but poor energy efficiency [18], [24], [28].
As demonstrated in [14] and [30], the FC topology can
be optimized for a near optimal noise and energy efficiency.
We also include area as an important design criterion and
utilized the FC OTA to achieve a better noise-power-area
tradeoff compared to the other topologies.
The schematic of the fully differential, low-noise FC OTA
A1 and its common-mode feedback (CMFB) circuit is shown
in Fig. 6. As evident from (5) that in order to minimize
the v ni,A1
2 , the gm of the input differential pair M1,2 need
to be maximized, whereas the gm of transistors M5,6 and
M13,14 should be minimized. To accomplish the task, current
scaling is applied between the input differential pair and the
folded branch with the bias current ratio of 1/12 (Fig. 6).
The input pair transistors M1,2 are biased in the subthreshold
region to achieve maximum gm1,2 for I B = 1 μA. The
effective gm is further increased by boosting the impedances
looking into the nodes X and Y , by using cascode transistors
M11 and M12 , respectively. This also eliminates a need for the
large source degeneration resistors (∼ hundreds of k) for the
current sink transistors, thereby lowering the area occupation.
The size of pMOS input transistors, M1,2 , is designed to be
comparatively large (W1,2 = 336 μm and L 1,2 = 0.7 μm)
to minimize the 1/ f noise component, as expressed in (5).
The pMOS transistors are chosen for the M1,2 for its lower
1/ f noise characteristics than the nMOS transistors.
A high gm1,2 , to obtain good noise performance at a
given I B , yields lower M1,2 overdrive voltages, thereby com-
promising the signal linearity. In order to meet the linear-
ity specification, two design strategies are employed. First,
two gain stages are designed, where the LNA gain is kept
low (38 dB) to limit its output signal swing and then the
second-stage PGA is designed for high linearity since its
noise specification is relaxed. Second, a very small W/L ratio
(1 μm/15 μm) and thus a large overdrive voltage is chosen
for the CMFB input pair transistors M15 –M18 to maximize the
output differential signal and hence the signal linearity at the
amplifier output.
C. PGA
The PGA comprises an FC OTA A2 with a reconfigurable
capacitive feedback (Fig. 5). Since the conventional capaci-
tive feedback PGA suffers from a low (sub-hertz) frequency
distortion due to the pole–zero pair created by C f 2 and
switch resistance (OFF-state), a switch-over feedback topology
is utilized that effectively removes this distortion [28].
The FC OTA A2 has a much relaxed specification on the
IRN and is mainly designed for a high linearity and high
dynamic range. Therefore, the schematic of OTA core A2 is
similar to the OTA A1 (Fig. 6) except it does not include the
cascode devices M11 and M12 . However, the current scaling
is still utilized to minimize the total power consumption of
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 8. Block diagram of fully differential third-order G m -C LPF core.
Fig. 9. Simplified schematic for the variable gmf -stages used in the LPF
core.
the AFE. A 0.5-μA bias current is used for the input pair
M1,2 transistors, while each folded branch draws 100 nA
from the 1.4-V regulated supply. In order to maximize the
output dynamic range and the linearity of the CMFB circuit,
a minimum size (0.5 μm/20 μm) is chosen for the transistors
M15 –M18 .
D. Gm –C LPF
A simplified schematic is given in Fig. 8 for the G m -C LPF
core, having a total of three poles. In each channel, two poles
are from a biquad stage and the other pole is from a single
pole stage. The transfer function of the filter core is
Vop (s) − Von (s)
Vip (s) − Vin (s)
(1/b)(gmf /C)3
= (6)
{s 2 + (gmf /aC)s + (gmf /C)2 }{s + (gmf /bC)}
where gmf is a single-stage transconductance. Fig. 9 depicts
a simplified schematic for the variable gmf -stage used in the
LPF core. The output resistance of transistors M3 and M4 ,
which are in the saturation mode, serves as a source degen-
eration resistor for transistors M5 and M6 . The linearity
is thereby enhanced allowing an acceptable total harmonic
distortion (THD) performance. The front-end stage dominates
the linearity performance, and the THD was measured to
be >56 dB over corners.
A differential current from the linearized input differential
pair is folded into a gilbert-type gain cell thereby enabling the
value of the transimpedance gain to be varied with the input
current Ivar . The current gain of the gmf -stage can therefore
Fig. 10. Schematic for the dynamic frequency control.
be described as
i out = (Ivar /I A ) × (i dp − i dn ). (7)
Thereby, the gmf is proportional to the input current Ivar .
The outputs are cascaded to help to keep the output resistance
high which results in the dc gain being equal to one.
Fig. 10 illustrates a schematic for an on-chip dynamic
frequency control block. The LPF core is given in the bottom
left of Fig. 10. It is configured for three poles (Fig. 8) where
the cutoff frequency for each stage is proportional to the
product of gmf and 1/C of the capacitors. A current from the
voltage-to-current (V –I ) converter is used to vary the cutoff
frequency of the filter by adjusting the gmf for each stage.
A reference current Iref flows into a reference gmR -block
in which the gain changes with current in the same way that
the gmf -stages in the LPF core change. The opamp-buffered
output of the reference gmR -block is effectively sampled with
the collection of switches shown in Fig. 10. A charge placed
on the C2 from sampling is then compared to a fixed ramp.
The system will dynamically adjust the charge on C2 com-
pared to a fixed ramp until they are equal. This configuration
improves upon the implementation in [34] with the addition of
a sample and hold after the opamp having C2 . The frequency
of the input clock controls the ramp time. The net effect, and
indeed the goal of the circuit is to able to control the cutoff
frequency of the LPF with the input clock.
Fig. 11(a) depicts simulated waveforms illustrating the
calibration for the cutoff frequency. Upon the assertion of
the ph2 signal, there is a negative step at the output of
the opamp (V2 ) feeding the ph_hold switch (Fig. 10). The
amplitude of the negative-going pulse is a measure of transcon-
ductance. Immediately after this the phi signal is asserted
and a ramp starts. The length of the ramp is a measure of
the frequency of the incoming clock. The value at the end
of the ramp is sampled with the ph_hold signal, and this
sampled value is servoed so it is equal to Vref . The negative-
going pulse will then be equal to the positive ramp; hence,
the transconductance of the gmR -stage is being controlled with
the frequency of the incoming clock. Fig. 11(b) illustrates the
Vcont signal for three different values of frequency.
The variable gmf -stages have internal poles and zeroes, and
we wanted to evaluate the overall filter performance including
these poles and zeroes. First, we varied the current Ivar to
the gmf stages in the LPF core so as to vary the cutoff
frequencies. This is depicted in Fig. 12. Notice the shape of
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHAMRA et al.: NOISE-POWER-AREA OPTIMIZED BIOSENSING FRONT END FOR WBSN
Fig. 11. LPF simulation results depicting (a) calibration for the LPF cutoff
frequency f LP and (b) Vcont signal for three different clock frequencies.
Fig. 12. Frequency sweep with Ivar to vary the cutoff frequency.
Fig. 13. Gain and phase plots to compare with ideal case with constant gmf .
the filter characteristics is maintained throughout. There is no
peaking or any other detrimental effect. The shape of the filter
characteristics is maintained throughout the calibration.
Next, the magnitude and phase characteristics of the filter
core for the cutoff frequencies from Fig. 12 were compared
to an ideal representation of (6). A copy of the core filter
was idealized by replacing the gm -stages with an ideal voltage
controlled current source to represent the appropriate gm value.
In this paper, the target transfer function was a three-pole
Bessel filter. Then, the gain and the phase were compared in
the pass region and also in the region within 5× of the cutoff
frequency. The simulation results are given in Fig. 13. It is
clear that in the pass region the characteristics of the actual
core filter and the ideal filter are virtually identical, and the
7
Fig. 14. Block diagram of 10-b SAR ADC.
Fig. 15. Split capacitive DAC array with unit attenuation capacitor (C0 ) and
switching waveforms.
phase for the region within 5× of the cutoff does not vary
more than 10° from the ideal Bessel case.
E. SAR ADC
Fig. 14 shows the block diagram of 10-b charge redistri-
bution SAR ADC that comprises a capacitive DAC array,
SAR digital control logic, and energy-efficient compara-
tor. We use a split capacitive DAC array to minimize the
total capacitance, and hence the active area of the ADC.
Fig. 15 shows the DAC array and switching waveforms
for the positive side of operation. Since the ADC is fully
differential, the operation for negative DAC array would be
complimentary to the positive side. Instead of being fractional,
the attenuation capacitor in the DAC array is implemented
by the unit capacitance C0 (95 fF) for better matching.
Although, the implementation of the attenuation capacitor with
C0 lowers the nonlinearity associated with fractional capacitor,
it leads to the 1-LSB of gain error. In order to ensure the gain
error to be always less than 1-LSB, we employ a dummy unit
capacitor C0 in the LSB DAC array. We utilized a common-
centroid layout scheme for the DAC array to minimize the
mismatches of the capacitor array.
The switching energy of the capacitive DAC array and
SAR control logic are optimized for ultralow power opera-
tion of the ADC. The DAC switching presented here uses
only two global phases namely–sampling 1 and reset 2 .
We derive the bit-cycling phase 2 from the reset phase 2
and combine them in a single phase. This simplifies the
DAC switching control. The MSB is coded as a sign bit
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 17. Chip microphotograph. (AFE includes LNA, PGA, and G m -C LPF.)

Fig. 16. Energy-efficient two-stage comparator for SAR ADC.

that is determined during the reset phase 2 by resetting the

DAC array to Vcm . Since the MSB is a sign bit, the value
of the MSB capacitor is only 16C0 , which is 2× lower than
the conventional split DAC array and 32× lower than the
conventional binary DAC array.
Fig. 16 shows the schematic of the energy efficient
two-stage dynamic comparator. The first stage of the compara- Fig. 18. Measured frequency response of the LNA with programmable f HP .
tor provides necessary voltage amplification, whereas the sec-
ond stage provides the output. The operation of the comparator
is modified from [35], which was mainly designed for high
speed rather than low power. When the “Clk” input is low
and “Clkb” is high, the comparator is in the reset state and the
nodes D P and D N are charged to the supply voltage through
transistors M3 and M4 , respectively. In this phase, the first
stage of the comparator presents a nonlinear capacitance to the
gates of the input pair transistors M1,2 , whose value depends
on the voltage on the node “X”. Instead of leaving the node
Fig. 19. Measured frequency response of the amplifier including PGA.
“X” floating, we connect it to the supply voltage through the
transistor M6 . This forces the transistors M1,2 in the strong
accumulation region to linearize its input gate capacitance. F. Clock Oscillator
Similarly, the nodes in the second stage “P”, “Q”, and “Y ”
are grounded through the transistors M13 , M14 , and M18 , We deploy a PV compensated clock oscillator [33] with
respectively. This avoids the nonlinear behavior of the input variable frequencies. The oscillator drives the ADC and gen-
capacitance presented by the second stage to the D P , and D N erates the stable clock phases (Fig. 10), which is used to
nodes. program the f LP of the AFE by tuning the cutoff frequency of
When the “Clk” signal is high, the normal operation of the G m -C LPF.
the comparator begins. In this phase, the difference between
the “Outp” and “Outn” voltages increases and the common- V. E XPERIMENTAL R ESULTS
mode voltage at D P and D N decreases. As the common-mode The chip is implemented in a 1P6M 0.18-μm CMOS
voltage at D P and D N approaches the threshold voltage of process. Fig. 17 shows the chip microphotograph with
the transistors M7,8 , the positive feedback amplification in the the annotated blocks. The active area of the entire chip
second stage is activated. This positive feedback along with is 0.15 mm2 . The AFE occupies only 0.0228 mm2 of silicon
the output inverters provides a rail-to-rail output signal. area and consumes 4.1-μA current from a 1.4-V regulator.
The entire 10-b SAR control logic uses only 14 flip flops
and operates at 1-V regulated supply that minimizes digital
power consumption. In order to reduce the leakage current of A. Analog Performance Measurement
the digital cells, several design techniques have been employed The measured frequency response of the LNA for various
that include the use of low-leakage high threshold voltage f HP frequencies is shown in Fig. 18. The mid-band gain
transistors, minimum transistor widths, increased transistor of the LNA is measured to be 37.9 dB (designed value
lengths, and the use of the stacked pair transistors [36]. Also, of 38 dB). This minute deviation in the gain is mainly due
the clock gating is used for the SAR logic to lower its dynamic to the finite OTA gain and the parasitic capacitance associated
power consumption. The ADC achieves a maximum sampling with the small feedback capacitor C f 1 . Fig. 19 depicts the
rate of 40 kS/s, while consuming only 306 nW from regulated measured frequency response of the biosensing amplifier,
supply and occupies 0.05 mm2 of silicon area. including PGA, for seven different gain settings. Fig. 20 shows
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BHAMRA et al.: NOISE-POWER-AREA OPTIMIZED BIOSENSING FRONT END FOR WBSN
Fig. 20. Measured IRN density of the LNA.
Fig. 21. Measured frequency response of the G m -C LPF with variable f LP .
Fig. 22. Measured DNL and INL of SAR ADC.
the measured input-referred noise spectral density of the
amplifier, which is obtained by dividing the output noise
spectrum by the mid-band gain. The total input-referred noise
of 2.98 μVrms is calculated by integrating the area under
the measured curve from 1 Hz–4.5 kHz, which results in the
NEF/PEF of 2.6/9.46. Fig. 21 shows the measured ac response
of the G m -C LPF with the programmable f LP. The THD of the
LPF is measured to be < −56.5 dB with a 500-mVPP input
sine wave.
To measure the ADC linearity, the histogram test was
performed with a 111.38-Hz, 1-VPP full-swing differential
sinusoidal input. The measured peak differential nonlinearity
and integral nonlinearity errors are +0.56/−0.69 LSB and
+1.14/−0.7 LSB, respectively (Fig. 22). A tone test was
performed to measure the dynamic performance of the ADC.
The output spectrum at 40 kS/s for the near-Nyquist (19.5 kHz)
operation is depicted in Fig. 23. The signal-to-noise-and-
distortion ratio at near-Nyquist sinusoid was measured to
be 56.1 dB resulting in effective-number-of-bits (ENOB) of
9.02 b. The figure-of-merit (FoM = P/2ENOB · f S ) was 14.3-
fJ/conversion step.
Table I presents the measured performance summary of
the chip. Table II compares the AFE with recently published
capacitively coupled AFEs. Thanks to the noise-power-area
9
Fig. 23. Measured 16 384-point fast Fourier transform spectrum at Nyquist.
TABLE I
M EASURED P ERFORMANCE S UMMARY
optimization methodology, this paper achieves lower NEF
and PEF and occupies smaller area than previously published
capacitively coupled biosensing front ends.
We also performed thorough process, voltage, and temper-
ature (PVT) and mismatch simulations to ensure the design
reliability. The Monte Carlo process and mismatch simulation
(500 runs) reveals the standard deviation of 1.76% in the FC
OTA bias current. Table III depicts the PVT simulation results
for the various design parameters.
B. In Vivo Experiments and Biopotential Signal Acquisition
The performance of the AFE was evaluated in a series
of in vivo rodent and ex vivo human experiments to eval-
uate the performance and versatility of the AFE in mea-
suring biopotentials that can serve as feedback or control
signals in bioelectronics [37]. The Purdue Animal Care and
Use Committee approved all experimental procedures. In the
first experiment, we implanted a custom-made, two-channel
Pt10Ir foil cuff electrode (cuff dimensions: 0.38-mm ID;
0.9-mm OD; 4-mm length; 2-mm electrode separation;
0.4-mm electrode width; 25-μm electrode thickness) around
the ventral gastric branch of the left vagal nerve in a female
Long-Evans rat to determine whether the AFE can measure
high-fidelity nerve fiber activity passing between the stomach
and central nervous system. The AFE was configured with
the gain of 72 dB, while f HP and f LP were set at 300 Hz and
5 kHz, respectively. The AFE ground reference was connected
to a lid speculum that was used to retract the abdominal tissue
in order to gain access to the target nerve. The electroneu-
rogram (ENG) was recorded, showing the individual activity
of dozens of neurons mediating the motor (efferent) and
sensory (afferent) functions of the ventral stomach (Fig. 24).
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10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE II
P ERFORMANCE C OMPARISON W ITH C APACITIVELY C OUPLED B IOSENSING F RONT E NDS

TABLE III
PVT S IMULATION R ESULTS

Fig. 25. Surface EMG recorded from Flexor carpi radialis muscle.

Fig. 26. ECG signal recorded from an anesthetized laboratory rat.

was place on the wrist and connected to the system ground.

Fig. 24. Experimental setup and raw ENG data recorded from the ventral
gastric branch of the left vagal nerve in a female Long-Evans rat.
In the second experiment, the EMG signal is recorded from
the Flexor carpi radialis—a human forearm muscle, while flex-
ing the wrist in a natural way. Two standard Ag/AgCl surface
electrodes were placed on the Flexor carpi radialis muscle of a
healthy human subject and connected to the differential inputs
of the AFE. The separation between these two electrodes was
approximately 2 cm. The third electrode (reference electrode)
The gain and bandwidth of the AFE were set at 48 dB and
20 Hz–1 kHz, respectively. The subject was asked to slowly
flex the wrist toward the forearm and then move it back to the
natural resting position. The surface EMG for this motion is
recorded at a sampling rate of 4 kHz, and the result is depicted
in Fig. 25.
Finally, the ECG of an anesthetized rat was recorded
with our chip. This experiment also utilized three standard
Ag/AgCl electrodes. Two electrodes were connected to the
AFE inputs, and the third electrode was connected to the
system’s ground while acting as a right leg drive. The AFE
was configured with the gain and bandwidth of 48 dB and
0.5–400 Hz, respectively. The recorded ECG signal is shown
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHAMRA et al.: NOISE-POWER-AREA OPTIMIZED BIOSENSING FRONT END FOR WBSN
in Fig. 26. We used the isoflurane gas for inhalation anesthesia,
which greatly attenuated the T-wave amplitude in the ECG
recording, as can be seen in Fig. 26 [38].
The recorded data, in each biological experiment shown in
this section, was normalized with the respective AFE gain.
VI. C ONCLUSION
Next-generation battery-less WBSNs and implantable
devices in a WBAN require a reconfigurable AFE that can
be used in multiple biosensing applications. In this paper,
we proposed a design and optimization methodology for
the capacitively coupled AFE, based on the mathematical
analysis of a number of design parameter tradeoffs. Each
individual block of the AFE is analyzed separately and then
optimized in the system to maximize these design tradeoffs.
The design methodology of our reconfigurable AFE is verified
by implementing a chip in a 0.18-μm CMOS process that also
includes a 10-b SAR ADC, a PMU, and a clock oscillator.
Finally, the chip functionality is verified in a number of in vivo
rodent and ex vivo human biological experiments.
ACKNOWLEDGMENT
The authors would like to thank J.-W. Tsai and Y.-W. Huang
for their support in the chip measurements.
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Hansraj Bhamra (S’13–M’16) received the B.E.
(Hons.) degree in electronics and communication
engineering from Pt. Ravishankar Shukla University,
Raipur, India, in 2004, the M.Tech. degree in RF
design and technology from IIT Delhi, New Delhi,
India, in 2006, and the Ph.D. degree in electrical and
computer engineering from Purdue University, West
Lafayette, IN, USA, in 2016.
From 2006 to 2010, he was a Senior Analog/Mixed
Signal Design Engineer with Conexant Systems,
Hyderabad, India. In 2012, he interned at Intel
Corporation, Hillsboro, OR, USA. He was an Analog/Mixed Signal Design
Intern at Broadcom Corporation, San Jose, CA, USA, in 2015, where he was
involved in the next-generation analog front-end design for the touch system.
He is currently an Analog/Mixed Signal IC Design Engineer with Apple
Inc, Melbourne, FL, USA. His current research interests include low-power
analog/mixed-signal and RF IC design for biomedical devices and wireless
sensor nodes.
John Lynch received the B.S. degree in electrical
engineering from Purdue University, West Lafayette,
IN, USA, in 1982, and the M.S. degree in electrical
engineering from National Technological University,
Fort Collins, CO, USA, in 1989. He is currently
pursuing the Ph.D. degree in electrical engineering
with Purdue University.
He was involved in consumer products at
Kodak, Rochester, NY, USA, mixed-signal design at
Cadence and LSI, Rochester, and touch and display
systems at National Semiconductor and Synaptics,
Rochester.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Matthew Ward received the B.S. degree in bio-
medical engineering and the Ph.D. degree in neural
engineering from Purdue University, West Lafayette,
IN, USA.
He is currently a Research Assistant Professor of
Biomedical Engineering with Purdue University, and
an Adjunct Assistant Professor of Medicine with the
Indiana University School of Medicine, Indianapolis,
IN, USA. He develops and translates technologies
that enable persistent, bidirectional communication
with the peripheral and central nervous system.
He has over a decade of training and experience in bioelectronic medicine,
signal processing, neurophysiology, and artificial intelligence in medical
devices. He currently develops adaptive, multifunctional brain–computer inter-
face technology to seamlessly connect patients to medical devices that treat
gastroparesis, depression, incontinence, and other conditions.
Pedro Irazoqui (M’95–SM’13) received the B.Sc.
and M.Sc. degrees in electrical engineering from
the University of New Hampshire, Durham, NH,
USA, in 1997 and 1999, respectively, and the Ph.D.
degree in neuroengineering from the University of
California, Los Angeles, CA, USA, in 2003, with
a focus on the design, manufacture, and packaging
of implantable integrated-circuits for wireless neural
recording.
He is currently the Director of the Purdue’s Center
for Implantable Devices, an Associate Head for
research, and a Professor with the Weldon School of Biomedical Engineering
and the School of Electrical and Computer Engineering, Purdue University,
West Lafayette, IN, USA.
Dr. Irazoqui has named as a Showalter Faculty Scholar and the Purdue
University Faculty Scholar, both in 2013. He received the Best Teacher
Award from the Weldon School of Biomedical Engineering in 2006 and 2009,
the Early Career Award from the Wallace H. Coulter Foundation in 2007 and
Phase II in 2009, the Marion B. Scott Excellence in Teaching Award from
Tau Beta Pi in 2008, the Outstanding Faculty Member Award from the
Weldon School of Biomedical Engineering in 2009, and the Excellence
in Research Award from Purdue in 2010, 2012, and 2013. He has been
serving as an Associate Editor of the IEEE T RANSACTIONS ON B IOMEDICAL
E NGINEERING since 2006.