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CAD OF ELECTRONICS LAB

LAB CONDUCT
AND
INSTRUCTIONS MANNUAL

SYLLABUS W.E.F. : 2016-17


SUBJECT CODE : NEC-653
YEAR : THIRD
SEMESTER : VI

DEPARTMENT OF ELECTRONICS &


COMMUNICATION ENGINEERING
BBD NATIONAL INSTITUTE OF TECHNOLOGY AND MANAGEMENT,
LUCKNOW-226028
TABLE OF CONTENTS
Exp. No Description Pages
--- List of experiments as per AKTU syllabus i
--- List of selected experiments from AKTU syllabus ii
Transient analysis and simulation of CMOS inverter.
1 1-3

Transient analysis and simulation of NAND gate.


2 4-6

Transient analysis and simulation of CMOS NOR gate.


3 7-8

Transient analysis and simulation of NMOS inverter.


4 9-10

Transient analysis and simulation of BJT inverter.


5 11-12

Design of 4:1 MUX using “with” statement.


6 13-14

7 Design of 4:1 MUX using “when” statement. 15-16


Design of 4:1 MUX using “case” statement.
8 17-18

Design of D flip-flop with “rest using VHDL”.


9 19-20

Design of full adder using half adders using for structural


10 modeling. 21-22

Design of 4-bit ripple carry adder using full adder as a


component for structural modeling.
11 23-24
List of experiments as per AKTU syllabus
PSPICE Experiments

1. (a)Transient Analysis of BJT inverter using step input.

(b)DC Analysis (VTC) of BJT inverter with and without parameters.

2. (a)Transient Analysis of NMOS inverter using step input.

(b)Transient Analysis of NMOS inverter using pulse input.

(c)DC Analysis (VTC) of NMOS inverter with and without parameters.

3. (a) Analysis of CMOS inverter using step input.

(b)Transient Analysis of CMOS inverter using step input with parameters.

(c)Transient Analysis of CMOS inverter using pulse input.

(d)Transient Analysis of CMOS inverter using pulse input with parameters.

(e)DC Analysis (VTC) of CMOS inverter with and without parameters.

4. Transient & DC Analysis of NOR Gate inverter.

5. Transient & DC Analysis of NAND Gate.

6. VHDL Experiments

a. Synthesis and simulation of Full Adder.

b. Synthesis and Simulation of Full Subtractor.

c. Synthesis and Simulation of 3 X 8 Decoder.

d. Synthesis and Simulation of 8 X 1 Multiplexer.

e. Synthesis and Simulation of 9 bit odd parity generator.

f. Synthesis and Simulation of Flip Flop (D, and T).

i
List of selected experiments from AKTU syllabus
1. Transient analysis and simulation of CMOS inverter.
2. Transient analysis and simulation of NAND gate.
3. Transient analysis and simulation of CMOS NOR gate.
4. Transient analysis and simulation of NMOS inverter.
5. Transient analysis and simulation of BJT inverter.
6. Design of 4:1 MUX using “with” statement.
7. Design of 4:1 MUX using “when” statement.
8. Design of 4:1 MUX using “case” statement.
9. Design of D flip-flop with “rest using VHDL”.
10. Design of full adder using half adders using for structural modeling.
11. Design of 4-bit ripple carry adder using full adder as a component for structural
modeling.

ii
Experiment-1

Object: Transient analysis and simulation of CMOS inveter

Software Used: Orcad Family Release 9.2.

Theory: CMOS inverters are the some of the most widely used and adaptable MOSFET
inverters used in chip design. They operate with very little power loss and at relatively high
speed,

A CMOS inverter contains a PMOS and a NMOS transiter connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, where Vin is connected to the date terminals and V OUT is connected to
the drain terninals.

The circuit below is the simplest CMOS logic gate

 When a low voltage (0 volt) is applied at the input , the top transistor (P- Type) is
conducting (switch closed) while the bottom transistor behaves like an open circuit.
 Therefore, the supply voltage(5V) appears at the output.
 Conversly when high voltage(5V) is applied at the input, the bottom transistor (N-Type)
is conducting (switch close) while the top transistor behaves like an open circuit.
 Hence output voltage is low(0V)
 The function of this gate can be summrized by the following table.

Input OutPut
High Low
Low High

 The ouput is the opposite of the input- this gate inverts the inputs.
 Notice that always one of the transistors will be an open circuit and no current flows from
the supply voltage to ground.

(1)
Transistor Switch Model

The switch model of of the mosfet transistor is defined as follows.

MOSFET Condition MOSFET State of MOSFET


NMOS Vgs < Vtn OFF
NMOS Vgs > Vtn ON
PMOS Vgs < Vtn OFF
PMOS Vgs > Vtn ON

When Vin is low, the NMOS is “off”, while the PMOS stays on “ON”: Instantly charging
Vout to logic high. When Vin is high , the NMOS is “on” and the PMOS is “ON”: draining
the volatage at Vout to logic low.

Procedure-

1.Open the blank project in orcade family release 9.2.


2.Include library;-ANALOG,BIPOLAR,PWRMOS,SOURCE,TRANSISTOR
3.Draw the circuit.
4.Go to Pspice and open new simulation profille
5.Perform transient analysis.
6.Create net list and then go to run.
7.Then we obtain final waveform.

Net List Description

M_M1 N000032 N00112 0 0 M2N6755

M_M2 N000032 N00112 N00165 N00165 IRF9520

V_V1 N00165 0 5Vdc

V_V2 N00112 0 +PULSE 0v 5v 0 0 0 50ns 100ns

(2)
M2 5.000V V1
5Vdc
IRF9520

V1 = 0v 0VM1
V2
V2 = 5v 0
V V
TD = 0
TR = 0 M2N6755
TF = 0
PW = 50ns 0 0
PER = 100ns

OUTPUT Waveform

(3)
Experiment-2

Object-Transient and simulation analysis of NAND gate.

Software used: Orcad Family Release 9.2.

Theory-

 The circuit below has two inputs and one output.


 Whenever at least one of the inputs is low ,the corresponding P –type transistor will be
conducting while the N-type transistor will be closed.
 Consequently ,the output voltage will be high .Conversely ,if both inputs are high ,then
both P-type transistors at the top will be open circuits and both N-type transistors will be
conducting.
 Hence, the output voltage is low.
 The function of this gate can be summarised by the following table:

V1 V2 Output
Low Low High
Low High High
High Low High
High High Low

 If logical 1’s are associated with high voltages then the function of this gate is called
NAND for negated AND.
 Again ,there is never conducting path from the supply voltage to ground.

(4)
Circuit Diagram

M4
5.000V
IRF9520 IRF9520
M3 V1
5Vdc

V1 = 0v V2 M1 5.000V 5.000V
V2 = 5v 0
V M2
V
TD = 0 0V
TR = 0 M2N6755 M2N6755V V3
TF = 0
PW = 50ns 0 TD = 0
PER = 100ns TF = 0
0PW = 50ns
PER = 100ns
0 V1 = 5v
TR = 0
V2 = 0v

NETLIST DESCRIPTION:

M_M1 N00222 N00328 N000030 N000030 M2N6755


M_M2 N000030 N00362 0 0 M2N6755
V_V3 N00362 0
+PULSE 5v 0v 0 0 0 50ns 100ns
M_M3 N00222 N00328 N00191 N00191 IRF9520
M_M4 N00222 N00362 N00191 N00191 IRF9520
V_V1 N00191 0 5Vdc
V_V2 N00328 0
+PULSE 0v 5v 0 0 0 50ns 100ns

(5)
Output Waveform
Experiment-3

Object:-Transient and simulation analysis of CMOS NOR gate.

Software Used: Orcad Family Realease 9.2

Theory:-

 The circuit below has two inputs and one ouput .


 Whenever at least one of the inputs is high ,the corresponding N-type transistor will be
closed the P-type transistor will be open.
 Consequently, the output voltage will be low .
 Conversely ,if both inputs are low ,then both P-type transistors at the top willl be closed
circuits and the N-type transistors will be open.
 Hence ,the output voltage is high.
 The function of this gate can be summarised by the following table:

V1 V2 OUTPUT
Low Low High
Low High Low
High Low Low
High High Low

 If logical 1’s are asssociated with high voltages then the function of this gate is
called NOR for negated OR.
 Again, there is never a conducting path from the supply voltage to ground.

Circuit Diagram

(7)
M3 5.000V V1
M4 5Vdc
IRF9241
IRF9241
0V
0
M2
V1 = 0v V2
V2 = 5v V M2N6755
5.000V
TD = 0 M1 1.734uV
TR = 0 V
TF = 0 V
V3
PW = 50ns 0 M2N6755
PER = 100ns 0V TD = 0
TF = 0
0 0PW = 50ns
PER = 100ns
V1 = 5v
TR = 0
V2 = 0v

NETLIST DESCRIPTION:
M_M1 N00413 N00536 0 0 M2N6755
M_M2 N00413 N00570 0 0 M2N6755
M_M3 N000552 N00536 N00626 N00626 IRF9241
M_M4 N00413 N00570 N000552 N000552 IRF9241
V_V1 N00626 0 5Vdc
V_V2 N00536 0
+PULSE 0v 5v 0 0 0 50ns 100ns
V_V3 N00570 0
+PULSE 5v 0v 0 0 0 50ns 100ns
Output Waveform
Experiment-4

Object :-Transient analysis and simulation of NMOS inverter.

Software Used:-Oracad Family Release 9.2.

Theory :-

Single Transistor, pulls Signal Low

Inverter Operation:

 Plus signal input turns transistor on.


 Ground is connected to output.
 A 0 input opens transistor and output is pulled high by resistor.
 Resistor dissipates heat.
 Asymmetric rise/fall times.

INPUT OUTPUT
A NOT A
0 1
1 0

(9)
M1 5. 000V V1
5Vdc
M2N 6755

4. 513V 0

M2
V
V1 = 0v V2
V2 = 5v M2N 6755 V
TD = 0
TR = 0 0
TF = 0
PW = 50ns 0
PER = 100ns

Netlist Description:

M_M1 N00111 N00111 N00203

R_R1 N00203 M2N6755

V_V2 N000291 0

+PULSE 0v 5v 0 0 0 50ns 100ns

M_M2 N00111 N000291 0 0 M2N6755

V_V1 N00203 0 5Vdc

Output Waveform
Experiment-5

Object-Transient analysis and simulation of BJT inverter.

Software used-Orcad Family Release9.2.

Theory-

The voltage transfer characteristic of a BJT inverter is consisting of threeregions,the cut off when
Vi is low, the active where the characteristic has a slope and the saturation region where the
collector current is the maximum and the output voltage is low equal to VCEsat.

1. Cut-off region.

2. Forward Active region.

3. Saturation region.

BJT Inverter can be best expressed by its voltage transfer characteristic (VTC) or DC transfer
characteristic. That relates the output voltage to the input one.

If:

1. Vi=Vol, Vo=Vcc: (VTC) or DC Transfer Characteristic The transistor is OFF.

2. Vi=Vil: The transistor begins to turn on.

3. Vi<Vil<Vih The transistor is in forward active region and operates as amplifier.

4. Vi=Voh The transistor will be deep is saturation,Vo=Vce(sat).

(11)
Circuit Diagram:

5.000V V1
R2 5Vdc
1k
Q1 Rbreak
R1
0
V
V1 = 0v V2 Rbreak
V2 = 5v 40238
V
TD = 0 1k
TR = 0 0
TF = 0
PW = 50ns 0
PER = 100ns

NETLIST DESCRIPTION:

Q_Q1 N000031 N000030 0 Q40238

V_V2 N000431 0

+PULSE 0v 5v 0 0 0 50ns 100ns

R_R1 N000431 N000030 R break 1k

R_R2 N00231 N000031 Rbreak 1k

V_V1 N00231 0 5Vdc

Output Wave Form


Experiment-6

Object:Design of 4:1 multiplexer using “with” statement.

Program:

*design of 4:1 multiplexer using “with” statement*

library ieee;

use ieee.std_logic_1164.all;

entity mux4_1 is

port (i0, i1, i2, i3: in std_logic;

s: in std_logic_vector(1 downto 0);

y: out std_logic);

end mux4_1;

architecture mux_with of mux4_1 is

signal s: std_logic_vector(1 downto 0);

begin

s <= s1 & s0;

with s select

y <= i0 when s = "00";

i1 when s = "01";

i2 when s = "10";

i3 when s = "11";

'x' when others;

end mux_with;

(13)
Representaion:
Experiment-7

Object: Design 4:1 mux using with statement.

Program:

*design 4:1 mux using when statement.*

library ieee;

use ieee.std_logic_1164.all;

entity mux4_1 is

port (i0, i1, i2, i3: in std_logic;

s: in std_logic_vector(1 downto 0);

y: out std_logic);

end mux4_1;

architecture when_mux of mux4_1 is

begin

y <= i0 when (s1 & s0) = "00" else;

i1 when (s1 & s0) = "01" else;

i2 when (s1 & s0) = "10" else;

i3 when (s1 & s0) = "11" else;

'x';

end when_mux;

(15)
Representation:

(16)
Experiment-8

Object: Design 4:1 mux using “case” statement.

Program:

*design 4:1 mux using case statement*.

library ieee;

use ieee.std_logic_1164.all;

entity mux4_1 is

port (i0, i1, i2, i3: in std_logic;

s: in std_logic_vector(1 downto 0);

y: out std_logic);

end mux4_1;

architecture case_mux of mux4_1 is

begin

process(s0, s1, i0, i1, i2, i3)

variable sel: std_logic_vector(1 downto 0);

begin

sel:= s1 & s0;

case sel is

when "00" => y <= i0;

when "01" => y <= i1;

when "10" => y <= i2;

when "11" => y <= i3;

when others => y <= 'x';

(17)
end case;

end process;

end case_mux;

Represtation:

(18)
Experiment-9

Object: Design d flip-flop with reset using vhdl.

Program:

*design d flip-flop with reset using vhdl*.

library ieee;

use ieee.std_logic_1164.all;

entity dff is

port(d, clk, reset, set: in std_logic;

q: out std_logic);

end dff;

architecture dff_res of dff is

begin

process(clk)

begin

if clk'event and clk='1' then

if reset='1' then

q <= '0';

elsif set='1' then

q <= '1';

else

q <= 'd';

end if;

end if:

(19)
end process;

end dff_res;

Representation:
Experiment-10

Object: Design full adder using half adder for structural modelling.

Program:

*design full adder using half adder for structural modelling*.

library ieee;

use ieee.std_logic_1164.all;

entity fa is

port(a, b, cin: in std_logic;

s, cout: out std_logic);

end fa;

architecture fa_struct of fa is

component ha

port(a, b: in std_logic;

s, c: out std_logic);

end component;

component or

port(a, b: in std_logic;

y: out std_logic);

end component;

signal i1, i2, i3: std_logic;

begin

ha1: ha port map(a, b, i2, i1);

(21)
ha2: ha port map(i2, cin, s, i3);

or1: or port map(i1, i3, cout);

end fa_struct;

Circuit Diagram:
Experiment-11

Object:Design of 4-bit ripple carry adder using full adder as a component for structural
modelling

Program:

*design of 4-bit ripple carry adder using full adder as a component for structural
modelling*.

library ieee;

use ieee.std_logic_1164.all;

entity rca_4-bit is

port(a, b: in std_logic_vector(3 downto 0);

cin: in std_logic;

s: out std_logic_vector(3 downto 0);

cout: out std_logic);

end rca_4-bit;

architecture rca_4-bit_struct of rca_4-bit is

signal c: std_logic_vector(2 downto 0);

component fa is

port(a, b, cin: in std_logic;

s, cout: out std_logic);

end component;

begin

fa1: fa port map(a(0), b(0), cin, s(0), c(0));

fa2: fa port map(a(1), b(1), c(0), s(1), c(1));

(23)
fa3: fa port map(a(2), b(2), c(1), s(2), c(2));

fa4: fa port map(a(3), b(3), c(2), s(3), cout);

end rca_4-bit_struct;

Representation:

(24)