This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2939562, IEEE Journal
of Emerging and Selected Topics in Power Electronics
Novel K-Type Multilevel Inverter with Reduced
Components and Self-Balance
Jun Zeng, Member, IEEE, Weijie Lin, Dehai Cen, and Liu Junfeng
Abstract— This paper proposed a single-source multilevel
inverter (MLI) based on the novel K-type unit (KTU). The 13-level
topology with two KTUs and 1.5 voltage gain is firstly introduced
and its operation modes at different output levels are described in
the paper. The two capacitors in series connection of each KTU
can get self-voltage balance due to their symmetric operation in a
cycle, reducing the complexity of control compared with
conventional MLIs. The analysis of self-balance and capacitance
calculation are given in detail. Afterward, the single-source
generalized structure equipped with more KTUs is presented for
increasing output levels. The output levels are significantly
increased with additional KTUs, and the voltage gain rises as well.
Moreover, through the comparative study against other MLI
topologies proposed in recent years, the advantages of the
proposed KTU topology are indicated in the aspects for reduced
components, self-balance, voltage stress, and overall cost. Finally,
the 13-level simulation and 1kVA experimental prototype with
fundamental frequency modulation are implemented to verify the
feasibility and transient performance of the proposed topology.
Index Terms—Multilevel, self-balance, voltage gain, reduced
components.
I. INTRODUCTION
Multilevel inverter (MLI) has attained promising attention,
and various MLIs were presented for industrial application,
power distribution field, transportation, renewable energy
generation (REG) system, and electric vehicle (EV) [1]-[4].
Compared with the traditional two-level inverter, MLI has the
benefits of decreased harmonic content, reduced voltage stress,
lower switching frequency and loss, improved electromagnetic
interference (EMI), and so on [5], [6]. There are mainly three
types of conventional MLIs: neutral point clamped (NPC),
flying capacitor (FC), and cascaded H-bridge (CHB) topologies
[7]-[9]. NPC and FC topologies suffer the drawbacks of voltage
unbalance of capacitors, and require numerous active and
Manuscript received; revised; accepted. Date of publication; date of current
version.
This work was supported in part by the National Natural Science Foundation
of China under Grants 61573155&51877085, in part by Guangdong Natural
Science Foundation No.2016A03031358, 2018A030313066, and in part by the
Fundamental Research Funds for the Central University of SCUT(No.
2018ZD50). (Corresponding author: Junfeng Liu).
J. Zeng is with the New Energy Research Center, South China University of
Technology, Guangzhou 510640, China (e-mail: junzeng@scut. edu.cn).
W. Lin and D. Cen are with the School of Electric Power, South China
University of Technology, Guangzhou 510640, China (e-mail:
a437654784@qq.com; 1035119050@qq.com).
J. Liu is with the School of Automation Science and Engineering, South
China University of Technology, Guangzhou 510640, China (e-mail: jf.liu@
connect.polyu.hk).
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1
passive devices, especially when the output level increases over
seven [10]. On the other hand, CHB topology extends its output
level through cascading additional H-bridge modules. The
optimal output level can be synthesized with asymmetrical
independent dc sources having specific magnitudes [11].
However, the demand for extra independent sources in H-
bridge modules leads to many difficulties in design.
Consequently, the efforts of developing MLIs have been
making towards two aspects: voltage balance and reduced
devices, especially the independent sources.
The derived topologies based on NPC and FC structures are
proposed to improve the mentioned defects. The modified FC
topologies with increased output levels are introduced in [12]
and [13], and the capacitors’ voltages can maintain balance with
the specific modulation. Moreover, the active-neutral-point-
clamped (ANPC) converters, which combine the flexibility of
FC and NPC to produce multilevel output, have been proposed
for medium or high voltage applications [14]-[16]. The voltage
and current sensors are essential for these ANPC converters and
help capacitors keep voltage balance with well dynamical
response, whereas bringing in higher complexity of design and
control. The similar method of voltage balance with sensors
can be also found in the seven-level inverters proposed in [17]
and [18], respectively. To reduce the complexity of control, the
self-balance unit with one capacitor is adopted in [19] and [20].
The capacitor’ voltage maintains at half of the input dc source
without sensors, facilitating a reduction of overall design cost.
However, extra symmetric isolated dc sources are needed.
On the other side, the cascaded MLIs integrating
symmetric/asymmetric dc sources are presented, and the
considerable output levels can be obtained with selected
magnitude of dc sources. It is evident that increased output level
achieves lower total harmonic distortion (THD), thus the
requirements for switching frequency and output filter can be
lower. The EMI caused by dv/dt of the adjacent output levels is
reduced meanwhile. Hereby, the square T-Type (STT) module
integrating four dc sources is presented in [21]. More than 17
output levels can be realized with one STT module. The THD
of its output voltage without LC filters is lower than 5%,
satisfying the standard of IEEE519 (i.e., max. of THD%<8%).
Its calculated efficiency at 5kW output is higher than 96.5% due
to the use of fundamental frequency modulation (FFM). Hence,
a relatively high number of output levels cooperating with FFM
is recommended for the similar MLIs [22]. The EMI and THD
are greatly improved with increased output levels; the
efficiency has been also guaranteed due to the low switching
frequency of FFM. Additionally, two types of switched-source
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2939562, IEEE Journal
of Emerging and Selected Topics in Power Electronics
2

MLIs are proposed as the substitution for CHB topology [22],
[23], aiming to generate multilevel output with fewer switches.
Typically, the transistor-clamped H-bridge (THB) is introduced
in [24]. The voltages of two capacitors in dc link can naturally
maintain at half of the input due to their symmetric operation in
positive and negative half cycles, and five-level output can be
realized. The THB units fed with asymmetric isolated dc
sources are further suggested to operate in series connection for
a higher number of output levels. The maximum line voltage
level in experiment reaches 41-level with two asymmetrical
cascaded THB units. And the measured THD of line voltage is
as low as 1.2% without any filters.
Furthermore, the switched-capacitor multilevel inverter
(SCMLI) has become a competitive issue due to its self-voltage
balance and expansibility of output level. The basic multilevel
modules based on switched capacitor have been presented for
cascaded applications [25], [26], where the series-parallel
technique is used for the self-balance of the capacitor. The five-
level module in [25] has twofold boost factor, while the seven-
level module in [26] has 1.5 voltage gain. A quasi-resonant
switched-capacitor multilevel is proposed for high-frequency
ac microgrids (HFAC) [27]. Its output level can be extended
with single dc source. However, it is incapable of boost ability.
The SCMLIs consisting of multiple switched-capacitor units
are introduced in [28]-[30]. Their output levels and boost factor
can be increased with additional switched-capacitor units. But
their highest voltage stress among the switches increases to a
high degree meanwhile. Hence, another self-balance step-up
SCMLI is proposed to improve this drawback [31]. Its highest
voltage stress keeps low, while numerous switches are required.
KTU(1) KTU(2)
S1a S1c S2a S2c
C1a C2a
b T1a T2a T2b
2Vdc
T1b
C1b C2b
S1b S1d S2b S2d
Fig. 1. The proposed 13-level inverter with two KTUs.
S1a S1c S2a S2c
Motivated by the aforementioned issues of voltage balance,
device count, single dc source and boost ability, this paper
presents the step-up multilevel inverter based on K-type unit
(KTU) with single source and self-balance ability. The
considerable number of output level and its less complexity for
voltage balance meet the requirements for the applications like
ac distribution system, EV, and REG. A 13-level topology
based on two KTUs is firstly introduced in Section II. Its
operation modes at different levels, the modulation method, and
the deduction of the self-balance of capacitors are illustrated in
detail as well. In Section III, the capacitance calculation and
losses analysis for the proposed 13-level topology are given.
Section IV presents the generalized step-up structure based on
KTU with single source and extended output levels. The
comparative study against other MLIs demonstrates its merits
on reduced devices, voltage stress, and overall cost. The self-
balance, transient response performance, boost, and inductive-
load ability are also validated in simulation and experiment in
Section V. Consequently, the conclusions have been drawn.
II. THE PROPOSED 13-LEVEL TOPOLOGY WITH TWO KTUS
A. Operation Principles of the Proposed 13-Level Topology
The proposed 13-level basic topology is shown as Fig. 1. It
consists of two K-type units and every KTU includes an H-
bridge. The clamping transistor T1a or T1b without anti-parallel
diode in KTU(1) can be also achieved by the transistor in series
with a diode or the back-to-back connected transistor (see Fig.
1). Their connection resembles a “K”, thus the proposed
topology is named as “K-type”. KTU(2) actually works as the
transistor-clamped H bridge, and for a convenient description
of the generalized structure in Section IV, it is named as the
second unit here. The single input source 2Vdc is connected to
a
the series capacitor C1a /C1b, and the multilevel output is
obtained from vab. The voltages of C1a and C1b naturally
maintain at Vdc, and voltages of C2a and C2b maintain at 0.5Vdc.
The proposed 13-level inverter can achieve 1.5 voltage gain.
S1a S1c S2a S2c S1a S1c S2a S2c

C1a C2a C1a C2a C1a C2a

b T1a T2a T2b a b T1a T2a T2b a b T1a T2a T2b a
T1b T1b T1b
C1b C2b C1b C2b C1b C2b

S1b S1d S2b S2d S1b S1d S2b S2d S1b S1d S2b S2d
(a) vout= 0.5Vdc (b) vout= Vdc (c) vout= 1.5Vdc
S1a S1c S2a S2c S1a S1c S2a S2c S1a S1c S2a S2c

C1a C2a C1a C2a C1a C2a

b T1a T2a T2b a b T1a T2a T2b a b T1a T2a T2b a
T1b T1b T1b
C1b C2b C1b C2b C1b C2b

S1b S1d S2b S2d S1b S1d S2b S2d S1b S1d S2b S2d
(d) vout= 2Vdc (e) vout= 2.5Vdc (f) vout= 3Vdc
Fig. 2. The operation modes and current flowing paths of the proposed 13-level inverter in positive half cycle.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2939562, IEEE Journal
of Emerging and Selected Topics in Power Electronics
3

S1a S1c S2a S2c S1a S1c S2a S2c S1a S1c S2a S2c

C1a C2a C1a C2a C1a C2a

b T1a T2a T2b a b T1a T2a T2b a b T1a T2a T2b a
T1b T1b T1b
C1b C2b C1b C2b C1b C2b

S1b S1d S2b S2d S1b S1d S2b S2d S1b S1d S2b S2d
(a) vout= -0.5Vdc (b) vout= -Vdc (c) vout= -1.5Vdc
S1a S1c S2a S2c S1a S1c S2a S2c S1a S1c S2a S2c

C1a C2a C1a C2a C1a C2a

b T1a T2a T2b a b T1a T2a T2b a b T1a T2a T2b a
T1b T1b T1b
C1b C2b C1b C2b C1b C2b

S1b S1d S2b S2d S1b S1d S2b S2d S1b S1d S2b S2d
(d) vout= -2Vdc (e) vout= -2.5Vdc (f) vout= -3Vdc
Fig. 3. The operation modes and current flowing paths of the proposed 13-level inverter in negative half cycle.

TABLE I
THE SWITCHING STATES OF THE PROPOSED 13-LEVEL INVERTER AT EACH LEVEL
Output level 3 2.5 2 1.5 1 0.5 +0 -0 0.5 1 1.5 2 2.5 3
S1a 0 0 0 0 0 0 0 1 1 1 1 1 1 1
KTU(1) S1c 1 1 1 1 0 0 0 1 1 1 0 0 0 0
T1a 0 0 0 0 1 1 1 0 0 0 1 1 0 0
T1b 0 0 1 1 0 0 0 1 1 1 0 0 0 0
S2a 0 0 1 1 0 0 0 1 1 1 0 0 1 1
KTU(2) S2c 1 0 1 0 1 0 0 1 0 0 0 0 0 0
S2d 0 0 0 0 0 0 1 0 0 1 0 1 0 1
T2a/T2b 0 1 0 1 0 1 0 0 1 0 1 0 1 0
*1 or 0: the switch is ON or OFF, respectively.

The operation modes of the proposed 13-level inverter at

different output levels in positive half cycle are presented in Fig.
2, while those in negative half cycle are shown in Fig. 3. As
shown in Fig. 2 and Fig. 3, the peak output voltage is 3Vdc thus
the boost factor of 1.5 can be achieved. (S1a, S1b), (S1c, S1d) and
(S2a, S2b) are complementary switch pairs, reducing the
complexity of control. Hereby, the switching states of the
transistors are summarized in Table I.
B. The Fundamental Frequency Modulation for the Proposed
Topology
Due to the considerable output levels, the fundamental
frequency modulation (FFM) in [21] is adopted for the
proposed topology. The FFM has the advantages of reduced
switching loss and low complexity. Fig. 4 indicates the staircase
output with FFM, where the switching angle of each output
level can be determined by the intersection of the reference sine
wave and the midpoint of its two adjacent output levels.
Therefore, the switching angle θi of each output level in Fig. 4
can be expressed by the following equation (i = 0, 0.5, 1,…, 2.5,
and 3). Particularly, θo is equal to 0
i  0.25
 i  arcsin( ) , , , , , , 0   i  0.5
3 The derivation method for voltage balance of capacitor in [19]
Due to the symmetric output in Fig. 4, once the switching
angle of each output level is determined, the control signals can
be simply generated by the controller with look-up table method
based on Table I [21].
Fig. 4. The staircase output with fundamental frequency modulation (FFM).
And T‹i› in Fig. 4 represents the duration of level i in 1/4 cycle.
Obviously, due to the symmetric output, it can be calculated by
the following equation (2). Particularly, T‹3› = T‹-3› = (0.5π-
θ3)/(2πfo).
  i
T i  T  i  i  0.5 (2)
2 f o
where fo is the fundamental frequency of output.
Comparing Fig. 2 with Fig. 3, C1a and C1b (or C2a and C2b)
operate symmetrically in positive half cycle and negative half
cycle. Thus the self-balance can be naturally achieved.
C. Self-Balance Analysis of the Capacitors
(1)
is adopted in this part and the parasitic parameters of
components are neglected for simplification. The magnitude of
dc source is set as 2Vdc without fluctuation. From Fig.2 and Fig.
3, the deviation of neutral point (NP) voltage of the series

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2939562, IEEE Journal
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capacitor C1a /C1b occurs during level ±m (m= 0.5, 1, 1.5, and 2 III. CAPACITANCE CALCULATION AND LOSS ANALYSIS
here). Hence, four kinds of equivalent circuits can be
summarized as Fig. 5. The dc source, C1a and C1b are regarded A. Voltage Ripple and Capacitance Calculation
as an integrated input part, while C2a, C2b and output load RL are Due to the symmetric output, only the behaviors of capacitors
regarded as an integrated load part here. C1b and C2b in positive half cycle are taken into analysis. The
C1a C1a C1a C1a complete equivalent circuits corresponding to Fig. 2(a)-(f) at
Zeq Zeq Zeq’
inp1 inp1 different output levels in positive half cycle are shown as Fig.
inp1
C1b Zeq C1b Zeq Zeq’ C1b inp1 C1b 6. It is supposed C1a=C1b=C1 and C2a=C2b=C2 for the same
voltage ripple. Assuming the circuit has operated at steady state,
(a) (b) (c) (d) the voltage changing of capacitors occurs in two cases: during
Fig. 5. The generalized equivalent circuits for C1a and C1b at different output the continuous duration of each output level, or during the
levels. (a) Equivalent circuit for C1b at level 0.5 and level 1. (b) Equivalent switching moment of two adjacent output levels
circuit for C1b at level 1.5 and level -2. (c) Equivalent circuit for C1a at level -0.5 i2a
i1a i1a i1a
and level -1. (d) Equivalent circuit for C1b at level -1.5 and level 2. C2a iL
C1a C1a C1a
iL i2b
The neutral point current inp1 of the series capacitor C1a /C1b i1b C2a i2a i1b C2a i2a C2b
iL i1b RL
is taken into consideration. With respect to level ±0.5 and level C1b i2b C1b i2b RL C1b
±1, the C2a, C2b and RL are equivalent to an impedance Zeq‹±m› C2b RL C2b
shown in Fig.5 (a) and (c). As for level ±1.5 and level ±2, the (a) vout= 0.5Vdc (b) vout= Vdc (c) vout= 1.5Vdc
capacitors C2a, C2b and output load RL are equivalent to two i2b i2a
impedances Zeq‹±m› and Zeq’ ‹±m›, which are respectively i1a i2a iL i2b iL
C2a i1a C2b i1aC2b C2a iL
connected to the neutral point and source side in Fig.5 (b) and C1a C1a C1a
i2b
(d). Consequently, the average neutral point current inp1 at level C2b
RL RL RL
m of positive half cycle and at level –m of negative half cycle i1b i1b i1b
C1b C1b C1b
can be expressed respectively as:
v C1 b 2V dc  vC1 b
inp1 m  , , , inp1  m  (3) (d) vout= 2Vdc (e) vout= 2.5Vdc (f) vout= 3Vdc
Z m
Z m Fig. 6. The equivalents circuits for different output levels in positive half cycle.
Therefore, the corresponding net charge of neutral point in
positive cycle and negative half cycles are given as (4) and (5): 1) Firstly, the voltage fluctuation of C1b and C2b in the
T 0.5 T1 T 1.5 T2 continuous duration of each level can be derived as follows.
 Q   2(    ) v C1 b (4) During level 0.5, the equivalent circuit is depicted as Fig.6 (a).
Z 0.5 Z 1 Z 1.5 Z 2
According to the Kirchhoff’s circuit laws (KCL), the currents
T 0.5 T1 T 1.5 T2 of C2a and output load can be expressed as (7) and (8).
Q 
 2(    )(2V dc  vC1 b ) (5)
Z  0.5
Z 1
Z  1.5
Z 2 dv1 a dv d (2V dc  v1b ) dv
i2 a  C1  C 1 1b  C 1  C 1 1b
where T‹m› represents the duration of level m in 1/4 cycle in Fig. dt dt dt dt
(7)
4 (T‹m› =T‹-m›). Actually, C2a, C2b and RL are in the same dv1b
  2 C1   2 i1b
connected form at level m and level -m, thus Zeq‹m› is equal to dt
Zeq‹-m› according to Fig. 2 and Fig. 3. Thereby, the total net dv dv dv d ( v1b  v 2 a )
iL  C 2 2 a  C 2 2 b  C 2 2 a  C 2
charge delivered/ absorbed by the capacitors C1a and C1b in a dt dt dt dt
complete cycle is dv 2 a dv1b C2 (8)
 2C 2 C2  2 i2 a  i1b
Q  Q   Q  dt dt C1
T 0.5 T1 T 1.5 T2 (6) Combining formulas (7) and (8), the currents of C1b and C2b
 4(    )( vC1 b  V dc ) can be expressed by the load current at level 0.5.
Z 0.5 Z 1 Z 1.5 Z 2
 C1 C1 V dc
According to the ampere-second balance of the capacitor at  i1b   4 C  C iL   4 C  C  2 R
its steady state, ∆Q is considered to be 0 over a symmetric cycle.  1 2 1 2 L
 (9)
Therefore, the conclusion for vC1b = Vdc at steady state can be  i   2 C1  C 2 i   2 C1  C 2  V dc
obtained, and vC1a= 2Vdc-vC1b = Vdc. As a result, the voltages of  2 b 4 C1  C 2
L
4 C1  C 2 2 R L
capacitors C1a and C1b will naturally maintain at Vdc without Hence, the discharging quantity of C1b and C2b during the
auxiliary balance techniques. The above self-balance and duration T‹0.5› of level 0.5 can be calculated as (10)
relevant inference are valid for any power factor as the power  C1 V dc T 0.5
distribution ratio of inverter is independent of power factor (or  Q1b 0.5  
 4 C1  C 2 2 RL
impendence angle) [19], [20]. The same method can be applied  (10)
for C2a and C2b, and their voltages maintain at 0.5Vdc at steady  2 C1  C 2 V dc T 0.5

state.  Q 2 b 0.5  4 C  C  2 R
 1 2 L

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Similarly, the discharging quantity of C1b and C2b during voltage changes of capacitors are accomplished instantaneously,
other output levels can be summarized and given as (11) and and the impact of output load is neglected during the switching
(12) based on Fig.6, respectively: moment of level 1→1.5. Thus from Fig. 6(c), the net charges of
 C1 V dc T 0.5 capacitors in the switching moment satisfy:
 Q1b 0.5   ,,,,,,,,,,,,,,,,,,,,,,,,, Q1b 2  0
 Q 2 a / 2 b   Q1 a   Q1b  2  Q1 a  2  Q1b (16)
 4 C1  C 2 2 RL
 2 C1 V dc T 1 where the subscript “2a/2b” represents the series capacitor
 Q1b 1   ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Q1b 2.5  0 (11) C2a/C2b. Hence, the voltage changes of the capacitors in
 4 C1  C 2 RL
 C1 1.5V dc T 1.5 switching moment can be written as
 Q1b 1.5   ,,,,,,,,,,,,,,,,,,, Q1b 3  0
  Q1 a  C1  U 1 a 11.5  C1 (V1 a 1  V1 a 1.5  )
 4 C1  C 2 RL

 2 C 1  C 2 V dc T 0.5
 C2 C (17)
  Q 2 a /2 b   U 2 a /2 b 11.5  2 (V 2 a /2 b 1.5   V 2 a / 2 b 1 )
 Q 2 b 0.5   ,,,,,,,,,,,,,,,,, Q 2 b 2  0  2 2
 4 C1  C 2 2 RL
 C2 V dc T 1 2.5V dc T 2.5 where V1a‹1+› and V1a‹1.5-› represent the voltage of C1a at the end
 Q 2 b 1   ,,,,,,,,,,,,,,,,,,,,,, Q 2 b 2.5  (12) moment of level 1 and at the beginning moment of level 1.5,
 4 C1  C 2 RL RL
 1 .5V dc T 1.5 3V dc T 3 respectively; ∆U1a‹1→1.5› is the C1a voltage fluctuation in the
2 C1
 Q 2 b 1.5   ,,,,,,,,,,,, Q 2 b 3  switching moment of level 1→1.5, and so on.
 4 C1  C 2 RL RL
Combining formulas (16) and (17), and considering V1a‹1.5-›
Moreover, the voltage fluctuation and discharging/charging equal to V2a/2b‹1.5-›, the voltages of C1a at the beginning moment
quantity of a capacitor satisfy the following equation. of level 1.5 can be express as (18), and its voltage fluctuation
 Q  C  U (13) during the switching moment is (19)
Considering 50Hz output frequency, the duration T‹m› (m= 0.5, 4 C1V1 a 1  C 2V 2 a /2 b 1
1, 1.5, 2, 2.5, and 3 here) of each output level can be determined V1 a 1.5  V 2 a / 2 b 1.5  (18)
4 C1  C 2
from (2), and the voltage drop on capacitors in each duration
C2
can be further calculated through formula (11), (12), and (13)  U 1 a 11.5   U 1b 11.5  (V  V 2 a / 2 b 1 ) (19)
4 C1  C 2 1 a 1
 2.69410  4 V dc
 U 1b 0.5   ,,,,,,,,,,,,,,,,,,, U 1b 2  0 Formulas (18) and (19) are the general conclusions which can
 4 C1  C 2 RL
be also applied to the switching moment of level 2.5→2 or level
 11.27410  4 V dc
 U 1 b 1   ,,,,,,,,,,,,,,,,,,, U 1b 2.5  0 (14) 1.5→1 in declining stage. Particularly, V2a/2b‹1+› is equal to 2Vdc-
 4 C1  C 2 RL
V1a‹1+› at level 1 from Fig. 6(b). Substituting this condition into
 9 .21810  4 Vdc (18) gives:
 U 1b 1.5   ,,,,,,,,,,,,,,,,,,, U 1b 3  0
 4 C1  C 2 RL 4 C1  C 2 C 2  4 C1
V1 a 1.5  V 2 a / 2 b 1.5   V dc  (V1 a 1  V dc )  V dc
 C 4 C1  C 2
 (5.387 1  2.69 4)10  4 (20)
C2 V dc C 2  4 C1
 U 2 b 0.5   ,,,,,,, U 2 b 2  0 V1b 1.5  2V dc  V1 a 1.5  V dc
 4 C1  C 2 RL
 11.27410  4 V dc 24.7910  4 Vdc That is to say, the voltage of C1b (or the series capacitor
 U 2 b 1   ,,,,,,,, U 2 b 2.5   (15) C2a/C2b) decreases below Vdc during level 0.5 and level 1 in
 4 C1  C 2 RL C2 RL
 C1 raising stage, and then it is clamped to Vdc again after the
 18.4 10  4
C2 V 39.2610  4 V dc switching moment of level 1→1.5 if capacitance C2 is selected
 U 2 b 1.5   dc ,,,,,,, U 2 b 3  
C2 approaching to 4C1. The same situation can be also observed in
 4 C1 C 2 RL RL
the switching moment of level 1.5→1 of declining stage.
So far, the voltage drops on capacitors C1b and C2b in each
3) Finally, the maximum voltage ripples on C1b and C2b can
duration of different levels have been obtained.
be calculated. Based on the above analysis, the lowest voltage
2) Secondly, the voltage changing during the switching
of C1b occurs after the total duration of level 1 and 1.5, and the
moment of two adjacent output levels is considered. Take the
corresponding voltage drop compared with the reference value
switching moment from level 1 to level 1.5 (denoted by level
Vdc can be calculated based on (14):
1→1.5) for an instance. From Fig. 4, the operation of inverter
13.96810  4 Vdc
in positive half cycle has two stages: output raising from level  U 1b (drop)   U 1b 0.5   U 1b 1   (21)
4 C1  C 2 RL
+0 to level 3, and output declining from level 3 to level +0. As
shown in Fig. 6(a) and (b), the capacitor C1b is in parallel with On the other hand, the voltage of series capacitor C2a/C2b
the series capacitor C2a/C2b, and their voltages continuously decreases during level 2.5 and level 3, and then becomes in
reduce from the reference value Vdc during level 0.5 and level 1 parallel with C1a during the switching moment of level 2.5→2
of raising stage, while the voltage of C1a increases. That is, the in declining stage. Thus the capacitors C2a and C2b are charged
voltage of C1b (or the series capacitor C2a/C2b) is below Vdc by C1a, and the voltage of C1b is increasing beyond Vdc
while the voltage of C1a is higher than Vdc at the end of level 1. meanwhile. So that the highest voltage on C1b occurs. Applying
Afterward, the series capacitor C2a/C2b becomes in parallel with the conclusion of (19), the corresponding voltage rise of C1b
the capacitor C1a at the beginning of level 1.5 in Fig. 6(c). Thus compared with the reference value Vdc can be given as
the series capacitor C2a/C2b is charged while C1a is discharging,
so that the voltage of C1b increases. It is assumed that the

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 U 1b (rise)   U 1b 2.5 2   U 1b 1.5 Therefore, the total ripple loss for C1a, C1b, C2a, and C2b of the
C2 proposed 13-level inverter is
 (V V 2 a / 2 b 2.5 )   U 1b 1.5 Pt_rip  f o [ C1 (Vdc  7%) 2  C 2 (0.5Vdc  9%) 2 ] (26)
4 C1  C 2 1 a 2.5 
C2 (22) 2) The conducting loss is caused by the parasitic parameters
 2(  U 2 b 2.5  2  U 2 b 3 )   U 1b 1.5
4 C1  C 2 included in the current path of the output load, which are mainly
the internal resistance rc of capacitor and on-state resistance rs
197.410  4 V dc
  of switch for the proposed topology. Taking positive half cycle
4 C1  C 2 RL
for an instance, it can be observed from Fig. 2 that the total
Comparing (21) and (22), it is obvious that the maximum output current during a level is supplied through several flowing
voltage ripple of C1b in positive half cycle is ∆U1b(rise) in (22). paths. Here, the current flowing path with maximum total
Hence, the maximum voltage ripple of C1a in the whole cycle is parasitic resistance is selected, and the total output current is
4
394.810 V dc assumed to entirely flow through it during a level. In this way,
 U 1b (max)  2  U 1b (rise)   (23)
4 C1  C 2 RL the maximum conducting loss can be calculated, and the
As for C2b, it is charged and its voltage increases during the guaranteed lowest efficiency of the topology can be further
switching moment for level 1→1.5 of raising stage, as well as obtained. Hence, the maximum total conducting in a cycle can
level 1.5→1 and level 2.5→2 of declining stage. Hence, the be expressed as
maximum voltage ripple of C2b can be approximately calculated Pt_con  4 f o ( Pcon 0.5  Pcon 1  Pcon 1.5  Pcon 2  Pcon 2.5  Pcon 3 )
by its continuous voltage drop during level 1.5, level 2.5 and  4 f o [ iL2 0.5 ( rc  5 rs )T 0.5  iL2 1 (2 rc  4 rs )T 1 
level 3 in raising stage, and level 3 and level 2.5 in declining (27)
iL2 1.5 (3 rc  5 rs )T 1.5  iL2 2 (4 rs )T 2  iL2 2.5 ( rc  5 rs )T 2.5
stage:
 U 2 b (max)   U 2 b 1.5  2  U 2 b 2.5  2  U 2 b 3  iL2 3 (2 rc  4 rs )T 3 ]
18.4 C1 / C 2 128 V (24) where rc and rs are set as 50mΩ and 100mΩ for simplified
(  )10  4  dc
4 C1  C 2 C2 RL calculation, respectively.
Here, RL is set as 80Ω for the simulation and experiment in 3) The switching loss occurs due to the turn-on or turn-off
Section V. Thereby, the three-dimensional diagrams for delay of a power switch. It can be calculated by considering the
maximum voltage ripples on C1b and C2b based on (23) and (24) parasitic parallel capacitor of the switch [35]. The switching
are depicted as Fig. 7. The purple shadow on X-Y plane in Fig. loss for one turned-on or turn-off process is
1
7(a) or (b) demonstrates the feasible region for maximum E sw  C pV b2 (28)
voltage ripple below 10% [33]. Meanwhile, considering the 2
precondition that C2 is approaching to 4C1 discussed above, the where Cp represents the parasitic parallel capacitor of the power
capacitances can be selected as: C1a=C1b=C1=1000μF, and switch, and Vb is the withstanding voltage of the power switch
C2a=C2b=C2=3300μF. The theoretical maximum voltage ripples before it turns on (or after it entirely turns off). Assuming Cp of
are 7% and 9% based on the selected capacitances. each switch is equal to 500pF, the switching loss of different
∆U1b(max) / % ∆U2b(max) / % switching moments between two adjacent output levels can be
summarized as follows:
 Psw 0  0  2 C p (2V dc ) 2  3C p (V dc ) 2

 Psw  0  0.5  C p (0.5V dc ) 2

 Psw 0.5  1
 C p (0.5V dc ) 2

 Psw  C p (2V dc ) 2  2 C p (V dc ) 2  C p (0.5V dc ) 2
C1 / mF  1  1.5
(29)
C1 / mF P
C2 / mF C2 / mF  C p (0.5V dc ) 2
 sw 1.5  2

(a) (b)
 1
 Psw 2  2.5  C p (2V dc ) 2  C p (V dc ) 2  C p (0.5V dc ) 2
Fig. 7. (a) The maximum voltage ripple of C1b depending on the capacitance C1  2
and C2. (b) The maximum voltage ripple of C2b depending on C1 and C2.  Psw  C p (0.5V dc ) 2
 2.5  3

B. Power Loss Analysis Based on the above formula, the total switching loss is
The ripple loss, conducting loss, and switching loss will Pt_sw  4 f o ( Psw  0  0  Psw  0  0.5  Psw 0.5 1  Psw 11.5 
occur during the operation of the proposed 13-level inverter. Psw 1.5 2  Psw 2  2.5  Psw 2.5  3 ) (30)
1) Ripple loss is caused by the continuous charging process 2 3
 4.3 f o C pV  10 dc
of the capacitor. It is irrelevant to the parasitic resistance in the
charging loop [33], and can be calculated as Consequently, the theoretical efficiency of the proposed 13-
1 level inverter can be express as
E rip  C U 2 (25) Pout
2    100%
Pt_rip  Pt_con  Pt_sw  Pout (31)
Neglecting the minor voltage changes of the capacitors, the
maximum voltage ripples are taken into consideration.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2939562, IEEE Journal
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The theoretical efficiency of 98.25% can be obtained under topology to highlight its pros and cons. The topologies in
the condition of 260V input and 1kW output with 80Ω load. comparative study are expected to use single input dc source
Vdc and produce the same 2m+1 output levels for reasonable
IV. GENERALIZED STRUCTURE AND COMPARATIVE STUDY contrast (m>6). The items for comparison cover capacitor
number Ncap, semiconductor device (power switch and power
A. The Generalized Structure with n KTUs diode) number Nsem, and total standing voltage stress (TSV) for
The 13-level MLI with two KTUs featuring self-balance and all switching devices. Note that the topologies in [12], [14], and
1.5 voltage gain has been analyzed in detail above. For further [27] are incapable of boost, thus to be fair, TSV is calculated by
extension, its generalized structure with n KTUs is shown in Fig. the ratio of total voltage stress on all switching devices to the
8. The output level can be increased with single dc source, the output peak voltage for a topology.
boost factor rises as well. The voltage of capacitor Cia or Cib The detailed numeric values are listed in Table II. As it can
(i=1, 2,…, n-1, n) in KTU(i) can naturally maintain at 2-(n-1)Vdc be seen, the topologies of [12] must operate with the specific
in a cycle. The number of output level NLevel and the boost factor modulation to get voltage balance. And the sensors and closed-
M under the condition of n KTUs can be expressed as (32). loop control are required for voltage balance in [14]. These
1 auxiliary balance methods lead to increased complexity for
N Level  2 n  2  3, , , , , , M  2  n 1 (32) system. To have a visualized contrast, the curve graphs of
2
It is obvious that the number of output level is almost double comparison based on step number m and each item are also
with one additional KTU. The increment of output level is given as Fig. 9(a)-(c), where the overlapped curves are marked
significant. The voltage stress of the transistors in KTU(i) will as well. It is obvious that the proposed KTU topology employs
not exceed the total voltage of Cia and Cib. And nearly twofold the fewest power switches and capacitors compared with others
boost can be achieved with the extension of KTUs. from Fig. 9(a) and (b). The significantly reduced components
KTU(1) KTU(2) … KTU(n) with the same output levels is the greatest advantage of the
S1a S1c S2a S2c Sna Snc proposed topology. TSV of the proposed is the second lowest
among the boost MLIs from Fig. 9(c), ranking only after that of
C1a C2a Cna [31]. However, it can be observed that the MLI in [31] uses the
b T1a T2a Tna Tnb a
most power switches to reduce the voltage stress.
2Vdc …
T1b T2b Furthermore, in order to evaluate the topologies with
C1b C2b Cnb
different comparative items in a comprehensive way, the cost
function (CF) introduced in [34] for estimating the overall cost
S1b S1d S2b S2d Snb Snd
of MLI is taken into consideration here
Fig. 8. The proposed generalized structure with n KTUS.
( N switch  N diode  N cap   TSV)  N source
CF  (33)
B. The Comparative Study against Other MLIs N Level
In this part, the MLIs with the ability for extending output where α is a coefficient for measuring the weightiness of TSV
levels are taken into comparison with the proposed KTU
TABLE II
THE COMPARATIVE RESULTS AMONG DIFFERENT MLIS
Topology [12] [14] [27] [28] [29] [30] [31] Proposed
m+2
Nsem 2m+2 2m+6 3m+2 3m+1 5m+3 3m+1 6m-2 6log2 -6
m+2
Ncap m-1 m m m-1 m m-1 m-1 2log2 -2
Balance Modulation Sensors Self Self Self Self Self Self
Boost × × × √ √ √ √ √
TSV 3 5 + m- 7- m+5- 7- 5- 6
m+2
CF 3m+4 3m+11 + m- 4m+7- 7m+8- 4m+7- 7m+2- 8log2 -2
Semicondutor number

Capacitor number

CF
TSV

[14]&[27]&[29]

[28]&[30]

[12]&[28]&[30]&[31]
[28]&[30]

propos ed
propos ed
propos ed propos ed

Step number m Step number m Step number m Step number m

(a) (b) (c) (d)
Fig. 9. The curve graphs of the comparison result. (a) Semiconductor device number vs m. (b) Capacitor number vs m. (c) TSV vs m. (d) CF vs m.

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of Emerging and Selected Topics in Power Electronics
8

for topology, and it is set as 1 here. Nsource and NLevel have been
set equal for different topologies in advance in this comparative
study, thus they can be omitted for simplification. Consequently,
CF values of different MLIs are also listed in Table II and the
corresponding curves are shown as Fig. 9(d). Evidently, the CF
value of the proposed topology maintains at the lowest with the
output level increasing, demonstrating its advantage on the
overall cost. In summary, the certain merits of the proposed
topology have been illustrated thoroughly.
Multiple aspects can be considered to evaluate the reliability
of the topology for actual applications. Firstly, the high
complexity of control inevitably leads to lower reliability. For
the conventional NPC and FC topologies, ANPC topologies, as
well as the converters of [12] and [14] in comparison, numerous
voltage/current sensors, signal processing circuits, high-cost
controller, and complex control algorithm are needed to deal
with the voltage balance of capacitors. These will introduce
much complexity and reduce the reliability of the system.
Conversely, the proposed topology has the feature of self-
balance without any sensors or complicated control, reducing
the negative factor for reliability. The good performance of the
transient response of the proposed topology in Section V further
demonstrates its high reliability for voltage balance in actual
applications. Afterward, the proposed topology requires fewer
devices to achieve more than 13 output levels compared to
conventional and other inverters, which means lower fault
probability and faster recondition for the practical operation.
The proposed KTU can be also implemented by the power
modules (full-bridge module and half-bridge module) with high
integrated design and reliability. Last but not least, the
The capacitors’ voltages at rated output in simulation are
shown as Fig. 11. The voltages of C1a and C1b both maintain at
130V, and the voltages of C2a and C2b both maintain at 65V,
which are in accordance with the theoretical values. The self-
balance of capacitors is testified. Furthermore, the parasitic
parameters of the components in simulation are set the same as
the theoretical calculation in Section III. And the average
efficiency of the proposed 13-level topology at rated output is
98.12% in simulation (measured for five times), which
basically agrees with the theoretical value.
vC1a / V , vC1b / V
130V
vC2a / V , vC2b / V
65V
t /s
Fig. 11. The simulation waveforms of voltages for C1a, C1b, C2a, and C2b.
The transient test for output frequency step-up is conducted
in simulation. The R-L load is set as 80Ω and 90mH. As shown
in Fig. 12, the fundamental output frequency of the proposed
topology changes from 50Hz to 60Hz at the time of 0.2s.
Evidently, the overall voltages of the capacitors can maintain at
normal degree during the change of output frequency,
indicating the stable performance of the proposed topology.
vo / V iL* 50 / A

overcurrent/overvoltage protective methods for output and

input are advised to conduct in the actual application in order to
further improve the reliability of the proposed prototype. vC1a / V , vC1b / V Output frequency changes

V. SIMULATION AND EXPERIMENT VERIFICATION

vC2a / V , vC2b / V
A. The Simulation for the 13-Leve KTU Topology
The simulation parameters are set the same as the theoretical
analysis. The input voltage is 260V, and output frequency and t /s
rated power are 50Hz and 1kW, respectively. Fig. 10(a) Fig. 12. The output frequency changes from 50Hz to 60Hz with inductive load
illustrates the 13-level performance at rated power with 80Ω of 80Ω and 90mH.
pure resistant load in simulation. 13 steady voltage levels can B. The Experiment for the 13-Level KTU Topology
be observed, and the output peak voltage reaches 390V,
A 1kVA experimental prototype of the proposed 13-level
agreeing with the operation modes and 1.5 voltage gain.
inverter with two KTUs is implemented, and relevant
Moreover, the inductive load of 80Ω and 90mH is also applied
experimental parameters are listed in Table III.
in Fig. 10(b). The load current is a well-performed sinusoid TABLE III
wave, and its THD is 0.82%. The inductive-load ability of the THE EXPERIMENTAL PARAMETERS
proposed KTHB can be proved. Input Output Rated
vo / V vo / V Item C1 C2
voltage frequency output
390V Value 260V 50Hz 1kVA 1000μF±10% 3300μF±10%

Fig. 13(a) shows the picture of the experimental prototype.

iL / A iL / A
Fig. 13(b) is the experimental waveform of 1kW rated output
(80Ω resistant load), where the output voltage and current are
both 13-level staircase wave without filters. Meanwhile, its
t /s t /s output peak voltage reaches nearly 390V, which is 1.5 times as
(a) (b)
Fig. 10. The simulation waveforms. (a) Output voltage and current at 1kW input voltage. The highest experimental efficiency at 1kW rated
power with 80Ω resistant load. (b) Output voltage and current with inductive output is 96.74%; and the average experimental efficiency at
load of 80Ω and 90mH. rated output is 96.8% (measured for five times). The experime-

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of Emerging and Selected Topics in Power Electronics
9

Control Board vo
Driver Board × 3 vo
390V

C1a C2a

iL
iL

C1b C2b

KTU(1) KTU(2) t（5ms/div） t（5ms/div）

(a) (b) (c)
Fig. 13. (a) The photograph of the experimental prototype. (b) Experimental output with 80Ω resistant load. (c) The case with inductive load of 80Ω and 56mH.
Harmonic components Harmonic components
Voltage THD Current THD

(a) (b)
Fig. 14. (a) THD and harmonic components of the staircase output voltage without filters. (b) THD and harmonic components of output current with R-L load.

ntal efficiency is commonly lower than the theoretical stress of the transistors in KTU(1) does not exceed the total
efficiency due to the extra wire impedance in circuit, contact voltage of C1a and C1b (260V) from Fig. 16(a); the voltage stress
resistances of connectors, thermal dissipation problem, and so of the transistors in KTU(2) does not exceed the total voltage of
on. The experimental efficiency can be improved with better C2a and C2b (130V) from Fig. 16(b), which both agree with the
circuit design and device selection. theoretical analysis in Section IV.
As depicted in Fig. 13(c), the inductive load of 80Ω and VDS S1c VDS S2c
56mH is applied for the proposed prototype, and its current 260V
130V
waveform becomes a sinusoid. The THD of staircase output T2a
voltage without filters is 5.3%; the THD of sinusoidal output T1a 65V
260V
current with inductive load is 2.3% (see Fig. 14(a) and (b) for S2a
S1a 130V
detail). All the results satisfy the harmonics standard (IEEE519). 260V
Hereby, considerable 13-level output with FFM help to improve t (5ms/div) t (5ms/div)
the output power quality greatly, and guarantee a relatively high (a) (b)
efficiency meanwhile. The requirement for output filter is Fig. 16. The voltage waveforms of D-S of the transistors. (a) The D-S
waveforms of S1c, T1a, and S1c in KTU(1). (b) The D-S waveforms of S2c, T2a, and
reduced as well. The 13-level output, 1.5 voltage gain, and
S2c in KTU(2).
inductive-load ability have been verified in the experiment.
C2a VC
65V
C2a
Vrippple The experiments of transient response have been also
C2b CC2b2b
conducted. In Fig. 17(a), the input voltage steps up to 260V
65V suddenly, and the voltages of capacitors rise up to their
C1a C1a respective expected values in a short period and remain stable
130V
C1b self-balance (vc1b is equal to Vin -vc1a thus it is not presented
C1b
t (5ms/div) here due to the four-channel oscilloscope). In Fig. 17(b), the
130V
load changes from 80Ω to 80Ω+56mH, that is, the output PF
t (5ms/div) changes from 1 to 0.975 and the active output power increases.
Fig. 15. The experimental waveforms of the capacitors’ voltages and their Obviously, the prototype can remain steady operation and each
corresponding voltage ripples in high resolution.
output level keeps unchanged, illuminating the performance of
Moreover, the performance of capacitors’ voltages is capacitors’ voltage balance from the side as well. Consequently,
indicated in Fig. 15. The voltages of C2a and C2b maintain at the feasibility of the proposed KTU topology has been proved
65V; the voltages of C1a and C1b can maintain at 130V as well. from steady case and transient case.
VC2a
Thus the self-balance of capacitors can be validated. Their vo
voltage ripples can be also observed. The maximum voltage VC2b

ripples on C1a and C1b are about 10V; as for C2a and C2b, they Input steps up
VC1a
are around 6V. The voltage ripples on capacitors accord with iL
PF changes
the theoretical values (7% and 9%) in Section III. The voltage vo
stress (D-S waveform) of the transistors in KTU(1) and KTU(2)
are also shown in Fig. 16. Only one D-S waveform of the t (10ms/div) t (5ms/div)
(a) (b)
transistor pair is given due to the same voltage stress, such as Fig. 17. The transient response experiment (a) Input voltage steps up from 80V
the transistor pairs (S1a, S1b), (S1c, S1d), and so on. The voltage to 260V. (b) Output power factor (PF) changes from 1 to 0.975.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2939562, IEEE Journal
of Emerging and Selected Topics in Power Electronics
VI. CONCLUSIONS
The 13-level inverter based on two KTUs with self-balance
and 1.5 voltage gain is firstly presented in the paper. The
operation modes, self-balance behaviors, and capacitance
calculation are presented in detail. Afterward, the generalized
step-up KTU topology with increased output levels is further
discussed, and taken into comparison with other MLIs proposed
in recent years. The comparative results have demonstrated its
merits of reduced components, self-balance, voltage stress, and
overall cost. Finally, the self-balance, transient response
performance, boost, and inductive-load ability of the proposed
KTU topology are verified through simulation and 1kVA
experimental prototype. The results of simulation and
experiment prove its feasibility for practical applications.
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2939562, IEEE Journal
of Emerging and Selected Topics in Power Electronics
11

Jun Zeng (M’11) received her Ph.D. degree in

control theory and control engineering from the
South China University of Technology, Guangzhou,
China in 2007. She is a professor in the Electric
Power College of the South China University of
Technology, Guangzhou, China. Her current research
interests include power electronics applications,
energy management and intelligence control in
distributed generation and integration of renewable
energy to smart grid.

Weijie Lin was born in Guangdong, China, in 1995.

He received the B.S. degree in electrical engineering
from Southwest Jiaotong University, Chengdu,
China, in 2018. He is currently working toward his
M.S. degree in the Electric Power College of the
South China University of Technology, Guangzhou,
China.
His current research interests include multilevel
converters, high-frequency ac power distributed
system, and resonant converters.

Dehai Cen was born in Guangxi, China, in 1995. He

received the B.S. degree in electrical engineering
from Hunan University, Changshang, China, in 2017.
He is currently pursuing the M.S. degree with the
Electric Power College, South China University of
Technology, Guangzhou, China. His current research
interests include Phase-locked loop and Grid-
connected Inverter.

Junfeng Liu received the M.S. degree in control

engineering from the South China University of
Technology, Guangzhou, China, in 2005, and the
Ph.D. degree from the Hong Kong Polytechnic
University, Kowloon, Hong Kong, in 2013.
From 2005 to 2008, he was a Development
Engineer of Guangdong Nortel Network, Guangzhou,
China. In 2014, he joined the South China University
of Technology, Guangzhou, where he was an
Associated Professor at School of Automation
Science and Engineering. His research interests
include power electronics applications, nonlinear control, high frequency
power distribution system, and motion control system.

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