AUTONOMOUS

Department of Electronics and Communication Engineering

MID-I QUESTION PAPER –NOVEMBER-2019

Course Code:
Programme: M. Tech
Year / Sem: I/I UR19-PC-PG-EC101
(VLSI&ES)
Date: 11.11.2019
Course Name: RTL Simulation
Total Marks: 30M Time: 90 min
and Synthesis with PLDs
CO: Course Outcome Level: Bloom’s Taxonomy (Level 1-6)
Answer All questions (3X10=30M)
CO
Level Q.No Question
no.
A) Design a one-input one-output sequence
6 1 detector that produces an output value 1 every
1 time the sequence 0101 is detected and an output
2 value 0 at all other times.
B) Explain different type of Clock issues.
3 6 2 Write a VHDL for the Control Logic of a Vending Machine.
2 6 3 Write a short note on ASIC Design Flow.

AUTONOMOUS
Department of Electronics and Communication Engineering
MID-I QUESTION PAPER –NOVEMBER-2019

Course Code:
Programme: M. Tech
Year / Sem: I/I UR19-PC-PG-EC101
(VLSI&ES)
Date: 11.11.2019
Course Name: RTL Simulation
Total Marks: 30M Time: 90 min
and Synthesis with PLDs
CO: Course Outcome Level: Bloom’s Taxonomy (Level 1-6)
Answer All questions (3X10=30M)
CO
Level Q.No Question
no.
A) Design a one-input one-output sequence
6 1 detector that produces an output value 1 every
1 time the sequence 0101 is detected and an output
2 value 0 at all other times.
B) Explain different type of Clock issues.
3 6 2 Write a VHDL for the Control Logic of a Vending Machine.
2 6 3 Write a short note on ASIC Design Flow.