ANALOG PROJECT 1

Current-Mode Multiplier-Divider Circuit(s) Based

on MOS Trans-linear Principle
Ankit Srivastava (2018H1230212H), Aditi Bagriya (2018H1230224H) and Sourabh Mittal (2018H1230209H)
Under supervision of: Dr. Saroj Mondal

Abstract—In this project, a novel current-mode analog multi- Where ‘k’ is an arbitrary constant (a.k.a area factor) which we
plier/divider circuit based on the principle of voltage-translinear came across during the calculation of geometric mean of two
loops are presented which features simplicity, precision and wide currents. For stacked topology, k=2. So the given operation
dynamic range. They are good for standard CMOS fabrication
and can be employed in a wide spectrum of analog signal pro- can be performed in two sub-operations:
cessing applications. In addition, insensitivity to temperature and
other process variations is inherited from its voltage-translinear 1) G-Mean circuit whose functionality is defined as:
nature. Two topologies which are stacked and up-down voltage- p
translinear loops, are explained in this report. Implementation Iout = k Ix Iy
of current-mode multiplier/divider incorporating stacked-based
translinear loop has been done using cadence tool at lower supply 2) Squarer circuit whose functionality is defined as:
voltage (of 1.8V) and lower dimensions of the MOSFET device. Iz2
Iout = k 2 Iw
Index Terms—translinear, T.E.
The above two expression are inverse of each other and they
can be implemented with stacked topology and reusing the
I. I NTRODUCTION same circuit by interchanging the input and output impedances
nalog multipliers are circuits that can be frequently found accordingly.
A in many analog systems, ranging from the conventional
peak detectors, phase detectors, modulators and synthesizers IV. B LOCK D IAGRAM
etc. A lot of work has been carried out in the field of analog
multiplier design, and many solutions in CMOS technology
are already available which can be reduced to two basic
modes of operation i.e. operation of transistors in saturation or
linear region. However, this classification applies only to the
trans-conductance type of multipliers, i.e., those whose inputs
are voltages and outputs are currents. There is still another
approach which is based on the application of the trans-linear
principle in MOS transistors operating under saturation region,
which automatically leads to simpler current relationships
of the type required, without the need of any nonlinearity
cancellation schemes.

II. O BJECTIVES
• To study the MOS Translinear principle for the proposed Fig. 1. Principle of current multiplier/divider circuit
Analog current multiplier/divider.
• To analyze, design and perform simulation of the proposed
circuit.
• Discuss the practical applications and feasibility of the V. VOLTAGE T RANSLINEAR P RINCIPLE
circuit.

III. P RINCIPLE O F O PERATION The translinear principle (TLP) states that in a closed loop
containing an even number of translinear elements (TEs) with
Operation that need to be performed:
an equal number of them arranged in clockwise and counter-
Ix Iy
Iz = Iw
clockwise, the product of the currents through the clockwise
translinear elements equals the product of the currents through
where, Ix ,Iy ,Iw and Iz are current siagnals. the counter-clockwise translinear elements. Therefore, they
Then alternatively, the above expression can be written as: form a translinear loop:
√ 2
(k Ix Iy )
Iz = 2
k Iw
ANALOG PROJECT 2

VI. BASIC T OPOLOGIES

Stacked topology:

Fig. 2. Voltage translinear loop made from diodes

Fig. 4. Voltage trans-linear loop implemented in stacked topology

Up-down topology:

The voltage translinear principle is based on the exponential I-

V relationship of BJTs and MOS transistors in weak inversion
and has recently been extended to topologies comprising loops
of MOS transistors operating in strong inversion, in which
the square law characteristics as a result of operation in
saturation lead to the realization of square and square roots of
currents. The voltage trans-linear circuits are based on linear Fig. 5. Voltage trans-linear loop implemented in up-down topology
dependence of the trans-conductance of a MOST operating
in strong inversion and in the saturation mode at the gate-
source voltage. Therefore, translinear principle for MOSFETs
Fig(4) and Fig(5) figures represent a four-transistor voltage-
in saturation regime can be defined as: (where Sj is the
translinear loop in stacked and up-down topology, respectively,
strength (W/L) of MOSFET device)
with two MOSTs connected clockwise and another pair con-
nected counter clock wise. Applying the KVL and assuming
equal MOS trans-conductance factors and threshold voltages,
the following expression is obtained for both cases (which is
also known as MOSFET translinear expression):
q q q q
I1 I2 I3 I4
(W/L) + 1 (W/L) = (W/L) +
2 (W/L)
3 4

Where Ii and Wi /Li represent drain current and aspect ratio.

Now squaring both sides:
Fig. 3. Voltage translinear loop made from NMOS transistors in saturation
region
√ √
I1 + I2 + 2 I1 I2 = I3 + I4 + 2 I3 I4

Even though the square law conformity on which the voltage- And by forcing I3 and I4 to be equal and of value:
trans linear principle relies is not as precise as the exponential I1 +I2 +2Iz
I3 = I4 = 4
conformity of BJTs, and its validity remains for approximately
1.5 decades of current, It offers high speed operation.
ANALOG PROJECT 3

Where Iz is a copy of Iout then: one of its low-impedance inputs into the high impedance
√ squarer/divider output. Thus, we get the squarer/divider output
Iout = I1 I2
current Iout as:
Iz2
VII. M ULTIPLIER -D IVIDER D ESIGN Iout = k 2 Iw
G-Mean circuit
The geometric-mean and squarer/divider blocks can be im-
plemented using either stacked or up-down voltage-translinear
loops. But in this report, the circuit(s) is implemented using
the stacked topology.
The geometric mean circuit can be obtained from the translin-
ear stacked loop topology by setting:
I1 = Ix , I2 = Iy , I3 = I4 = Ix + Iy + Iz

The four transistors of translinear loop are sized as:

4 (W/L)1 = 4 (W/L)2 = (W/L)3 = (W/L)4
Fig. 7. Squarer cell based on stacked translinear loop toplology

Then plugging these values in the MOSFET translinear ex-

pression, Iz becomes as: Multiplier Divider circuit
p
Iz = 2 Ix Iy Introducing the output current of geometric mean circuit as ‘Iz’
input of the squarer-divider circuit through a cascode current
mirroring circuit, a current multiplier-divider is obtained given
as:
√ 2
I2 (2 Ix Iy ) I I
Iout = 4Izw = 4Iw = Ixwy
Fig (8) shows the resulting multiplier-divider circuit, where
the output of the geometric-mean cell is inverted by a cascode
current mirror in order to properly inject it into the squarer-
divider circuit.

Circuit Diagram of multiplier/divider circuit

Combining these two sub-operations in order to generate the
multiplier-divider circuit:

Fig. 6. G-mean cell based on stacked translinear loop toplology

The voltage-translinear loop is formed by transistors M1–M10,

also the bulk terminals of these transistors are connected to
their sources and thus avoiding the body effect. M13 and
M26 are diode-connected transistors included for minimize
the channel-length modulation effect in M1 and M2, respec-
tively. Transistors M11–M12 form a regular current mirror
and M14–M25 realizes high-swing cascode current copiers
Fig. 8. Voltage translinear multiplier-divider circuit based on stack topology
which are responsible for injecting the required combinations
of currents into the voltage-translinear loop circuit to get the
desired output current.
The above circuit uses a cascode current mirror to properly
Squarer circuit inject the output of G-mean circuit to the input Iz of the
The squarer circuit is obtained by performing a minor change squarer circuit such that the output of squarer circuit is
on the geometric-mean cell in order to transform its geometric- reminiscent to the multiplier-divider operation. In this way
mean output into a low-impedance squarer/divider input, and high-speed multiplier-divider circuit is achieved.
ANALOG PROJECT 4

VIII. I MPLEMENTATION IN C ADENCE

The G-mean circuit is implemented in cadence at 1.8V supply

voltage. At output, a resistor of 0.1 ohms is appended to mea-
sure the current. The current is then measured by performing
the DC analysis of the circuit and printing the DC operating
points.

Fig. 11. Multiplier/Divider circuit

Input Parameters

Fig. 9. G-Mean schematic

The Squarer circuit is implemented in cadence at 1.8V supply

voltage. At output, a resistor of 0.1 ohms is appended to mea-
sure the current. The current is then measured by performing
the DC analysis of the circuit and printing the DC operating
points.

IX. R ESULTS AND D ISCUSSION

TABLE I
S IMULATION R ESULTS

Iw Ix Iy Actual Simulated Percentage

12µA 30µA 13µA 32.5µA 27.336µA 15.88%
15µA 30µA 10µA 20µA 17.956µA 10.22%
13µA 12µA 15µA 13.846µA 13.1693µA 4.88%
13µA 13µA 15µA 15µA 14.1518µA 5.65%
14µA 16µA 13µA 14.857µA 13.9084µA 6.38%
15µA 15µA 13µA 11.2µA 12.2834µA 9.673%
16µA 14µA 12µA 10.5µA 10.0643µA 4.14%

Fig. 10. Squarer schematic

From this table, it can be inferred that accuracy increases when

Finally, the Multiplier-Divider circuit is implemented using difference between the inputs is minimum.
above mentioned circuits in cadence at 1.8V supply voltage.
A cascode current mirror is used to properly inject the inverted X. C ONCLUSIONS
current as per the requirements of the squarer circuit. At
A novel analog multiplier/divider scheme that has been pro-
output, a resistor of 0.1 ohms is appended to measure the
posed is obtained by a means of much simpler method, it
current. The current is then measured by performing the DC
presents interesting features such as precision and simplicity,
analysis of the circuit and printing the DC operating points.
and can be implemented in a small area. Due to the afore-
mentioned features, this constitutes in versatile building blocks
ANALOG PROJECT 5

suitable for being applied in various analog applications, in-

cluding square-root domain systems, artificial neural networks
and analog fuzzy hardware.

XI. F UTURE S COPE

• The proposed circuit has applications in artificial neural
networks and fuzzy logic controllers.
• Further optimization(s) can be done to improve its efficiency.
• Further implementation of this circuit in smaller technology
nodes like 45nm and 90nm may be possible.

XII. R EFERENCES
[1] L´opez-Mart´ın, A. J. and Carlosena, A., “A systematic
approach to the synthesis of square-root domain systems,” In
Proc. of IEEE Int. Symp. on Circuits and Systems, Orlando,
FL, vol. V, 1999,pp. 306–309.
[2] Gilbert, B., “Translinear circuits: A proposed classifica-
tion.” Electron. Lett. 11(1), pp. 14–16, January 1975.
[3] Gilbert, B., “Translinear circuits: An historical overview.”
Analog Integrated Circuits and Signal Processing 9(2), pp.
95–118,March 1996.