JMX568

ZigBee Compliant Platform

2.4GHz High Power Transceiver
Module for IEEE 802.15.4 Standard

DATA SHEET
Version A

Quan International Co., Ltd.,

JMX568 Datasheet

JMX568 Features
 Fully compliant 802.15.4 Standard and can support fully
Zigbee features:
— 2.4GHz, 16 selectable channels in the 2.4 GHz ISM band.
— Programmable output power, +18dBm maximum.
— Receive sensitivity of -90 dBm.
— Supports up to 250 kbps O-QPSK data and full spread-
spectrum encode and decode.
 Hardware acceleration for IEEE® 802.15.4 applications:
— DMA interface.
— AES-128 Security module.
— 16-Bit random number generator.
— 802.15.4 Auto-sequence support.
— 802.15.4 Receiver Frame filtering.
 Two power modes provide super low power consumption
benefits.
 256 KB Flash and 32KB RAM for application programming and
no additional MCU cost.
 Up to 20 Digital IO Pins (DIO).
 2xUART0/1, 1xSPI, 2x I²C, 5xPWM(4x timer & 1 timer/counter).
 Supply voltage monitor with 8 programmable thresholds.
 4-input 10-bit ADC, comparator.
 Compact size with i-Pex RF connector or chip antenna on
board.
 Pin-27 stamp hole for 2.0mm pitch.
 “Ready to go” modules speeding up products development.

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JMX568 Datasheet

Applications
 Home Automation : Security control , HVAC/Lighting control,
access control, lawn & garden irrigation, energy management,
smart home network.
 Building Automation : security, HVAC, ARM, lighting control,
access control.
 Industry Automation : Asset management, process control,
environmental monitoring, energy management.
 Cable replacement.
 JenNet-IP networks, ZigBee SE networks, ZigBee Light Link
networks.

Specifications
 256KB flash memory with block protection and security and up
to 32KB RAM, allows for application programming space and
save the cost for additional MCU.
 Input voltage: 2.0V ~ 3.6V.
 RF Data rate: 250kbps.
 Low power modes (Sleep & Deep sleep modes, less than 2 μA
in Deep sleep).
 Fully compliant 802.15.4 Standard transceiver supports 250
kbps O-QPSK data in 5.0 MHz channels and full spread-
spectrum encode and decode.
 Programmable output power with 0 dBm nominal output power,
programmable from -40 dBm to +18dBm.
 Receive sensitivity of -90 dBm (typical) at 1% PER, 20-byte
packet, much better than the IEEE 802.15.4 Standard of -85
dBm.
 Operates on one of 16 selectable channels in the 2.4 GHz ISM
band.
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JMX568 Datasheet

 Serial communications interface - Universal Asynchronous

Receiver/Transmitter (UART):
— Fully programmable data formats: baud rate, start, stop and
parity settings.
— Optional modem flow control signals CTS and RTS on
UART0.
— Baud rate is programmable up to 1Mbps.
— False start bit detection, parity, framing and FIFO overrun
error detect and break indication.
— Internal diagnostic capabilities: loop-back controls for
communications link fault isolation.
— Flow control by software or automatically by hardware.
— Used to set number of data bits (5, 6,7 or 8), even, odd, set-
at-1, set-at-0 or no-parity detection and generation of single or
multiple stop bit, (for 5 bit data, multiple is 1.5 stop bits; for 6, 7
or 8 data bits, multiple is 2 bits).
 Serial peripheral interface Master (SPI-Master):
— Full-duplex, three-wire synchronous data transfer.
— Programmable bit rates (up to 16Mbit/s), transaction size up
to 32-bits.
— Manual or Automatic slave select generation (up to 3 slaves)
— Programmable transaction size up to 32-bits.
— Maskable transaction complete interrupt.
— LSB First or MSB First Data Transfer.
— Supports delayed read edges.
 Serial peripheral interface Slave (SPI-Slave):
— Full-duplex synchronous data transfer.
— Slaves to external clock up to 8MHz.
— Supports 8 bit transfers (MSB or LSB first configurable),
with SPISSEL deselected between each transfer.
— Internal FIFO up to 255 bytes for transmit and receive.
— Standard SPI mode 0, data is sampled on positive clock
edge.
 Two-Wire Serial Interface (I²C):
Common to both master and slave:
— Compatible with both I2C and SMbus peripherals.

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JMX568 Datasheet

— Support for 7 and 10-bit addressing modes.

— Optional pulse suppression on signal inputs (60ns
guaranteed, 125ns typical).
Master only:
— Multi-master operation.
— Supports Slave clock stretching.
— Software programmable acknowledge bit.
— Interrupt or bit-polling driven byte-by-byte data-transfers.
— Bus busy detection.
Slave only:
— Programmable slave address.
— Simple byte level transfer protocol.
— Write data flow control using acknowledge mechanism.
— Read data flow control using clock stretching , preloaded or
provided as required.
 Peripheral Timer/Counters:
— Clocked from internal system clock (16MHz).
— 16-bit counter, 16-bit Rise and Fall (period) registers.
— Timer : can generate interrupts off Rise and Fall counts.
Can be gated by external signal.
— Counter : counts number of transitions on external event
signal. Can use low-high, high-low or both transitions.
— PWM/Single pulse : outputs repeating Pulse Width
Modulation signal or a single pulse. Can set period and mark-
space ratio.
— Capture : measures times between transitions of an applied
signal.
— Delta-Sigma : Return-To-Zero (RTZ) and Non-Return-to-
Zero (NRZ) modes.
 10-bit Analogue to Digital Converter(ADC):
— Six multiplexed single-ended input channels: four available
externally, one connected to an internal temperature sensor,
and one connected to an internal supply monitoring circuit.
— ADC is clocked from a common clock source derived from
the 16MHz clock.

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JMX568 Datasheet

 Up to 20 I/O Pins, include GPIOs, UARTs, I²C, PWMs, ADC

etc.,and provide flexible interfaces for product development
and integration.
 Minimal external components are required such as antenna,
matching circuit and power, provides simple and flexible
options for applications development.
 Operating Temperature: -40 to +85˚C.
 Additional RF switch to minimize the noise caused by internal
RF switch. And this greatly enhances the communication
distance.
 Power Consumption:
 Hibernate : 4μA.
 Transmit Mode : 100 mA (output power = 18dBm).
 Receive Mode : 25 mA (typical).
 Small module size: 30mm x 16mm.

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JMX568 Datasheet

System Diagram

Electrical Specifications
Item Min Typical Max Unit
Frequency 2.400 2.485 GHz
Supply voltage 2.0 3.3 3.6 V
Active mode 17 mA
MCU current
Sleep mode 4 μA
consumption
Deep sleep mode 0.15 μA

RF current TX 100 mA
consumption RX 25 mA
TX output power -40 0 18 dBm
TX EVMt 3 4.5 %
RX sensitivity(250Kbps) -90 dBm
Maximum input signal 10 dBm
Frequency error tolerance 200 kHz
Operation temperature -40 25 85 ℃

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JMX568 Datasheet

Module Diagram

Front View

Side View
Pad Pitch : 2.0mm
Pad width : 1.25mm
Dimensions : Length: 30mm x Width: 16mm x Height: 1.3mm

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JMX568 Datasheet

Clearance Area for Chip Antenna

If programming code set to use chip antennat to transmit and
receive, please leave the red area (6x6mm) clear of metal/parts in
order to get the best RF performance.

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JMX568 Datasheet

Module Pinouts

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 JMX568 Datasheet

Pin Assignment
Pin Primary Alternate Functions Single Type Description
1 ADC1 3.3V ADC inputs 1
Port0, SPI Master Select
2(1) D0 (I/O) SPISEL1 / ADC3 CMOS
Output 1 or ADC input 3
Port1, SPI Master Select
3 D1 (I/O) SPISEL2 / ADC4 CMOS Output 2, ADC input 4 or
Pulse Counter 0 Input
Port2, Radio Receive Control
4(1) D2 (I/O) RFRX / TIM0CK_GT CMOS Output or Timer0 Clock/Gate
Input
Port3, Radio Transmit
5(1) D3 (I/O) RFTX / TIM0CAP CMOS Control Output or Timer0
Capture Input
Port0,SPI Master Clock
6 D0 (O) SPICLK / PWM2 CMOS
Output or PWM2 Output
Port1, SPI Master In Slave
7(2) D1 (O) MISO / PWM3 CMOS
Out Input or PWM3 Output
Port18, SPI Master Out
8 D18 (I/O) MOSI CMOS
Slave In Output
Port19, SPI Master Select
9 D19 (I/O) SSZ CMOS
Output 0
10 GND 0V Ground
Port4, UART 0 Clear To
CTS0 / JTCK / Send Input, JTAG CLK Input,
11 D4 (I/O) CMOS
TIM0OUT / PC0 Timer0 PWM Output, or
Pulse Counter 0 input
Port7, UART 0 Receive Data
12 D7 (I/O) RXD0 / JTDI / PWM3 CMOS Input, JTAG Data Input or
PWM 3 Output
Port6, UART 0 Transmit
13 D6 (I/O) TXD0 / JTDO / PWM2 CMOS Data Output, JTAG Data
Output or PWM2 Output
Port5, UART 0 Request To
Send Output, JTAG Mode
14 D5 (I/O) RTS0 / JTMS / PWM1 CMOS
Select Input, PWM1 Output
or Pulse Counter 1 Input
15 VCC 3.3V Power Supply
Port8, Timer0 Clock/Gate
TIM0CK_GT / PC1 /
16 D8 (I/O) CMOS Input, Pulse Counter1 Input
PWM4
or PWM 4 Output
17 GND 0V Ground
Port11, PWM1 Output or
18 D11 (I/O) PWM1 / TXD1 CMOS UART 1 Transmit Data
Output

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 JMX568 Datasheet

Pin Primary Alternate Functions Single Type Description

Port12, PWM2 Output,
UART 0 Clear To Send
PWM2 / CTS0 /
Input, JTAG CLK Input,
19 D12 (I/O) JTCK / ADO / CMOS
Antenna Diversity Odd
SPISMOSI
Output or SPI Slave Master
Out Slave In Input
Port13, PWM3 Output,
UART 0 Request To Send
PWM3 / RTS0 / JTMS Output, JTAG Mode Select
20 D13 (I/O) CMOS
/ ADE / SPISMISO Input, Antenna Diversity
Even output or SPI Slave
Master In Slave Out Output
Port14, Serial Interface
Clock, UART 0 Transmit
I²C_CLK / TXD0 Data Output, UART 1
21 D14 (I/O) TXD1 / JTDO / CMOS Transmit Data Output, JTAG
SPISEL1 / SPISSEL Data Output, SPI Master
Select Output 1 or SPI Slave
Select Input
Port15, Serial Interface Data,
UART 0 Receive Data Input,
I²C_SDA / RXD0
UART 1 Receive Data Input,
22 D15 (I/O) RXD1 / JTDI / SEL2 / CMOS
JTAG Data Input, SPI Master
SPISCLK
Select Output 2 or SPI Slave
Clock Input
Port16, Comparator Positive
COMP1P / I²C_CLK / Input, Serial Interface clock
23 D16 (I/O) CMOS
SPISMOSI or SPI Slave Master Out
Slave In Input
Port17, Comparator Negative
COMP1M / I²C_SDA / Input, Serial Interface Data
24 D17 (I/O) CMOS
SPISMISO or SPI Slave Master In Slave
Out Output
25 RESET CMOS Reset input
26 ADC2 1.8V ADC input 2
27 GND 0V Ground

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JMX568 Datasheet

(1)
Pin Mode
Note :

D0 (I/O) / D2 (I/O) /
D3 (I/O) / RFTX /
Mode SPISEL1 / RFRX /
TIM0CAP
ADC3 TIM0CK_GT

RF *PA Mode Float (external) Float (external) Float (external)

*PA=Power Amplifier.

Note(2):

Mode D1 (O) / MISO / PWM3

Programming Mode Low (external)

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