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Chapter Two Features of 8086 μprocessor

The 8086 microprocessors architecture 8086 is a 16 bit μp that has the following features;
o It has a 20 bit address bus can access up to 220 memory
locations ( 1 MB) .
For DTU o It can support upto 64K I/O ports.
Those shaded out are not for DTU o It provides 14, 16-bit registers.
o It has multiplexed address and data bus AD0- AD15 and
A16 – A19.
o Two modes of operation, Minimum & Maximum mode.
o It can pre fetch up to 6 instruction bytes from memory
and queue them to speed up instruction execution.
By: o It requires +5V power supply.
Achamie A o 40 pin dual in line package.

8086 Microprocessor–Functional Units 8086 architecture

6-bit ALU: performs arithmetic and logical operations like
Addition, Subtraction, AND, OR, etc.
A set of 16-bit registers which inclue Accumulator, general
purpose registers, program counter, stack pointer, Flag
registers, …)
Instruction register and decoder: fetch
instruction from memory and store in queue which will be
decoded successively by the ins. decoder.
Timing and control signal like
o Control Signals: READY, RD’, WR’, ALE
o Status Signals: S0, S1, IO/M’
o DMA Signals: HOLD, HLDA
o RESET Signals: RESET IN, RESET OUT

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I. Bus Interface Unit (BIU)
 BIU establish communications with external devices and
peripherals including memory via the bus
 It contains the system bus which is group of wires
connecting memory & I/O to microprocessor. Three types;
Address Bus
• Unidirectional
• Identifying peripheral or memory location
 Data Bus
• Bidirectional
• Transferring data
Control Bus
• Synchronization signals
• Timing signals
• Control signal
BIU has a separate adder for obtaining a physical address
while addressing memory.
The segment address value is taken from an appropriate
segment register (based on whether code, data or stack are
to be accessed)
Offset may be content of IP, BX, SI, DI,SP or an immediate
16-bit value, depending on addressing mode.
8086 has two main components, Bus Interface Unit (BIU)
and Execution Unit (EU)
The 16 lines (0-15) are multiplexed. i,.e used for both data
and address (A0-A15 or D0-D15) where as the remaining 4
higher lines are for address only (A16-A19).
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I. Bus Interface Unit (BIU)
It has the following functions:
 Instruction fetch, Instruction queuing, Operand fetch and
storage, Address relocation and Bus control.
 BIU calculate the physical address from offset address and
segment address to locate a memory location within the
segmented main memory.
8086 addresses a segmented memory. The 20-bits complete physical
address is generated using segment and offset registers, each 16-bits
long.
o Segment address: base address of one the four segments in main
memory
o Offset address: offset distance of a particular memory location
from base of the selected segment.
 The BIU uses a mechanism known as an instruction queue
to implement a pipeline architecture.
The FIFO queue in the BIU permits prefetch of up to six bytes of
instruction code with 2 bytes at a time (within a single memory
cycle).
EU access instructions from the end of the queue.
If the queue is full and EU is not requesting for instructions, there
will not be queue activity called idle state.
These prefetching instructions are held/stored in its FIFO queue till
the EU reads them for execution.
This is much faster than sending out an address to the
system memory and waiting for memory to send back the
next instruction byte or bytes.
 The BIU is also responsible for generating bus control
signals such as those for memory read or write and I/O read
or write
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THE EXECUTION UNIT
The EU is responsible for decoding and executing
all instructions
The EU;
Extracts instr’ns from top of the queue in the
BIU,
decodes them,
generates operands if necessary,
passes them to the BIU and requests it to
perform the read or write bytes to memory or I/O
and
perform operation specified by the instruction
on the operands.
Decoder: translates instructions fetched from
memory into a series of actions, which the
EU carries out.
ALU: a 16-bit unit which can add, subtract, AND,
OR, XOR, increment, decrement, complement, or
shift binary numbers.
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What if there is branch instruction?
When the EU executes a branch or jump instruction;
it transfers control to a location corresponding to
another set of sequential instructions.
Thus, BIU resets the queue and begins to fetch
instructions from a new location to refill the queue
The EU contains also Control Circuitry, Instruction
Decoder, and ALU
Control circuitry: directs internal operations.
Register Organization
 All registers within 8086 are 8 bit registers
 they can be used separately or can be used in groups of 2
for storing 16 bit data or address.
I. General-Purpose Registers
 Within EU there are eight general-purpose registers, AH,
AL(Accumulator), BH, BL, CH, CL, DH and DL.
 These registers are used individually for temporary storage
of 8-bit data or in pairs of two to store 16-bit data words.
 These are AH and AL(together called AX register), BH and
BL (called BX register), CH and CL (CX), and DH and DL
(DX).
 Using internal registers enables EU to access data much
more quickly since data is already within the EU.
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II. Flag Register
 They are nine 8 bit registers
 Used to hold the status of the microprocessor before or
after execution of an operation.
 so, certain instructions check these flags to before
executing an instruction.
S-Sign Flag: This flag is set, when the result of any
computation is negative. For signed computations, the
sign flag equals the MSB of the result.
Z-Zero Flag: This flag is set, if the result of the
computation or comparison performed by the previous
instruction/instructions is zero.
P-Parity Flag: This flag is set to 1, if the lower byte of
the result contains even number of 1s.
C-Carry Flag: This flag is set, when there is a
carry out of MSB in case of addition or a borrow
in case of subtraction.
AC-Auxiliary Carry Flag: This is set, if there is a
carry from the lowest nibble, i.e. bit three, during
addition or borrow for the lowest nibble, i.e. bit
three, during subtraction.
D-Direction Flag: This is used by string
manipulation instructions. If this flag bit is '0’ the
string is processed beginning from the lowest
address to the highest address, i.e. auto
incrementing mode. Otherwise, the string is
processed from the highest address towards the
lowest address, i.e. auto-decrementing mode.

O-Overflow Flag: This flag is set, if an overflow III. Segment registers

occurs, i.e. if the result of a signed operation is
large enough to be accommodated in a destination
register.
For example, in case of the addition of two signed numbers, if the result overflows into
the sign bit, i.e. the result is of more than 7-bits in size in case of 8-bit signed
operations and more than 15-bits in size in case of 16-bit signed operations, and then
the overflow flag will be set.
OF = C7 XOR C6 (for 8-bit signed operations)
= C15 XOR C14 (for 16-bit signed operations)
 The BIU sends out 20-bit addresses, so it can address any of
220(1,048,576 or 1Mb)bytes of memory.
 However, at any given time the 8086 works with only four
segments(each 216 or 64-Kbyte) within the 1Mbyte) range.
 Code segment: a region for storing instruction codes,
 Data segment : a region for string Data,
 Stack segment: a region for store Stack.
=> A stack is a section of memory set aside to store addresses
and data while a subprogram executes
 Extra segment: a region for storing data

 Four segment registers in the BIU are used to hold the upper
16 bits of the starting addresses of the four memory
segments the 8086 is working currently.
 These are (CS), the stack segment (SS), the extra segment
(ES) and the data segment (DS) registers.

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The figure shows an example of
segmentation of the main memory at a
given instance.
For example if the code segment
register contains 348AH, then the
code segment will start at address
348A0H.
In other words, a 64-Kbyte segment
can be located anywhere within the
1- Mbyte address space,
Example: IF currently the content of CS=348A and IP=4214, then find
the physical address where the BIU is currently fetching instruction and
data from within the main memory.
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IV. Instruction pointer (IP) register
 This holds the 16-bit offset within the code segment address
(vertical displacement from the base of Code segment) of the
next code byte to be fetched.
 This offset value will be added to the segment base address in
CS to produce the required 20-bit physical address sent out by
the BIU.
How a physical address is generated from segment base and
offset addresses?
The content of a segment register(segment address) is shifted left
bit-wise four times and to this result, content of an offset register
(offset address) is added, to produce a 20-bit physical
address. This 20 bit physical address is sent out through the
address bus to fetch data or instruction from the main memory.
An alternative way of representing a 20-bit physical address is
the segment base : offset form.
For the address of a code byte, the format for this alternative
form will be CS:IP.
Point Summary
The CS register contains the upper 16 bits of the starting
address of the code segment in the 1-Mbyte address range
of the 8086. The instruction pointer register contains a
16-bit offset, which tells where in that 64-Kbyte code
segment the next instruction byte is to be fetched from.
The actual physical address sent to memory is produced
by adding the offset contained in the IP register to the
segment base represented by the upper 16 bits in the CS
register. Any time the 8086 accesses memory, the BIU
produces the required 20-bit physical address by adding
an offset to a segment base value represented by the
contents of one of the segment registers.
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V. Stack segment register and stack pointer register VI. Pointer and index registers
 A stack is a section of memory set aside to store The EU contains a 16-bit base pointer (BP), a 16-bit
addresses and data while a subprogram is executing. source index (SI) and a 16- bit destination Index
 The 8086 allow you to set aside an entire 64-Kbyte (DI) registers.
segment as a stack. These are used to hold the 16-bit offset of a data
 The upper 16 bits of the base address of this segment word in Data segment or Extra segment
are kept in the stack segment register.
These registers, of course, can be used as temporary
 The stack pointer (SP) register in the execution unit
holds the 16-bit offset from the base of the segment to storage of data like general purpose registers.
the particular memory slot where a word was most
recently stored on the stack.
 The memory location where a word was most recently
stored is called the top of stack.

Consider the following example Memory segmentation

 The 8086 has a 20-bit address bus so that it can address up to 1MB of
physical memory.
 However, it has segmented memory architecture. So, it can directly
address only 64KB of data at a time. I.e. a memory segment can start
at any of its 1M bytes of memory using a 16-bit base address.
 A single chunk of memory is known as a segment and hence the
phrase segmented memory architecture.
 Memory address is normally defined by their hexadecimal addresses.
So, in segmented memory address location is identified with a
segment and an offset address.
 The standard notation is segment:offset which is the logical address
where as the actual physical address is calculated by shifting the
segment address 4 bits (or one hexa) left and adding the result with the
offset address.

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But why we need segmented memory?

Segmented memory architecture in general ensures;
The segment: offset, scheme requires only a 16-bit
number to represent the base and offset addresses Multi User Operating Systems
Thus manipulate and store only 16-bit quantities instead Ease of Programming
of 20-bit quantities which makes an easier interface with
8- and 16-bit-wide memory boards and with the 16-bit Process Mobility in the Address Space
registers in the 8086. Multiprocessor Context switching
Protection across Processes
Different user's program can also be assigned a separate
set of logical segments for its code and data. Intra process protection: Separation of Code, Data
The user's program will contain offsets or displacements and Stack
from these segment bases. Segmentation, therefore makes
it easy to keep users’ programs and data separate from one Inter process protection
another, and segmentation makes it easy to switch from
one user's program to another user's program.

8086 Pin configuration

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 A15-A0 (Address Bus): These lines provide the address bits A0 to

A15 in the entire bus cycle. These need not be latched for obtaining a
stable valid address. These are active high and are tri stated during the
'acknowledge' cycles.
 M/IO: This pin is similar to M/IO pin of 8086, but it offers an 8085
compatible, memory/IO bus interface.
 S2,S1,S0, Status Lines These are the status lines which reflect the
type of operation, being carried out by the processor. They are
decoded to interpret the activities of the microprocessor as given in
the following table