Beruflich Dokumente
Kultur Dokumente
PD60213 revC
IR2114SS/ IR21141SS
IR2214SS/IR22141SS
The IR2114/21141/2214/IR22141 gate driver family is suited to drive a single Soft shutdown time (typ) 9.25 µsec
half bridge in power switching applications. The high gate driving capability (2A
source, 3A sink) and the low quiescent current enable bootstrap supply
techniques in medium power systems. These drivers feature full short circuit
Package
protection by means of the power transistor desaturation detection and manages
all the half-bridge faults by turning off smoothly the desaturated transistor
through the dedicated soft shut down pin, therefore preventing over-voltages and
reducing EM emissions. In multi-phase system IR2114/21141/2214/IR22141
drivers communicate using a dedicated local network (SY_FLT and FAULT/SD
signals) to properly manage phase-to-phase short circuits. The system controller
may force shutdown or read device fault state through the 3.3 V compatible
CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, 24-Lead SSOP
the control and power ground use dedicated pins enabling low-side emitter
current sensing as well. Undervoltage conditions in floating and low voltage
circuits are managed independently.
Typical connection
DC+
15 V VCC VB
HOP
LIN HON
SSDH
HIN
DSH
IR2214
DC BUS uP,
FAULT/SD
Motor
Control VS
(1200V) FLT_CLR
SY_FLT
LOP
LON
SSDL
DSL
VSS COM
DC-
1
IR2114/IR21141/IR2214/IR22141
2
IR2114/IR21141/IR2214/IR22141
comparator
VCC/VB internal
UV
signal
VCCUV/VBSUV
VSS/VS
schmitt
trigger
HIN/LIN/ internal
FLTCLR signal
10k
VSS
3
IR2114/IR21141/IR2214/IR22141
FAULT/SD fault/hold
SY_FLT internal signal
schmitt
trigger
VSS
VCC/VBS
100k active
bias
comparator
DSL/DSH internal
SSD signal
VDESAT 700k
COM/VS
4
IR2114/IR21141/IR2214/IR22141
200ns VCC/VB
oneshot
VOH
on/off
internal signal
LOP/HOP
on/off SSDL/SSDH
internal signal
VOL
RON,SSD
desat
internal signal
COM/VS
5
IR2114/IR21141/IR2214/IR22141
AC Electrical Characteristics
VCC = VBS = 15V, VS = VSS and TA = 25°C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn on propagation delay 220 440 660 VIN = 0 & 1
toff Turn off propagation delay 220 440 660 VS = 0 to 600V or
1200V
tr Turn on rise time (CLOAD=1nF) — 24 — HOP shorted to HON,
LOP shorted to LON,
tf Turn off fall time (CLOAD=1nF) — 7 — Figure 7
ton1 Turn on first stage duration time 120 200 280 Figure 8
tDESAT1 DSH to HO soft shutdown propagation delay at HO 2000 3300 4600
turn on VHIN= 1
tDESAT2 DSH to HO soft shutdown propagation delay after 1050 — — VDESAT = 15V,Fig.10
Blanking
tDESAT3 DSL to LO soft shutdown propagation delay at LO 2000 3300 4600
turn on VLIN = 1
tDESAT4 DSL to LO soft shutdown propagation delay after 1050 — — VDESAT = 15V,Fig.10
Blanking
tDS Soft shutdown minimum pulse width of desat 1000 — — Figure 9
tSS Soft shutdown duration period 5000 9250 13500 ns VDS=15V,Fig. 9
6
IR2114/IR21141/IR2214/IR22141
3.3V
HIN 50% 50%
LIN PW in
t off
t on tr tf
PW out
Ton1
Io1+
Io2+
3.3V
HIN/LIN
t DS
DSH/DSL 8V 8V
t SS
t DESAT
HO/LO
7
IR2114/IR21141/IR2214/IR22141
50% 50%
HIN
50%
LIN
8V 8V
DSH
8V 8V
DSL
FAULT/SD
FLTCLR
tDESAT1 tDESAT2 Turn_Off propagation Delay
LIN
HIN 50% 50%
DTH DTL
LO (LOP=LON) 50%
50%
MDT=DTH-DTL
8
IR2114/IR21141/IR2214/IR22141
Lead Assignments
HIN 1 24 DSH
LIN VB
FLT_CLR N.C.
SY_FLT HOP
FAULT/SD HON
24-Lead SSOP
SSOP24
VSS VS
SSDL SSDH
COM N.C.
LON N.C.
LOP N.C.
VCC N.C.
DSL 12 13 N.C.
Lead Definitions
Symbol Description
VCC Low side gate driver supply
VSS Logic Ground
HIN Logic input for high side gate driver outputs (HOP/HON)
LIN Logic input for low side gate driver outputs (LOP/LON)
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates fault
FAULT/SD condition. As an input, shuts down the outputs of the gate driver regardless HIN/LIN status.
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates SSD
SY_FLT sequence is occurring. As an input, an active low signal freezes both output status.
FLT_CLR Fault clear active high input. Clears latched fault condition (See figure 17)
LOP Low side driver sourcing output
LON Low side driver sinking output
DSL Low side IGBT desaturation protection input
SSDL Low side soft shutdown
COM Low side driver return
VB High side gate driver floating supply
HOP High side driver sourcing output
HON High side driver sinking output
DSH High side IGBT desaturation protection input
SSDH High side soft shutdown
VS High side floating supply return
9
IR2114/IR21141/IR2214/IR22141
SCHMITT
on/off
TRIGGER on/off (HS) on/off LATCH di/dt control HOP
HIN INPUT
Driver
INPUT OUTPUT LOCAL DESAT soft HON
LEVEL
SHOOT HOLD SHUTDOWN PROTECTION
SHIFTERS shutdown
THROUGH LOGIC LOGIC on/off (LS) desat
LIN PREVENTION SOFT SHUTDOWN
SSDH
(DT) Deadtime UV_VBS DETECT
DSH
Hard ShutDown
internal Hold
VS
UV_VCC
DETECT UV_VCC on/off
LOP
di/dt control
DesatHS
Driver
SSD HOLD soft LON
SY_FLT FAULT LOGIC LOCAL DESAT
PROTECTION shutdown
managemend
FAULT SD
FAULT/SD (See figure 14) SOFTSHUTDOWN SSDL
DesatLS
FLT_CLR DSL
VSS COM
State Diagram
Start-Up
Sequence
LT
_F
SY
FAULT
/SD
HO=LO=0 ShutDown
FA U
LT/S
D
INL
N/
HI
R
VCC
D
CL
/S
U
LT
T_
V_
UV_
U
FL
VB
FA
S
UnderVoltage UnderVoltage
FAULT VCC VBS
HO=LO=0 HO=0, LO=LIN
/LIN
DESAT UV_VCC
SY
HIN
EVENT
_F
L
C
T
_ VC
HO/LO=1 UV
UV_VBS
SD
FAU
T/
L
Soft H/ LT/S
UL
SY_
DS D
FA
ShutDown
FLT
Freeze
L
H/
DS
10
IR2114/IR21141/IR2214/IR22141
Logic Table
Under Voltage
Yes: V< UV threshold
INPUTS INPUT/OUTPUT No : V> UV threshold
X : don’t care
OUTPUTS
11
IR2114/IR21141/IR2214/IR22141
12
IR2114/IR21141/IR2214/IR22141
sensing
VB/Vcc diode
PreDriver
HOPH/L
ONE
on/off SHOT
(ton1)
HONH/L
tBL
Blanking
SSDH/L
Ron,ss
tss
RDSH/L
One Shot
DesatHS/LS
tDS
filter
DSH/L
desat
comparator VDESAT
VS/COM
SY_FLT
(external
hold)
FAULT/SD
(external hard
shutdown)
SET
Q S DesatHS
Q CLR
R DesatLS
UVCC
FLTCLR
The external sensing diode should have BV>600V after TBL, desaturation is detected and the driver
or 1200V and low stray capacitance (in order to will turn off.
minimize noise coupling and switching delays). Eligible desaturation signals initiate the Soft
The diode is biased by an internal pull-up resistor Shutdown sequence (SSD). While in SSD, the
RDSH/L (equal to VCC/IDS- or VBS/IDS- for IR2114 or output driver goes in high impedance and the SSD
IR2214) or by a dedicated circuit (see the active- pull-down is activated to turn off the IGBT through
bias section for IR21141 and IR22141). When VCE SSDH/L pin. The SY_FLT output pin (active low,
increases, the voltage at DSH/L pin increases too. see figure 14) reports the gate driver status all the
Being internally biased to the local supply, DSH/L way long SSD sequence lasts (tSS). Once finished
voltage is automatically clamped. When DSH/L SSD, SYS_FLT releases, and the gate driver
exceeds the VDESAT+ threshold the comparator generates a FAULT signal (see the FAULT/SD
triggers (see figure 13). Comparator output is section) by activating FAULT/SD pin. This
filtered in order to avoid false desaturation generates a hard shut down for both high and low
detection by externally induced noise; pulses output stages (HO=LO=low). Each driver is latched
shorter than tDS are filtered out. To avoid detecting low until the fault is cleared (see FLT_CLR).
a false desaturation during IGBT turn on, the Figure 14 shows the fault management circuit. In
desaturation circuit is disabled by a Blanking signal this diagram DesatHS and DesatLS are two
(TBL, see Blanking block in figure 13). This time is internal signals that come from the output stages
the estimated maximum IGBT turn on time and (see figure 13).
must be not exceeded by proper gate resistance It must be noted that while in Soft Shut Down, both
sizing. When the IGBT is not completely saturated Under Voltage fault and external Shut Down (SD)
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IR2114/IR21141/IR2214/IR22141
are masked until the end of SSD. Desaturation 3. FAULT/SD is externally driven low either
protection is working independently by the other from the controller or from another
entire control pin and it is disabled only when the IR2x14x device. This event is not latched;
output status is off. therefore the FLT_CLR cannot disable it.
Only when FAULT/SD becomes high the
device returns in normal operating mode.
FAULT
5 Active bias
VCC
LIN
VB
HOP
VCC
LIN
VB
HOP
VCC
LIN
VB
HOP
For the purpose of sensing the power transistor
HIN
FLT_CLR
HON
SSH
HIN
FLT_CLR
HON
SSH
HIN
FLT_CLR
HON
SSH
desaturation the collector voltage is read by an
external HV diode. The diode is normally biased by
DSH DSH DSH
IR2214
IR2214
IR2214
SY_FLT SY_FLT SY_FLT
VS VS VS
FAULT/SD
LOP
LON
FAULT/SD
LOP
LON
FAULT/SD
LOP
LON
an internal pull up resistor connected to the local
SSL
DSL
SSL
DSL
SSL
DSL supply line (VB or VCC). When the transistor is “on”
the diode is conducting and the amount of current
VSS COM VSS COM VSS COM
100K ohm
14
IR2114/IR21141/IR2214/IR22141
At turn off, a single n-channel sinks up to 3A (IO-)
6 Output stage and offers a low impedance path to prevent the
self-turn on due to the parasitic Miller capacitance
The structure is shown in figure 13 and consists of
in the power switch.
two turns on stages and one turn off stage.
When the driver turns on the IGBT (see figure 8), a
first stage is constantly activated while an 7 Timing and logic state diagrams
additional stage is maintained active only for a description
limited time (ton1). This feature boost the total The following figures show the input/output logic
driving capability in order to accommodate both diagram.
fast gate charge to the plateau voltage and dV/dt Figure 17 shows the SY_FLT and FAULT/SD
control in switching. signals as output, whereas figure 18 as input.
A B C D E F G
HIN
LIN
DSH
DSL
SY_FLT
FAULT/SD
FLT_CLR
HO(HOP/HON)
LO(LOP/LON)
Figure 17: I/O timing diagram with SY_FLT and FAULT/SD as output
A B C D E F
HIN
LIN
SY_FLT
FAULT/SD
FLT_CLR
HO (HOP/HON)
LO (LOP/LON)
Figure 18: I/O logic diagram with SY_FLT and FAULT/SD as input
Referred to timing diagram of figure 17: SY_FLT goes high the FAULT/SD goes
A. When the input signals are on together low. While in SSD, if LIN goes up, LO
the outputs go off (anti-shoot through). does not change (freeze).
B. The HO signal is on and the high side C. When FAULT/SD is latched low (see
IGBT desaturates, the HO turn off softly FAULT/SD section) FLT_CLR can disable
while the SY_FLT stays low. When
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IR2114/IR21141/IR2214/IR22141
it and the outputs go back to follow the
inputs. This method has the advantage of being simple
D. The DSH goes high but this is not read and low cost but may force some limitations on
because HO is off. duty-cycle and on-time since they are limited by
E. The LO signal is on and the low side the requirement to refresh the charge in the
IGBT desaturates, the low side behaviour bootstrap capacitor.
is the same as described in point B. Proper capacitor choice can reduce drastically
F. The DSL goes high but this is not read these limitations.
because LO is off.
G. As point A (anti-shoot through). Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is to
Referred to timing diagram figure 18: establish the minimum voltage drop (∆VBS) that
A. The device is in hold state, regardless of we have to guarantee when the high side IGBT is
input variations. Hold state is forced by on.
SY_FLT forced low externally If VGEmin is the minimum gate emitter voltage we
B. The device outputs goes off by hard want to maintain, the voltage drop must be:
shutdown, externally commanded. A
through B is the same sequence adopted ∆VBS ≤ VCC − VF − VGE min − VCEon
by another IR2x14x device in SSD
procedure.
C. Externally driven low FAULT/SD under the condition:
(shutdown state) cannot be disabled by
forcing FLT_CLR (see FAULT/SD VGE min > VBSUV −
section).
D. The FAULT/SD is released and the where VCC is the IC voltage supply, VF is bootstrap
outputs go back to follow the inputs. diode forward voltage, VCEon is emitter-collector
E. Externally driven low FAULT/SD: outputs voltage of low side IGBT and VBSUV- is the high-
go off by hard shutdown (like point B). side supply undervoltage negative going
F. As point A and B but for the low side threshold.
output.
Now we must consider the influencing factors
contributing VBS to decrease:
Sizing tips
− IGBT turn on required Gate charge (QG);
− IGBT gate-source leakage current (ILK_GE);
Bootstrap supply
− Floating section quiescent current (IQBS);
− Floating section leakage current (ILK)
The VBS voltage provides the supply to the high − Bootstrap diode leakage current (ILK_DIODE);
side driver circuitry of the gate driver. This supply
− Desat diode bias when on (IDS- )
sits on top of the VS voltage and so it must be
− Charge required by the internal level shifters
floating.
(QLS); typical 20nC
The bootstrap method to generate VBS supply can
be used with any of the IR2114, IR21141, − Bootstrap capacitor leakage current
IR2214, IR22141. The bootstrap supply is formed (ILK_CAP);
by a diode and a capacitor connected as in figure − High side on time (THON).
19.
ILK_CAP is only relevant when using an electrolytic
bootstrap bootstrap
capacitor and can be ignored if other types of
resistor diode DC+
capacitors are used. It is strongly recommend
Rboot
VF using at least one low ESR ceramic capacitor
(paralleling electrolytic and low ESR ceramic may
VCC VB
result in an efficient solution).
VCC
HOP
bootstrap
HON
VBS
capacitor VGE
Then we have:
IR2214
ILOAD
motor
VS
QTOT = QG + Q LS + ( I LK _ GE + I QBS +
SSDH
COM
The minimum size of bootstrap capacitor is:
16
IR2114/IR21141/IR2214/IR22141
17
IR2114/IR21141/IR2214/IR22141
Gate resistances
18
IR2114/IR21141/IR2214/IR22141
NOTICE: Turn on time must be lower than TBL to As a result, when τ is faster than the collector rise
avoid improper desaturation detection and SSD time (to be verified after calculation) the transfer
triggering. function can be approximated by:
HS Turning ON
dV/dt
Vth
RGoff < − RDRn
dV
CRESoff
CRESoff ⋅
dt
RGoff
OFF
In any case, the worst condition for unwanted turn
ON on is with very fast steps on IGBT collector.
RDRn C IES In that case collector to gate transfer function can
be approximated with the capacitor divider:
CRESoff
Vge = Vde ⋅
Figure 22: RGoff sizing: current path when Low (CRESoff + CIES )
Side is off and High Side turns on which is driven only by IGBT characteristics.
The transfer function between IGBT collector and As an example, table 3 reports RGoff (calculated
IGBT gate then becomes: with the above mentioned disequation) for two
popular IGBTs to withstand dVout/dt = 5V/ns.
Vge s ⋅ ( RGoff + RDRn ) ⋅ CRESoff
= NOTICE: the above-described equations are
Vde 1 + s ⋅ ( RGoff + RDRn ) ⋅ (CRESoff + CIES )
intended being an approximated way for the gate
resistances sizing. More accurate sizing may
Which yields to a high pass filter with a pole at: account more precise device modelling and
1 parasitic component dependent on the PCB and
1/τ = power section layout and related connections.
( RGoff + RDRn ) ⋅ (CRESoff + CIES )
19
IR2114/IR21141/IR2214/IR22141
b)
IGC
VB/ VCC
gate
resistance CGC
H/LOP
H/LON
SSDH/L
Gate Drive VGE
Loop
VS/COM
c)
Figure 23: gate drive loop
Figure 24: layout example: top (a), bottom (b) and
Supply capacitors: ground plane (c) layer
IR2x14x output stages are able to quickly turn on
IGBT with up to 2 A of output current. The supply Referred to figure 24:
capacitors must be placed as close as possible to Bootstrap section: R1, C1, D1
the device pins (VCC and VSS for the ground tied High side gate: R2, R3, R4
supply, VB and VS for the floating supply) in order High side Desat: D2
to minimize parasitic inductance/resistance. Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
20
IR2114/IR21141/IR2214/IR22141
Case Outline
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been designed and qualified for industrial market
Data and specifications subject to change without notice. 3/24/2005
21