Hot Features of OSN 1832 01 - Planning

Hot Features of OSN 1832
Issue 01
Date 2018-08-30
HUAWEI TECHNOLOGIES CO., LTD.

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Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. i

Hot Features of OSN 1832 Contents
Contents
1 Change History.............................................................................................................................. 1
2 WDM/OTN Clock Feature .......................................................................................................... 2
2.1 About This Document.................................................................................................................................................... 3
2.2 Why Does the WDM/OTN Network Need Clock Synchronization?.............................................................................4
2.3 Clock Synchronization Requirements of Service Networks.......................................................................................... 6
2.4 Frequency Synchronization Solutions............................................................................................................................ 8
2.5 Phase Synchronization Solutions..................................................................................................................................10
2.6 E2E WDM/OTN Clock Solution..................................................................................................................................12
2.7 Physical Clocks (OTN & Packet & SDH)....................................................................................................................12
2.7.1 Introduction of Physical Clocks (OTN & Packet & SDH)........................................................................................12
2.7.2 Principles................................................................................................................................................................... 14
2.7.2.1 Building the Master-Slave Clock Hierarchy...........................................................................................................14
2.7.2.2 Clock Protection..................................................................................................................................................... 15
2.7.2.2.1 Stop SSM Protocol and Start Standard SSM Protocol........................................................................................ 16
2.7.2.2.2 Start Extended SSM Protocol and Clock Source ID........................................................................................... 17
2.7.2.3 Clock Source Interface........................................................................................................................................... 19
2.7.2.4 Synchronous Ethernet.............................................................................................................................................22
2.7.3 Dependencies and Limitations...................................................................................................................................24
2.7.3.1 Limitations on the Physical Clocks Feature........................................................................................................... 24
2.7.3.2 Affected Features....................................................................................................................................................28
2.7.3.3 Mutually Exclusive Features.................................................................................................................................. 28
2.7.4 Configuring Physical Clock (OSN 1832/8800/9800 Universal Platform Subrack/M Series Subrack).................... 28
2.7.4.1 Configuration Process.............................................................................................................................................29
2.7.4.2 Configuring the Frequency Source Mode.............................................................................................................. 30
2.7.4.3 Configuring Clock Attributes of Boards to Implement Synchronous Frequency Synchronization....................... 31
2.7.4.4 Configuring External Clock Ports.......................................................................................................................... 33
2.7.4.5 Configuring Clock Attributes................................................................................................................................. 35
2.7.4.6 Configuring the Clock Source Protection...............................................................................................................40
2.7.4.7 Viewing Clock Synchronization Status.................................................................................................................. 42
2.7.4.8 Viewing the Clock Tracing Status.......................................................................................................................... 43
2.7.4.9 Configuring Clock Source Switching.....................................................................................................................43
2.7.4.10 Configuring Clock Attributes of Boards to Implement Synchronous Ethernet Transparent Transmission......... 45
2.7.4.11 Configuring the ST2/AST2 Board to Transparent Transmission of Clock Information...................................... 46
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2.7.4.12 Parameters: Physical Clock (OSN 1832/8800/9800 Universal Platform Subrack/M Series Subrack)................ 47
2.7.4.12.1 Parameters: Frequency Source Mode................................................................................................................ 48
2.7.4.12.2 Parameters: Clock Attribute Configuration....................................................................................................... 48
2.7.4.12.3 Parameters: Clock Port Link..............................................................................................................................51
2.7.4.12.4 Parameters: System Clock Source Priority List................................................................................................ 52
2.7.4.12.5 Parameters: Priority for PLL Clock Sources of 1st External Output................................................................ 54
2.7.4.12.6 Parameters: Priority for PLL Clock Sources of 2nd External Output............................................................... 56
2.7.4.12.7 Parameters: Clock Subnet..................................................................................................................................59
2.7.4.12.8 Parameters: Clock Source Quality.....................................................................................................................62
2.7.4.12.9 Parameters: Manual Setting of Quality Level 0................................................................................................ 64
2.7.4.12.10 Parameters: SSM Output Control.................................................................................................................... 65
2.7.4.12.11 Parameters: Clock ID Status............................................................................................................................ 66
2.7.4.12.12 Parameters: Clock Source Reversion Parameter............................................................................................. 67
2.7.4.12.13 Parameters: Clock Source Switching.............................................................................................................. 68
2.7.4.12.14 Parameters: Clock Synchronization Status......................................................................................................69
2.7.4.12.15 Parameters: Clock Source Switching Conditions............................................................................................ 74
2.7.4.12.16 Parameters: Phase-Locked Source Output by External Clock........................................................................ 76
2.7.4.12.17 Parameters: Clock Signal Pass-through...........................................................................................................82
2.7.5 Configuring Physical Clocks (OSN 9800 U Series: U1CTU/S1CTU)..................................................................... 82
2.7.5.1 Configuration Process.............................................................................................................................................82
2.7.5.2 Configuring Transport Clock Attributes of Boards................................................................................................ 84
2.7.5.3 Configuring External Clock Ports.......................................................................................................................... 85
2.7.5.4 Configuring Clock Attributes................................................................................................................................. 86
2.7.5.5 Configuring the Clock Source Protection...............................................................................................................89
2.7.5.6 Viewing Clock Synchronization Status.................................................................................................................. 91
2.7.5.7 Viewing the Clock Tracing Status.......................................................................................................................... 91
2.7.5.8 Configuring Clock Source Switching.....................................................................................................................92
2.7.5.9 Configuring OTUs or Tributary Boards to Implement Synchronous Ethernet Transparent Transmission............ 93
2.7.5.10 Parameters: Physical Clocks (OSN 9800 U Series: U1CTU/S1CTU)................................................................. 94
2.7.5.10.1 Parameters: System Clock Source Priority List................................................................................................ 94
2.7.5.10.2 Parameters: Priority for PLL Clock Sources of 1st External Output................................................................ 95
2.7.5.10.3 Parameters: Priority for PLL Clock Sources of 2nd External Output............................................................... 96
2.7.5.10.5 Parameters: Clock Source Quality...................................................................................................................100
2.7.5.10.6 Parameters: Clock Source Reversion Parameter............................................................................................. 101
2.7.5.10.7 Parameters: Clock Source Switching.............................................................................................................. 102
2.7.5.10.8 Parameters: Clock Synchronization Status......................................................................................................103
2.7.5.10.9 Parameters: Phase-Locked Source Output by External Clock........................................................................ 105
2.7.6 Physical Clock Capability of Huawei WDM/OTN Networks.................................................................................107
2.7.6.1 Availability........................................................................................................................................................... 107
2.7.6.1.1 OSN 9800 Universal Platform Subrack Hardware and Version Support.......................................................... 108
2.7.6.1.2 OSN 9800 U Series Hardware and Version Support......................................................................................... 108
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2.7.6.1.3 OSN 9800 M Series Hardware and Version Support.........................................................................................110

2.7.6.1.4 OSN 8800 Hardware and Version Support........................................................................................................ 111
2.7.6.1.5 OSN 6800 Hardware and Version Support........................................................................................................ 114
2.7.6.1.6 OSN 1832 X16 Hardware and Version Support................................................................................................ 115
2.7.6.1.7 OSN 1832 X8 Enhanced Hardware and Version Support................................................................................. 118
2.7.6.2 Physical Clocks Specifications............................................................................................................................. 121
2.7.6.3 Feature Updates.................................................................................................................................................... 122
2.7.6.3.1 OSN 9800 Feature Updates............................................................................................................................... 122
2.7.6.3.2 OSN 8800&6800 Feature Updates.................................................................................................................... 123
2.7.7 Standard and Protocol Compliance......................................................................................................................... 129
2.8 IEEE 1588v2 (OTN & Packet)................................................................................................................................... 129
2.8.1 Introduction of IEEE 1588v2 (OTN & Packet).......................................................................................................129
2.8.2 Principles................................................................................................................................................................. 130
2.8.2.1 Building the Master-Slave Clock Hierarchy.........................................................................................................130
2.8.2.2 IEEE 1588v2 Clock Architecture......................................................................................................................... 131
2.8.2.3 Clock Subnet and Clock ID in IEEE 1588v2....................................................................................................... 132
2.8.2.4 Time Source Interface...........................................................................................................................................133
2.8.2.5 BMC Algorithm....................................................................................................................................................137
2.8.2.6 Delay Correction...................................................................................................................................................138
2.8.2.7 IEEE 1588v2-Compliant Phase Synchronization.................................................................................................139
2.8.2.8 IEEE 1588v2-Compliant Frequency Synchronization......................................................................................... 141
2.8.3 Dependencies and Limitations.................................................................................................................................142
2.8.3.1 Limitations on the IEEE 1588v2 Feature............................................................................................................. 142
2.8.3.2 Affected Features..................................................................................................................................................147
2.8.3.3 Mutually Exclusive Features................................................................................................................................ 148
2.8.4 Configuring IEEE 1588v2 Clock (OSN 1832/8800/9800 Universal Platform Subrack/M Series Subrack).......... 149
2.8.4.1 Configuration Process...........................................................................................................................................149
2.8.4.2 Enabling IEEE 1588v2......................................................................................................................................... 151
2.8.4.3 Configuring PTP NEs........................................................................................................................................... 152
2.8.4.4 Configuring PTP Ports..........................................................................................................................................157
2.8.4.5 Configuring External Time Ports..........................................................................................................................162
2.8.4.6 Viewing Port Status.............................................................................................................................................. 165
2.8.4.7 Viewing the Clock Tracing Status........................................................................................................................ 166
2.8.4.8 Parameters: IEEE 1588v2 (OSN 1832/8800/9800 Universal Platform Subrack/M Series Subrack)...................167
2.8.4.8.3 Parameters: Clock Synchronization Attribute................................................................................................... 169
2.8.4.8.4 Parameters: Clock Source at Port...................................................................................................................... 183
2.8.4.8.5 Parameters: PTP Clock Subnet..........................................................................................................................184
2.8.4.8.6 Parameters: BMC (Clock Subnet)..................................................................................................................... 185
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2.8.4.8.7 Parameters: Basic Attribute............................................................................................................................... 189

2.8.4.8.8 Parameters: BMC (External Time Interface).....................................................................................................190
2.8.4.8.9 Parameters: Cable Transmitting Distance..........................................................................................................194
2.8.4.8.10 Parameters: MAC Address Configuration.......................................................................................................197
2.8.5 Configuring a IEEE 1588v2 Clock (OSN 9800 U Series: U1CTU/S1CTU).......................................................... 198
2.8.5.2 Enabling IEEE 1588v2......................................................................................................................................... 200
2.8.5.6 Querying the Clock Source Received at the Port................................................................................................. 212
2.8.5.8 Parameters: IEEE 1588v2 (OSN 9800 U Series: U1CTU/S1CTU)..................................................................... 213
2.8.6 IEEE 1588v2 Clock Capability of Huawei WDM/OTN Networks........................................................................ 233
2.8.6.1 Availability........................................................................................................................................................... 233
2.8.6.1.1 License Support................................................................................................................................................. 233
2.8.6.1.3 OSN 9800 U series Hardware and Version Support..........................................................................................233
2.8.6.1.4 OSN 9800 M Series Hardware and Version Support........................................................................................ 235
2.8.6.1.5 OSN 8800 Hardware and Version Support........................................................................................................236
2.8.6.2 IEEE 1588v2 Specifications................................................................................................................................. 243
2.8.6.3 Feature Updates.................................................................................................................................................... 245
2.9 ITU-T G.8275.1/G.8273.2 (OTN & Packet).............................................................................................................. 250
2.9.1 Introduction of ITU-T G.8275.1/G.8273.2 (OTN & Packet).................................................................................. 250
2.9.2 Principles................................................................................................................................................................. 252
2.9.2.1 Establishing the Master/Slave Clock Structure.................................................................................................... 252
2.9.2.2 Time Source Interface...........................................................................................................................................254
2.9.2.3 ITU-T G.8275.1 Time Synchronization Principles.............................................................................................. 258
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2.9.2.4 ITU-T G.8275.1 Frequency Synchronization Principles......................................................................................260

2.9.2.5 Alternative BMC algorithm..................................................................................................................................261
2.9.3 Dependencies and Limitations.................................................................................................................................263
2.9.3.1 Limitations on the ITU-T G.8275.1 Feature.........................................................................................................263
2.9.3.2 Affected Features..................................................................................................................................................268
2.9.3.3 Mutually Exclusive Features................................................................................................................................ 268
2.9.4 Configuring ITU-T G.8275.1 Clock (OSN 1832/8800/9800 Universal Platform Subrack/M Series Subrack)......268
2.9.4.2 Configuring the PTP Protocol.............................................................................................................................. 270
2.9.4.3 Enabling ITU-T G.8275.1.................................................................................................................................... 271
2.9.4.7 Viewing the Port Status........................................................................................................................................ 282
2.9.4.9 Parameters: ITU-T G.8275.1 (OSN 1832/8800/9800 Universal Platform Subrack/M Series Subrack).............. 284
2.9.4.9.1 Parameters: PTP Protocol.................................................................................................................................. 284
2.9.4.9.6 Parameters: PTP Clock Subnet..........................................................................................................................293
2.9.4.9.10 Parameters: Cable Transmitting Distance........................................................................................................301
2.9.4.9.11 Parameters: MAC Address Configuration.......................................................................................................304
2.9.5 Configuring ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/S1CTU)...................................................................305
2.9.5.2 Configuring the PTP Protocol.............................................................................................................................. 307
2.9.5.3 Enabling ITU-T G.8275.1.................................................................................................................................... 307
2.9.5.7 Querying the Port Status.......................................................................................................................................317
2.9.5.9 Parameters: ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/S1CTU)................................................................ 318
2.9.5.9.1 Parameters: Global Configuration..................................................................................................................... 319
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2.9.6 ITU-T G.8275.1/G.8273.2 Clock Capability of Huawei WDM/OTN Networks....................................................335
2.9.6.1 Availability........................................................................................................................................................... 335
2.9.6.1.1 License Support................................................................................................................................................. 335
2.9.6.1.3 OSN 9800 U Series Hardware and Version Support......................................................................................... 336
2.9.6.1.4 OSN 9800 M Series Hardware and Version Support........................................................................................ 337
2.9.6.2 ITU-T G.8275.1/G.8273.2 Specifications............................................................................................................ 346
2.9.6.3 Feature Updates.................................................................................................................................................... 348
3 L1 Service Encryption Feature.................................................................................................352

3.1 About This Document................................................................................................................................................ 353
3.2 Why Does a WDM/OTN Network Need to Be Encrypted?.......................................................................................354
3.3 Application Scenarios of L1 Service Encryption....................................................................................................... 356
3.4 Encryption Features of OSN Equipment.................................................................................................................... 359
3.5 Principle of L1 Service Encryption............................................................................................................................ 361
3.5.1 Components of the L1 Service Encryption System.................................................................................................361
3.5.2 Security of the L1 Service Encryption System........................................................................................................363
3.5.3 Encryption Process for Bidirectional Services........................................................................................................ 364
3.5.4 Encryption Process for Unidirectional Services...................................................................................................... 369
3.6 Encryption Dependencies and Limitations.................................................................................................................373
3.6.1 Limitations on the Encryption Feature.................................................................................................................... 373
3.6.2 Affected Features.....................................................................................................................................................375
3.6.3 Mutually Exclusive Features................................................................................................................................... 375
3.6.4 Limitations on SMT.................................................................................................................................................376
3.7 Configuring Encryption Using the U2000 and SMT..................................................................................................376
3.7.1 Configuration Process..............................................................................................................................................377
3.7.2 Authorizing an Encryption Administrator Account on the U2000..........................................................................378
3.7.2.1 Setting Licenses.................................................................................................................................................... 378
3.7.2.2 Creating an Encryption Administrator Account................................................................................................... 379
3.7.2.3 Allocating Encryption Ports to Encryption Administrator Accounts................................................................... 381
3.7.3 Configuring Service Encryption on the SMT..........................................................................................................382
3.7.3.1 Logging In to the SMT......................................................................................................................................... 382
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3.7.3.2 Creating and Logging In to an NE........................................................................................................................384

3.7.3.3 Performing EMK Authentication......................................................................................................................... 386
3.7.3.4 Encrypting Bidirectional P2P Services.................................................................................................................388
3.7.3.4.1 Creating Bidirectional P2P Services..................................................................................................................388
3.7.3.4.2 Configuring Bidirectional P2P Encryption........................................................................................................389
3.7.3.5 Encrypting Unidirectional Static P2P/P2MP Services......................................................................................... 391
3.7.3.5.1 Creating Unidirectional Static P2P/P2MP Services.......................................................................................... 391
3.7.3.5.2 Setting a Customer Key..................................................................................................................................... 392
3.7.3.5.3 Configuring Unidirectional Static P2P/P2MP Service Encryption................................................................... 395
3.7.3.6 Encrypting Dynamic Group Services................................................................................................................... 396
3.7.3.6.1 Creating a Dynamic Group................................................................................................................................396
3.7.3.6.2 Setting a Customer Key..................................................................................................................................... 397
3.7.3.6.3 Enabling the Encryption Feature of a Dynamic Group..................................................................................... 398
3.7.4 Maintaining Service Encryption on the SMT..........................................................................................................398
3.7.4.1 Encryption Sub-account Management..................................................................................................................399
3.7.4.1.1 Creating an Encryption Sub-account................................................................................................................. 399
3.7.4.1.2 Allocating Encryption Ports to Encryption Sub-accounts................................................................................. 401
3.7.4.2 Setting the Port Maintenance Status..................................................................................................................... 402
3.7.4.3 Modify Encryption Services................................................................................................................................. 402
3.7.4.3.1 Modifying Unidirectional Static P2P/P2MP Services.......................................................................................402
3.7.4.3.2 Modifying a Dynamic Group............................................................................................................................ 404
3.7.4.4 Querying Port Encryption Status and Information............................................................................................... 405
3.7.4.5 Setting Port Encryption Status and Information...................................................................................................407
3.7.4.6 Querying Logs...................................................................................................................................................... 408
3.7.5 FAQ..........................................................................................................................................................................409
3.7.5.1 How Can I Handle a Failure of Logging In to an NE from the SMT?................................................................. 409
3.7.5.2 How Can I Handle EMK Lockout?...................................................................................................................... 410
3.7.5.3 What Can I Do When the EMK Is Forgotten?..................................................................................................... 410
3.7.5.4 Troubleshooting Encryption Services...................................................................................................................411
3.7.6 Parameter Description..............................................................................................................................................411
3.7.6.1 Parameter Description for U2000.........................................................................................................................412
3.7.6.2 Parameter Description for SMT........................................................................................................................... 413
3.8 Encryption Capability of Huawei WDM/OTN Networks.......................................................................................... 418
3.8.1 Availability.............................................................................................................................................................. 418
3.8.1.1 Required License.................................................................................................................................................. 419
3.8.1.2 Supported Hardware and Versions of the OSN 9800........................................................................................... 419
3.8.1.3 Supported Hardware and Versions of the OSN 8800/6800.................................................................................. 420
3.8.1.4 Supported Hardware and Versions of the OSN 1832........................................................................................... 421
3.8.2 Specifications...........................................................................................................................................................422
3.8.2.1 Overview.............................................................................................................................................................. 423
3.8.2.2 Encryption Capability of the OSN 9800...............................................................................................................423
3.8.2.3 Encryption Capability of the OSN 8800/6800..................................................................................................... 424
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3.8.2.4 Encryption Capability of the OSN 1832...............................................................................................................425

3.8.3 Feature Updates....................................................................................................................................................... 426
3.8.3.1 OSN 9800 Feature Updates.................................................................................................................................. 426
3.8.3.2 OSN 8800/6800 Feature Updates......................................................................................................................... 428
3.8.3.3 OSN 1832 Feature Updates.................................................................................................................................. 429
3.8.4 Reference Standards and Protocols......................................................................................................................... 431
Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. ix

Hot Features of OSN 1832 1 Change History
1 Change History
Updates between document issues are cumulative. Therefore, the latest document issue
contains all updates made in previous issues.
Updates in Issue 01 (2018-08-30)

This issue is the first official release.
Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. 1

Hot Features of OSN 1832 2 WDM/OTN Clock Feature
2 WDM/OTN Clock Feature
About This Chapter
To provide a synchronous clock source for mobile base stations, the entire WDM/OTN
transport network must support clock synchronization. This document describes the clock
functions of Huawei OSN series of WDM/OTN devices, including application scenarios,
technical principles, operation guide, and support capabilities of each device.
2.1 About This Document
The physical clock, IEEE 1588v2, and ITU-T G.8275.1/G.8273.2 features of the WDM/OTN
network support all-scenario, high-reliability, and high-performance clock synchronization
networks to provide clock synchronization for downstream devices.
2.2 Why Does the WDM/OTN Network Need Clock Synchronization?
transport network must support clock synchronization.
2.3 Clock Synchronization Requirements of Service Networks
2.4 Frequency Synchronization Solutions
This topic describes the implementation modes and typical application scenarios of frequency
synchronization.
2.5 Phase Synchronization Solutions
This topic describes the implementation methods and typical application scenarios of phase
synchronization.
2.6 E2E WDM/OTN Clock Solution
The following figure shows an example of the end-to-end (E2E) clock solution from the
access layer to the backbone layer.
2.7 Physical Clocks (OTN & Packet & SDH)
2.8 IEEE 1588v2 (OTN & Packet)
2.9 ITU-T G.8275.1/G.8273.2 (OTN & Packet)

2.1 About This Document

The physical clock, IEEE 1588v2, and ITU-T G.8275.1/G.8273.2 features of the WDM/OTN
network support all-scenario, high-reliability, and high-performance clock synchronization
networks to provide clock synchronization for downstream devices.
This document describes the clock functions of Huawei OSN series of WDM/OTN devices,
including application scenarios, technical principles, operation guide, and support capabilities
of each device.
Related Versions
The following table lists the product initial versions to which this document can be applied.
Product Name Initial Version
OSN 9800 V100R001C20
OSN 8800 V100R002C00
OSN 6800 V100R005C00
OSN 1832 V100R003C05
For details about the specifications of this feature supported by each product version, see
l Physical Clocks Feature Updates
l IEEE 1588v2 Feature Updates
l ITU-T G.8275.1/G.8273.2 Feature Updates
Intended Audience
This document is intended for:
l Network planning and design engineers

l Commissioning engineers
l Network monitoring engineers
l Data configuration engineers
l Network administrators
l Maintenance engineers
l Onsite maintenance engineers
Symbol Conventions
The symbols that may be found in this document are defined as follows.

Symbol Description
Indicates a hazard with a high level of risk, which if not

avoided, will result in death or serious injury.
Indicates a hazard with a medium or low level of risk, which

if not avoided, could result in minor or moderate injury.
Indicates a potentially hazardous situation, which if not

avoided, could result in equipment damage, data loss,
performance degradation, or unexpected results.
Indicates a tip that may help you solve a problem or save

time.
Provides additional information to emphasize or supplement

important points of the main text.
GUI Conventions
Convention Description
Boldface Buttons, menus, parameters, tabs, window, and dialog titles

are in boldface. For example, click OK.
> Multi-level menus are in boldface and separated by the ">"

signs. For example, choose File > Create > Folder.
Change History
Updates between document issues are cumulative. Therefore, the latest document issue
contains all updates made in previous issues.
Updates in Issue 01 (2018-08-30)

This issue is the first official release.
2.2 Why Does the WDM/OTN Network Need Clock

Synchronization?
transport network must support clock synchronization.

Mobile Backhaul Network Requires the WDM/OTN Network to Implement

Clock Synchronization
In a mobile backhaul network, clock synchronization must be strictly implemented between
base stations. Currently, there are multiple clock synchronization solutions in the industry,
such as GPS and IEEE 1588v2.
l Traditional GPS clock synchronization:
– High cost: Each base station must be configured with a GPS system.
– High failure rate: Each base station is configured with only one satellite card
(receiving GPS signals), which is not protected.
– Poor maintainability: If the GPS fails, you must replace the hardware onsite, and
remote maintenance cannot be performed.
l IEEE 1588v2 clock synchronization:
– Low cost: Only two GPS devices need to be configured to implement clock
synchronization on the entire network. The GPS system is not required for each
base station.
– High reliability: End-to-end clock protection can be configured.
– High maintainability: There is no construction restriction, deployment is simple,
and unified management is implemented using the NMS.
However, IEEE 1588v2 requires that all devices on a network support the IEEE 1588v2
protocol. Otherwise, the clock performance may not meet the high-precision clock
requirements of a wireless network if only simple transparent transmission of time is
implemented.
The WDM/OTN network itself does not need to implement clock synchronization. To provide
clock signals for a PTN/SDH network, the WDM/OTN network needs to obtain the active and
standby clock sources from the building integrated timing supply (BITS) system to implement
clock synchronization on the entire network.
The PTN/SDH network needs only to use the clock source of the WDM/OTN network to
implement clock synchronization, and then provides the clock source for base stations to
achieve synchronization.
SDH Modernization Requires the WDM/OTN Network to Implement Clock

Synchronization
With the advent of 4K video, LTE/LTE-A, and cloud era, the demand for high bandwidth is
strong. The network bandwidth of existing SDH devices is low and cannot satisfy the
development requirements of new services. In addition, SDH devices are old and have high
power consumption and OPEX. Therefore, carriers are in urgent need of reconstructing
networks to improve customer experience.
Huawei's MS-OTN solution inherits all SDH capabilities and implements unified transmission
of TDM/OTN/PKT services. It also features ultra-high bandwidth, simplified O&M, and
future-oriented smooth evolution. It is the best solution for SDH modernization.
The SDH network is a synchronous network. Therefore, when a WDM/OTN network is used
to replace the SDH network, SDH services are directly processed as a part of the SDH
network. Therefore, the WDM/OTN network must support clock synchronization.

Architecture of a WDM/OTN Clock Synchronous Network

A complete clock synchronous network consists of clock sources, transmission network, and
base stations. Huawei WDM/OTN devices are located in the transmission network.
l Clock source: Generally, master and slave clock/time source devices are configured on a
clock synchronous network. The clock sources are configured with different clock
quality and priorities to implement backup.
l Transmission network: Common topologies of a transmission network are ring, tree,
chain, and mesh. Ring topologies are recommended for transmission networks because a
synchronous network requires network protection. At the edge of the network, chain
topologies can be used.
l Base station: A radio transceiver station transmits information between a Node B and a
mobile terminal through a mobile communication center.
Figure 2-1 Architecture of the clock synchronous network
2.3 Clock Synchronization Requirements of Service

Networks
Clock synchronization includes both frequency synchronization and phase synchronization.
Frequency synchronization is the basis of phase synchronization. That is, the frequencies of
devices with synchronized phases are also synchronized.
l Frequency Synchronization: Frequency synchronization means that different signals

have the same number of pulses within the same time interval, so that all devices on the
communication network run at the same rate.

l Phase Synchronization: Phase synchronization means that not only signals have the same
number of pulses within the same time interval, but also the start time and end time of
each pulse are the same.
Figure 2-2 Frequency synchronization and Phase Synchronization
With the development of wireless networks such as LTE TDD and LTE FDD, service
networks, especially radio access networks (RANs), have strict requirements on clock
synchronization.
Table 2-1 Clock synchronization requirements of mobile communication networks
Wireless Required Required Recommended Synchronization Mode

Access Frequency Phase
Mode Synchroniz Synchron
ation ization
Precision Precision
GSM 0.05 ppm Phase Physical clocks

synchroniz
ation is not
required.
WCDMA 0.05 ppm Phase Physical clocks

synchroniz
ation is not
required.
TD-SCDMA 0.05 ppm ±1.5 µs Physical clocks+IEEE 1588v2/ITU-T G.

8275.1/G.8273.2
CDMA2000 0.05 ppm ±3 µs Physical clocks+IEEE 1588v2/ITU-T G.

8275.1/G.8273.2
WiMax FDD 0.05 ppm Phase Physical clocks

synchroniz
ation is not
required.

Wireless Required Required Recommended Synchronization Mode

Access Frequency Phase
Mode Synchroniz Synchron
ation ization
Precision Precision
WiMax TDD 0.011 ppm/ ±1 µs Physical clocks+IEEE 1588v2/ITU-T G.

3.5G, 7 8275.1/G.8273.2
carrier wave
LTE FDD 0.05 ppm Phase Physical clocks

synchroniz
ation is not
required.
LTE TDD 0.05 ppm ±1.5 µs Physical clocks+IEEE 1588v2/ITU-T G.

8275.1/G.8273.2
In addition to the communication network, billing systems and network management systems
also require phase synchronization. Table 2-2 lists the requirements of some common systems
on phase synchronization.
Table 2-2 Phase synchronization requirements of other common systems

System Required Phase Recommended
Synchronization Synchronization Mode
Precision
Billing system 500 ms IEEE 1588v2/ITU-T G.

8275.1/G.8273.2
Communication network 500 ms IEEE 1588v2/ITU-T G.

management system 8275.1/G.8273.2
Signaling system No.7 1 ms IEEE 1588v2/ITU-T G.

8275.1/G.8273.2
Positioning system 1 µs (equivalent to a IEEE 1588v2/ITU-T G.

positioning precision of 300 8275.1/G.8273.2
m)
2.4 Frequency Synchronization Solutions

This topic describes the implementation modes and typical application scenarios of frequency
synchronization.
Solution Comparison
WDM devices support the following frequency synchronization solutions. You are advised to
use the same solution on an entire WDM/OTN network.

l (Recommended) Physical clocks: Devices directly restore clock frequency signals from
physical signals. This mode requires the device hardware to support clock extraction. In
other words, the frequency can be synchronized on the entire network only when all
nodes on the network support physical clocks.
l IEEE 1588v2/ITU-T G.8275.1/G.8273.2: Frequency synchronization is implemented
based on the timestamp information of Sync messages. This mode involves frequency
prediction and correction, whose synchronization precision is lower than physical clocks.
In addition, the synchronization is implemented hop by hop, which requires that each
node in the synchronization network must support the IEEE 1588v2/ITU-T G.8275.1/G.
8273.2 function.
Table 2-3 frequency synchronization

Solution Description
Physical clock l The technology is mature and easy to implement.

l The performance is stable and reliable, and is not affected by
network load changes.
l Maintainability is good.
IEEE 1588v2 l The synchronization precision reaches the sub-microsecond level,

and the application scope is wide.
l Reliability is high, and cost is low.
l Maintainability is good.
ITU-T G.8275.1 l The advantages of IEEE 1588v2 are inherited.

l The scenario applies only to the telecommunications field.
l A new BMCA algorithm is defined to trace the shortest path and
prevent the clock from being traced reversely. The performance is
high.
ITU-T G.8273.2 l The advantages of G.8275.1 are inherited.

l The time synchronization performance of a single device is defined
systematically, including time deviation, noise margin, noise
transfer.
Frequency Source Input/Output

The WDM/OTN device is interconnected with the BITS or PTN device in the following ways
to implement frequency source input/output:
l (Recommended) 2M external clock interface: When the frequency source needs to be
obtained from the BITS or the clocks of the master and slave subracks need to be
cascaded, the frequency source can be obtained through the 2M external clock port.
l Ethernet interface: When the WDM/OTN device is interconnected with a PTN device, an
SDH device, or a router, you are advised to use an Ethernet interface to obtain the
frequency source.

Internal Frequency Synchronization of the WDM/OTN Network

l (Recommended) OSC mode: The optical supervisory channel (OSC) board is used to
transmit frequency information.
l ESC mode: The OTU board, tributary/line board, or packet service board is used to
transmit frequency information.
Typical Scenario
The following figure uses physical clocks as an example to describe the typical scenario of
frequency synchronization. In this scenario, all devices on the WDM/OTN network must
support physical clocks.
Figure 2-3 Networking of a typical scenario
2.5 Phase Synchronization Solutions

This topic describes the implementation methods and typical application scenarios of phase
synchronization.
Solution Comparison
WDM devices support the following phase synchronization solutions. You are advised to use
the same solution on an entire WDM/OTN network.
Frequency synchronization is the basis of phase synchronization. That is, the frequencies of
devices with synchronized phases are also synchronized.
Table 2-4 phase synchronization
(Recommended) Physical The synchronization precision is high, and the bandwidth

clock frequency usage is low.
synchronization+IEEE
1588v2 phase
synchronization

IEEE 1588v2 frequency This scenario features easy deployment and simple O&M.
and phase synchronization Compared with typical scenario (Physical clock frequency
synchronization+IEEE 1588v2 phase synchronization), the
scenario provides lower synchronization precision but
requires higher bandwidth usage.
Physical clock frequency The scenario applies only to the telecommunication field.
synchronization+ITU-T G. Compared with typical scenario (Physical clock frequency
8275.1/G.8273.2 phase synchronization+IEEE 1588v2 phase synchronization) Using
synchronization the BMCA algorithm, the Grandmaster that has the shortest
path can be traces, therefore providing higher synchronization
precision and preventing reverse tracing.
ITU-T G.8275.1/G.8273.2 The BMCA algorithm is used to prevent reverse tracing.

frequency and phase
synchronization
Phase Source Input/Output

The WDM/OTN device is interconnected with the BITS or PTN device in the following ways
to implement phase source input/output:
l (Recommended) 1PPS+TOD external time interface: When the phase source needs to be
obtained from the BITS or the master and slave time subracks need to be cascaded, the
1PPS+TOD external time port can be used to obtain the phase source.
l Ethernet interface: When the WDM/OTN device is interconnected with a PTN device, an
SDH device, or a router, you are advised to use an Ethernet interface to obtain the phase
source.
Internal Phase Synchronization of the WDM/OTN Network

l (Recommended) OSC mode: The optical supervisory channel (OSC) board is used to
transmit phase information.
l ESC mode: The OTU board, tributary/line board, or packet service board is used to
transmit phase information.
Typical Scenario
The following figure uses physical clocks + IEEE 1588v2 as an example to describe the
typical scenario of phase synchronization. In this scenario, all devices on the WDM/OTN
network must support IEEE 1588v2.

Figure 2-4 Networking of a typical scenario
2.6 E2E WDM/OTN Clock Solution

The following figure shows an example of the end-to-end (E2E) clock solution from the
access layer to the backbone layer.
Figure 2-5 E2E clock networking diagram
2.7 Physical Clocks (OTN & Packet & SDH)
2.7.1 Introduction of Physical Clocks (OTN & Packet & SDH)

WDM/OTN devices support physical-layer clocks to implement frequency synchronization.
To implement phase synchronization, physical clocks must work with other features.

Description
In physical clock synchronization mode, WDM devices restore frequency signals from
physical signals such as Ethernet links, packet links, and SDH links to achieve frequency
synchronization of the upstream and downstream devices. Physical clocks require the device
hardware to support clock extraction. Therefore, each node must support physical-layer clocks
to achieve frequency synchronization on the entire network.
Application Scenario
Physical clocks can be used in the following scenarios:
l Physical clock (OTN): Supports synchronous Ethernet processing and synchronous
Ethernet transparent transmission to implement frequency synchronization.
– Synchronous Ethernet processing: The system clock performs frequency
synchronization for upstream NEs one by one. Synchronous Ethernet processing
can be used with IEEE 1588v2 to implement phase synchronization.
– Synchronous Ethernet transparent transmission: It only transmits the clock to the
destination node to guarantee clock quality. Internal free-run on the NE is
implemented, and frequency is not synchronized with the upstream NE.
Synchronous Ethernet transparent transmission cannot work with IEEE 1588v2 to
implement phase synchronization.
l Physical clock (packet): On a packet network, packet boards can be used to implement
frequency synchronization.
l Physical clock (SDH): In an SDH modernization scenario where the SDH network must
be synchronized, SDH boards can be used to implement frequency synchronization and
provide synchronization for base stations.

Figure 2-6 Physical clock scenarios
2.7.2 Principles
At the physical layer, clock reference information is transported to each control point with
high accuracy based on the master-slave relationship between nodes and the clock
synchronization mechanism.
2.7.2.1 Building the Master-Slave Clock Hierarchy

All NEs trace the same PRC through a specific clock synchronization path, thereby
implementing the network-wide synchronization.
Clock sources can be traced correctly after physical clock synchronization is implemented in
master/slave synchronization mode. In this synchronization mode, each slave clock usually
needs to work in three modes, and clock source priorities must be specified manually to
ensure clocks are traced level by level. In addition, timing loops can be prevented by
expanding the synchronization status message (SSM) protocol, therefore ensuring
synchronization of physical clocks on the entire network.
Master/Slave Synchronization Mode

The physical clock synchronization mode supported by the WDM/OTN equipment is the
master/slave synchronization mode. In master/slave synchronization mode, clocks of various
levels are used. Clocks of each level are synchronized with clocks at higher levels. On a
network, clocks of the highest level are referred to as primary reference clocks (PRCs).
The main advantages of the master/slave synchronization mode are that the network is stable,
the networking is flexible, tree and star networking modes are applicable, the control is

simple, and the network capability of fighting against jitters is good. The main disadvantage is
that this mode is sensitive to faults of PRCs and transmission links. Once a PRC is faulty, the
entire network is affected. Hence, a PRC must have several backups to enhance reliability.
Working Mode of the Slave Clock

In master/slave synchronization mode, the slave clock can work in one of the following
modes:
l Tracing mode:
It is a normal working mode, indicating that the local clock is synchronized with the
PRC.
l Holdover mode:
When all external timing references are lost, the protection clock enters the holdover
mode. In this mode, the protection clock takes the timing reference from the frequency
information saved before a loss of timing reference signals.
l Free-run mode:
A slave clock works in free-run mode when the slave clock of an NE loses all external
timing references and memories, or when the holdover mode does not exist.
2.7.2.2 Clock Protection

The WDM/OTN equipment supports clock source protection based on priorities,
synchronization status message (SSM) protection, and extended SSM protection.
Physical clock synchronization supports selecting and switching a clock source under this
three SSM protocol modes.
l Stop SSM Protocol:
– When the SSM protocol is disabled, clock signals do not contain clock quality
information. Clocks are selected based on the specified clock source priorities. In
this mode, timing loops may result.
– This mode is used on a non-ring network with multiple clock sources. The clock
source is selected according to the clock source priority list.
l Start Standard SSM Protocol:
– When the standard SSM protocol is enabled, clock quality levels are used to prevent
timing loops.
– This mode is used on a non-ring network with multiple clock sources. The clock
signal carries quality information. It is used when the WDM/OTN device
interconnects with a third-party device.
l Start Extended SSM Protocol:
– When the extended SSM protocol is enabled, clock IDs are used to prevent timing
loops.
– This protocol is applicable only to a ring network. It is a Huawei proprietary
protocol and cannot be used when the WDM/OTN device interconnects with a
third-party device. If the extended SSM protocol is enabled on an NE, the standard
SSM protocol can be configured on the downstream NEs; however, it cannot be
configured on the NE if the standard SSM protocol is enabled on the upstream NEs.

2.7.2.2.1 Stop SSM Protocol and Start Standard SSM Protocol

The WDM/OTN equipment supports clock source protection based on priorities, stop SSM
protocol, and start standard SSM Protocol.
SSM Protocol Disabled

A clock priority table is the basis of clock selection and switching when the SSM protocol is
disabled. Each clock source listed in Figure 2-7 is assigned with a unique priority. NEs select
a clock with the highest priority from the priority table as their clock sources.
Figure 2-7 Clock priorities when the SSM protocol is disabled
Standard SSM Protocol Enabled

Priorities of clocks traced by the NEs on a common WDM/OTN network can be specified
manually to provide clock synchronization and protection. However, in some special OTN
networks, timing loops may be generated if only clock priorities are specified. To prevent
timing loops, users need to enable the standard SSM protocol.
Physical clocks can contain SSM bytes to determine the quality level of physical clocks.
Clock quality is identified by bit 5 to bit 8 in an SSM byte. A smaller value represents a
higher clock quality. Table 2-5 lists the meanings of the clock quality bits in an SSM byte.
As the standard SSM protocol contains clock quality information, an NE can automatically
select a clock with the highest quality and priority after the standard SSM protocol is enabled.
The quality level of a clock source can be specified manually according to Table 2-5. If the
quality level of the clock source is set to 0xff for an NE, clock quality is extracted
automatically. With the clock quality is set to 0xff, the NE selects a clock source among those
that are available based on the quality reported originally.
After the standard SSM protocol is enabled for an NE, automatic clock switching is
performed based on following principles:
l The NE takes precedence to select a clock source with the highest quality from the
specified clock priority table.
l If there are multiple clock sources with the highest quality, then the NE selects the clock
source with the highest priority from them.

l The NE broadcasts the quality level of the selected clock source to the downstream NEs
using S1 bytes. Meanwhile, the NE informs the upstream NEs of its clock quality using
other S1 bytes along the reverse synchronization path, telling the upstream NEs not to
synchronize to its clock.
Table 2-5 Meanings of bit values in an SSM message
SSM Code Quality Level
0x00 Do Not Use For Synchronization
0x02 G.811 Reference Clock
0x04 G.812 Transit Clock
0x08 G.812 Local Clock
0x0b Synchronous equipment timing source (SETS)
0x0f The clock signals are unavailable
0xff Automatic Extraction
2.7.2.2.2 Start Extended SSM Protocol and Clock Source ID

The WDM/OTN devices support the extended SSM protocol, so that clock source ID can be
used to prevent clock loops and implement clock source protection based on priorities.
Extended SSM Protocol Enabled

Huawei developed the extended SSM protocol by adding clock IDs to the standard SSM
protocol. By using the extended SSM protocol, users can assign any clock source an ID. The
clock ID of a synchronization source is transmitted together with SSM bytes. The clock IDs
and SSM bytes together determine automatic clock switching. A clock ID identifies whether
the clock is from the local NE. If the clock is from the local NE, the clock source is
considered invalid to prevent timing loops. The extended SSM protocol is mainly used for
interconnection of Huawei transmission devices
After the extended SSM protocol is enabled for an NE, automatic clock switching is
performed based on following principles:
l The NE takes precedence to select a clock source with the highest quality from the
specified clock priority table.
l If the ID of a clock source indicates that the clock source is synchronized to the NE's
clock, then the NE will not select this clock source to trace.
l If there are multiple clock sources with the highest quality, then the NE selects the clock
source with the highest priority from them.
l The NE broadcasts the quality and ID of the selected clock source to the downstream
NEs using S1 bytes. Meanwhile, the NE informs the upstream NEs of its clock quality
using other S1 bytes along the reverse synchronization path, telling the upstream NEs not
to synchronize to its clock.

Clock Source ID
For simple networks such as chain networks, only the clock priority table needs to be
configured for clock protection. Clock source protection is not required. For complex
networks including ring networks and their derived networks such as tangent and intersecting
ring networks, the extended SSM protocol must be enabled for clock source protection. To
prevent timing loops, the clock source ID must be configured.
l A clock source ID uses bit 1 to bit 4 of an SSM byte, and the value ranges from 0x0 to
0xf. The value ranges from 0x0 to 0xf. Basically, a clock source ID is used to distinguish
the clock information between local and other nodes to prevent a node from tracing the
clock signal that is locally transmitted and comes from the negative direction. Hence, a
timing loop is prevented.
l A value of 0 indicates that a clock source ID is invalid. Hence, the default value of a
clock source ID is 0 when an ID is not set for a clock source. When enabling the
extended SSM protocol, an NE does not select the clock source whose ID is 0 as the
current clock source.
l A clock source ID is a tag set for a reference timing source. The clock sources at the
same quality level that carry different IDs mean different timing signals and are not
different in priority levels and other aspects.
Set the Clock Source ID according to the following principles:
l Allocate a Clock Source ID to each external BITS device.
l Allocate a Clock Source ID to the internal clock source of each node that has an external
BITS device.
l Allocate a Clock Source ID to the internal clock source of each node that enters into
another ring network from one chain or ring network.
l Allocate a Clock Source ID to the line clock source of the node that enters into another
ring network from one chain or ring network when the line clock source exists.
As shown in Figure 2-8, the PTN device obtains clock signals from the connected BITS
device and sends the clock signals to the connected the product on the OTN network over
Ethernet services. Then, the product transmits the clock signals to other devices on the
network to provide frequency synchronization for the entire network. All the NEs on the
WDM/OTN network enable the extended SSM protocol for clock source protection.

Figure 2-8 Clock Source ID
2.7.2.3 Clock Source Interface

Clock source information can be received through external clock ports and service clock
ports.
A clock source is a signal source containing reference timing information. Each NE
synchronizes its local clock phase to the reference timing using its phase-locked loop (PLL).
The WDM/OTN equipment supports the following clock sources:
l External clock source: a clock source extracted from 2 MHz or 2 Mbit/s signals that are
received through an external clock port.
l Line clock source: on the WDM/OTN network, the boards that support physical clocks
are used to recover clock signals from WDM-side service signals. The product on the
WDM/OTN network uses electrical or Optical Multiplexer and Demultiplexing Boards
to transmit system clocks.
l E1 tributary clock source: Timing information is extracted from E1 signal streams.
l Ethernet clock source: a clock source extracted from Ethernet signals by using
synchronous Ethernet.
l Internal clock source: On the WDM/OTN network, the clock generated by the free-
running oscillator of an NE.

Input and Output Ports
Table 2-6 Port types

Clock Port Supported Port Mode Function
Type Format
External 2.048 MHz or RJ45/SMB l Receives clock signals

clock port 2.048 Mbit/s from the BITS or other
devices that have the
same port.
l Cascades with other
devices of the same type
at the same site.
l Connects to the lower-
layer PTN/SDH network.
Service clock Ethernet Inband port that runs Connects to the lower-layer
port services with services. PTN/SDH network without
including GE, equipment room or site
10GE, 40GE sharing restrictions.
and so on
External Clock Ports
Table 2-7 Clock ports

Product Type Board Type Clock Port
OSN 9800 universal platform subrack STG CLK

OSN 8800 universal platform subrack
OSN 6800
OSN 1832 X16 AUX SYNC
OSN 1832 X8 Enhanced AUX SYNC
OSN 1832 X4 Enhanced TMA1UXCL CLK/TOD/MON
OSN 9800 U series/M series EFI CLK1 and CLK2
OSN 8800 T32/T64 STI CLK1 and CLK2
OSN 8800 T16 ATE CLK1 and CLK2
NOTE
For the port description and pin definitions of each board, see the description of Front Panel of each
board.

External Clock Connection Mode

l External clock mode: It is used to interconnect with the BITS or other devices. The
output clock can be synchronized with the system clock of an NE or the line source
specified by the NMS.
l Cascading clock mode: It is used only for the interconnection between multiple subracks
of the WDM/OTN product and is always synchronized with the system clock.
NOTE
l The OSN 1832 supports only the input/output mode of the external clock, but does not support clock
cascading.
l On the NMS, enable or disable the Enabled Status mode to set different working modes. When this
parameter is Enabled, the cascading input/output mode is used. When this parameter is Disabled,
the external clock input/output mode is used.

Clock Port Supported Application Networking Diagram
Type Format Scenario
External All subracks l Applies to OSN Figure 2-9

clock mode work in the 9800/8800
external clock products.
input or output l Applies to the
mode. scenarios when the
OSN 8800/6800 is
connected to the
OSN 9800/1832.
Cascading All subracks The cascading mode is Figure 2-10

clock mode work in the applicable only to
cascading input scenarios where OSN
or output mode 8800 and OSN 6800
with protection subracks are configured
paths. on the same NE.
Figure 2-9 Connection diagram of external clock mode

Figure 2-10 Connection diagram of cascading clock mode
2.7.2.4 Synchronous Ethernet

Synchronous Ethernet is an Ethernet physical layer clock frequency synchronization
technology that directly extracts clock signals from the serial bit streams on Ethernet lines and
transmits the clock signals.
The following figure shows the advantages and limitations of Synchronous Ethernet.
Figure 2-11 Advantages and limitations of Synchronous Ethernet
Principle
Figure 2-12 shows the implementation principle of the synchronous Ethernet function.

Figure 2-12 Implementation Principle
When the Ethernet port functions as the clock source of the NE:
1. The PHY component on the Ethernet port restores clocks from the bit streams of the
Ethernet links, divides the frequency and then transmits the clocks to the system clock
module.
2. The system clock module selects the clock with the highest priority according to the
clock source priority table and synchronizes the clock with the system clock.
When the Ethernet port functions as the output clock of local NE to the downstream device:
1. The system clock module transmits a high-precision system clock to the Ethernet port.
2. The PHY component on the Ethernet port transmits the clock by means of the bit streams
on Ethernet links.
Synchronous Ethernet Processing and Transparent Transmission

The support for synchronous Ethernet varies depending on the service encapsulation types
supported by boards. Two implementation modes are available: synchronous Ethernet
processing and synchronous Ethernet transparent transmission.
Figure 2-13 Synchronous Ethernet processing and transparent transmission

2.7.3 Dependencies and Limitations

This topic describes the limitations on and precautions for physical clocks.
2.7.3.1 Limitations on the Physical Clocks Feature
Table 2-9 Limitations on the Physical Clocks Feature

Item Dependency and Limitation Details
Clock feature Networks at the convergence layer should be configured with

clock protection and be set with the primary and secondary
PRCs for active/standby switching of clock. In the case of
networks at the access layer, generally, only one PRC is set
on the central NE. Other NEs trace the clock of the central
NE.
Service boards l Slots 15 and 16 in the OSN 6800 subrack can house clock
boards and service boards.
l Slots 3 and 4 in universal platform subrack can house
clock boards and service boards.
l Before configuring the clock function, ensure that the port
status of the tributary board is normal and no abnormal
alarm is reported.
Clock view When two sites use ST2/AST2+SFIU to configure physical

clocks, the physical clock view will be supported if there is
no other optical-layer board between the two sites. Otherwise,
the physical clock view will not be supported.

ST2/AST2 l If the ST2/AST2 board uses the clock function, it must be

installed in a subrack housing clock boards.
l Planning the ST2/AST2 boards:
– A maximum of four ST2/AST2 boards can be
configured on either side of a cross-connect board in a
cabinet.
– After a clock board is installed in an OSN 6800
subrack, no sufficient room is available for the network
cables of ST2/AST2 boards on right side of the clock
board because fibers, clock cables, and power cables
occupy the fiber management space on the right of the
cross-connect board. Therefore, do not configure a
ST2/AST2 board on the right side of the clock board.
– Do not insert the ST2/AST2 to the last slot on the right
of universal platform subrack. Otherwise, it is hard to
connect or disconnect a network cable.
l When an OLA is not configured with a clock board, the
ST2/AST2 board at the site can transparently transmit
physical clock signals.
l When the ST2 board is used with the STG board in
universal platform subrack, the board can process physical
clock signals and IEEE 1588v2.
Methods of obtaining l The optical supervisory channel and timing transmission

clock sources board AST2/AST4 does not support configuration of the
2M clock priority list.
l For OSN 9800 earlier than V100R001C20SPC300, only
the second external clock interface CLK2 on the EFI
board can correctly export line source clocks, and the
outputs of the CLK1 and CLK2 external clock interfaces
on the EFI board must be the same. To correctly export
different line source clocks using the CLK1 and CLK2
external clock interfaces on the EFI board, you must
upgrade the EFI board software to OSN 9800
V100R001C20SPC300 or later.

The clock source l The central node or the node with high reliability provides
the clock source.
l If the building integrated timing supply system (BITS) or
other external clock equipment with high precision exists,
use the external timing mode for the NE. Otherwise, use
the line timing mode instead. It is recommended that you
use the internal timing as a clock source of the lowest
level.
l Clock signals need to be compensated after a long clock
chain in order to avoid the drift of clock signals after they
are transmitted through multiple sites. According to ITU-
T G.781, clock signals need to be compensated after a
long clock chain contains 20 NEs. Considering factors
such as the transmission distance of the fiber, clock
signals are usually compensated after the chain reaches 10
NEs.
l If a long clock chain contains more than 20 NEs, clock
signals need to be output to the BITS through a 2M clock
port (CLK port) for regeneration. Moreover, the
regenerated clock signals should be sent back to the NEs
and serve as clock source to be transmitted to the line side.
The shortest path Ensure that the path is the shortest when the line clock is
traced.
l In the case of a ring network that consists of fewer than
six NEs, the PRC can be traced from one direction.
l In the case of a ring network that consists of at least six
NEs, ensure that the tracing path is the shortest. That is,
when a network consists of N NEs, one half of the number
of NEs should be tracing the reference clock from one
direction and the other half of the NEs should be tracing
the reference clock from another direction. "N" represents
the number of NEs. When N is an odd number, the
intermediate NEs can trace the reference clock in either
direction.

SSM protocol l If the SSM protocol is disabled, the clock network can be
configured to unidirectional only and the clocks cannot be
configured into rings.
l The settings of the SSM protocol information for all NEs
in the network should be consistent if the protocol is
enabled.
l The principles for enabling the SSM protocol when the
clock switching occurs are as follows:
– If you only want an NE to select a clock source
according to the preset priority without consideration
for the quality of the clock source, the SSM protocol
can be disabled.
– If you want an NE to select a clock source with the
highest quality and priority automatically, the standard
SSM protocol needs to be enabled. If the clock
network consists of the Huawei equipment and that of
other vendors, you can enable the standard SSM
protocol only and the extended SSM protocol cannot
be enabled.
– If you want an NE to select a clock source with the
highest quality and priority automatically and the clock
network consists of Huawei equipment only, you can
enable the extended SSM protocol. The clock ID
provided by this protocol can avoid timing loops in the
clock network.
l The following principles must be applied if different SSM
protocols are enabled:
– If you enable the standard SSM protocol, you can
configure the clock network to bidirectional but cannot
configure the clocks into rings.
– If you enable the extended SSM protocol, you can
configure the clock network to bidirectional or
configure the clocks into rings. In this case, however,
intersection and tangent rings are not permitted.
SDH clocks An SDH network is a synchronous system and has high

requirements on clock synchronization. Therefore, ensure that
SDH clocks have been configured before configuring services
and features.
Configuring Attributes of Changing the service type between GE(TTT-GMP) and

Transport Clock for GE(GFP-T) for a board will interrupt services on the board.
Boards After the operation, the services will be automatically
restored.
For the OSN 6800, changing the value of Synchronous
Clock Enabled for a board will cause a transient service
interruption on the board.

Configuring Clock Source l Allocate the same subnet number to NEs tracing the same
Protection clock source.
l If the extended SSM protocol is enabled, you are not
advised to change the ID of the clock source being traced
by the master NE when the clock tracing performance is
stable. This ensures proper transmission of clock IDs and
prevents a clock loop.
Switching a Clock Source l Performing clock source switching may cause service
interruption.
l Before switching the clock source, ensure that a new clock
source that is not locked and that has good quality is
created in the priority table.
2.7.3.2 Affected Features
Table 2-10 Affected Features

Loopback For a board port that is configured with physical-layer clocks

function, if the loopback test is to be configured on the port or
the interconnected port, the clock trace source of the NE
where the port is located must be switched to the protection
clock source, ensuring that the port loopback has no impact
on the clock function.
Optical line protection and When optical line protection, intra-board 1+1 protection, and
intra-board 1+1 protection physical clock (SDH) are configured at the same time, you
are advised to retain the default value 0 for parameter Clock
Source Hold-Off Time(100ms). Otherwise, the SDH service
interruption time may be longer than 50 ms.
DLAG For OSN 1832, if both DLAG and synchronous Ethernet are
to be configured on the TDM plane of the equipment,
configure DLAG first and then synchronous Ethernet.
2.7.3.3 Mutually Exclusive Features

None.
2.7.4 Configuring Physical Clock (OSN 1832/8800/9800 Universal

Platform Subrack/M Series Subrack)

2.7.4.1 Configuration Process

This topic describes the clock configuration process based on a flow chart.
Figure 2-14 Configuration process for physical synchronization
Configure physical-layer clocks to implement frequency synchronization and query the clock
synchronization status. For details, see Table 2-11.
Table 2-11 Clock configuration process

Operation Remarks
2.7.4.2 Mandatory.
Configuring Before configuring clocks, specify Frequency Source Mode as required.
the Frequency
Source Mode l If physical clock frequency synchronization is used, select Physical
Synchronization.
l If IEEE 1588v2 frequency synchronization is used, select PTP
Synchronization.
2.7.4.3 Optional.
Configuring When the line boards and tributary boards are used to provide clock
Clock synchronization, Service Type, Port Mapping, and Synchronous Clock
Attributes of Enabled must be set.
Boards to
Implement
Synchronous
Frequency
Synchronizati
on
2.7.4.4 Optional.
Configuring This operation is performed only when an NE needs to receive or
External transmit external clock signals. The external port of a clock board can be
Clock Ports used to connect the external time. In addition, the external port can be
used for cascading the clock boards within a multi-subrack NE.
To prevent clock signal deterioration, you must add a BITS clock source
for clock compensation when more than 10 NEs are configured. In this
case, you must set parameter Phase-Locked Source Output of External
Clocks.

Operation Remarks
2.7.4.5 Mandatory.
Configuring This operation specifies the priority of each required clock source. This
Clock provides a criterion for selecting clock sources in case of a clock
Attributes switching event.
To provide a clock source selection basis for each clock source during
clock switching, you must set parameters System Clock Source Priority
Table, 2M External Clock Source Priority Table, Clock Quality, and
Higher-Priority Clock Source Reversion.
2.7.4.6 Optional.
Configuring Clock synchronization at the physical layer supports clock source
the Clock selection and switching in the following scenarios:
Source
Protection l When the SSM protocol is not enabled: Configuring the clock source
protection is not required.
l When the standard SSM protocol is enabled: Enabling standard SSM
protocol control and configuring the SSM output are required.
l When the extended SSM protocol is enabled: Enabling extended SSM
protocol control, configuring the clock subnet, and configuring the
SSM output are required.
2.7.4.7 Mandatory.
Viewing Clock After all the clock configuration operations are completed, query all
Synchronizati ports for the clock synchronization status to ensure that the port
on Status synchronization status is the same as defined in the networking diagram.
2.7.4.8 Mandatory.
Viewing the Correct clock tracing relationships are critical to ensure the clock
Clock Tracing synchronization within the entire network. Using the U2000, you can
Status monitor the clock tracing status of each NE.
2.7.4.9 Optional.
Configuring When the clock source quality deteriorates, you must manually switch
Clock Source clock sources by performing operations To manually switch clock
Switching sources, perform the operations of setting clock source switching
conditions, enabling clock source switching, and starting clock source
switching.
2.7.4.2 Configuring the Frequency Source Mode

In practical application, the frequency source mode of an NE must be configured before
configuring a clock.
Prerequisites
You are an NMS user with "Operator Group" privilege or higher.

Procedure
Step 1 Configure the Frequency Source Mode.
NOTE
Before configuring clocks, specify Frequency Source Mode as required.

l If physical clock frequency synchronization is used, select Physical Synchronization.
l If IEEE 1588v2 frequency synchronization is used, select PTP Synchronization.
----End
2.7.4.3 Configuring Clock Attributes of Boards to Implement Synchronous

Frequency Synchronization
To achieve frequency synchronization, the Service Type, Port Mapping, Synchronous
Clock Enabled, SSM Timeout Period (500ms) parameters must be correctly set for relevant
boards on the U2000.
Prerequisites
You are an NMS user with "Guests" privilege or higher.
Context
NOTICE
Changing the service type between GE(TTT-GMP) and GE(GFP-T) for a board will
interrupt services on the board. After the operation, the services will be automatically
restored.

NOTICE
For OSN 6800, changing the value of Synchronous Clock Enabled for a board will cause a
transient service interruption on the board.
Procedure
Step 1 Configure Service Type and Port Mapping in the following way:
For details about how to configure synchronous Ethernet on each board, see 2.7.6.1
Availability.
Step 2 Configure Synchronous Clock Enabled. For details about the parameters, see 2.7.4.12.2
Parameters: Clock Attribute Configuration.
Step 3 Optional: When the following boards are interconnected with third-party devices, you must
set parameter SSM Timeout Period (500ms) of the boards to guarantee SSM quality. Other
boards do not need to be configured. For details about the parameters, see 2.7.4.12.2
Parameters: Clock Attribute Configuration.

NOTE
Only the following boards support this parameter:
l OSN 8800: TN54TOA and TN54THA.
l OSN 1832 X16: TNF5TOA, TNF6TOA, TNF5TQX, TNF2LDX, TNF2ELOM (STND), TNF6TTA,
TNF1LDCA.
l OSN 1832 X8 Enhanced: TNF2LDX, TNF2ELOM (STND), TNF6TTA, TNF1LDCA.
----End
2.7.4.4 Configuring External Clock Ports

This topic describes how to configure attributes of external clocks for a device so that the
device can properly extract external clock signals. These attributes include the cascading
mode of external clock ports on clock boards and PLL output.
Prerequisites
l You are an NMS user with "Operator Group" privilege or higher.
l The STG board has been created.
l For the OSN 6800, when concatenation of the external ports of a clock board is
configured, the 120ohm external clock interface cable should be used as the network
cable for the concatenation.
Configuring External Port Cascading Mode for Clock Boards

The external port of a clock board can be used to connect the external time. In addition, the
external port can be used for cascading the clock boards within a multi-subrack NE.
l Each subrack has two clock ports and two timing ports. These ports are used to
concatenate and transmit the clock or timing signals among multiple subracks, or are
used to input or output external clock and timing signals. By default, the Enabled Status
is unused. If any ports need to be used for the input or output of external clock and
timing signals, the ports should be set to the disabled state. One NE supports a maximum
of two ports for the input or output of external clock and timing signals.
l After PTP Synchronization is enabled for an NE, the NE automatically switches the
frequency source mode to Physical Synchronization when the Enabled Status of the

external clock port on the NE's clock board changes from Enabled to Disabled or
changes from Unused to Disabled. When this occurs, manually set the frequency source
mode of the NE to PTP Synchronization.
Step 1 Configure Enabled Status. For details about the parameters, see 2.7.4.12.3 Parameters:
Clock Port Link.
----End
Configuring Phase-Locked Source Output of External Clocks

When a clock signal passes through 10 or more NEs, frequency offset and drift may occur. As
a result, the clock signal transmitted to the downstream NE is degraded. To prevent this from
happening, a 2M phase-locked source must be used to optimize the clock signal.
Step 1 Configure Phase-Locked Source Output by External Clock. For details about the
parameters, see 2.7.4.12.16 Parameters: Phase-Locked Source Output by External Clock.

NOTE
In the event of forced shutdown of the output of the external clock, the 2 Mbit/s and 2 MHz of the two
external clocks are shut down and there is no output signal from the two clocks. This command has a
higher shutdown priority than all other automatic shutdown functions provided by software. By default,
the forced shutdown of the external clock output is disabled.
----End
2.7.4.5 Configuring Clock Attributes

Clock attributes include system clock source priority table, 2M external clock source priority
table, clock quality, and clock source reversion mode.
Prerequisites
l The relevant board has been created.
Configuring the System Clock Source Priority Table

Configuring the system clock source priority table specifies the priority of each required clock
source. This provides a criterion for selecting clock sources in the event that of clock
switching occurs.
Step 1 Configure System Clock Source Priority List.
NOTE
l The internal clock source has the lowest priority.

l The clock sources are arranged in a descending order according to their priorities.
l The NE supports a maximum of 32 clock sources.
l Before you configure physical-layer clock synchronization at sites A and B, configure the clock
source priority table for sites A and B. If site A needs to trace clocks from site B, set the clock
source priority of site B to 1. If site B needs to trace clocks from site A, set the clock source priority
of site A to 1. If there are sites A, B, and C, site A needs to trace clocks from site B, and site B needs
to trace clocks from site C, set the clock source priority of the most upstream site (site C) to 1.

Step 2 Select a clock source and click or to adjust the clock source priority.
Step 3 Optional: Select a clock source and then click Delete to delete the clock source. For details
about these parameters, see 2.7.4.12.4 Parameters: System Clock Source Priority List.
----End
Configuring the 2M External Clock Source Priority Table

Configuring the system clock source priority table specifies the priority of each required
external clock source. This provides a criterion for selecting clock sources in the event that of
clock switching occurs.
Step 1 Check the 2M PLL clock source of the external clock port.
NOTE
l The relationship between the 2M PLL clock source and the external clock port depends on the
sequence of setting the cascaded external ports on the clock board.
l The optical supervisory channel and timing transmission board AST2/AST4 does not support
configuration of the 2M clock priority list.
Step 2 Configure Priority for PLL Clock Sources of 1st External Output or Priority for PLL
Clock Sources of 2nd External Output.

NOTE
Step 3 Select a clock source and click or to adjust the clock source priority.
NOTE
Users can configure the priority table for the two clock outputs of a 2M external clock source.
Specifically, users can configure the priorities of the first and second clock source in the first or second
external clock output priority table.
Step 4 Click Apply.
about these parameters, see 2.7.4.12.5 Parameters: Priority for PLL Clock Sources of 1st
External Output and 2.7.4.12.6 Parameters: Priority for PLL Clock Sources of 2nd
External Output.
----End
Configuring the Quality of Clock Sources

In a complex clock network, there may be some unknown clock sources. You can uniformly
define these clock sources as unavailable clocks so that NEs do not trace wrong clock sources.
The NE obtains their quality information automatically for clock sources that are allocated to
an NE. You should define the quality level of clock sources only during testing and
maintenance.
Step 1 Configure Clock Quality. For details about these parameters, see 2.7.4.12.8 Parameters:
Clock Source Quality.

NOTE
The default value Automatic Extraction is recommended for most situations.

NOTE
The SSM source selection algorithm of an NE first compares the quality level of a clock source with the
SSM Input Quality Threshold.
l SSM Input Quality Threshold: indicates the lowest input clock quality level. By default the
value is Not Inferior to G.813 SETS Clock Signal.
l If the quality level is lower than the SSM Input Quality Threshold, the NE reports an
SSM_QL_FAILED alarm, and specifies the clock source as invalid.
l If the quality level is higher than or the same as the SSM Input Quality Threshold, the NE
transparently transmits the quality level of the clock source to the normal select flow so that the
normal select flow selects the clock as its clock source.
Step 2 Configure Manual Setting of Quality Level. For details about these parameters, see
2.7.4.12.9 Parameters: Manual Setting of Quality Level 0.

----End
Configuring the Clock Source Reversion

When there are multiple clock sources for an NE, set the clock sources to automatic reversion
mode, so that the deteriorated clock source automatically becomes the traceable timing
reference after it recovers.
Step 1 Configure Higher-Priority Clock Source Reversion, Clock Source WTR Time(min)Clock
Source Hold-Off Time(100ms). For details about these parameters, see 2.7.4.12.12
Parameters: Clock Source Reversion Parameter.

NOTE
l Do not set Clock Source WTR Time(min) to be 0 to avoid repeated switching when the clock is
unstable.
l Clock Source Hold-Off Time(100ms): by default the value is 0, which means that the hold-off
timer is disabled. The Clock Source Hold-Off Time(100ms) can be set within the range of 300 ms
to 1800 ms with the step length of 100 ms.
l When a clock source for an NE fails, the status of the clock is sent to the select flow only after the
specified Clock Source Hold-Off Time(100ms) elapses so that the NE can determine whether to
select another clock source. The Clock Source Hold-Off Time(100ms) ensures that a short-term
clock signal failure is not sent to the select flow for clock source switching.
----End
2.7.4.6 Configuring the Clock Source Protection

In a complex clock network, clock protection needs to be configured for all NEs. The standard
SSM protocol or extended SSM protocol can be enabled to prevent NEs from tracing
incorrect clock sources and to implement clock protection.
Prerequisites
Configuring the SSM Protocol

Step 1 Configure Start Standard SSM Protocol or Start Extended SSM Protocol. If the Start
Extended SSM protocol is selected, set the Clock Source ID of the Clock Source. For
details about these parameters, see 2.7.4.12.7 Parameters: Clock Subnet.

NOTICE
If the extended SSM protocol is enabled, you are not advised to change the ID of the clock
source being traced by the master NE when the clock tracing performance is stable. This
ensures proper transmission of clock IDs and prevents a clock loop.
NOTE
l The same SSM protection protocol must be used within the same clock protection subnet.
l Allocate the same subnet number to NEs tracing the same clock source.
Step 2 Optional: If the Clock Source ID is specified for the line clock of an NE, click the Clock ID
Output tab, and set the Output Clock ID to Enabled. Click Apply. For details about these
parameters, see 2.7.4.12.11 Parameters: Clock ID Status.
----End
Configuring the SSM Output

If the standard SSM or extended SSM protocol is enabled, the clock signals carry SSM
messages automatically. You can prevent clock sources from sending SSM messages to other
clock subnets. This ensures that the equipment of different clock subnets does not affect each
other at the edge of clock networks.
Step 1 Configure SSM Output. For details about these parameters, see 2.7.4.12.10 Parameters:
SSM Output Control.

----End
2.7.4.7 Viewing Clock Synchronization Status

If the clocks between NEs in the network are not synchronous, pointer justification errors, bit
errors, and even service interruption may occur on the NE. Using the U2000, you can
ascertain and monitor the synchronization status of the NE clocks.
Prerequisites
Procedure
Step 1 View clock synchronization status.

NOTE
l SSM Output Quality Threshold: indicates the highest output clock quality level. By default the
value is G.811 Clock Signal.
l If the clock quality level of an NE is equal to or higher than SSM Output Quality Threshold, the
specified SSM Output Quality Threshold is sent to the downstream NE.
l If the clock quality level is lower than the specified SSM Output Quality Threshold, the actual
clock quality level is sent to the downstream NE.
----End
2.7.4.8 Viewing the Clock Tracing Status

Correct clock tracing relationships are critical to ensure the clock synchronization within the
entire network. Using the U2000, you can monitor the clock trace status of each NE.
Prerequisites
Context
When the clock tracing relationships are changed, the U2000 refreshes the tracing status in the
Clock View automatically.
Procedure
Step 1 In the Main Topology, select Clock View from the Current View drop-down list.
Step 2 In the Clock View, right-click and choose Search Clock Link from the shortcut menu.
Step 3 In the Search Clock Link window, set Clock Type, Search Mode and select the NE to be
queried, click OK.
Step 4 In the Result dialog box, click Close.
----End
2.7.4.9 Configuring Clock Source Switching

When a traced clock source degrades, clock switching needs to be performed manually. To
manually perform clock source switching, users first need to configure clock source switching
conditions and enable clock source switching.
Prerequisites
l The clock source has been created.
Configuring Switching Conditions for Clock Sources

For OSN 8800/OSN 6800/OSN 1832, if the traceable clock source of an NE is a line clock,
you can customize switching conditions for the clock source so that the NE switches to other
clocks when the clock source fails. Taking this measure will minimize the impact that a clock
failure has on services.

Step 1 Double-click the parameter column and set the alarms and performance events that are to be
used as the clock source switching conditions to Yes. For details about these parameters, see
2.7.4.12.15 Parameters: Clock Source Switching Conditions.
----End
Enabling Clock Source Switching

Enabling or disabling the clock source switching function for a configured clock source is
actually a process of unlocking or locking the clock source.
Step 1 Enable clock source switching. For details about these parameters, see 2.7.4.12.13
Parameters: Clock Source Switching.
----End
Switching a Clock Source

When the traceable clock source in a network deteriorates, NEs may not be able to execute a
switch on the clock source. Users need to manually switch the clock source to prevent clock
deterioration from affecting the normal running of NEs.

NOTICE
Performing clock source switching may cause service interruption.
Step 1 Perform clock source switching, including the operation of selecting Forced Switching or
Manual Switching.
NOTE
Before switching the clock source, ensure that a new clock source that is not locked and that has better
quality is created in the priority table.
Step 2 Optional: To restore the automatic clock source selection mode, right-click the switched
clock source and choose Clear Switching.
----End
2.7.4.10 Configuring Clock Attributes of Boards to Implement Synchronous

Ethernet Transparent Transmission
OTUs or tributary boards provide the synchronous Ethernet transparent transmission function
to transparently transmit frequency signals only but not extract or synchronize the frequency
signals. To implement synchronous Ethernet transparent transmission, ensure that the Service
Type and Port Mapping values of boards are correctly specified on the U2000.
Prerequisites
Context
NOTE
When a board supports transparent transmission of synchronous Ethernet services, before changing the
value of Port Mapping for a port on the board from Bit Transparent Mapping to Mac Transparent
Mapping, you must delete the port from the clock priority table.

NOTICE
restored.
Procedure
Step 1 Set Service Type and Port Mapping.
Availability.
----End
2.7.4.11 Configuring the ST2/AST2 Board to Transparent Transmission of Clock

Information
When no clock board is configured for an optical line amplifier (OLA) site, you are advised to
configure the ST2/AST2 board at the site to transparently transmit physical clocks and IEEE
1588v2 clocks. In other words, use the board to transparently transmit frequency/phase
signals to the downstream site but not extract or process the frequency/phase signals.
Prerequisites
l You are an NMS user with "Monitor Group" authority or higher.
l The board has been configured at the OLA site.

Context
Figure 2-15 Configuring the Board to Transparent Transmission of Clock Information
Procedure
Step 1 Configure the board to transparent transmission. For details on parameter settings, refer to
2.7.4.12.17 Parameters: Clock Signal Pass-through
Step 2 Optional: If clock pass-through settings need to be deleted on the NMS, select the settings
and click Delete. In the Are you sure to delete? dialog box that is displayed, click OK.
----End
2.7.4.12 Parameters: Physical Clock (OSN 1832/8800/9800 Universal Platform

Subrack/M Series Subrack)
This topic describes the parameters in process of configurations.

2.7.4.12.1 Parameters: Frequency Source Mode

In this user interface, you can specify the mode of the frequency source that the NE traces
according to the network planning.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > Frequency
Source Mode from Function Tree.
Parameters
Field Value Description
NE Name For example: NE7183 Displays the NE name.
Frequency Source Mode Physical Synchronization, Displays the mode of the

PTP Synchronization frequency source that the
NE traces.
NOTE
Before configuring clocks,
specify Frequency Source
Mode as required.
l If physical clock frequency
synchronization is used,
select Physical
Synchronization.
l If IEEE 1588v2 frequency
select PTP
Synchronization.
2.7.4.12.2 Parameters: Clock Attribute Configuration

In this interface, you can set and query Synchronous Clock Enabled, Synchronous/
Asynchronous Mode, and SSM Timeout Period (500ms) for clocks.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > Clock Attribute
Configuration.
Parameters
Clock Board For example: Shelf8(Slave Chooses a clock board.

shelf8)-5-53TDX(STND)
Port For example: Shelf8(Slave Displays the clock port.

shelf8)-5-53TDX(STND)-4(
RX2/TX2)

Synchronous Clock Enabled Disabled, Enabled l Enabled: Synchronous

Default: Disabled Ethernet is supported.
l Disabled: Synchronous
Ethernet is not
supported.
Synchronous/Asynchronous - Sets the clock port to work

Mode in synchronous mode or
asynchronous mode.
The equipment does not
support this parameter.

SSM Timeout Period 0 to 120 When the following boards

(500ms) Default: 10 are interconnected with
third-party devices, you
must set parameter SSM
Timeout Period (500ms) of
the boards to guarantee SSM
quality. Other boards do not
need to be configured. For
details about the parameters,
see 2.7.4.12.2 Parameters:
Clock Attribute
Configuration.
When the reference source
port configured in the
priority table cannot extract
valid SSM information
within the consecutive time
specified by SSM Timeout
Period (500ms), the port
reports an SSM_LOS alarm
to perform clock source
switching.
NOTE
Only the following boards
support this parameter:
l OSN 8800: TN54TOA and
TN54THA.
l OSN 1832 X16:
TNF5TOA, TNF6TOA,
TNF5TQX, TNF2LDX,
TNF2ELOM (STND),
TNF6TTA, TNF1LDCA.
l OSN 1832 X8 Enhanced:
TNF2LDX, TNF2ELOM
(STND), TNF6TTA,
TNF1LDCA.
NOTE
l This parameter is valid
only when Synchronous
Clock Enabled is set to
Enabled.
l The unit is 500 ms.
Therefore, the actual
timeout period is 500 times
of the specified value. For
example, if the value is 10,
the actual timeout period
will be 5000 ms.

2.7.4.12.3 Parameters: Clock Port Link

In this user interface, you can set whether the external ports on clock boards are used for
concatenating the clock signals among the clock boards in the multiple subracks on an NE.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > Port Cascading
from Function Tree.
Parameters
Port shelf ID (shelf name)-slot Displays the port name.

number-board name-
external clock interface,
shelf ID (shelf name)-slot
number-board name-
external time interface

Enabled Status Enabled, Disabled, Unused The Enable Status

Default: Unused parameter provides an
option to enable or disable
the external port on the
clock board as a cascading
port.
In the case of the maser-
slave subracks, clock
synchronization and time
synchronization are based
on the cascading ports. If
this parameter is set
improperly, the master and
slave subracks fail to
maintain clock
synchronization or time
synchronization.
l Enabled: Indicates that
the external port is used
as a cascading port.
l Disabled: Indicates that
the external port inputs/
outputs the external
clock/time.
l Unused: Indicates that
the external port is
unused.
NOTE
Currently, only master
subracks of OSN 1832 support
the clock function but slave
subracks do not. Therefore,
Enabled Status can only be
set to Disabled or Unused but
cannot be set to Enabled.
2.7.4.12.4 Parameters: System Clock Source Priority List

In this user interface, you can query, modify and set the priority list of clock sources, select
the external clock source mode, and select the tributary board for tributary clock source.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > Physical Clock
> Clock Source Priority from the Function Tree. Click the System Clock Source Priority
tab.

Parameters
Clock Source Internal Clock Source, The clock sources in the list
External Clock Source, used by the current NE have
Shelf ID (shelf name)-slot different priorities according
number-board name-port to their sequences, with the
number (port name) uppermost clock source
having the highest priority.
The NE supports a
maximum of 32 clock
sources.
Other Fiber End For example: NE2- Indicates the port connected
Shelf18(subrack)-18-11ST2- to the clock source by a
2(RM2/TM2) fiber.
External Clock Source 2Mbit/s, 2MHz The External Clock Source

Mode Default: 2Mbit/s Mode parameter provides
an option to set the format
of the input clock signals
from the external clock
source.
l 2Mbit/s: 2 Mbit/s signals
l 2MHz: 2 MHz signals
If the external input port is
connected to an external
output port of the local
system, the input mode of
the input port must be
consistent with the output
mode of the output port.
Synchronous Status Byte SA4, SA5, SA6, SA7, SA8 The Synchronous Status
Default: SA4 Byte parameter provides an
option to set the timeslots
for the SSM quality
information in the input
external clock signals.
l SA4: sa4 timeslot
l SA5: sa5 timeslot
l SA6: sa6 timeslot
l SA7: sa7 timeslot
l SA8: sa8 timeslot
This parameter is valid only
when External Clock
Source Mode is set to
2Mbit.

Clock Source Priority The integer greater than or Displays the priority
Sequence (Highest: 1) equal to 1 sequence of this clock
source.
2.7.4.12.5 Parameters: Priority for PLL Clock Sources of 1st External Output
When you need to use the line clock source of the equipment as the phase-locked source, you
must configure the priority table for phase-locked sources in this user interface. In this user
interface, you can also query and set priority table for phase-locked sources of first external
output clocks and adjust the priority of each clock source.
The available clock source with the highest priority can be used as the phase-locked source to
lock the phase of first external output clock. An internal source can be assigned with the
lowest priority level only.
NOTE
When two 2M phase-locked loops (PLLs) are required to track line sources, it is recommended that the
2M PLLs of OSN 9800 universal platform subracks be used. The 2M PLLs of OSN 9800 electrical
subrack is used to track system clock sources by default.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > Physical Layer
Clock > Clock Source Priority from the Function Tree. Click the Priority for PLL Clock
Sources of 1st External Output tab.
Parameters
Clock Source For example: Internal Clock Displays the name of the
Source clock source.
2(RM2/TM2) fiber.
Current Status Valid, Invalid Displays the active state of

the clock source. If the clock
source exists, its active state
is displayed as Valid.

S1 Byte For example: Synchronous The S1 Byte Received

Source Unavailable parameter indicates the
value of the S1 byte of the
current traced source in the
system clock priority table.
This field displays no
information until the S1 byte
(clock protection function)
is activated.
l SDH equipment timing
source (SETS) signal:
Indicates that the clock
quality of the current
traced source is 0x0b.
l G.812 Local Clock:
traced source is 0x08.
l G.812 Transit Clock:
l G.811 Reference Clock:
l Synchronous Source
Unavailable: Indicates
that the clock quality of
the current traced source
is 0x0f.

Lock Status Lock, Unlock Sets the locking state of the

Default: Unlock clock source, which is
usually set to Unlock.
l Lock: Indicates that a
certain channel of clock
source in the priority
table is in the lock status
where the switching of
clock sources is not
allowed.
l Unlock: Indicates that a
table is in the unlock
status where the
switching of clock
sources is allowed.
Switching Source For example: 18- Displays the switched clock

ST2-2(RM2/TM2) source that the NE is
For example: Internal Clock tracing.
Source
Current Trace Source For example: 18- Displays the clock source
ST2-2(RM2/TM2) that the NE is currently
Source
Switching Status Forced Switching, Manual Displays the switching

Switching, Normal status of clock source.
2.7.4.12.6 Parameters: Priority for PLL Clock Sources of 2nd External Output
must configure the priority table for phase-locked sources in this user interface. You can also
query and set priority table for phase-locked sources of second external output clocks and
adjust the priority of each clock source.
lock the phase of second external output clock. An internal source can be assigned with the
NOTE
When two 2M phase-locked loops (PLLs) are required to track line sources, it is recommended that the
2M PLLs of OSN 9800 universal platform subracks be used. The 2M PLLs of OSN 9800 electrical
subrack is used to track system clock sources by default.

Navigation Path
In the NE Explorer, click the NE and select Configuration > Clock > Physical Layer Clock
> Clock Source Priority from the Function Tree. Click the Priority for PLL Clock Sources
of 2nd External Output tab.
Parameters
Clock Source For example: Internal Clock Displays the name of the
2(RM2/TM2) fiber.


S1 Byte For example: Synchronous The S1 Byte Received

Source Unavailable parameter indicates the
value of the S1 byte of the
current traced source in the
system clock priority table.
This field displays no
information until the S1 byte
(clock protection function)
is activated.
traced source is 0x0b.
Unavailable: Indicates
that the clock quality of
the current traced source
is 0x0f.

Lock Status Lock, Unlock Sets the locking state of the

Default: Unlock clock source, which is
usually set to Unlock.
l Lock: Indicates that a
table is in the lock status
where the switching of
clock sources is not
allowed.
l Unlock: Indicates that a
table is in the unlock
status where the
switching of clock
sources is allowed.
Switching Source For example: 18- Displays the switched clock

ST2-2(RM2/TM2) source that the NE is
Source
Current Trace Source For example: 18- Displays the clock source
ST2-2(RM2/TM2) that the NE is currently
Source
Switching Status Forced Switching, Manual Displays the switching

Switching, Normal status of clock source.
2.7.4.12.7 Parameters: Clock Subnet

In this interface, you can query, set or activate clock subnets, clock source IDs, the SSM
protocol and the S1 byte of an NE.
Navigation Path
> Clock Subnet Configuration > Physical Clock Subnet Configuration from the Function
Tree. Click the Clock Subnet tab.
Parameters
Affiliated Subnet 0 to 255 This field enables you to set

Default: 0 the clock subnet number of
the NE.

Protection Status Start Extended SSM The Protection Status

Protocol, Start Standard parameter indicates the
SSM Protocol, Stop SSM working mode of the clock
Protocol protocol for a clock subnet.
Default: Stop SSM Protocol The protection status of the
entire clock subnet should
be consistent. To avoid a
clock tracing loop on a ring
or mesh network, it is
recommended that you set
this parameter to Start
Extended SSM Protocol.
l Stop SSM Protocol:
– When the SSM
protocol is disabled,
clock signals do not
contain clock quality
information. Clocks
are selected based on
the specified clock
source priorities. In
this mode, timing
loops may result.
– This mode is used on
a non-ring network
with multiple clock
sources. The clock
source is selected
according to the clock
source priority list.
l Start Standard SSM
Protocol:
– When the standard
SSM protocol is
enabled, clock quality
levels are used to
prevent timing loops.
a non-ring network
with multiple clock
sources. The clock
signal carries quality
information. It is used
when the WDM/OTN
device interconnects
with a third-party
device.

l Start Extended SSM

Protocol:
– When the extended
SSM protocol is
enabled, clock IDs
are used to prevent
timing loops.
– This protocol is
applicable only to a
ring network. It is a
Huawei proprietary
protocol and cannot
be used when the
WDM/OTN device
interconnects with a
third-party device. If
the extended SSM
protocol is enabled on
an NE, the standard
SSM protocol can be
configured on the
downstream NEs;
however, it cannot be
configured on the NE
if the standard SSM
the upstream NEs.
Clock Source Internal Clock Source, This field displays the

External Clock Source, configured clock source of
Shelf ID (shelf name)-slot the NE. You can either add
number-board name-port or delete a clock source in
number (port name) the clock source priority list.

Clock Source ID 1 to 15 The Clock Source ID

Default: None parameter provides an
option to set an ID for a
clock source. ITU-T defines
only the lower four bits of
the S1 byte and Huawei
defines the higher four bits
of the S1 byte as the clock
source ID. In the case of a
network fault, an NE may
trace its own clock and the
clock cross-tracing problem
may occur. The clock source
ID helps avoid such a
problem.
When the system traces an
external clock source or a
clock source of another
clock subnet, this parameter
should be set. For the line
clock sources of other
subnets, however, this
parameter does not need to
be set.
2.7.4.12.8 Parameters: Clock Source Quality

In this user interface, you can query the clock source quality and set the clock source
parameters, such as configuration quality and clock quality.
Navigation Path
Tree. Click the Clock Quality tab. Click the Clock Source Quality tab.
Parameters
Clock Source Internal Clock Source, This field displays the name
External Clock Source, of the configured clock
Shelf ID (shelf name)-slot source. You can either add
number-board name-port or delete a clock source in
number (port name) the clock source priority list.

Configured Quality Unknown Synchronization The Configured Quality

Quality, G.811 Clock Signal, parameter provides an
G.812 Transit Clock Signal, option to set the
G.812 Local Clock Signal, configuration quality level
G.813 SDH Equipment of a clock source. This
Timing source (SETS) parameter is applicable to
Signal, Do Not Use For certain special scenarios or
Synchronization, Automatic tests and therefore does not
Extraction need to be set in most cases.
Default: Automatic When the parameter value
Extraction changes, the clock source
selecting protocol re-selects
a clock source. As a result, a
clock source switching may
occur.
Set this parameter only
when a clock source does
not contain the clock quality
information or the clock
quality information
contained in a clock source
is not required. For example,
in the case of an external
clock in 2MHz mode, this
parameter needs to be set.
Received Quality - The Received Quality

parameter indicates the
quality information about
the clock source received by
an NE. When receiving a
clock source, the NE
extracts the clock quality
information from the S1
byte in the clock source.
In most cases, the clock
source of the highest quality
is most likely to be selected
as the current clock source.

SSM Input Quality Not Inferior to G.811 Clock Indicates the threshold of
Threshold Signal, Not Inferior to G. input clock sources quality
812 Transit Clock Signal, for an NE. The clock
Not Inferior to G.812 Local sources are specified for the
Clock Signal, Not Inferior to NE according to this
G.813 SETS Clock Signal threshold.
Default: Not Inferior to G. The SSM source selection
813 SETS Clock Signal algorithm of an NE first
compares the quality level
G.811 Clock Signal, G.812 of a clock source with the
Transit Clock Signal, G.812 SSM Input Quality
Local Clock Signal, G.813 Threshold.
SETS Clock Signal
l If the quality level is
Default: G.813 SETS Clock lower than the SSM
Signal Input Quality
Threshold, the NE
reports an
SSM_QL_FAILED
alarm, and specifies the
clock source as invalid.
higher than or the same
as the SSM Input
Quality Threshold, the
NE transparently
transmits the quality
level of the clock source
to the normal select flow
so that the normal select
flow selects the clock as
its clock source.
2.7.4.12.9 Parameters: Manual Setting of Quality Level 0

In this user interface, you can query and set the quality level of a clock.
Navigation Path
Tree. Click the Clock Quality tab. Click the Manual Setting of Quality Level tab.
Parameters

Quality Level 0 Do Not Use For The Quality Level 0

Synchronization, G.811 parameter provides an
Reference Clock, Between option to set the quality
G.811 Reference Clock and level when the quality
G.812 Transit Clock, G.812 information of a clock
Transit Clock, Between G. source is unknown.
812 Transit Clock and G. According to the SSM
812 Local Clock, G.812 protocol, when the quality
Local Clock, Between G. level of a clock source is 0,
812 Local Clock and it indicates that the clock
synchronous equipment information of the clock
timing source (SETS), SETS source is unknown. Hence,
Clock, Between the SSM protocol enables
synchronous equipment compatibility with the signal
timing source (SETS) and source that does not support
quality unavailable the SSM protocol. To
Default: Do Not Use For include a clock source with
Synchronization unknown quality
information in the SSM
protocol, a quality level
should be defined for the
clock source.
All the clock sources with
unknown quality
information can be included
in the source selecting
protocol. This parameter has
an impact on selection of the
clock source.
Set this parameter according
to the quality of the
unknown clock sources in
the system and the specific
application scenarios of the
unknown clock sources.
When the quality level of a
clock source is manually set
as unknown, set the quality
level for the clock source
similarly.
2.7.4.12.10 Parameters: SSM Output Control

In this user interface, you can decide whether the clock signal that the equipment outputs
through the external clock interface contains SSM messages.

Navigation Path
Tree. Click the SSM Output tab.
Parameters
Line Port External Clock Source, This field displays the line
Shelf ID (shelf name)-slot port and the external clock
number-board name-port interface name.
number (port name)
2(RM2/TM2) fiber.
Output S1 Byte Info Enabled, Disabled Output S1 Byte Info-

Default: Enabled Enables an NE in a clock
subnet to send SSM
messages to the NEs in
other clock subnets if the
standard or extended SSM
protocol is enabled. In
normal situation, however,
this parameter should be
disabled to prevent mutual
interference of clock
subnets.
for the line clock source.
2.7.4.12.11 Parameters: Clock ID Status

When you create a clock subnet or handle a clock fault, you can distinguish different clock
sources by clock ID. In this user interface, you can query and set the enabling status of clock
IDs.
Navigation Path
Tree. Click the Clock ID Output tab.

Parameters
Line Port Shelf ID (shelf name)-slot This field displays the name
number-board name-port of the tributary and line port.
number (port name)
2(RM2/TM2) fiber.
Output Clock ID Enabled, Disabled This field allows you to set

Default: Enabled whether the output service
through the port carries any
clock ID signal or not.
2.7.4.12.12 Parameters: Clock Source Reversion Parameter

In this user interface, you can query and set the reversion mode and WTR time of clock
sources.
Navigation Path
In the NE Explorer, select an NE and choose Configuration > Clock > Physical Clock >
Clock Source Switching from the Function Tree. Click the Clock Source Reversion tab.
Parameters
NE Name For example: NE1 Displays the name of an NE.
Higher-Priority Clock Auto-Revertive, Non- If two clock sources have

Source Reversion Revertive the same quality level but
Default: Auto-Revertive different priorities, the NE
automatically switches to
the clock source with a
lower priority when the
clock source with a higher
priority is degraded. When
higher priority recovers, you
can set the Higher-Priority
Clock Source Reversion
parameter to determine
whether to enable the NE to
automatically switch to the
priority.

Clock Source WTR 0 to 12 The Clock Source WTR

Time(min) Default: 5 Time(min) parameter
provides an option to set the
time from detection of
signal recovery to triggered
response of the clock
selector. The WTR time is
set to prevent the clock
selector from responding to
a transient signal recovery.
In this manner, the clock
signals are re-selected as the
clock source only when the
synchronous clock signals
recover from a failure and
stay valid within the WTR
time.
Clock Source Hold-Off 0, 3 to 18, step length is 1. Indicates the hold-off time
Time(100ms) Default: 0 of a clock source switching
event.
l By default the value is 0,
which means that the
hold-off timer is
disabled.
l When a clock source for
an NE fails, the status of
the clock is sent to the
select flow only after the
specified Clock Source
Hold-Off Time(100ms)
elapses so that the NE
can determine whether to
select another clock
source. The Clock
Source Hold-Off
Time(100ms) ensures
that a short-term clock
signal failure is not sent
to the select flow for
clock source switching.
2.7.4.12.13 Parameters: Clock Source Switching

In this user interface, you can query the clock source switching status and perform clock
source switching.

Navigation Path
Clock Source Switching from the Function Tree. Click the Clock Source Switching tab.
Parameters
Clock Source Internal Clock Source, This field displays the

External Clock Source, configured clock source.
Shelf ID (shelf name)-slot
number-board name-port
number (port name)
Current Status Valid, Invalid This field shows the clock

source is valid or invalid.
For query only.
Lock Status Lock, Unlock This field allows you to

enable or disable the
switching operation.
Switching Source Internal Clock Source, This field displays the

External Clock Source, switched clock source that
Shelf ID (shelf name)-slot the NE is tracing.
number-board name-port
number (port name)
Switching Status Forced Switching, Manual This field displays the

Switching, Normal switching status of clock
source.
2.7.4.12.14 Parameters: Clock Synchronization Status

In this user interface, you can query clock synchronization status of equipment, and set NE
clock working mode, synchronous source and data output method in the holdover mode.
Navigation Path
Clock Synchronization Status from the Function Tree.
Parameters
NE Name For example: NE3 Displays the name of an NE.

NE Clock Mode Tracing Mode, Holdover The NE Clock Mode

Mode, Free-Run Mode parameter indicates the
current working mode of the
clock board on the NE. The
NE selects the best clock
source by running a
protocol. If the best clock
source is the local clock, the
clock board is in the tracing
mode. In the tracing mode,
if all the clock sources are
lost, the clock board
switches to the holdover
mode. If the priority table
contains only the local clock
source, the clock board
directly switches to the free-
run mode.
l Tracing Mode: Indicates
the normal working
mode. When there are
services on the NE, the
NE maintains
synchronization with the
input reference clock
source.
l Holdover Mode:
Indicates that the local
clock considers the
stored frequency
information as the timing
reference when all the
reference clock sources
are lost.
l Free-Run Mode:
Indicates that the local
clock functions on the
basis of the internal
oscillator.

S1 Byte Synchronous Synchronous Source Specifies the

Quality Info Unavailable, Quality synchronization quality
Unknown, G.811 Reference information in the S1 byte
Clock, G.812 Transit Clock, that is output by the
G.812 Local Clock, SDH currently traced
equipment timing source synchronous source.
(SETS) signal The S1 Byte Synchronous
Quality Info parameter
indicates the quality of the
traced clock source. As
defined in the SSM
protocol, each clock source
corresponds to a certain
quality level. The clock of
the highest priority and
quality is selected according
to the protocol.
Unavailable: indicates
that the SSM protocol is
disabled and the S1 byte
synchronization quality
information output by
the synchronous source
is not available.
l Quality Unknown:
indicates that the SSM
protocol is enabled but
the S1 byte
is unknown.
protocol is enabled and
the S1 byte
is the G.811 reference
clock.
the S1 byte

is the G.812 transit

clock.
the S1 byte
is the G.812 local clock.
the S1 byte
is the synchronous
equipment timing source
(SETS) clock.
S1 Byte Clock Synchronous Source Specifies the

Synchronous Source Unavailable, Quality synchronization quality
Unknown, G.811 Reference information in the S1 byte
Clock, G.812 Transit Clock, that is output by the
G.812 Local Clock, SDH currently traced
equipment timing source synchronous source.
(SETS) signal The S1 Byte Clock
Synchronous Source
parameter indicates the best
clock source. As defined in
the SSM protocol, the entire
NE traces the best clock
source, that is, the clock
source with the highest
quality and priority.

Synchronous Source External Clock Source, Displays the trace source of

Shelf ID (shelf name)-slot the current NE clock. For
number-board name-port query only.
number (port name) Normally, the synchronous
source should be a clock
priority among the clock
stratums. If the synchronous
source cannot be traced, try
to trace a clock source with
a lower priority level
according to the sequence of
the clock stratums.
Data Output Method in Normal Data Output, Keep The Data Output Method
Holdover Mode the Latest Data in Holdover Mode
Default: Normal Data parameter provides an
Output option to set the method of
outputting data in holdover
mode. When all the clock
sources of an NE are lost,
the NE enters the holdover
mode. The NE may keep the
latest data forever or
maintain the holdover state
for 24 hours or a specified
period. If the NE maintains
the holdover state, the NE
switches to the free-run
mode when the period of 24
hours or a specified period
expires.

SSM Output Quality G.811 Clock Signal, G.812 Indicates the threshold of
Threshold Transit Clock Signal, G.812 output clock sources quality
Local Clock Signal, G.813 for an NE.
SETS Clock Signal l if the clock quality level
Default: G.811 Clock Signal of an NE is equal to or
higher than SSM Output
specified SSM Output
Quality Threshold is
sent to the downstream
NE.
l if the clock quality level
is lower than the
specified SSM Output
actual clock quality level
is sent to the downstream
NE.
SSM Input Quality G.811 Clock Signal, G.812 Indicates the threshold of
Threshold Transit Clock Signal, G.812 input clock sources quality
Local Clock Signal, G.813 for an NE. The clock
SETS Clock Signal sources are specified for the
Default: G.811 Clock Signal NE according to this
threshold.
lower than the SSM
Input Quality
Threshold, the NE
reports an
SSM_QL_FAILED
alarm, and specifies the
clock source as invalid.
higher than or the same
as the SSM Input
NE transparently
transmits the quality
level of the clock source
to the normal select flow
so that the normal select
flow selects the clock as
its clock source.
2.7.4.12.15 Parameters: Clock Source Switching Conditions

In this user interface, you can query and set clock source switching conditions, and the status
of switching condition enabling.

Navigation Path
Clock Source Switching from the Function Tree. Click the Clock Source Switching
Conditions tab.
Parameters
Clock Source Shelf ID (shelf name)-slot This field displays the

number-board name-port name of the clock source.
number (port name)
OTU1_DEG Alarm Yes, No Specifies the switching

Default: No condition enabling status.
When an OTU1_DEG
alarm occurs in the NE,
the NE regards that the
corresponding clock
source fails.
OTU2_DEG Alarm Yes, No This field allows you to

Default: No set the switching
condition enabling status.
When an OTU2_DEG
corresponding clock
source fails.

When an OTU3_DEG
corresponding clock
source fails.

When an OTU4_DEG
corresponding clock
source fails.

ODU2_PM_AIS Alarm Yes, No This parameter allows you

Default: No to set the switching
When an ODU2_PM_AIS
corresponding clock
source fails.
ODU2_PM_DEG Alarm Yes, No This parameter allows you

Default: No to set the switching
When an
ODU2_PM_DEG alarm
occurs in the NE, the NE
regards that the
corresponding clock
source fails.
MS_AIS Alarm Yes, No Sets the switching

Default: No condition enable status.
When an MS_AIS alarm
regards that the
corresponding clock
source fails.
B2_EXC Alarm Yes, No This field allows you to

When an B2_EXC alarm
regards that the
corresponding clock
source fails.
2.7.4.12.16 Parameters: Phase-Locked Source Output by External Clock

In this user interface, you can set the external clock source attributes of the 2M phase-locked
source. You can set the output mode, output timeslot, output threshold, failure condition, and
failure action of the 2M phase-locked source external clock.
Navigation Path
> Phase-Locked Source Output by External Clock from the Function Tree.

Parameters
2M Phase-Locked Source External Clock Source 1, This field displays the

Number External Clock Source 2 numbering IDs of the
outputs from external clock
sources.
External Clock Output 2Mbit/s, 2MHz The External Clock

Mode Default: 2Mbit/s Output Mode parameter
format of the 2M output
clock signals from the
external clock source.
The 2 MHz clock signals
cannot carry any other
information. If you set 2M
Phase-Locked Source Fail
Action to 2M Output S1
Byte Unavailable or Send
AIS, the failure information
cannot be transmitted to the
equipment using the
external output clock signals
when the external output
fails.
External Clock Output ALL, SA4, SA5, SA6, SA7, The External Clock
Timeslot SA8 Output Timeslot parameter
Default: ALL provides an option to set the
timeslots used by the SSM
quality information in the
output clock signals.
l ALL: All timeslots
l SA4: sa4 timeslot
l SA5: sa5 timeslot
l SA6: sa6 timeslot
l SA7: sa7 timeslot
l SA8: sa8 timeslot
when External Clock
Output Mode is set to
2Mbit/s.

External Source Output Threshold Disabled, Not The External Source

Threshold Inferior to G.813 SETS Output Threshold
Signal, Not Inferior to G. parameter provides an
812 Local Clock Signal, Not option to specify the extent
Inferior to G.812 Transit to which the 2M external
Clock Signal, Not Inferior to output clock signals are
G.811 Clock Signal degraded to cause an output
Default: Threshold Disabled failure.
If the SSM protocol is
running in the Stop SSM
Protocol mode, setting this
parameter is ineffective,
because the current clock
source does not contain
quality information.
When the quality of the
traced clock source is lower
than the specified threshold,
the 2M clock signals are
output according to the 2M
Action value.

2M Phase-Locked Source AIS, LOF, AIS OR LOF, No The 2M Phase-Locked

Failure Condition Failure Condition Source Failure Condition
Default: No Failure parameter provides an
Condition option to specify the alarm
in 2M external input clock
as a condition of an input
failure.
The parameter value has a
direct impact on clock
source selection of the
system. For example, when
the AIS alarm is not
considered as a condition of
an input failure, the system
still traces the 2M external
input clock and does not
switch the clock sources,
even when the system
detects an AIS alarm.
If the system needs to the
trace the external clock even
when the system receives
the AIS or LOF alarm, do
not enable the AIS or LOF
alarm as a failure condition.
Otherwise, enable the AIS
or LOF alarm as a failure
condition.
l AIS
– If the AIS alarm is
enabled as a failure
condition, the 2M
external input clock is
considered failed
when the system
detects an AIS alarm.
– If the AIS alarm is
not enabled as a
failure condition, the
2M external input
clock is not
considered as a
failure even when the
system detects an AIS
alarm.
l LOF
– If the LOF alarm is
enabled as a failure

condition, the 2M
external input clock is
considered as a
failure when the
system detects a LOF
alarm.
– If the LOF alarm is
not enabled as a
failure condition, the
2M external input
clock is not
considered as a
failure even when the
system detects a LOF
alarm.
The AIS or LOF alarm can
be detected only when the
mode of the external clock
source is set to 2Mbit/s.
When the mode of the
external clock source is set
to 2MHz, this parameter is
invalid.

2M Phase-Locked Failure 2M Output S1 Byte The 2M Phase-Locked

Handing Unavailable, Send AIS, Shut Failure Handing parameter
Down Output provides an option to
Default: Shut Down Output specify the type of the
signals output by the
external clock port when the
2M phase-locked source
fails.
to the application scenarios
of the external output and
the processing capability of
the equipment that uses the
external output clock.
l 2M Output S1 Byte
Unavailable:
The external clock
signals are output
normally but the quality
information in the S1
byte is unavailable.
l Send AIS:
The external output is
still available and the
AIS signals are output.
l Shut Down Output:
The 2M external output
port is disabled when the
phase-locked source
fails.
If the ongoing working
mode of the SSM protocol is
Stop SSM Protocol, the S1
byte of the external output
clock is unavailable. In this
case, if you set this
parameter to 2M Output S1
Byte Unavailable, this
parameter is ineffective.
When External Clock
Source Mode is set to
2MHz, the S1 byte and AIS
signals cannot be carried. In
this case, if you set this
parameter to 2M Output S1
AIS, this parameter is
ineffective.

Force Output Shutdown Enabled, Disabled This field allows you to

Default: Disabled enable or disable the forced
shutdown of outputs.
2.7.4.12.17 Parameters: Clock Signal Pass-through

In this interface, you can query and set the parameters of the clock signal pass-through.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > Clock Signal Pass-
through.
Parameters
Source Slot For example: Indicates the source slot

Shelf1(subrack)-22-11ST2 name.
Source Port For example: 1(RM1/TM1) Indicates the source port

name
Sink Slot For example: Indicates the sink slot name.

Shelf4(subrack)-1-11TS2
Sink Port For example: 2(RM2/TM2) Indicates the sink port name.
Pass-through Type PTP Clock Sets the pass-through type

of the clock.
2.7.5 Configuring Physical Clocks (OSN 9800 U Series: U1CTU/

S1CTU)

This topic describes the clock configuration process based on a flow chart.
Figure 2-16 Configuration process for Physical Synchronization

Configure physical-layer clocks to implement frequency synchronization and query the clock
synchronization status. For details, see Table 2-12.
Table 2-12 Clock configuration process

Operation Remarks
2.7.5.2 Optional.
Configuring When the line boards and tributary boards are used to provide clock
Transport synchronization, Service Type, Port Mapping must be set.
Clock
Attributes of
Boards
2.7.5.3 Optional.
Configuring To prevent clock signal deterioration, you must add a BITS clock source
External for clock compensation when more than 10 NEs are configured. In this
Clock Ports case, you must set parameter Phase-Locked Source Output of External
Clocks.
2.7.5.4 Mandatory.
Configuring This operation specifies the priority of each required clock source. This
Clock provides a criterion for selecting clock sources in case of a clock
Attributes switching event.
To provide a clock source selection basis for each clock source during
clock switching, you must set parameters System Clock Source Priority
Table, 2M External Clock Source Priority Table, Clock Quality, and
Higher-Priority Clock Source Reversion.
2.7.5.5 Optional.
Configuring Clock synchronization at the physical layer supports clock source
the Clock selection and switching in the following scenarios:
Source
Protection l When the SSM protocol is not enabled: Configuring the clock source
protection is not required.
l When the standard SSM protocol is enabled: Enabling standard SSM
protocol control and configuring the SSM output are required.
l When the extended SSM protocol is enabled: Enabling extended SSM
protocol control, configuring the clock subnet, and configuring the
SSM output are required.
2.7.5.6 Mandatory.
Viewing Clock After all the clock configuration operations are completed, query all
Synchronizati ports for the clock synchronization status to ensure that the port
on Status synchronization status is the same as defined in the networking diagram.
2.7.5.7 Mandatory.
Viewing the Correct clock tracing relationships are critical to ensure the clock
Clock Tracing synchronization within the entire network. Using the U2000, you can
Status monitor the clock tracing status of each NE.

Operation Remarks
2.7.5.8 Optional.
Configuring When the clock source quality deteriorates, you must manually switch
Clock Source clock sources by performing operations To manually switch clock
Switching sources, perform the operations of setting clock source switching
conditions, enabling clock source switching, and starting clock source
switching.
2.7.5.2 Configuring Transport Clock Attributes of Boards

To achieve frequency synchronization, the Service Type, Port Mapping.
Prerequisites
Context
NOTE
After the 9800 V100R001C20 version, you do not need to set Synchronous Clock Enabled.
NOTICE
restored.
Procedure
Availability.

----End
2.7.5.3 Configuring External Clock Ports

This topic describes how to configure attributes of external clocks for a device so that the
device can properly extract external clock signals.
Prerequisites
l The CTU board has been created.
Procedure
When a clock signal passes through 10 or more NEs, frequency offset and drift may occur. As
a result, the clock signal transmitted to the downstream NE is degraded. To prevent this from
happening, a 2M phase-locked source must be used to optimize the clock signal.
Step 1 Set the external clock attributes of the 2M phase-locked source. Set the parameters manually,
such as External Clock Output Shutdown, External Clock Output Mode, External Clock
Output Timeslot, and External Source Output Threshold. For details about these
parameters, see 2.7.5.10.9 Parameters: Phase-Locked Source Output by External Clock.

----End
2.7.5.4 Configuring Clock Attributes

Clock attributes include system clock source priority table, 2M external clock source priority
table, clock quality, and clock source reversion mode.
Prerequisites
Configuring the System Clock Source Priority Table

Configuring the system clock source priority table specifies the priority of each required clock
switching occurs.
NOTE
When packet boards are configured to transmit physical clock signals to downstream devices, the port
on the local end also needs to be added to the clock source priority list. Otherwise, the clock signals will
be interrupted.
Step 1 Configure System Clock Source Priority List.

about these parameters, see 2.7.5.10.1 Parameters: System Clock Source Priority List.
----End
Configuring the 2M External Clock Source Priority Table

Configuring the system clock source priority table specifies the priority of each required
external clock source. This provides a criterion for selecting clock sources in the event that of
clock switching occurs.
Step 1 Check the 2M PLL clock source of the external clock port.
NOTE
The relationship between the 2M PLL clock source and the external clock port depends on the sequence
of setting the cascaded external ports on the clock board.
Step 2 Configure Priority for PLL Clock Sources of 1st External Output List or Priority for
PLL Clock Sources of 2nd External Output List.

NOTE
Users can configure the priority table for a 2M external clock. In addition, users can configure line clock
sources as phase-locked sources, and configure the priorities of line clock sources in the priority table
for the output phase-locked source of the first or second external clock.
about these parameters, see 2.7.5.10.2 Parameters: Priority for PLL Clock Sources of 1st
External Output and 2.7.5.10.3 Parameters: Priority for PLL Clock Sources of 2nd
External Output.
----End
Configuring the Quality of Clock Sources

In a complex clock network, there may be some unknown clock sources. You can uniformly
define these clock sources as unavailable clocks so that NEs do not trace wrong clock sources.
The NE obtains their quality information automatically for clock sources that are allocated to
an NE. You should define the quality level of clock sources only during testing and
maintenance.
Step 1 Configure Clock Quality to the desired level. For details about these parameters, see
2.7.5.10.5 Parameters: Clock Source Quality.

NOTE
The default value Auto is recommended for most situations.
----End
Configuring the Clock Source Reversion Mode

When there are multiple clock sources for an NE, set the clock sources to automatic reversion
mode, so that the deteriorated clock source automatically becomes the traceable timing
reference after it recovers.
Step 1 Configure Higher-Priority Clock Source Reversion, Clock Source WTR Time(min),
Clock Source HoldOff Time(100ms) correspondingly. For details about these parameters,
see 2.7.5.10.6 Parameters: Clock Source Reversion Parameter.
NOTE
l Do not set Clock Source WTR Time(min) to be 0 to avoid repeated switching when the clock is
unstable.
l Clock Source HoldOff Time(100ms): The Clock Source HoldOff Time(100ms) can be set within
the range of 300 ms to 1800 ms with the step length of 100 ms.
l When a clock source for an NE fails, the status of the clock is sent to the select flow only after the
specified Clock Source HoldOff Time(100ms) elapses so that the NE can determine whether to
select another clock source. The Clock Source HoldOff Time(100ms) ensures that a short-term
clock signal failure is not sent to the select flow for clock source switching.
----End
2.7.5.5 Configuring the Clock Source Protection

In a complex clock network, clock protection needs to be configured for all NEs. After the
clock source is set and the clock priority level for the NEs is specified, the standard SSM or
extended SSM protocol can be enabled to prevent the NEs from tracing an incorrect clock
source.
Prerequisites

Procedure
Step 1 Configure Enable Standard SSM Protocol Control or Enable Extend SSM Protocol
Control.
NOTE
The same SSM protection protocol must be used within the same clock protection subnet.
Step 2 Optional: If the Enable Extend SSM Protocol Control is selected, set the Clock Source ID
of the Clock Source. For details about these parameters, see 2.7.5.10.4 Parameters: Clock
Subnet.

NOTICE
If the extended SSM protocol is enabled, it is not recommended to change the ID of the clock
source being traced by the master NE when the clock tracing performance is stable. This
ensures proper transmission of clock IDs and prevents a clock loop.
----End
2.7.5.6 Viewing Clock Synchronization Status

If the clocks between NEs in the network are not synchronous, pointer justification errors, bit
errors, and even service interruption may occur on the NE. Using the U2000, you can
ascertain and monitor the synchronization status of the NE clocks.
Prerequisites
Procedure
Step 1 View clock synchronization status. For details about these parameters, see 2.7.5.10.8
Parameters: Clock Synchronization Status.
----End

Prerequisites

Context
Procedure
queried, click OK.
----End
2.7.5.8 Configuring Clock Source Switching

When a traced clock source degrades, clock switching needs to be performed manually.
Prerequisites
l The clock source has been created.
Procedure
When the traceable clock source in a network deteriorates, NEs may not be able to execute a
switch on the clock source. Users need to manually switch the clock source to prevent clock
deterioration from affecting the normal running of NEs.
NOTICE
Performing clock source switching may cause service interruption.
Step 1 Perform clock source switching, including the operation of selecting Forcible Source
Selection or Manual Source Selection. For details about these parameters, see 2.7.5.10.7
Parameters: Clock Source Switching.

Step 2 Optional: To restore the automatic clock source selection mode, right-click the switched
clock source and choose Clear Source Selection.
----End
2.7.5.9 Configuring OTUs or Tributary Boards to Implement Synchronous

Ethernet Transparent Transmission
OTUs or tributary boards provide the synchronous Ethernet transparent transmission function
to transparently transmit frequency signals only but not extract or synchronize the frequency
signals. To implement synchronous Ethernet transparent transmission, ensure that the Service
Type and Port Mapping values of boards are correctly specified on the U2000.
Prerequisites
Context
NOTE
When a board supports transparent transmission of synchronous Ethernet services, before changing the
value of Port Mapping for a port on the board from Bit Transparent Mapping to Mac Transparent
Mapping, you must delete the port from the clock priority table.
NOTICE
restored.
Procedure

Availability.
----End
2.7.5.10 Parameters: Physical Clocks (OSN 9800 U Series: U1CTU/S1CTU)

2.7.5.10.1 Parameters: System Clock Source Priority List

In this user interface, you can query, modify and set the priority list of clock sources, select
the external clock source mode, and select the tributary board for tributary clock source.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > Physical Layer
Clock > Clock Source Priority from the Function Tree. Click the System Clock Source
Priority List tab.
Parameters
Clock Source Type For example: Internal Clock Displays the type of the
Clock Source For example: local Displays the name of the

clock source.
External Clock Source 2M Bit/s, 2M Hz The External Clock Source

Mode Default: 2M Bit/s Mode parameter provides
an option to set the format
of the input clock signals
from the external clock
source.

Synchronous Status Byte Sa4, Sa5, Sa6, Sa7, Sa8 The Synchronous Status
Default: Sa4 Byte parameter provides an
option to set the timeslots
for the SSM quality
information in the input
external clock signals.
Clock Source Priority (1 is 0 to 255 Displays the priority

the highest) Default: 1 sequence of this clock
source.
2.7.5.10.2 Parameters: Priority for PLL Clock Sources of 1st External Output
must configure the priority table for phase-locked sources in this user interface. In this user
interface, you can also query and set priority table for phase-locked sources of first external
output clocks and adjust the priority of each clock source.
lock the phase of first external output clock. An internal source can be assigned with the
Navigation Path
Sources of 1st External Output List tab.
Parameters
Shelf ID /slot number/sub- source. You can either add
board number/port number or delete a clock source in
the clock source priority list.

Clock Source Priority(1 is 0 to 255 Set the priority sequence of

the highest) Default: 1 this clock source.

2.7.5.10.3 Parameters: Priority for PLL Clock Sources of 2nd External Output
must configure the priority table for phase-locked sources in this user interface. You can also
query and set priority table for phase-locked sources of second external output clocks and
adjust the priority of each clock source.
lock the phase of second external output clock. An internal source can be assigned with the
Navigation Path
Sources of 2nd External Output List tab.
Parameters
Shelf ID /slot number/sub- source. You can either add
board number/port number or delete a clock source in

Clock Source Priority(1 is 0 to 255 Set the priority sequence of

the highest) Default: 1 this clock source.
2.7.5.10.4 Parameters: Clock Subnet

In this interface, you can query, set or activate clock subnets, clock source IDs, the SSM
protocol and the S1 byte of an NE.
Navigation Path
Clock > Clock Subnet Configuration from the Function Tree. Click the Clock Subnet
Configuration Attribute tab.

Parameters
Affiliated Subnet 0 to 255 This field enables you to set

Default: 0 the clock subnet number of
the NE.

Protection Status Enable Standard SSM The Protection Status

Protocol Control, Enable parameter indicates the
Extend SSM Protocol working mode of the clock
Control, Disable SSM protocol for a clock subnet.
Protocol Control l Stop SSM Protocol:
Default: Disable SSM
Protocol Control – When the SSM
protocol is disabled,
clock signals do not
contain clock quality
information. Clocks
are selected based on
the specified clock
source priorities. In
this mode, timing
loops may result.
a non-ring network
with multiple clock
sources. The clock
source is selected
according to the clock
source priority list.
l Start Standard SSM
Protocol:
– When the standard
SSM protocol is
enabled, clock quality
levels are used to
prevent timing loops.
a non-ring network
with multiple clock
sources. The clock
signal carries quality
information. It is used
when the WDM/OTN
device interconnects
with a third-party
device.
l Start Extended SSM
Protocol:
– When the extended
SSM protocol is
enabled, clock IDs
are used to prevent
timing loops.

– This protocol is
applicable only to a
ring network. It is a
Huawei proprietary
protocol and cannot
be used when the
WDM/OTN device
interconnects with a
third-party device. If
the extended SSM
an NE, the standard
SSM protocol can be
configured on the
downstream NEs;
however, it cannot be
configured on the NE
if the standard SSM
the upstream NEs.
Clock Source For example: local This field displays the

configured clock source of
the NE. You can either add
or delete a clock source in
Clock Source ID 0 to 15 The Clock Source ID

Default: 0 parameter provides an
option to set an ID for a
clock source. ITU-T defines
only the lower four bits of
the S1 byte and Huawei
defines the higher four bits
of the S1 byte as the clock
source ID. In the case of a
network fault, an NE may
trace its own clock and the
clock cross-tracing problem
may occur. The clock source
ID helps avoid such a
problem.
When the system traces an
external clock source or a
clock source of another
clock subnet, this parameter
should be set. For the line
clock sources of other
subnets, however, this
parameter does not need to
be set.

2.7.5.10.5 Parameters: Clock Source Quality

In this user interface, you can query the clock source quality and set the clock source
parameters, such as configuration quality and clock quality.
Navigation Path
Clock > Clock Subnet Configuration from the Function Tree. Click the Clock Quality tab.
Parameters
Clock Source For example: local This field displays the name
of the configured clock
source. You can either add
or delete a clock source in
Configured Quality Auto, G.811 Clock, G.812 The Configured Quality

TNC, G.812 LNC, SDH, parameter provides an
Unavailable Clock Source, option to set the
Unknown SSM Level configuration quality level
Default: Auto of a clock source. This
parameter is applicable to
certain special scenarios or
tests and therefore does not
need to be set in most cases.
When the parameter value
changes, the clock source
selecting protocol re-selects
a clock source. As a result, a
clock source switching may
occur.
Set this parameter only
when a clock source does
not contain the clock quality
information or the clock
quality information
contained in a clock source
is not required. For example,
in the case of an external
clock in 2MHz mode, this
parameter needs to be set.

Received Quality - The Received Quality

parameter indicates the
quality information about
the clock source received by
an NE. When receiving a
clock source, the NE
extracts the clock quality
information from the S1
byte in the clock source.
In most cases, the clock
source of the highest quality
is most likely to be selected
as the current clock source.
2.7.5.10.6 Parameters: Clock Source Reversion Parameter

In this user interface, you can query and set the reversion mode and WTR time of clock
sources.
Navigation Path
In the NE Explorer, select an NE and choose Configuration > Clock > Physical Layer
Clock > Clock Source Switching from the Function Tree. Click the Clock Source
Reversion tab.
Parameters
Higher-Priority Clock Revertive Mode, Non- If two clock sources have

Source Reversion Revertive Mode the same quality level but
Default: Revertive Mode different priorities, the NE
automatically switches to
lower priority when the
priority is degraded. When
higher priority recovers, you
can set the Higher-Priority
Clock Source Reversion
parameter to determine
whether to enable the NE to
automatically switch to the
priority.

Clock Source WTR 0 to 12 The Clock Source WTR

Time(min) Default: 5 Time(min) parameter
response of the clock
set to prevent the clock
In this manner, the clock
clock source only when the
synchronous clock signals
time.
Clock Source HoldOff 3 to 18, step length is 1. Indicates the hold-off time
Time(100ms) Default: 10 of a clock source switching
event.
When a clock source for an
NE fails, the status of the
clock is sent to the select
flow only after the specified
Clock Source HoldOff
Time(100ms) elapses so
that the NE can determine
whether to select another
clock source. The Clock
Source HoldOff
Time(100ms) ensures that a
short-term clock signal
failure is not sent to the
select flow for clock source
switching.
2.7.5.10.7 Parameters: Clock Source Switching

In this user interface, you can query the clock source switching status and perform clock
source switching.
Navigation Path
Clock > Clock Source Switching from the Function Tree. Click the Clock Source Switching
tab.

Parameters
Clock Source For example: local This field displays the

configured clock source.
Current Status Valid, Invalid This field shows the clock

source is valid or invalid.
For query only.
Switching Status Forcible Source Selection, This field displays the

Manual Source Selection, switching status of clock
Normal source.
Switching Source Type For example: Internal Clock This field displays the
Source switched clock source type
that the NE is tracing.
Switching Source For example: local This field displays the

switched clock source that
the NE is tracing.
2.7.5.10.8 Parameters: Clock Synchronization Status

In this user interface, you can query clock synchronization status of equipment, and set NE
clock working mode, synchronous source and data output method in the holdover mode.
Navigation Path
Clock > Clock Synchronization Status from the Function Tree.

Parameters
Ne Clock Mode Free-Run, Fast Lock, Trace, The Ne Clock Mode

Hold parameter indicates the
current working mode of the
clock board on the NE. The
NE selects the best clock
source by running a
protocol. If the best clock
source is the local clock, the
clock board is in the tracing
mode. In the tracing mode,
if all the clock sources are
lost, the clock board
switches to the holdover
mode. If the priority table
contains only the local clock
source, the clock board
directly switches to the free-
run mode.
S1 Byte Synchronous - The S1 Byte Synchronous

Quality Info Quality Info parameter
indicates the quality of the
traced clock source. As
defined in the SSM
protocol, each clock source
corresponds to a certain
quality level. The clock of
the highest priority and
quality is selected according
to the protocol.
S1 Byte Synchronous - The S1 Byte Clock

Source Synchronous Source
parameter indicates the best
clock source. As defined in
the SSM protocol, the entire
NE traces the best clock
source, that is, the clock
quality and priority.

Synchronous Source For example: local Displays the trace source of

the current NE clock. For
query only.
Normally, the synchronous
source should be a clock
priority among the clock
stratums. If the synchronous
source cannot be traced, try
to trace a clock source with
a lower priority level
according to the sequence of
the clock stratums.
Data Output Method in 24th Keep, Long Term Keep The Data Output Method
Holdover Mode Default: 24th Keep in Holdover Mode
parameter provides an
option to set the method of
outputting data in holdover
mode. When all the clock
sources of an NE are lost,
the NE enters the holdover
mode. The NE may keep the
latest data forever or
maintain the holdover state
for 24 hours or a specified
period. If the NE maintains
the holdover state, the NE
switches to the free-run
mode when the period of 24
hours or a specified period
expires.
Unknown SSM Level Map G.811 Clock, G.812 TNC, The Unknown SSM Level
G.812 LNC, SDH, Map parameter provides an
Unavailable Clock Source option to set the quality
level when the quality
information of a clock
source is unknown.
2.7.5.10.9 Parameters: Phase-Locked Source Output by External Clock

In this user interface, you can set the external clock source attributes of the 2M phase-locked
source. You can set the output mode, output timeslot, and output threshold.
Navigation Path
Clock > Phase-Locked Source Output by External Clock from the Function Tree.

Parameters
2M Phase-Locked Source bits0, bits1 This field displays the

Number numbering IDs of the
outputs from external clock
sources.
External Clock Output false, true This field allows you to

Shutdown Default: false enable or disable the forced
shutdown of outputs.
External Clock Output 2M Bit/s, 2M Hz The External Clock

Mode Default: 2M Bit/s Output Mode parameter
format of the 2M output
clock signals from the
The 2 MHz clock signals
cannot carry any other
information. If you set 2M
Action to 2M Output S1
AIS, the failure information
cannot be transmitted to the
equipment using the
external output clock signals
when the external output
fails.
External Clock Output ALL, Sa4, Sa5, Sa6, Sa7, The External Clock
Timeslot Sa8 Output Timeslot parameter
Default: ALL provides an option to set the
timeslots used by the SSM
quality information in the
output clock signals.
when External Clock
Output Mode is set to 2M
Bit/s.
l ALL: All timeslots
l SA4: sa4 timeslot
l SA5: sa5 timeslot
l SA6: sa6 timeslot
l SA7: sa7 timeslot
l SA8: sa8 timeslot

External Source Output Unavailable Clock Source, The External Source

Threshold SDH, G.812 LNC, G.812 Output Threshold
TNC, G.811 Clock parameter provides an
Default: Unavailable Clock option to specify the extent
Source to which the 2M external
output clock signals are
degraded to cause an output
failure.
If the SSM protocol is
running in the Stop SSM
Protocol mode, setting this
parameter is ineffective,
because the current clock
source does not contain
quality information.
When the quality of the
traced clock source is lower
than the specified threshold,
the 2M clock signals are
output according to the 2M
Action value.
External Source Invalid No Condition, AIS Alarm, The External Source

Condition LOF Alarm, AIS or LOF Invalid Condition
Alarm parameter provides an
Default: No Condition option to specify the alarm
in 2M external input clock
as a condition of an input
failure.
2MPLL Los External Shutdown External Clock The 2MPLL Los External
Clock Output Action Output, External Clock Tx Clock Output Action
AIS Alarm, External Clock parameter provides an
Tx DNU Level option to specify the type of
Default: Shutdown External the signals output by the
Clock Output external clock port when the
2M phase-locked source
fails.
2.7.6 Physical Clock Capability of Huawei WDM/OTN Networks
2.7.6.1 Availability
This topic describes the board types and software versions that support physical clocks.

2.7.6.1.1 OSN 9800 Universal Platform Subrack Hardware and Version Support
This topic describes the board types and software versions of OSN 9800 universal platform
subrack that support physical clocks.
Table 2-13 Boards and device versions that support physical clocks (OTN & Packet & SDH)
in 9800 universal platform subrack (optical-layer configuration)
Board Type Board Name Device Start Version
Clock Boards TN12STG V100R001C20
TN13STG V100R002C10
OSC Boards ST2 V100R001C20
AST2 V100R002C10
Optical Multiplexer and SFIU V100R001C20

Demultiplexing Boards
2.7.6.1.2 OSN 9800 U Series Hardware and Version Support

This topic describes the board types and software versions of OSN 9800 U series subracks
that support physical clocks.
in OSN 9800 U series subracks (electrical-layer configuration)
Clock Boards TNU1CTU V100R001C20
TNS1CTU V100R001C30
Clock Interface EFI V100R001C20

Boards
Tributary T130, T216, T210, T220, G210, V100R001C20

Boards G220
E124, E208, E212, E302, E401 V100R001C30
S216, T230, TNV3T404, S208 V100R002C10
G402, G404, T220E V100R003C10
TNV3T401, TNV3T402 V100R005C00
Line Boards Turbo WDM boards V100R001C20
U401, U210 V100R001C30
TNU2N402, TNU2N401a V100R002C00

TNU3N401, TNU3N402, V100R002C10

TNU3SN402, TNU5N402,
TNU5N404, N402P
G402, G404 V100R003C10
U402 V100R005C00
TNU5N401, TNU4N501, V100R006C00

TNU4N502
TNU2N401P V100R006C10
l a: partially some board types supported. For details about the supported board types,
please email to supportmaster@huawei.com.
l T216/TNV1T210: Only ports 1-4 support synchronous Ethernet processing.
l T130/TNV3T230/TNV3T220/TNV3T210/TNV2T220E: When an electrical module is
inserted into a port, the port does not support physical clocks.
l When the line boards working in relay mode, they cannot work in physical clock mode
but can be used as regeneration boards to transparently transmit clock signals.
l When the ODUk cross-connect granularity of the line boards is configured as the
maximum granularity of supported services, the line board does not support physical-
layer clocks. The line board supports physical-layer clocks only when its ODUk cross-
connect granularity is configured as the lower-order cross-connect granularity.
When Ethernet services are received on a board, the port supporting synchronous Ethernet
varies according to the encapsulation type. The following table lists the supported
synchronous Ethernet processing and transparent transmission of the port.
Table 2-15 Synchronous Ethernet processing and transparent transmission

Service Access Port Mapping Processing of Synchronous
Synchronous Ethernet
Ethernet Packets Transparent
Transmission
GE GE (GFP-T) Supported Not supported
GE (TTT-GMP) Not supported Supported
10GE LAN Mac Transparent Mapping Supported Not supported

(10.7G)
Bit Transparent Mapping Not supported Supported

(11.1G)
100GE Mac Transparent Mapping Supported Not supported

ODU4 (100G)


Transmission

ODU4 (100G)
NOTE
When the port working mode is ODUflex non-aggregation mode (Any->ODUflex), synchronous
Ethernet processing is supported, and synchronous Ethernet transmission is not supported.
NOTE
When Ethernet services are received on a packet board in Table 2-14, the board supporting synchronous
Ethernet processing.
2.7.6.1.3 OSN 9800 M Series Hardware and Version Support

This topic describes the board types and software versions of OSN 9800 M series subracks
in OSN 9800 M series subracks (electrical-layer configuration)
Implementatio Board Type Device Start Version
n Method
Clock Boards CXP V100R006C00
Clock Interface EFI V100R006C00

Boards
Tributary Boards A212, G402, T206, T212, T402 V100R006C00
T401, M402 V100R006C10
Line Boards A212, G402, N206, N210, V100R006C00

TNU5N402, TNU5N401
Turbo WDM boards, U402, V100R006C10

TNG1N401, N501P


Transmission

(10.7G)

(11.1G)

ODU4 (100G)

ODU4 (100G)
NOTE
When the port working mode is ODUflex non-aggregation mode (Any->ODUflex), synchronous
Ethernet processing is supported, and synchronous Ethernet transmission is not supported.
2.7.6.1.4 OSN 8800 Hardware and Version Support

This topic describes the board types and software versions of OSN 8800 subracks that support
physical clocks.
in OSN 8800 subracks (optical-layer configuration)
AST2 V100R011C00
Optical SFIU V100R005C00

Multiplexer and
Demultiplexing
Boards
Table 2-19 Boards and device versions that support physical clocks (OTN & Packet) in OSN
8800 subracks (electrical-layer configuration)
Clock Boards TN52STG, TNK2STG V100R002C00

TN16XCH V100R006C00
TN16UXCM V100R007C00
TN12STG V100R008C10
TN54STG V100R009C10
TN13STG, TNK3STG V100R010C10
Clock Interface TN52STI V100R002C00

Boards
TN16ATE V100R006C00
Tributary Boards TOG V100R002C00
LEM24, LEX4 V100R005C00
THA, TOA, TN55TQX, V100R006C01

TN53TDX
TEM28 V100R006C03
TOX, THX, EG16, EX2 V100R007C00
TN55TTX V100R009C00
EX8 V100R008C10
TN55TSC V100R011C10
LQCP V100R013C00
Line Boards TN54NQ2, TN52ND2 V100R002C00
TN54NS3 V100R005C00
NPO2, NPO2E, TN53NQ2, V100R006C01

TN53ND2, TN53NS2,
TN57NQ2, TN57ND2
PND2 V100R007C00
NPS4, NPS4E, HUNS3, V100R009C10

HUNQ2
NOTE
The TN52ND2T04 board does not support the physical clock.
Table 2-20 Boards and device versions that support physical clocks (SDH) in OSN 8800
subracks (electrical-layer configuration)
Clock Boards TN16XCH, TN16UXCM, V100R007C00

TN16ATE, TN52STG

TN54STG V100R009C10
TNK3STG V100R010C10
Clock Interface TN52STI, TNL1STI V100R007C00

Boards
Tributary N1EGSH, N3EAS2 V100R007C00

Boards
Line Boards N4SLO16, N4SLQ64, V100R007C00

N3SLH41, N4SFD64,
N4SF64, N1SF64A,
N4SLD64, N4SL64,
N4SLQ16
HUNS3, HUNQ2 V100R008C00
TN54HSNS4 V100R011C10
NOTE
The TX2/RX2 and TX4/RX4 optical ports of the N1EGSH board can process synchronous Ethernet
clock signals.

Transmission

(10.7G)

(11.1G)

ODU4 (100G)

ODU4 (100G)

2.7.6.1.5 OSN 6800 Hardware and Version Support

This topic describes the board types and software versions of OSN 6800 subracks that support
physical clocks.
Table 2-22 Boards and device versions that support physical clocks (OTN) in OSN 6800
subracks (optical-layer configuration)
Board Name Board Name Device Start Version
AST2 V100R011C00
Optical SFIU V100R005C00

Multiplexer
and
Demultiplexin
g Boards
Table 2-23 Boards and device versions that support physical clocks (OTN) in OSN 6800
Cross Connect TN12XCS V100R005C00

Boards
Clock Boards TN11STG V100R005C00
TN12STG V100R008C10
TN13STG V100R010C10
Tributary LEM24, LEX4, V100R005C00

Boards TN52TOG, TN52TDX
TN53TDX, TN55TQX V100R006C01
Line Boards TN12ND2, TN52ND2 V100R005C00
TN53NQ2, TN53ND2, V100R006C01

TN53NS2
NOTE
The TN52ND2T04 board does not support the physical clock.


Transmission

(10.7G)

(11.1G)

ODU4 (100G)

ODU4 (100G)
2.7.6.1.6 OSN 1832 X16 Hardware and Version Support

This topic describes the board types and software versions of 1832 X16 subracks that support
physical clocks.
in OSN 1832 X16 subracks (optical-layer configuration)
ST4 V100R006C20
Optical DSFIU V100R005C00

Multiplexer
and
Demultiplexing
Boards
1832 X16 subracks (electrical-layer configuration)
Clock Boards TNF5UXCM V100R003C05
TNF5XCH V100R005C00
TNF5UXCME V100R005C20

TNZ5UXCMS V100R006C10
Clock Interface TNF1AUX V100R003C05

Boards
Tributary TNF5TOA, TNF5EM20 V100R003C05

Boards
TNF5TQX V100R005C00
TNF5TDX V100R005C10
TNF2LDX, V100R006C00
TNF2ELOM (STND)
TNZ5EX4, TNZ5EG10 V100R006C10
TNF6TTA V100R006C20
TNF6TOA V100R007C00
TNF1LDCA V100R008C10
Line Boards TNF5HUNQ2, V100R003C05

TNF5ND2
TNF5HSNQ2 V100R005C10
TNZ5UNQ2 V100R006C10
TNZ5UNS4, V100R006C20
TNF6HSNS4,
TNF6NP200,
TNF6NP200E
TNF2ELOM (STND) V100R007C10
TNZ5NP200, V100R008C00
TNZ5NP200E
NOTE
In ODU1_ODU0 mode (OTU1->ODU1->ODU0), the TNF5TOA/TNF6TTA/TNF6TOA board receives
OTU1 services from the client side and supports physical-layer clock processing, but does not support
transparent transmission of physical-layer clock signals.
Table 2-27 Boards and device versions that support physical clocks (SDH) in OSN 1832 X16
Clock Boards TNF5UXCM V100R003C05

TNF5XCH V100R005C00
TNF5UXCME V100R005C20
TNZ5UXCMS V100R006C10

Boards
Tributary TNF1PL3T, TNF1SP3D V100R003C05

Boards
TNF1EGS4 V100R005C00
TNF1CQ1, TNF1MD1 V100R006C10
TNF1TSP V100R006C20
TNF1PD1, TNF1DMS, V100R008C00

TNF1PL4D
Line Boards TNF1SL4D, V100R003C05

TNF1SL1Q,
TNF5HUNQ2
TNF5SLNO, V100R005C00
TNF5SL64D
TNF5NS4 V100R006C00
TNZ5UNQ2 V100R006C10
TNF6NP200, V100R006C20
TNF6NP200E,
TNZ5UNS4,
TNF6HSNS4,
TNF1TSP
TNZ5NP200, V100R008C00
TNZ5NP200E


Transmission

(10.7G)

(11.1G)

ODU4 (100G)

ODU4 (100G)
NOTE
l When the TNF1LDCA board receives OTU2 and OTU4 services on the client side, synchronous Ethernet
processing is supported and synchronous Ethernet transparent transmission is not supported.
l When the TNF1LDX board receives 10GE LAN services on the client side and the value of Port
Mapping is Bit Transparent Mapping (11.1G), only synchronous Ethernet transparent transmission is
supported. The TNF1LDX board does not support synchronous Ethernet processing.
2.7.6.1.7 OSN 1832 X8 Enhanced Hardware and Version Support

This topic describes the board types and software versions of 1832 X8 Enhanced subracks
in OSN 1832 X8 Enhanced subracks (optical-layer configuration)
OSC Boards ST2, AST4 V100R007C10
Optical DSFIU V100R007C10

Multiplexer
and
Demultiplexin
g Boards

1832 X8 Enhanced subracks (electrical-layer configuration)
Clock Boards TNZ1UXCL V100R007C10
TNZ2UXCL V100R008C10

Boards
Tributary TNF2LDX, V100R007C10

Boards TNF2ELOM(STND),
TNF6TTA, TNF6TOA,
TNZ5EX4, TNZ5EG10,
TNF1EG4C,
TNZ1UXCL(EX1)
TNF1LDCA, V100R008C10
TNZ2UXCL(EX1)
Line Boards TNZ5UNQ2, V100R007C10

TNF6HSNQ2,
TNF2ELOM(STND)
NOTE
The physical clock (OTN) processing function is supported only when the TNF6TTA/TNF6TOA board
is working in ODU1_ODU0 mode (OTU1->ODU1->ODU0).
Enhanced subracks (electrical-layer configuration)
Clock Boards TNZ1UXCL V100R007C10
TNZ2UXCL V100R008C10

Boards
Tributary TNF1SP3D, V100R007C10

Boards TNF1PL3T, TNF1CQ1,
TNF1MD1,
TNF1EGS4, TNF1TSP

Line Boards TNF1SL4D, V100R007C10

TNF1SL1Q,
TNF5SLNO,
TNZ5UNQ2,
TNF6HSNQ2,
TNZ1UXCL(SL64),
TNZ1UXCL(PSNS2)
TNZ2UXCL(PSNS2) V100R008C10

Transmission

(10.7G)

(11.1G)

ODU4 (100G)

ODU4 (100G)
NOTE
When the TNF1LDCA board receives OTU2 and OTU4 services on the client side, synchronous
Ethernet processing is supported and synchronous Ethernet transparent transmission is not supported.
2.7.6.1.8 OSN 1832 X4 Enhanced Hardware and Version Support

This topic describes the board types and software versions of 1832 X4 Enhanced subracks

Table 2-33 Boards and device versions that support physical clocks (Packet) in OSN 1832 X4
Clock Boards TMA1UXCL(STG) V100R008C10
Tributary TNZ5EG10, V100R008C10

Boards TMA1UXCL(EX2),
TMA1UXCL(G12A)
Line Boards TMA1UXCL(PSND2) V100R008C10
Clock Boards TMA1UXCL(STG) V100R008C10
Tributary TNF1SP3D, V100R008C10

Boards TNF1PL3T, TNF1EGS4
Line Boards TNF5SLNO, V100R008C10

TMA1UXCL(PSND2),
TMA1UXCL(SLND)
2.7.6.2 Physical Clocks Specifications

This topic describes the physical layer clock synchronization specifications that the OSN
equipment supports.
Table 2-35 Physical layer clock synchronization specifications
Item Specifications
Clock working modes l Tracing mode

l Holdover mode
l Free-run mode
Clock source l Synchronous Ethernet clock

l External clock
l E1 tributary clock source
l Line clock source
l Internal clock source
Synchronous Ethernet GE, 10GE, 100GE
External clock port 2.048 MHz or 2.048 Mbit/s signals ITU-T

G.703 compliance port

Item Specifications
Clock frequency accuracy 50ppb
Maximum number of NEs on a clock chain 20
Synchronization Status Message (SSM) Supported

protocol and extended SSM protocol
Clock sources The NE supports a maximum of 32 clock

sources.
Master and slave subrack clock cascading l OSN 9800:

– In a multi-subrack configuration,
master and slave universal platform
subracks are cascaded to achieve
frequency/phase synchronization.
– Multiple electrical subracks cannot
be cascaded in master/slave mode to
achieve frequency/phase
synchronization among the subracks.
Therefore, only one electrical
subrack of each NE supports
frequency/phase synchronization.
You are advised to configure all
boards on which the frequency and
phase must be synchronized in the
same subrack.
– The universal platform subrack and
electrical subrack cannot be cascaded
in master/slave mode to achieve
frequency/phase synchronization
among the subracks.
l OSN 1832 does not support cascading of
master and slave clock subracks.
l OSN 8800/6800 supports cascading of
master and slave clock subracks.
2.7.6.3 Feature Updates

This topic describes the physical clocks feature updates in the product versions, the reasons
for the updates, and the corresponding information updates. Any product versions that are not
listed in the document means that they have no feature updates.
2.7.6.3.1 OSN 9800 Feature Updates

The physical clock (OTN) is available since the OSN 9800 of V100R001C20 version. The
physical clock (SDH & Packet) is available since the OSN 9800 of V100R001C30 version.

Update of V100R006C00 Compared with V100R005C10SPC200

Feature Update Reason for the Update Information Update
The OSN 9800 M24 The OSN 9800 M24 subrack 2.7.6.1.3 OSN 9800 M
subrack is added and it is new to the product and Series Hardware and
supports physical clocks. should support the basic Version Support:
equipment functions. Added the descriptions of
the OSN 9800 M24 subrack.
Update of V100R001C30SPC100 Compared with V100R001C30

The OSN 9800 U16 The OSN 9800 U16 subrack 2.7.6.1.2 OSN 9800 U
subrack is added and it is new to the product and Series Hardware and
supports physical clocks. should support the basic Version Support:
equipment functions. The OSN 9800 U16 subrack
is added and it supports
physical clocks.
The U2000 graphical user The U2000 GUI is 2.7.5 Configuring Physical
interface (GUI) for physical optimized. Clocks (OSN 9800 U
clocks of OSN 9800 Series: U1CTU/S1CTU):
U64/U32/U16 subracks is The entire section is added.
modified.
Update of V100R001C20
The feature is available Physical clock The entire chapter is added.

since this version. synchronization is a method
of recovering clock
frequencies from physical
signals. Physical clock
synchronization is used to
implement frequency
synchronization among
upstream and downstream
devices so that services are
transmitted correctly.
2.7.6.3.2 OSN 8800&6800 Feature Updates

The physical clock (OTN) is available since the OSN 8800 of V100R002C00 version and the
OSN 6800 of V100R005C00 version. The physical clock (SDH & Packet) is available since
the OSN 8800 of V100R007C00 version.

Updates of V100R009C10SPC300 Compared with V100R009C10SPC200

The TN54TOA and The timeout duration for l 2.7.4.3 Configuring

TN54THA boards are SSM packets is now flexibly Clock Attributes of
added to support the setting configured (it is fixed at 5s Boards to Implement
of SSM Timeout Period in the past). In this way, the Synchronous Frequency
(500ms). receive rate of SSM packets Synchronization: The
is increased, improving the procedure for setting
SSM quality. SSM Timeout Period
(500ms) is added.
l 2.7.4.12.2 Parameters:
Clock Attribute
Configuration: SSM
Timeout Period (500ms)
is added.
Updates of V100R008C10 Compared with V100R008C00SPC200

Feature Update Reason for the Change Information Update
The OSN 8800 universal The clock functions are 2.7.3 Dependencies and
platform subrack newly enhanced. Limitations:
supports physical clocks. Descriptions of the OSN
8800 universal platform
subrack are added.
The TN12STG board is The product function is 2.7.6.1.4 OSN 8800

added, and it supports clock enhanced. Hardware and Version
source acquisition. Support:
Descriptions of the
TN12STG board are added.
Updates of V100R007C02 Compared with V100R007C00SPC310

The 10GE LAN port U2000 GUI element None.

mapping mode of the modification.
TN55TQX, TN53TDX,
TOX boards are changed
from MAC transparent
mapping (10.7G) support
1588 to MAC transparent
mapping (10.7G).

Updates of V100R007C00 Compared with V100R006C03

The physical clock (SDH & The product function is Descriptions of physical
Packet) is available. enhanced. clock (SDH & Packet) are
added.
The EX2 and EG16 boards To enhance the clock 2.7.6.1.4 OSN 8800
are added and they support functions of packet service Hardware and Version
physical clocks. boards. Support:
A description is added to
explain that packet service
boards support physical
clocks.
The TOA board supports This feature update is to None.

physical clock extend the range of clocks at
synchronization when the physical layer.
OTU1 signals are
provisioned on the client
side.
The service type for the U2000 GUI element None.

TOG, TOA and THA board modification.
are changed from GE(TTT-
AGMP) to GE(TTT-GMP).
Clock Source Hold-Off The Clock Source Hold-Off l 2.7.4.5 Configuring

Time newly added for the Time parameter is added for Clock Attributes: The
clock feature. the clock feature. This Clock Source Hold-Off
parameter specifies the time Time configuration
period from the point when a process is described.
clock source switching l 2.7.4.12.12 Parameters:
condition is generated to the Clock Source Reversion
point when a clock source Parameter: A
switchover occurs. description of Clock
Source Hold-Off Time is
added.

SSM Input Quality The SSM Input Quality l 2.7.4.5 Configuring

Threshold newly added for Threshold parameter Clock Attributes: The
the clock feature. specifies the quality SSM Input Quality
thresholds of external clocks Threshold configuration
to facilitate clock source process is described.
selection. When selecting a l 2.7.4.12.8 Parameters:
clock source, the SSM Clock Source Quality: A
algorithm compares the description of SSM Input
quality of a clock source Quality Threshold is
with the SSM input quality added.
threshold specified for the
clock source.
l If the quality of the clock
source is worse than the
specified SSM Input
Quality Threshold, an
SSM_QL_FAILED
alarm is reported and the
clock source is identified
as invalid.
l If the quality of the clock
is better than or the same
as the specified SSM
Input Quality
Threshold, the clock
quality is transparently
transmitted for the clock
to participate in clock
source selection.

SSM Output Quality The SSM Output Quality l 2.7.4.7 Viewing Clock
Threshold newly added for Threshold parameter Synchronization Status:
the clock feature. specifies the quality The SSM Output
threshold of a clock that an Quality Threshold
NE outputs. configuration process is
l When the SSM output described.
quality of the NE is l 2.7.4.12.14 Parameters:
better than or the same as Clock Synchronization
the specified SSM Status: A description of
Output Quality SSM Output Quality
Threshold, the specified Threshold is added.
threshold is considered as
the SSM output quality
and transmitted
downstream.
l If the SSM output quality
of the NE is poorer than
the specified SSM
Output Quality
Threshold, the actual
SSM output quality is
transmitted downstream.

N/A Information optimization 2.7.4.11 Configuring the

ST2/AST2 Board to
Transparent Transmission
of Clock Information:
An example is provided
showing how to configure
the ST2 board to
transparently transmit clock
signals.


N/A Information optimization 2.7.6.1.4 OSN 8800

Hardware and Version
Support:
Information is added to show
whether a tributary board
processes synchronous
Ethernet packets under a
specific client service
configuration.
2.7.6.3.3 OSN 1832 Feature Updates

The following table lists the initial versions of physical clock (OTN & SDH & packet)
features.
Table 2-36 Start versions supporting this feature

Feature Start Version Supporting This Feature
Physical clocks (OTN) l 1832 X16 V100R003C05

l 1832 X8 Enhanced V100R007C10
Physical clocks (SDH) l 1832 X16 V100R003C05

Physical clocks (Packet) l 1832 X16 V100R003C05

Updates in V100R008C10 Compared with V100R008C00

The 1832 X4 Enhanced The 1832 X4 Enhanced is The 2.7.6.1.8 OSN 1832 X4
chassis is added to support new to the product and Enhanced Hardware and
physical clocks (SDH & should support the basic Version Support is added.
Packet). equipment functions.

Updates in V100R007C10 Compared with V100R007C00

The 1832 X8 Enhanced The 1832 X8 Enhanced is The 2.7.6.1.7 OSN 1832 X8
chassis is added to support new to the product and Enhanced Hardware and
physical clocks (OTN & should support the basic Version Support is added.
SDH & Packet). equipment functions.
2.7.7 Standard and Protocol Compliance

This topic describes the standards and protocols specific to clocks.
The standards specific to clock synchronization are listed below:
l ITU-T G.810: Definitions and terminology for synchronization networks
l ITU-T G.811: Timing characteristics of primary reference clocks
l ITU-T G.812: Timing requirements of slave clocks suitable for use as node clocks in
synchronization networks
l ITU-T G.813: Timing characteristics of SDH equipment slave clocks (SEC)
l ITU-T G.823: The control of jitter and wander within digital networks which are based
on the 2048 kbit/s hierarchy
l ITU-T G.825: The control of jitter and wander within digital networks which are based
on the synchronous digital hierarchy (SDH)
l ITU-T G.8261/Y.1361: Timing and Synchronization aspects in Packet Networks
l ITU-T G.781: Synchronization layer functions
2.8 IEEE 1588v2 (OTN & Packet)
2.8.1 Introduction of IEEE 1588v2 (OTN & Packet)

WDM/OTN devices support IEEE 1588v2 to implement frequency and phase
synchronization.
Description
Traditional GPS signals can satisfy time synchronization requirements but feature high
installation and maintenance costs. In addition, GPS signals depend on satellites, which may
bring security risks. As a remedy, the IEEE organization defines the IEEE 1588v2 standard,
which enables precise clock synchronization between distributed and standalone devices in
measurement and control systems through the precision time protocol (PTP). The phase
synchronization precision reaches nanosecond level.
Application Scenario
Different from physical clocks that recover clock information from service bit streams, IEEE
1588v2 implements frequency and phase synchronization through PTP packet exchanges, as

shown in the following figure. The synchronization is implemented hop by hop, which
requires that all devices in the synchronization network must support the IEEE 1588v2
function.
Figure 2-17 IEEE 1588v2 application scenario
2.8.2 Principles
A IEEE 1588v2 clock transfers the reference time to each control point accurately by building
the master-slave relationship between the nodes on a network, and by using the time
synchronization mechanism.
2.8.2.1 Building the Master-Slave Clock Hierarchy

An IEEE 1588v2 clock system uses the master-slave hierarchy. The grandmaster clock
(GMC) that is the clock at the highest level transmits clock information to the terminal
equipment through an ordinary clock (OC), a boundary clock (BC), and a transparent clock
(TC).
The best clock in the entire system is the GMC due to its stability, accuracy, and certainty.
According to the precision and level of clocks on each node and the traceability of UTC, the
BMC algorithm selects the master clock in each subnet automatically (see 2.8.2.5 BMC
Algorithm). In the system where there is only one subnet, GMC is the master clock. Each
system has only one GMC, and each subnet has only one master clock. Slave clocks are kept
synchronized with the master clock.
Figure 2-18 shows the process of building the master-slave hierarchy between the OC and BC
in a PTP clock subnet.

Figure 2-18 Master-slave clock hierarchy
In Figure 2-18, Ordinary clock-1 is at the bottom of the hierarchy and is referred to as
grandmaster. Port-1 of Boundary clock-1 is a SLAVE (S for short) compared with the
grandmaster. The other ports of Boundary clock-1 are all MASTER (M for short) compared
with the clock equipment that is connected to the ports. Hence, port-1 of Boundary clock-2 is
a SLAVE compared with Boundary clock-1.
The master-slave hierarchy of a PTP clock system is built depending on the Announce
packets received by the port from other clock ports, port data sets, BMC algorithms, and port
state machines. The process of building the master-slave hierarchy is as follows:
1. Receive and authenticate the Announce packets from other clock ports.
2. Use the BMC algorithm to determine the recommended state of a port.
3. Update the port data set based on the decision point specified by the port status decision
algorithm for entering the recommended state.
4. The port state machine determines the actual state of the port based on the recommended
state and status decision event, and builds the master-slave hierarchy.
NOTE
The Master-slave clock hierarchy exists only between the OC and BC, and only the BC can have the
branch nodes in the master-slave hierarchy. For example, trails 1, 2, 3, 4, and 5 may contain TCs, but the
TC equipment is not involved in the master-slave hierarchy and does not maintain the relationship.
2.8.2.2 IEEE 1588v2 Clock Architecture

The clock architecture specified in the IEEE 1588v2 standard classifies NE clocks into three
models: ordinary clock (OC), boundary clock (BC), and transparent clock (TC).
Clock Port Status

Every port of the OC and BC maintains an independent PTP state machine that defines the
status allowed by ports and the port status conversion rules. A port may be in one of the
following states:
l MASTER: The port provides a timing source for the downstream equipment on the trail.
l SLAVE: The port is kept synchronized with the port in MASTER state on the upstream
equipment on the trail.
l PASSIVE: Indicates that the port on the path is not in the MASTER status and does not
maintain synchronization with the port in the MASTER status. That is, the upstream port
and downstream port are isolated.

l FAULTY: The state of a port changes from master, slave, or passive to faulty when a
LOS, AIS, or LinkDown and other alarm is reported for the port.
Clock Models
The following concepts are essential for the IEEE 1588v2 clock models:
l PTP device: A clock device that supports the IEEE 1588v2 protocol is defined as a PTP
device.
l PTP port: A port that supports the IEEE 1588v2 protocol on a PTP device is defined as a
PTP port.
Figure 2-19 Clock Models
TCs are classified into P2P TCs and E2E TCs according to different mechanisms of
processing delay.
l P2P TC: When PTP packets enter a P2P TC, the P2P TC rectifies the PTP packet
residence time and measures the transmission delay of the link connecting to the PTP
port. The P2P TC is mainly applied in a mesh network.
l E2E TC: Uses the end-to-end delay measurement mechanism between the master and
slave clocks. The intermediate node is not involved in processing the transmission delay,
but only transparently processes PTP packets. The E2E TC is mainly applied in a chain
network.
2.8.2.3 Clock Subnet and Clock ID in IEEE 1588v2

A clock synchronous network can be divided into independent clock subnets. In each clock
subnet, a clock participating in IEEE 1588v2 clock source selection needs to be assigned a
unique identifier, which is called a clock source ID.
Clock Subnet
An IEEE 1588v2 clock subnet is a logical set in which clocks are synchronized with each
other using the IEEE 1588v2 protocol. A physical packet switched network can be divided
into multiple logical clock subnets. The clocks within a subnet are synchronized with each
other. Each clock subnet uses its own synchronization source.

l An ordinary clock (OC) or boundary clock (BC) can be configured in a clock subnet. It
processes the IEEE 1588v2 packets of this clock subnet and discards the IEEE 1588v2
packets from other clock subnets.
l A transparent clock (TC) does not need to be configured in a clock subnet. It
transparently transmits IEEE 1588v2 packets or correct transmission delays in the IEEE
1588v2 packets.
In an IEEE 1588v2 packet, a clock subnet ID occupies one byte.
Clock Source ID
A clock source ID identifies a clock in an IEEE 1588v2 clock subnet. In an IEEE 1588v2
packet, a clock source ID occupies eight bytes. It consists of two parts:
l Organizational Unique Identifier (OUI): an organization identifier uniformly assigned by
the IEEE standard.
l Extended ID: an identifier uniformly assigned by the organization represented by the
OUI to ensure that the clock ID in each IEEE 1588v2 packet is unique.
2.8.2.4 Time Source Interface

Time source information can be received through external time ports and service time ports.
Input and Output Ports

Time Port Supported Port Mode Function
Type Format
External time 1PPS+TOD RJ45 l Receives time signals

port from the BITS or other
devices that have the
same port.
l Cascades with other
devices of the same type
at the same site.
l Connects to the lower-
layer PTN/SDH network.
Service time Ethernet Inband port that runs Connects to the lower-layer
port services with services. PTN/SDH network without
including GE, equipment room or site
10GE, 40GE sharing restrictions.
and so on
A synchronous network using the IEEE 1588v2 protocol obtains time signals from the
reference time source grandmaster time using external time ports.
1PPS+TOD time signals
1PPS+TOD time signals consist of 1PPS signals and TOD time information.

l 1PPS
1PPS is short for one pulse per second. 1PPS signals are used for time scaling and work
at the RS-422 levels. The pulse frequency of 1PPS is 1 Hz. That is, one pulse is
transmitted per second. The 1PPS signal pulse width ranges from 20 ms to 200 ms. On
the rising edge of the pulse, UTC time signals are aligned.
l TOD
TOD is short for time of day. TOD messages provide time in ASCII format. TOD signals
also work at the RS-422 levels and provide a baud rate of 9600 bit/s. A TOD message
contains information such as current date/time, time standard ID, 1PPS status flag, date/
time adjusted based on UTC leap seconds, leap second adjustment directive, and GPS
time.
The STG clock board supports mutual conversion between 1PPS+TOD quality information
and IEEE 1588v2 time quality levels.
l If the manually specified Time Quality Level is not the default value 187, the manually
specified IEEE 1588v2 time quality level applies.
l If the manually specified Time Quality Level is the default value 187, the STG clock
board automatically converts the quality information carried in the TOD into the IEEE
1588v2 time quality level based on the predefined conversion table.
Table 2-38 provides the mapping between the TOD status information and IEEE 1588v2 time
quality level.
Table 2-38 Mapping between the TOD status information and IEEE 1588v2 time quality level
TOD Status Information IEEE 1588v2 Time Quality
Level
0x00: normal 6
0x01: holdover on the time synchronous device (atomic 7

clock)
0x02: unavailable 255
0x03: holdover on the time synchronous device (high 52

stability crystal oscillator)
0x04: holdover on the transmission device 187
0x05: holdover on the local rubidium clock 8
Other (remain) 255

External Time Ports
Table 2-39 Time ports

Product Type Board Type Time Port
OSN 9800 universal platform subrack STG TOD

OSN 8800 universal platform subrack
OSN 6800
OSN 1832 X16 AUX TOD0 and TOD1
OSN 1832 X8 Enhanced AUX TOD0 and TOD1
OSN 1832 X4 Enhanced TMA1UXCL CLK/TOD/MON
OSN 9800 U series/M series EFI TOD1 and TOD2
OSN 8800 T32/T64 STI TOD1 and TOD2
OSN 8800 T16 ATE TOD1 and TOD2
NOTE
For the port description and pin definitions of each board, see the description of Front Panel of each
board.
External Time Connection Mode

l External time mode: It is used to interconnect with the BITS or other devices. The output
time can be synchronized with the system time of an NE or the line source specified by
the NMS.
l Cascading time mode: It is used only for the interconnection between multiple subracks
of the WDM/OTN product and is always synchronized with the system time.

External time All subracks Applicable to scenarios Figure 2-20

mode work in the where time signals
external time need to be input or
input or output output through external
mode. time ports. Currently,
OSN 8800 and OSN
9800 can use this
mode.



time mode 1 work in the applicable only to
to form ring subracks are configured
protection. on the same NE.

time mode 2 work in the applicable only to
with protection subracks are configured
paths. on the same NE.
Figure 2-20 Connection diagram of external time mode
Figure 2-21 Connection diagram of cascading time mode 1

Figure 2-22 Connection diagram of cascading time mode 2
2.8.2.5 BMC Algorithm

The best master clock (BMC) algorithm can determine the GMC in any network structure and
build the master-slave hierarchy. In addition, the BMC algorithm transfers the master clock
and reference time to each node level by level for the best possible clock precision.
Overview
The BMC algorithm compares the description data of two clocks to determine which data
better describes the clock. In other words, the algorithm is used to determine which of the
multiple Announce messages received by the local clock port describes the best clock. The
algorithm is also used to determine whether a new clock source (that is, the external
MASTER) has better quality than the local clock. The data that describes the external
MASTER information is contained in the Grandmaster field of an Announce message. The
data that describes the local clock is contained in the data set of the clock.
The BMC algorithm runs on each clock in a domain independently. That is, each clock does
not need to negotiate with the other clocks, but calculates the status of its own ports. The
algorithm prevents situations where multiple master clocks exist in the PTP clock system at
the same time, there is no master clock, or the PTP clock system is in the free-run mode.
Overview of BMC Algorithm

The BMC algorithm consists of two parts, which are:
l Data group comparison algorithm
The algorithm compares the advantages and disadvantages of the two groups of data of
two clock ports. One group of data represents the default features of the local clock, and
the other group of data represents the information contained in the synchronous packets
received from the external port.
l Status decision algorithm
The algorithm calculates the recommended status of each port based on the comparison
result of data groups. The states include primary site, secondary site, standby, listen only,
and inhibited.
The BMC algorithm is dynamic. That is, when the BMC algorithm runs in a clock
synchronization system, the BMC algorithm continuously calculates the port status based on
the real-time data and then adjusts the status of each node and port dynamically while also
adjusting the route of transmitting the time signals. Hence, when the active master clock is

faulty or its performance deteriorates, the system may select another suitable node to serve as
the master clock.
The BMC algorithm runs on each port of each clock locally. The BMC algorithm specifies the
order in which data is compared and the comparison rules, namely, clock level, clock
identifier, clock variable, trail length, and so on. The current status of each port of each clock
can be obtained after the data is compared.
NOTE
Static BMC can be set to either Enabled or Disabled to enable or disable the IEEE 1588v2 protocol.
When it is set to Enabled, users can manually configure the port status as master or slave.
Figure 2-23 shows a typical application of the BMC algorithm for clock C0 that has N ports.
Figure 2-23 BMC clock algorithm model
1. For each port, the BMC module compares the data groups of the qualified announce
packets received by other clock ports that are connected to the port on the
communication trail, and the data group comparison algorithm determines the best
packets Erbest for the port.
2. In the case of N ports of clock C0, the BMC module compares Erbest of each port and
determines the best packets Ebest of N ports.
3. In the case of each port of N ports of clock C0, the BMC module uses the status decision
algorithm and the state machine of the port to determine the port status based on Ebest,
Erbest, and the default data group D0.
2.8.2.6 Delay Correction

When the product connects to a clock device through its external time port, transmission delay
of the cable connecting to the external time port and PTP link asymmetry can be corrected.
Correction for the Transmission Delay of the Cable Connecting to the External
Time Port
Time information is required for transmitting electrical signals. Therefore, 1PPS+TOD time
signals needs to be sent to a slave clock device through a cable. There is a difference between

the time when the slave clock device receives the timescale pulse and the time that the pulse
actually represents. Accurate time synchronization can be achieved by correcting the delay
introduced by the cable connecting to the external time port.
NOTE
The external time port on the product is not a PTP port and does not support the IEEE 1588v2 protocol.
The transmission delay cannot be measured automatically. Therefore, the transmission delay of the cable
connecting to the external time port must be measured using a test instrument or computed based on the
cable length.
Correction for PTP Link Asymmetry

The PTP link asymmetry means that the cables for receiving and transmitting PTP messages
between two devices have different lengths. This causes a variation between the cable
transmission delays in the receive and transmit directions.
The IEEE 1588v2 packet delay measurement algorithm is based on the assumption that the
PTP link transmission delays in the receive and transmit directions are the same. If the receive
and transmit cables on the PTP link are asymmetric, the computed delay will differ from the
actual transmission delay.
The PTP asymmetry correction mechanism uses the asymmetric delay variation compensation
value to correct the computed value, thereby achieving accurate time synchronization. The
compensation value can be obtained by measuring the difference between the lengths of the
receive and transmit cables on the PTP link. Also, users can measure the times spent on
transmitting and receiving the PTP messages measured by using a test instrument and then
calculate the difference between the two times. The compensation value takes effect only after
it is manually set for the PTP ports.
NOTE
The IEEE 1588v2 protocol can detect the mean transmission delay of two connected PTP ports but
cannot detect the transmission delay caused by the PTP link asymmetry. Asymmetric delay must be
measured with a test instrument or computed based on the cable lengths.
2.8.2.7 IEEE 1588v2-Compliant Phase Synchronization

The IEEE 1588v2 clock system ensures that slave clocks remain synchronized with the master
clock through PTP packets according to the PTP synchronization mechanism.
IEEE 1588v2 Packet

The packets in PTP telecommunication defined in the IEEE 1588v2 protocol include the
following types:
l Announce packets are used to build the master-slave synchronization hierarchy.
l Sync packets are used by the master clock to initiate a synchronization request.
l Follow_Up packets are used by two-step clocks to carry timestamps.
l Delay request packets are used by a slave clock to initiate a delay measurement request.
Delay_Req is used in the E2E mode, while Pdelay_Req is used in the P2P mode.
l Delay response packets that are used to respond to the delay measurement request from a
slave clock. Delay_Resp is used in the E2E mode, while Pdelay_Resp is used in the P2P
mode.
l Management packets are used to query and update the PTP data set that a clock
maintains, and are also used to customize a PTP system, initialization, and fault

management. The management packets are used between the administration node and the
clock equipment.
IEEE 1588v2 Clock Phase Synchronization Mechanism

The IEEE 1588v2 protocol is based on the most accurate match time at which synchronous
data packets are propagated and received. Each slave clock is synchronized with the master
clock by exchanging the synchronous packets with the master clock. The synchronization
process consists of two phases, which are the deviation measurement phase and delay
measurement phase.
The PTP clock synchronization process is shown in Figure 2-24.
Figure 2-24 IEEE 1588v2 clock phase synchronization process
1. At the time of t1, the master clock sends a Sync message. If the master clock is a one-
step clock, the t1 timestamp is contained in the Sync message and sent to the slave clock.
If the master clock is a two-step clock, then the t1 timestamp is contained in the
subsequent Follow_Up message and sent to the slave clock.
2. At the time of t2, the slave clock receives the Sync message and obtains the t1 timestamp
from the Sync message or from the subsequent Follow_Up message.
3. At the time of t3, the slave clocks send delay request messages.
4. At the time of t4, the master clocks receive delay request messages.
5. At the time of t5, the master clock sends delay response messages that carry the
information of the time of t4.
The method of calculating the time difference between the master and slave clocks and the
link delay is as follows:
Because
t2 - t1 = Delay - Offset
t4 - t3 = Delay + Offset
Hence,

Offset= [(t4 - t3) - (t2 - t1)]/2
Delay= [(t4 - t3) + (t2 - t1)]/2
NOTE
l Offset: The time difference between the master and slave clocks.
l Delay: The delay time caused by network transmission.
2.8.2.8 IEEE 1588v2-Compliant Frequency Synchronization

Frequency synchronization is implemented based on the received and transmitted timestamps
in Sync messages defined by the IEEE 1588v2 protocol.
NOTE
l IEEE 1588v2-compliant frequency synchronization involves two actions: frequency gauging and
frequency correction. The synchronization precision of this method is close to that of frequency
synchronization based on physical clocks.
l Synchronous Ethernet is preferred for the Ethernet ports that support both synchronous Ethernet and
IEEE 1588v2-compliant frequency synchronization.
Figure 2-25 shows the time of receiving and transmitting Sync messages between clock A
(slave) and clock B (master) when clock A synchronizes to clock B. Clock A can correct its
clock frequency after comparing the interval between two message transmitting timestamps
with the interval between two message receiving timestamps. In this manner, clock A
synchronizes to clock B. If the changes in the link delay and residence time are negligible, the
clock frequency of clock A can be corrected using the following formula:
(t1[N] - t1[0])/(t2[N] - t2[0])
l If the value of the "t2[N] - t2[0]" is equal to the value of "t1[N] - t1[0]": This means that
clock A and clock B run at the same rate.
l If the value of the "t2[N] - t2[0]" is greater than the value of "t1[N] - t1[0]": This means
that clock A runs faster than clock B and needs to slow down its frequency.
l If the value of the "t2[N] - t2[0]" is less than the value of "t1[N] - t1[0]": This means that
clock A runs slower than clock B and needs to accelerate its frequency.
NOTE
l t2[N] - t2[0]: Indicates the number of clock cycles within the interval between two Sync messages
received by clock A.
l t1[N] - t1[0]: Indicates the number of clock cycles within the interval between two Sync messages
transmitted by clock B.
l In one-step mode, t1[n] is contained in the Sync message. In two-step mode, t1[n] is contained in the
Follow_Up message.
In practical application, transmission delays and the residence times on a TC clock must be considered
and corrected.

Figure 2-25 Intervals of transmitting Sync messages
2.8.3 Dependencies and Limitations

This topic describes the limitations on and precautions for IEEE 1588v2 clocks.
2.8.3.1 Limitations on the IEEE 1588v2 Feature
Table 2-41 Limitations on the IEEE 1588v2 Feature

PRCs l Networks at the convergence layer should be configured

with clock protection and be set with the primary and
secondary PRCs for active/standby switching of clock.
l In the case of networks at the access layer, generally, only
one PRC is set on the central NE. Other NEs trace the
clock of the central NE.
Clock Source l The central node or the node with high reliability provides
the clock source.
l If the BITS or other external clock equipment with high
precision exists, use the external timing mode for the NE.
Otherwise, use the line timing mode instead. It is
recommended that you use the internal timing as a clock
source of the lowest level.

Methods for obtaining If a core site on an OTN network consists of multiple NEs,
frequency and phase two methods are available for obtaining frequency and phase
information information:
l If physical OSC or ESC connections are established
between the NEs, the OSC or ESC channels can be used
to transmit IEEE 1588v2 frequency and phase information
between the NEs.
l If the NEs are deployed in the same telecommunication
room and the intervals between the them are less than 200
m, the external 2M clock ports or 1PPS+TOD time ports
on the NEs can be used to transmit the frequency and
phase information between them.
l To transmit IEEE 1588v2 signals between OTN devices,
you are advised to use line boards or OSC boards. To
transmit IEEE 1588v2 signals between an OTN device
and a third-party device, you are advised to use tributary
boards.
TN55TTX/TN56TOX TN55TTX/TN56TOX board does not support IEEE 1588v2

when the mapping path is 10GE LAN -> ODUflex.
TN54EX2/TN54EG16 When TN54EX2 or TN54EG16 boards are used to deploy

IEEE 1588v2 clocks, due to the limited processing
capabilities of the boards, the OC/BC ports may receive
packets from multiple clock sources when physical loops are
present on a network. As a result, IEEE 1588v2 clocks cannot
be synchronized. Therefore, you are not advised to configure
the working mode of an NE on which E-LAN services are
configured to the TC mode (including pure TC, TC+OC, and
TC+BC). When physical loops are present on a network, the
OC/BC mode is recommended networkwide.
TN16AUX In an OSN 8800 T16 subrack, two TN16AUX boards must be

configured if the IEEE 1588v2 function is required.
Tributary Board Before configuring the clock function, ensure that the port
status of the tributary board is normal and no abnormal alarm
is reported.
Clock board l Slots 15 and 16 in the OSN 6800 subrack can house clock
boards and service boards. However, IEEE 1588v2 is not
supported by all service boards and the ST2/AST2 boards
in slots 15 and 16 in an OSN 6800 subrack.
l Slots 3 and 4 in universal platform subrack can house
clock boards and service boards. However, IEEE 1588v2
is not supported by all service boards and the ST2/AST2
boards in slots 3 and 4 in universal platform subrack.

ST2/AST2 l If the ST2/AST2 board uses the clock function, it must be

installed in a subrack housing clock boards.
l Planning the ST2/AST2 boards:
– A maximum of four ST2/AST2 boards can be
configured on either side of a cross-connect board in a
cabinet.
– After a clock board is installed in an OSN 6800
subrack, no sufficient room is available for the network
cables of ST2/AST2 boards on right side of the clock
board because fibers, clock cables, and power cables
occupy the fiber management space on the right of the
cross-connect board. Therefore, do not configure a
ST2/AST2 board on the right side of the clock board.
– Do not insert the ST2/AST2 to the last slot on the right
of universal platform subrack. Otherwise, it is hard to
connect or disconnect a network cable.
l When an OLA is not configured with a clock board, the
ST2/AST2 board at the site can transparently transmit
IEEE 1588v2 clock signals.
l When the ST2/AST2 board is used with the STG board in
universal platform subrack, the board can process physical
clock signals and IEEE 1588v2.
10GE LAN tributary board l For a port on each 10GE LAN tributary board installed on
an OSN 9800 of V100R001C00 or V100R001C01, Port
Mapping can be set to MAC Transparent Mapping
(10.7G). After the OSN 9800 is upgraded to
V100R001C20, configuring the port as a PTP port to
support IEEE 1588v2 interrupts traffic on the port. The
traffic is restored automatically after the configuration is
completed.
ANNOUNCE Packet When the TN52TOG/TN54TOA/TN54THA/ELOM/

Period(s) TNF5TOA board is interconnected with a PTN device to
transmit IEEE 1588v2 clock signals, ANNOUNCE Packet
Period(s) must be set to 64/1028; otherwise, the
interconnected PTN device may fail to properly trace clock
sources after the link is broken.

Packet service board l When the EX2/TN54EG16 board is used to implement

IEEE 1588v2, due to the chip limitations of the boards,
the VLAN ID for the DCN at the local equipment must
differ from that carried in an IEEE 1588v2 packet
transmitted by the peer equipment. If they are the same,
the IEEE 1588v2 packet cannot be transmitted normally,
so IEEE 1588v2 clock synchronization cannot be
achieved.
l When the packet service board is used to implement IEEE
1588v2 and the TC port of device A and OC/BC port of
device B are interconnected to transparently transmit
third-party clocks, Direction at both ends must be set to
UNI-UNI and Encapsulation Type cannot be set to
QinQ.
l For packet service boards EX2 and TN54EG16, a TC
clock service must be created on each TC port. In
addition, the TC clock service must be assigned a TC tag.
Interface Protocol Type l When an NE works in 1PPS+Time mode, a warm reset on

the NE's active clock board will generate alarms
indicating time source switching and loss of time source
on the downstream NE. For the product, perform active/
standby clock board switching and then perform a warm
reset on the standby clock board.
l When an NE works in 1PPS+Time mode, a cold reset on
the NE's active clock board will generate alarms
indicating time source switching and loss of time source
on the downstream NE. For the product, perform active/
standby clock board switching and then perform a cold
reset on the standby clock board.
NOTE
No active/standby clock board switching is required before the soft
reset on the TN13STG, TN54STG, or TNK3STG board.
Frequency Source Mode l After PTP Synchronization is enabled for an NE, the NE
will automatically switch the frequency source mode to
Physical Synchronization when the Enabled Status of
the external clock port on the NE's clock board changes
from Enabled to Disabled or changes from Unused to
Disabled. When this occurs, manually set the frequency
source mode of the NE to PTP Synchronization.
l The PTP Synchronization mode, clock priorities, and
SSM settings can be manually modified but the settings
take effect only when an NE switches back to the Physical
Synchronization.
l When the external time port on an NE is set to 1PPS
+Time input, the NE cannot work in PTP clock
synchronization mode.

Setting the PTP Packet l If the PTP synchronization scheme is used, set the SYNC
Attributes Packet Period(s) to 8/1024 or a larger value.
l If the physical synchronization scheme is used, retain the
SYNC Packet Period(s) 64/1024 for the SYNC Packet.
Static BMC When NE Clock Type is TC or TC+OC for a port, Static

BMC cannot be set to Disabled.
SLAVE_ONLY For OSN 1832, The port of the clock equipment that is Slave
Only cannot be in the MASTER state. That is, this clock
equipment cannot function as the clock source for the
downstream equipment on the trail. Only the port of the clock
equipment that is NON_SLAVE_ONLY can be in the
MASTER state. That is, this clock equipment can function as
the clock source for the downstream equipment on the trail.
Hence, at least one piece of clock equipment that is
NON_SLAVE_ONLY should be included in the PTP system.
NE Clock Type For OSN 1832,

l In the OC work mode, only one clock port can be created.
l Set NE Clock Type to TC for equipment ports. It is
recommended that IEEE 1588v2 packets be configured in
higher-priority QoS queues for forwarding.
l After NE Clock Type is modified, you need to re-create
all PTP clock ports on the NE.
l When NE Clock Type is set to TC+BC and you modify
the value of PTP Mode for a port, you need to re-create
the port.
IEEE 1588v2 l IEEE 1588v2 clock synchronization is available only

when active and standby system control, switching, and
timing boards are upgraded to versions that support IEEE
1588v2 clock synchronization.
l During the resetting (warm or cold) of a system control,
switching, and timing board, OSN equipment does not
provide external time signals (1PPS+TOD). It provides
external time signals only when the system control,
switching, and timing board works normally.
Consequently, the equipment that uses the time signals
provided by the OSN equipment may malfunction during
the resetting of the system control, switching, and timing
board.
l The SDH clock synchronization function will be
unavailable after IEEE 1588v2 clock synchronization is
enabled.

Attributes of the PTP For OSN 1832,

clock port (Packet) l If two interconnected NEs are clock synchronized using
the IEEE 1588v2 protocol, the ports at both ends must be
enabled. In addition, PTP Packet VLAN, PTP Packet
Encapsulation Format, Step Module, and P/E Mode
must be set to the same for the two NEs.
l For NEs that use IEEE 1588v2 for frequency
synchronization, set SYNC Packet Period(s) to 4/1024 or
8/1024.
l f the TC port of equipment A is interconnected with the
OC or BC port of equipment B to transparently transmit
third-party clocks, the interconnected ports cannot be NNI
logical ports and cannot be set to S-TAG encapsulation
mode.
2.8.3.2 Affected Features
Table 2-42 Affected Features

intra-board 1+1 or optical If IEEE 1588v2 is configured together with intra-board 1+1
line protection or optical line protection, IEEE 1588v2 time synchronization
can be implemented only in single-fiber bidirectional mode
(ST2/AST2+SFIU). If IEEE 1588v2 time synchronization is
implemented in two-fiber bidirectional mode (ESC or OSC),
fiber asymmetry will occur after protection switching on the
related boards such as OLP, DCP, and OTU, affecting the
time synchronization precision.
Packet Features l When the IEEE 1588v2 clock feature works with the
LAG/APS/ERPS packet features LAG/APS/ERPS, it is recommended that
the P2P TC mode be used if NE Clock Type is set to TC.
Otherwise, set NE Clock Type to TC+BC.
l When the IEEE 1588v2 clock feature works with the
packet feature LAG, it is recommended that Load
Balancing be set to Non-Sharing for LAG on the
interconnection points of BC/OC equipment if NE Clock
Type is set to TC+BC.
Loopback For a board port that is configured with the IEEE 1588v2
function, if the loopback test is to be configured on the port or
the interconnected port, the clock trace source of the NE
where the port is located must be switched to the protection
clock source, ensuring that the port loopback has no impact
on the clock function.

Fiber Doctor System When the IEEE 1588v2 clock feature works with the feature
Fiber Doctor System, service running and the IEEE 1588v2
clock synchronization may be affected. For details, see the
dependencies and limitations of the feature Fiber Doctor
System.
2.8.3.3 Mutually Exclusive Features
Table 2-43 Mutually exclusive features

Client 1+1 protection Client 1+1 protection and IEEE 1588v2 are mutually
exclusive. If both are configured, IEEE 1588v2 will become
abnormal.
Fiber Doctor System When the AST4 board works with the F5XCH/F5UXCME/
F5UXCM board, the line fiber quality monitoring function
and IEEE 1588v2 are mutually exclusive. If both are
configured, IEEE 1588v2 will become abnormal.
Optical-layer ASON When an SFIU board is used (in scenarios where a DAPXF
board is used as the SFIU board) to configure or reserve the
IEEE 1588v2 function, the optical-layer ASON is not
supported.
SDH ASON If a TNV2U210 or TNU3U401 board is used, SDH ASON

and IEEE 1588v2 are mutually exclusive as follows:
l If the SDH ASON function is enabled on the NMS, IEEE
1588v2 clock source ports cannot be configured.
l If IEEE 1588v2 clock source ports are configured, the
SDH ASON function will not take effect.
Ring MSP If a TNV2U210 or TNU3U401 board is used, the ring MSP

and IEEE 1588v2 are mutually exclusive as follows:
l If ring MSP has been configured on any port of a board,
no IEEE 1588v2 clock port can be created on the board.
l If an IEEE 1588v2 clock port has been created on a board,
ring MSP cannot be configured for the board.
Latency measurement The overhead bytes used during latency measurement are the
(OTN) same as those of IEEE 1588v2 on the OTN interface. If these
overhead bytes transmit IEEE 1588v2 protocol packets, the
IEEE 1588v2 is interrupted so that services are affected.
Therefore, it is not recommended that you measure trail
latency if IEEE 1588v2 is used.

2.8.4 Configuring IEEE 1588v2 Clock (OSN 1832/8800/9800

Universal Platform Subrack/M Series Subrack)

This topic describes how to configure an IEEE 1588v2 clock.
Figure 2-26 shows the process of configuring an IEEE 1588v2 clock.
Figure 2-26 IEEE 1588v2 clock configuration flowchart
Table 2-44 provides the detailed procedures for configuring IEEE 1588v2-compliant
frequency and phase synchronization.
NOTE
The procedures provided in Table 2-44 are only used to configure IEEE 1588v2-compliant frequency
and phase synchronization. To provide physical clock frequency synchronization and IEEE 1588v2-
compliant phase synchronization, configure the physical clock by referring to 2.7.4.1 Configuration
Process and then perform the procedures provided in Table 2-44 to configure IEEE 1588v2 packets.
Table 2-44 Procedures for configuring IEEE 1588v2-compliant frequency and phase
synchronization
Operation Remarks
2.8.4.2 Enabling Mandatory.

IEEE 1588v2 You must enable IEEE 1588v2 before configuring it for a NE.
The number of available licenses is deducted by 1 each time
IEEE 1588v2 is enabled for a subrack.
NOTE
Since OSN 1832 V100R007C00, before IEEE 1588v2 is enabled,
Protection Status of SSM must be set to Start Extended SSM Protocol
or Start Standard SSM Protocol.

Operation Remarks
2.8.4.3 Configuring Mandatory.

PTP NEs l Setting Frequency Source Mode:
– When physical clock frequency synchronization and IEEE
1588v2-compliant phase synchronization are required, set
Frequency Source Mode to Physical Synchronization.
– When IEEE 1588v2-compliant frequency and phase
synchronization is required, set Frequency Source Mode
to PTP Synchronization.
l Set clock synchronization attributes. According to the actual
networking, you need to set the clock synchronization
attributes of each NE on the U2000, including setting the PTP
working mode, system time, and system time calibration
parameters.
l Configure the BMC static source selection. The status of the
master, slave, and passive ports is manually set to achieve
time synchronization. The dynamic BMC automatic source
selection algorithm is not enabled. If a port is abnormal,
automatic switching is not triggered.
l Configuring clock subnets. When a physical OTN needs to be
divided into multiple clock domains, clock subnets must be
configured.
l Set the attributes of the local clock. According to the actual
networking, you must set the local clock parameters received
by the local NE, so that the clock selection module can
calculate the best master clock.
2.8.4.4 Configuring Mandatory.

PTP Ports l Create a clock port and set port packet attributes. The ports
that transmit or receive IEEE 1588v2 packets must be
configured as PTP ports to trace PTP clock sources.
l Set the Cable Transmission Warp parameter of the clock
port. Set the parameters of the cable transmission deviation
according to the actual situation to compensate for the delay
generated by external time cables.
2.8.4.5 Configuring Optional.

External Time Ports When an NE needs to input or output external time signals, you
must enable the port cascading function and set external time
interface attributes and the Cable Transmission Warp
parameter.
2.8.4.6 Viewing Port Mandatory.

Status After all the clock configuration processes are completed, users
need to query all ports for the clock synchronization status to
ensure that the port synchronization status is the same as that
defined in the networking diagram.

Operation Remarks
2.8.4.7 Viewing the Mandatory.

Clock Tracing Status Correct clock tracing relationships are critical to ensure the clock
synchronization within the entire network. Using the U2000, you
can monitor the clock tracing status of each NE.
2.8.4.2 Enabling IEEE 1588v2

You must enable IEEE 1588v2 before configuring it for a NE. The number of available
licenses is deducted by 1 each time IEEE 1588v2 is enabled for a subrack.
Prerequisites
l The license of IEEE 1588v2 resources is available.
Procedure
Step 1 Enable IEEE 1588v2 for a new subrack.
NOTE
ITU-T G.8275.1 and IEEE 1588v2 share the same license resources. ITU-T G.8275.1 is enabled after
IEEE 1588v2 is enabled on the U2000.

NOTE
l OSN 9800:
– In a multi-subrack configuration, master and slave universal platform subracks are cascaded to
achieve frequency/phase synchronization.
– Multiple electrical subracks cannot be cascaded in master/slave mode to achieve frequency/
phase synchronization among the subracks. Therefore, only one electrical subrack of each NE
supports frequency/phase synchronization. You are advised to configure all boards on which
the frequency and phase must be synchronized in the same subrack.
– The universal platform subrack and electrical subrack cannot be cascaded in master/slave
mode to achieve frequency/phase synchronization among the subracks.
l OSN 1832 does not support cascading of master and slave clock subracks.
l OSN 8800/6800 supports cascading of master and slave clock subracks.
Step 2 Enable IEEE 1588v2 for the created subrack.
----End
2.8.4.3 Configuring PTP NEs

To ensure normal operation of the PTP clock for each NE in a network, users need to
configure clock synchronization attributes, static BMC, the frequency source mode, PTP
clock subnet, local clock attributes for the NE.
Prerequisites

l The IEEE 1588v2 has been enabled.
Configuring the Frequency Source Mode

Based on the actual networking situation, configure the frequency source mode of an NE
before configuring a clock.
Step 1 Configure the Frequency Source Mode.
NOTE
Before configuring clocks, specify Frequency Source Mode as required.

l If physical clock frequency synchronization is used, select Physical Synchronization.
l If IEEE 1588v2 frequency synchronization is used, select PTP Synchronization.
----End
Configuring Clock Synchronization Attributes

Based on the actual networking situation, you need to set the clock synchronization attributes
of each NE on the U2000. The attributes include PTP work mode, PTP system time, and time
adjustment.
Step 1 Change PTP System Time.

NOTE
l The PTP System Time can be set only when the NE traces the local clock source.
l The time range for the setting is: 2000-01-01 00:00:00 to 2069-12-31 23:59:59.
Step 2 Configure NE Clock Type, Slave Only, and PTP Time Adjustment. For parameter details,
see 2.8.4.8.3 Parameters: Clock Synchronization Attribute.

NOTE
l The Slave Only parameter is available only when NE Clock Type is set to OC.
l If only frequency synchronization is required, set PTP Time Adjustment to Disabled; if both
frequency and time synchronization are required, set PTP Time Adjustment to Enabled.
l When NE Clock Type of an NE is set to OC, Clock Type of PTP ports on the NE must be set to
OC and only one PTP port on the NE can be enabled.
l When NE Clock Type of an NE is set to BC, Clock Type of PTP ports on the NE must be set to
BC.
l When NE Clock Type of an NE is set to TC, Clock Type of PTP ports on the NE must be set to
TC.
l When NE Clock Type of an NE is set to TC+OC, Clock Type of PTP ports on the NE can be set to
either TC+OC or TC.
l When NE Clock Type of an NE is set to TC+BC, Clock Type of PTP ports on the NE can be set to
either TC or BC.
l When NE Clock Type of an NE is set to TC+BC, and Static BMC is set to Enabled, do not change
the Clock Type of PTP ports on the NE to TC.
l Equipment that is in the BC or OC work mode can belong to only one clock subnet, and its clock
source can be selected only from within the same clock subnet.
NOTICE
This is a risky operation. If PTP Time Adjustment is set to Disabled, the time
synchronization function will be unavailable. If only PTP frequency synchronization is
required and phase synchronization is not, PTP Time Adjustment can be set to Disabled. By
default, it is set to Enabled and the default setting does not need to be changed in most cases.
----End
Configuring Static BMC

Unlike the dynamic clock source selection function that uses the dynamic BMC algorithm, the
static clock source selection function uses the static BMC algorithm to achieve time
synchronization after you manually set the port state (master, slave, or passive). Automatic
source switching is not triggered when a port becomes abnormal.
Step 1 Configure Static BMC.

----End
Configuring a PTP Clock Subnet

Network planning personnel need to divide the entire network into different clock subnets in
planning the clock network depending on the scheme for the site. Within each subnet, time
synchronization can be implemented for all clocks.
The calculation of the PTP clock source is based on the clock subnet. Each clock subnet
calculates its own current clock source separately. For an NE, only one time domain is
supported at a time. Each BC or OC equipment can only be configured with one clock subnet.
The clock source should be selected from within the same clock subnet. The packets sent
from different clock subnets are discarded by the NE.
Step 1 Configure PTP Clock Subnet. For parameter details, see 2.8.4.8.5 Parameters: PTP Clock
Subnet.
NOTE
l The NEs that have the same subnet number belong to the same clock subnet.
----End

Configuring the Local Clock Attributes

Depending on the networking scheme for the site, you need to set the clock attributes of the
local clock sources received at the NE, so that the best master clock can be calculated by the
clock selection module.
Step 1 Configure Time Quality Level, Time Precision, Clock Source Type, and so on. Then
configure the settings for each parameter. For the details about these parameters, see 2.8.4.8.6
Parameters: BMC (Clock Subnet).
----End
2.8.4.4 Configuring PTP Ports

To ensure that precision time protocol (PTP) ports of every NE on a network work correctly,
users need to create logical PTP ports, configure attributes of PTP packets, specify the cable
transmission deviation of PTP clock ports, and configure the MAC address.
Prerequisites
l The corresponding board must be created.
Configuring a Clock Port

l A clock port can be used to trace the PTP clock source. Clock ports are created to enable
a PTP clock port so that PTP packets can be received.
l The clock port is used to synchronize the time between two clock nodes. Depending on
the scheme for the site, several clock ports can be created for a board to connect to other
clock nodes.
Step 1 Configure a clock port.

NOTICE
Services on an optical port of the TN52TOG board will be interrupted transiently when users
create or delete the PTP port on the optical port.
For a port on each 10GE LAN tributary board installed on an OSN 9800 of V100R001C00 or
V100R001C01, Port Mapping can be set to MAC Transparent Mapping (10.7G). After the
OSN 9800 is upgraded to V100R001C20, configuring the port as a PTP port to support IEEE
1588v2 interrupts traffic on the port. The traffic is restored automatically after the
configuration is completed.
NOTE
In the OC work mode, only one clock port can be created.
Step 2 Set the parameters related to the port status.

NOTE
l After static BMC is enabled, the status of all ports enabled with IEEE 1588v2 must be manually
specified. The default port status is LISTENING.
l If you want to change the selected port, select the desired port from the Selected Port area, and then
click to add the port to Available Port.
----End
Configuring the PTP Clock Domain

When tributary or packet service boards exchange PDELAY packets and the following
conditions are met, the PTP clock domain ID can differ from the clock subnet ID.
l Work Mode is set to TC or TC+OC for PTP port.

l P/E Mode is set to P2P for PTP port.
Setting the clock domain ID for PTP ports ensures that the clock domain IDs of the PTP ports
are the same as those of the peer equipment, achieving connections between them. When
Work Mode is set to BC, OC for PTP ports, the clock domain ID of the PTP ports is the
same as the clock subnet ID of NEs.
Step 1 Configure Domain ID. For details about these parameters, see 2.8.4.8.3 Parameters: Clock
Synchronization Attribute.
----End
Configuring the PTP Packet Attributes

To ensure the normal operation of the PTP clock for each NE in the network, you need to set
the corresponding PTP packet attributes based on the work mode of each NE.
Step 1 Select a port, and configure the settings in the following fields: P/E Mode, SYNC Packet
Period(s), DELAY Packet Period(s), PDELAY Packet Period(s), ANNOUNCE Packet
Period(s), and ANNOUNCE Packet Timeout Coefficient. For parameter details, see
2.8.4.8.3 Parameters: Clock Synchronization Attribute.

NOTE
The DELAY Packet Period(s) field is available only when the P/E Mode is set to E2E; the PDELAY
Packet Period(s) field is available only when the P/E Mode is set to P2P.
----End
Configuring the Cable Transmission Deviation for the Clock Port

When the transmission time and length of a cable in the receive and transmit directions are
not consistent, the transmission deviation of a cable needs to be set to rectify the PTP clock
synchronization process.
The transmission deviation of a cable means the time difference of the clock signals in the
cable transmission in the receive and transmit directions between two NEs. Generally, the
actual time difference of cable transmission for the two directions is calculated by GPS in the
deployment. The cable transmission deviation can be represented by time or by length.
Step 1 Select a port and configure settings in the following fields: Warp Direction, Warp Mode,
Warp Length(m), and Warp Time(ns). For parameter details, see 2.8.4.8.3 Parameters:
Clock Synchronization Attribute.

NOTE
l The value Positive of the Warp Direction field specifies that transmission distance through the
receiving direction is longer than the distance through the sending direction, or the transmission time
of the receiving direction is longer than the time of the sending direction; the value Negative
specifies just the opposite.
l The Warp Length(m) field is available only when the Warp Mode is set to Length; the Warp
Time(ns) field is available only when the Warp Mode is set to Time.
l The values of the Warp Length(m) and Warp Time(ns) are set according to the networking
scheme for the site.
----End
Configuring the MAC Address

This function can be used to configure the physical addresses for sending PTP and SSM
packets so that fields can be filled in to the sent packets based on the requirements of the
downstream equipment, improving the configuration flexibility for interconnection with third-
party equipment.
NOTE
Only the following boards support this parameter:
l OSN 8800: TN54TOA and TN54THA.
l OSN 1832 X16: TNF5TOA, TNF6TOA, TNF5TQX, TNF2LDX, TNF2ELOM (STND), TNF6TTA,
TNF1LDCA.
l OSN 1832 X8 Enhanced: TNF2LDX, TNF2ELOM (STND), TNF6TTA, TNF1LDCA.
Step 1 Select a port and configure MAC Address. For parameter details, see 2.8.4.8.10 Parameters:
MAC Address Configuration.
----End

2.8.4.5 Configuring External Time Ports

When there are external clock sources for an NE, users need to configure the clock attributes
of the external clock sources, such as configuring the external port cascading mode for clock
boards, configuring attributes of external time ports, and configuring the cable transmission
distance permitted by an external time port. Based on the configured clock attributes, the
clock selection module can compute which clock is best to use as the best master clock.
Prerequisites
l The STG board has been created.
l For the OSN 6800, when concatenation of the external ports of a clock board is
configured, the 120ohm external clock interface cable should be used as the network
cable for the concatenation.
Configuring External Port Cascading Mode for Clock Boards

The external port of a clock board can be used to connect the external time. In addition, the
external port can be used for cascading the clock boards within a multi-subrack NE.
l Each subrack has two clock ports and two timing ports. These ports are used to
concatenate and transmit the clock or timing signals among multiple subracks, or are
used to input or output external clock and timing signals. By default, the Enabled Status
is unused. If any ports need to be used for the input or output of external clock and
timing signals, the ports should be set to the disabled state. One NE supports a maximum
of two ports for the input or output of external clock and timing signals.
l After PTP Synchronization is enabled for an NE, the NE automatically switches the
frequency source mode to Physical Synchronization when the Enabled Status of the
external clock port on the NE's clock board changes from Enabled to Disabled or
changes from Unused to Disabled. When this occurs, manually set the frequency source
mode of the NE to PTP Synchronization.
Step 1 Configure Enabled Status. For details about the parameters, see 2.7.4.12.3 Parameters:
Clock Port Link.

----End
Configuring External Time Ports

When there are external clock sources for an NE, users need to set the attributes of the
external time ports so that the NE can use the correct external clock.
The Enabled Status of the external time interface must be set to Disabled.
Step 1 Select an external time interface and configure the settings in the following fields: Direction,
Interface Protocol Type, and Interface Level. For parameter details, see 2.8.4.8.7
Parameters: Basic Attribute.
NOTE
For the Interface Level field, the OSN 6800 only supports the value RS422.
Step 2 Configuring Time Quality Level, Time Precision, Clock Source Type, Clock Source
Priority 1, Clock Source Priority 2, and Clock Source Deviation fields. Then configure the
settings for each parameter. For parameter details, see 2.8.4.8.8 Parameters: BMC (External
Time Interface).

The STG clock board supports mutual conversion between 1PPS+TOD quality information
and IEEE 1588v2 time quality levels.
l If the manually specified Time Quality Level is not the default value 187, the manually
specified IEEE 1588v2 time quality level applies.
l If the manually specified Time Quality Level is the default value 187, the STG clock
board automatically converts the quality information carried in the TOD into the IEEE
1588v2 time quality level based on the predefined conversion table.
Table 2-45 provides the mapping between the TOD status information and IEEE 1588v2 time
quality level.
Table 2-45 Mapping between the TOD status information and IEEE 1588v2 time quality level
TOD Status Information IEEE 1588v2 Time Quality
Level
0x00: normal 6
0x01: holdover on the time synchronous device (atomic 7

clock)
0x02: unavailable 255
0x03: holdover on the time synchronous device (high 52

stability crystal oscillator)
0x04: holdover on the transmission device 187
0x05: holdover on the local rubidium clock 8
Other (remain) 255
----End
Configuring Cable Transmission Distance Permitted by an External Time Port

Users need to set the cable transmission distance based on the actual length of an external
time cable to facilitate the recovery and transmission of time signals.

Step 1 Select an external time interface and configure settings in the following fields: Transmitting
Direction, Transmitting Distance Mode, Transmitting Length(m), and Transmitting
Time(ns). For parameter details, see 2.8.4.8.9 Parameters: Cable Transmitting Distance.
NOTE
l The Transmitting Length(m) field is available only when the Transmitting Distance Mode is set
to Length; the Transmitting Time(ns) field is available only when the Transmitting Distance
Mode is set to Time.
l The values of the Transmitting Length(m) and Transmitting Time(ns) are set depending on the
networking scheme for the site.
----End
2.8.4.6 Viewing Port Status

The U2000 supports the function of querying the clock source received at the port. By using
this function, you can query the tracing status of the NE time.
Prerequisites
l The clock port has been created.
Viewing Port Status

Step 1 Query port status. Ensure that slave ports carry the designated clock tracing paths.

----End
Viewing the Clock Source Received at the Port

Step 1 Query the clock source received at the port.
----End

Prerequisites
Context

Procedure
queried, click OK.
----End
2.8.4.8 Parameters: IEEE 1588v2 (OSN 1832/8800/9800 Universal Platform

Subrack/M Series Subrack)
2.8.4.8.1 Parameters: Frequency Source Mode

In this user interface, you can specify the mode of the frequency source that the NE traces
according to the network planning.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > Frequency
Source Mode from Function Tree.
Parameters
Frequency Source Mode Physical Synchronization, Displays the mode of the

PTP Synchronization frequency source that the
NE traces.
NOTE
Before configuring clocks,
specify Frequency Source
Mode as required.
l If physical clock frequency
select Physical
Synchronization.
l If IEEE 1588v2 frequency
select PTP
Synchronization.
2.8.4.8.2 Parameters: Clock Port Link

In this user interface, you can set whether the external ports on clock boards are used for
concatenating the clock signals among the clock boards in the multiple subracks on an NE.

Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > Port Cascading
from Function Tree.
Parameters
Port shelf ID (shelf name)-slot Displays the port name.

number-board name-
external clock interface,
shelf ID (shelf name)-slot
number-board name-
external time interface
Enabled Status Enabled, Disabled, Unused The Enable Status

Default: Unused parameter provides an
option to enable or disable
the external port on the
clock board as a cascading
port.
In the case of the maser-
slave subracks, clock
synchronization and time
synchronization are based
on the cascading ports. If
this parameter is set
improperly, the master and
slave subracks fail to
maintain clock
synchronization or time
synchronization.
l Enabled: Indicates that
the external port is used
as a cascading port.
l Disabled: Indicates that
the external port inputs/
outputs the external
clock/time.
l Unused: Indicates that
the external port is
unused.
NOTE
Currently, only master
subracks of OSN 1832 support
the clock function but slave
subracks do not. Therefore,
Enabled Status can only be
set to Disabled or Unused but
cannot be set to Enabled.

2.8.4.8.3 Parameters: Clock Synchronization Attribute

In this user interface, you can configure and query the NE and port attributes, such as the PTP
system time, working mode, packet transmission period on the port, and transmission
deviation of the cable, in the PTP clock system.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > PTP Clock >
Clock Synchronization Attribute from Function Tree.
Parameters
Table 2-46 Clock Synchronization Attribute

PTP System Time For example: 2009-02-01 Displays the PTP system
01:01:01 time. You can manually
modify this parameter.

NE Clock Type OC, TC, BC, TC+BC, TC The NE Clock Type

+OC parameter provides an
Default: BC option to set the working
mode (OC, TC, BC, TC
+BC, TC+OC) of the node
that adopts the IEEE 1588v2
clock. According to the
network planning, an NE on
the network must work in
the OC, TC, BC, TC+BC,
TC+OC mode. The specific
working mode of the NE
must be determined in the
network planning phase.
During network planning,
first determine the position
and function of the NE and
each port on the NE. Then,
set the working mode of the
NE according to the features
of each working mode.
l OC: As a clock device
with only one PTP port
in the clock domain, OC
maintains the time stamp
used in the clock
domain. The clock
device can function as a
master clock device to
provide a clock source or
as a slave clock device to
keep synchronous with
other clock devices.
l TC: TC forwards certain
PTP event messages and
records the residence
time of the PTP event
messages on it. In
addition, TC provides the
recorded information to
the clock that receives
the PTP event messages.
Then, the recorded
information is used for
transparent transmission
of packets and
adjustment of the
residence time of the

packets on the
equipment.
l BC: As a clock device
with multiple PTP ports
in the clock domain, BC
maintains the time stamp
used in the clock
domain. The clock
device can function as a
master clock device to
provide a reference clock
source or as a slave clock
device to keep
synchronous with other
clock devices.
l TC+BC: TC+BC has the
same features as BC,
except for that the former
only processes delay but
excludes itself from
clock synchronization.
l TC+OC: TC+OC is a
mode for transparently
transmitting time signals.
An NE working in this
mode does not recover
the time, but it recovers
the clock. For an NE to
transparently transmit
time signals, Frequency
Source Mode must be
set to PTP
Synchronization, and
NE Clock Type must be
set to TC+OC.
Static BMC Enabled, Disabled Static BMC can be set to

Default: Disabled either Enabled or Disabled
to enable or disable the
IEEE 1588v2 protocol.
When it is set to Enabled,
users can manually
configure the port status as
master or slave.

Slave Only Yes, No The Slave Only parameter

Default: Yes provides an option to set the
Slave_Only attribute for an
OC port. This attribute
determines whether the OC
port works only as a slave
clock port.
NOTE
This parameter is available
only when NE Clock Type is
set to OC.
l Yes: The port works only
as a slave clock port.
l No: The port works as a
slave clock port or a
master clock port.
PTP Time Adjustment Enabled, Disabled During network planning,

Default: Enabled set this parameter according
to the networking. If the NE
requires only frequency
synchronization, set this
parameter to Disabled. If
the NE requires both
frequency synchronization
and time synchronization,
set this parameter to
Enabled.
Protocol Packet Format NMEA, UBX Configures and queries the

Default: UBX protocol packet format of
external time.
The Protocol Packet
Format parameter is valid
only when Interface
Protocol Type of the
external time interface is set
to 1PPS+Time.

WTR Time(min) 0 to 12 WTR Time parameter

Default: 5 provides an option to set the
response of the Time
set to prevent the Time
In this manner, the Time
Time source only when the
synchronous Time signals
time.
Local Clock Source No. For example: Displays the clock number
Company Code: 00259E of the local clock source of
the NE.
Supplying Code: 30
NE ID: 007E028B
Current Master Clock No. For example: The Current Master Clock
Company Code: 00259E No. parameter indicates the
number of the clock source
Supplying Code: 30 traced by the NE, which is
NE ID: 007E028B the number of the master
clock traced by the NE after
the NE selects the clock
source.
Ingress of Current Master shelf ID (shelf name)-slot Displays the local clock
Clock number-board name-port input interface of the master
number (port name) clock that the NE traces
after you specify the clock
source for the NE.
Table 2-47 Port Status

Port shelf ID (shelf name)-slot Displays the name of the

number-board name-port ports where the PTP clocks
number (port name) are synchronized.

Clock Type OC, BC, TC, TC+OC The Clock Type parameter
Default: BC provides an option to set the
working mode (OC, BC,
Each board supports the TC, or TC+OC) of the node
clock type, refer to the that adopts the IEEE 1588v2
availability of IEEE 1588v2. clock. According to the
network planning, an NE on
the network must work in
the OC, BC, TC, or TC+OC
mode. The specific working
mode of the NE must be
determined in the network
planning phase.
l OC: When ports on an
NE are set to OC mode,
the NE can work only in
master or slave status. A
port in OC mode can be
used only for time input
or output.
l BC: When ports on an
NE are set to BC mode,
the master or slave status
of the NE is determined
by using the BMC
algorithm.
l TC: If ports on an NE are
set to TC mode, the NE
only transparently
transmits time messages
and does not restore
clock or time
information. In addition,
the NE does not have the
master or slave status.
l TC+OC: When ports on
an NE are set to TC+OC
mode the NE restores
clock information but
does not restore time
information, achieving
TC performance
transmission.
l When NE Clock Type of
an NE is set to OC,
Clock Type of PTP ports
on the NE must be set to
OC and only one PTP

port on the NE can be

enabled.
an NE is set to BC,
BC.
an NE is set to TC,
TC.
an NE is set to TC+OC,
on the NE can be set to
either TC+OC or TC.
an NE is set to TC+BC,
on the NE can be set to
either TC or BC.
an NE is set to TC+BC,
and Static BMC is set to
Enabled, do not change
the Clock Type of PTP
ports on the NE to TC.
Step Mode One step, Two step Specifies whether an IEEE

Default: One step 1588 port works in the one-
step or two-step mode.
l In the one-step mode, the
actual Tx time stamp is
sent through the Sync
packet to be transmitted.
The one-step mode
requires the equipment
of high precision and
accuracy.
l In the two-step mode, the
actual Tx time stamp is
not added to the Sync
packet to be transmitted.
Instead, the time stamp is
sent through the
subsequent Follow-Up
message.

PTP Packet VLAN 1 to 4094, or 0xFFFF The PTP Packet VLAN

Default: 0xFFFF parameter provides an
option to set the VLAN IDs
with the PTP packets at a
port. In the scenario of
interconnection with other
client-side equipment, the
transmitted PTP packets
must contain VLAN IDs.
l 1 to 4094: Indicates that
the specified VLAN ID
is equal to the VLAN ID
of the packets.
l 0xFFFF: Indicates that
the VLAN ID is invalid.
PTP Packet Encapsulation PTP ETH, PTP IP Sets the encapsulation

Format Default: PTP ETH format of the PTP packet.
Based on the actual
networking, when local
client-side equipment is
interconnected with other
client-side equipment, you
need to set the encapsulation
format of the PTP packet of
the local equipment
accordingly because the
other client-side equipment
may use L2 or L3
forwarding mode.

Current Port Status MASTER, SLAVE, The Current Port Status

PASSIVE, LISTENING, parameter indicates the
FAULTY status of the clock source
port on the service board.
The BMC algorithm
computes the port status
based on the quality and
priority of the clock source.
l MASTER: Indicates that
the port can provide a
clock source for the
downstream equipment
on the path.
l SLAVE: Indicates that
the port maintains
upstream equipment with
the port in the MASTER
status on the path.
l PASSIVE: Indicates that
the port on the path is not
in the MASTER status
and does not maintain
port in the MASTER
status. That is, the
upstream port and
downstream port are
isolated.
l LISTENING: Indicates
that the port is expecting
the Announce packets
from the MASTER port.
This status ensures that
the clocks are added to
the domain in an order.
l FAULTY: The state of a
port changes from
MASTER/SLAVE/
PASSIVE to faulty when
a LOS, AIS, or
LinkDown alarm is
reported for the port.
Reference Clock Source NE clock ID-port ID This parameter is used to set

No. the number of the clock that
is set as the clock source for
the port to trace.

Domain ID 0-255 Indicates the domain ID.

Default: 0
Table 2-48 Port Message



P/E Mode Cancel, P2P, E2E The P/E Mode parameter

Default: E2E provides an option to set and
query the P/E mode of a
PTP port.
l P2P: Indicates the P2P
port mode.
l E2E: Indicates the E2E
port mode.
l Cancel: Indicates no port
mode.
TCs are classified into P2P
TCs and E2E TCs according
to different mechanisms of
processing delay.
l P2P TC: When PTP
packets enter a P2P TC,
the P2P TC rectifies the
PTP packet residence
time and measures the
transmission delay of the
link connecting to the
PTP port. The P2P TC is
mainly applied in a mesh
network.
l E2E TC: Uses the end-
to-end delay
measurement mechanism
between the master and
slave clocks. The
intermediate node is not
involved in processing
the transmission delay,
but only transparently
processes PTP packets.
The E2E TC is mainly
applied in a chain
network.
SYNC Packet Period(s) 4/1024, 8/1024, 16/1024, The SYNC Packet

32/1024, 64/1024, Period(s) parameter
128/1024, 256/1024, provides an option to set the
512/1024, 1, 2 period at which the PTP port
Default: 8/1024 transmits the Sync packets.
The delay-to-respond
mechanism uses the Sync,
Delay_Req, Follow_Up, and
Delay_Resp packets to
achieve synchronization
between OC and BC.

DELAY Packet Period(s) 64/1024, 128/1024, The DELAY Packet

256/1024, 512/1024, 1, 2, 4, Period(s) parameter
8, 16 provides an option to set the
Default: 1 period at which the PTP port
transmits the Delay packets.
The delay-to-respond
mechanism uses the Sync,
Delay_Req, Follow_Up, and
Delay_Resp packets to
achieve synchronization
between OC and BC.
This parameter can be set
only when P/E Mode is set
to E2E.
PDELAY Packet Period(s) 64/1024, 128/1024, The PDELAY Packet

256/1024, 512/1024, 1, 2, 4, Period(s) parameter
Default: 1 period at which the PTP port
transmits the Pdelay
packets. The Pdelay_Req,
Pdelay_Resp, and
Pdelay_Resp_Follow_Up
packets are used to measure
the link delay between two
clock ports where the Pdelay
mechanism functions.
only when Work Mode is
set to TC and P/E Mode to
P2P for the port.

ANNOUNCE Packet 64/1024, 128/1024, The ANNOUNCE Packet

Period(s) 256/1024, 512/1024, 1, 2, 4, Period(s) parameter
Default: 128/1024 period at which the PTP port
transmits the ANNOUNCE
packets. The ANNOUNCE
packets contain the clock
attributes of an NE and are
used to set up a synchronous
system.
NOTE
When the TN52TOG/
TN54TOA/TN54THA/ELOM/
TNF5TOA board is
interconnected with a PTN
device to transmit IEEE
1588v2 clock signals,
ANNOUNCE Packet
Period(s) must be set to
64/1028; otherwise, the
interconnected PTN device
may fail to properly trace
clock sources after the link is
broken.
ANNOUNCE Packet For TN54TOA and The ANNOUNCE Packet

Timeout Coefficient TN54THA and 1832, the Timeout Coefficient
value range is 3 to 255. For parameter provides an
other boards, the value option to set the timeout
range is 3 to 10. coefficient of receiving the
For OSN 3800 and OSN ANNOUNCE packets. By
9800, Default: 4 default, if the ANNOUNCE
packets are not received for
For OSN 6800, four consecutive periods, the
l TN12ND2 packet receiving times out
8 and the link fails.
l TN52ND2, TN11ST2,
TN52TOG, TN55TQX,
TN53TDX
4
For OSN 1832, Default: 3
Table 2-49 Cable Transmitting Warp



Warp Direction Positive, Negative The Warp Direction

Default: Positive parameter provides an
option to set how the time of
transmission over the cables
between two NEs warps in
the transmit and receive
directions.
l Positive indicates that
the transmission distance
or transmission time in
the receive direction is
longer than that in the
transmit direction.
l Negative indicates that
the transmission distance
or transmission time in
the transmit direction is
longer than that in the
receive direction.
Warp Mode Length, Time The Warp Mode parameter

Default: Time provides an option to set the
mode of warp in
transmission over the cables
in the transmit and receive
directions between two NEs.
l Length Indicates that
there is a warp of
transmission distance in
directions on the line
between two NEs.
l Time Indicates that there
is a warp of transmission
time in the transmit and
receive directions on the
line between two NEs.

Warp Length(m) OSN 8800/6800/1832: 0 to The Warp Length(m)

1700000 parameter provides an
OSN 9800: 0 to 3555555 option to set the warp of
transmission distance over
Default: 0 the cables in the transmit
and receive directions
between two NEs. Then,
adjust the time
synchronization according
to the actual warp of
transmission distance.
NOTE
only when the Warp Mode
parameter is set to Length.
Warp Time(ns) 0 to 8000000 The Warp Time(ns)

option to set the warp of
transmission time over the
cables in the transmit and
receive directions between
two NEs. Then, adjust the
time synchronization
according to the actual warp
in transmission time.
NOTE
only when the Warp Mode
parameter is set to Time.
2.8.4.8.4 Parameters: Clock Source at Port

This topic describes how to query the clock source that the port receives and the link status.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > PTP Clock > Clock
Source at Port from Function Tree.
Parameters
Board shelf ID (shelf name)-slot Selects the board to be

number-board name-optical queried.
port number(optical port
name)

Port shelf ID (shelf name)-slot Displays the port to be

number-board name-port queried.
number (port name)-optical
port number(optical port
name)
PTP Clock Source No. For example: Displays the clock number
Company Code: 00259E of the clock source that the
port receives.
Supplying Code: 30
NE ID: 007E028B
Tracing Direction upstream, downstream When the specified port can

receive ANNOUNCE
messages from the
connected port and has no
abnormal alarm, Tracing
Direction is upstream;
otherwise, the status is
downstream.
2.8.4.8.5 Parameters: PTP Clock Subnet

In this user interface, you can set the clock subnet to ensure that the clocks in the same clock
subnet are synchronized according to the network planning.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > PTP Clock > PTP
Clock Subnet Configuration from the Function Tree. Then, click the PTP Clock Subnet
tab.
Parameters
PTP Clock Subnet No. 0 to 255 Specifies the clock subnet

Default: 0 number to which the NE
belongs.
The NEs with the same
clock subnet number belong
to the same clock subnet.

2.8.4.8.6 Parameters: BMC (Clock Subnet)

In this user interface, you can set the BMC algorithm that the local clock source uses, so that
the system can calculate and select the best clock source according to the set attributes, such
as precision and priority.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > PTP Clock > PTP
Clock Subnet Configuration from the Function Tree. Then, click the BMC tab.
Parameters
Time Quality Level 6, 7, 13, 14, 52, 58, 68 to The Time Quality Level
122, 133 to 170, 216 to 232, parameter provides an
187, 193, 248, 255 option to set the quality
Default: 187 level of the time or
frequency allocated by the
master clock device. A
smaller parameter value
indicates a higher quality
level.
This parameter has an
impact on selection of the
external clock source for
tracing. If the PTP Clock
Source Priority1 values of
the clock candidates are the
same, Time Quality Level
determines which clock is
preferred. That is, the clock
with a smaller Time
Quality Level value is of a
higher quality level and is
preferred as the time source
for tracing.

Time Precision OSN 9800 M series, OSN The Time Precision

1832 subrack: 0 to 255, parameter provides an
other subrack is 32 to 49. option to set the time
Default: OSN 9800 M precision of the master clock
series, OSN 1832 subrack: or expected time precision
254, other subrack is 49. of the candidate master
clock. A smaller parameter
value indicates a higher
quality level.
Source Priority1 and Time
Quality Level values of the
clock candidates are the
same, Time Precision
with a smaller Time
Precision value is of higher
time precision and is
preferred as the clock source
for tracing.

PTP Clock Source Type ATOMIC_CLOCK, GPS, The PTP Clock Source
TERRESTRIAL_RADIO, Type parameter provides an
PTP, NTP, HAND_SET, option to set the type of the
OTHER, clock source.
INTERNAL_OSCILLATO l ATOMIC_CLOCK:
R Indicates an atomic
Default: clock.
INTERNAL_OSCILLATO l GPS: Indicates a GPS
R time source.
l TERRESTRIAL_RADI
O: Indicates any device
synchronized through
any of the radio
distribution systems that
distribute time and
frequency tied to
international standards.
l PTP: Indicates a clock
source compliant with
the PTP protocol.
l NTP: Indicates a clock
the network time
protocol (NTP).
l HAND_SET: Indicates a
clock source manually
set.
l OTHER: Indicates other
clock sources.
l INTERNAL_OSCILLAT
OR: Indicates an internal
clock source.

PTP BClock Source 0 to 255 The PTP Clock Source

Priority 1 Default: 128 Priority 1 parameter
primary priority of the clock
source. A smaller parameter
priority.
tracing. This parameter is
the primary factor that
determines the quality of a
clock source. That is, the
clock source with a smaller
PTP Clock Source Priority
1 value is of a higher quality
level and is preferred as the
clock source for tracing.
PTP Clock Source Priority 0 to 255 The PTP Clock Source

2 Default: 128 Priority 2 parameter
auxiliary priority of the
clock source. A smaller
parameter value indicates a
higher priority.
tracing. When the PTP
Clock Source Priority 1,
Time Quality Level, Time
Precision, and PTP Clock
Source Drift Rate values of
same, this parameter
determines the clock quality.
That is, the clock source
with a smaller PTP Clock
Source Priority 2 value is
of higher quality and is
for tracing.

PTP Clock Source 0 to 65535 The PTP Clock Source

Deviation Default: Deviation parameter
l OSN 1832 subrack: drift of the master clock
65535 from the standard time. A
l Other subrack: 32768 smaller parameter value
indicates a lower clock drift
rate and better clock signals.
Source Priority1, Time
Quality Level, and Time
Precision values of the
same, PTP Clock Source
Deviation determines which
clock is preferred. That is,
the clock with a smaller
PTP Clock Source
Deviation value is of higher
for tracing.
2.8.4.8.7 Parameters: Basic Attribute

In this user interface, when an NE is connected to an external clock source, you can set the
interface attributes of the external clock source, so that the NE can extract the external clock
properly.
Navigation Path
External Time Interface from the Function Tree. Click the Basic Attribute tab.
Parameters
External Time Interface shelf ID (shelf name)-slot Displays the name of the
number-board name- input interface of the
external clock interface external clock source on the
NE.
Direction Ingress, Egress Displays the direction of the

Default: Egress external clock source.

Interface Protocol Type 1PPS+Time The Interface Protocol

Default: 1PPS+Time Type parameter provides an
option to set the protocol
type for the interface with
the external clock source on
an NE.
only when Enabled Status
is set to Disabled for the
port.
Interface Level RS422 Specifies the interface level

Default: RS422 according the interface type
when the NE is connected to
an external clock source.
RS422 indicates that the
interface type is RJ45.
2.8.4.8.8 Parameters: BMC (External Time Interface)

In this user interface, when the NE is connected to an external clock source, you can set the
BMC algorithm that the external clock source uses through the external interface, so that the
system can calculate and select the best clock source according to the set attributes, such as
precision and priority.
Navigation Path
External Time Interface from the Function Tree. Click the BMC tab.
Parameters
NE.

Time Quality Level 6, 7, 13, 14, 52, 58, 68 to The Time Quality Level
122, 133 to 170, 216 to 232, parameter provides an
187, 193, 248, 255 option to set the quality
Default: 187 level of the time or
frequency allocated by the
master clock device. A
smaller parameter value
indicates a higher quality
level.
Source Priority 1 values of
same, Time Quality Level
with a smaller Time
Quality Level value is of a
higher quality level and is
preferred as the time source
for tracing.
Time Precision OSN 9800 M series, OSN The Time Precision

1832 subrack: 0 to 255, parameter provides an
other subrack is 32 to 49. option to set the time
Default: OSN 9800 M precision of the master clock
series, OSN 1832 subrack: or expected time precision
254, other subrack is 49. of the candidate master
clock. A smaller parameter
quality level.
Source Priority 1 and Time
Quality Level values of the
same, Time Precision
with a smaller Time
Precision value is of higher
for tracing.

PTP Clock Source Type ATOMIC_CLOCK, GPS, The PTP Clock Source
TERRESTRIAL_RADIO, Type parameter provides an
PTP, NTP, HAND_SET, option to set the type of the
OTHER, clock source.
INTERNAL_OSCILLATO l ATOMIC_CLOCK:
R Indicates an atomic
Default: clock.
INTERNAL_OSCILLATO l GPS: Indicates a GPS
R time source.
l TERRESTRIAL_RADI
O: Indicates any device
synchronized through
any of the radio
distribution systems that
distribute time and
frequency tied to
international standards.
l PTP: Indicates a clock
the PTP protocol.
l NTP: Indicates a clock
the network time
protocol (NTP).
l HAND_SET: Indicates a
clock source manually
set.
l OTHER: Indicates other
clock sources.
l INTERNAL_OSCILLAT
OR: Indicates an internal
clock source.


primary priority of the clock
source. A smaller parameter
priority.
tracing. This parameter is
the primary factor that
determines the quality of a
clock source. That is, the
clock source with a smaller
PTP Clock Source Priority
1 value is of a higher quality
level and is preferred as the
clock source for tracing.

auxiliary priority of the
clock source. A smaller
parameter value indicates a
higher priority.
tracing. When the PTP
Clock Source Priority 1,
Time Quality Level, Time
Precision, and PTP Clock
Source Drift Rate values of
same, this parameter
determines the clock quality.
That is, the clock source
with a smaller PTP Clock
Source Priority 2 value is
of higher quality and is
for tracing.

PTP Clock Source 0 to 65535 The PTP Clock Source

Deviation Default: Deviation parameter
l OSN 1832 subrack: drift of the master clock
65535 from the standard time. A
l Other subrack: 32768 smaller parameter value
indicates a lower clock drift
rate and better clock signals.
Source Priority 1, Time
Quality Level, and Time
Precision values of the
same, PTP Clock Source
Deviation determines which
clock is preferred. That is,
the clock with a smaller
PTP Clock Source
Deviation value is of higher
for tracing.
Local Priority 1 to 255 Indicates the clock source

Default: 128 priority of the port.
The smaller the value, the
higher the priority.
2.8.4.8.9 Parameters: Cable Transmitting Distance

In this user interface, when the NE is connected to an external clock source, you can set the
cable transmission distance to modify the clock synchronization.
Navigation Path
External Time Interface from the Function Tree. Click the Cable Transmitting Distance
tab.

Parameters
NE.
Transmitting Direction Ingress, Egress Sets the transmission

direction of the cable of the
NOTE
l When Enabled Status of a
port is set to Enabled,
Transmitting Direction
can be set to only Ingress.
l When Enabled Status of a
port is set to Disabled,
Transmitting Direction
can be set to Ingress and
Egress.
Transmitting Distance Length, Time The Transmitting Distance

Mode Default: Length Mode parameter provides
an option to set the
transmission distance mode
for the clock interface. This
parameter can be set to
Length or Time.
If the delay can be
measured, set this parameter
to Time; otherwise, set this
parameter to Length.
l Length: Indicates that the
transmission distance is
expressed in terms of
length.
l Time: Indicates that the
transmission distance is
expressed in terms of
time.

Transmitting Length(m) 0 to 300 The Transmitting

Default: 0 Length(m) parameter
transmission distance of the
external clock source over
cables. Set this parameter
according to the actual
transmission length to adjust
the delay in transmitting the
clock signals.
to the measured length of
the transmission cable. If
Enable Status is set to
Enabled for the port, the
delay can be compensated
only at the receive end and
the compensation should be
the same as the actual
distance. If Enable Status is
set to Disabled for the port,
the delay can be
compensated at both the
transmit and receive ends.
The sum of compensation at
ends should be equal to the
actual distance.
only when Transmitting
Distance Mode is set to
Length. In the case of the
transmit direction, the delay
at the transmit end is
compensated. In the case of
the receive direction, the
delay at the receive end is
compensated.

Transmitting Delay(ns) 0 to 1350 The Transmitting

Default: 0 Delay(ns) parameter
delay in transmitting the
clock source over the cable.
Set this parameter properly
to adjust time
synchronization.
In the case of the transmit
direction, the delay at the
transmit end is
compensated. In the case of
the receive direction, the
delay at the receive end is
compensated.
only when Transmitting
Distance Mode is set to
Time.
2.8.4.8.10 Parameters: MAC Address Configuration

In this user interface, you can query or set the physical address of boards. This address will be
carried in PTP and SSM packets.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > PTP Clock > MAC
Address Configuration.
Parameters
Board For example: Shelf5(Slave Indicates the clock board.

shelf5)-5-54TOA(STND)

MAC Address For example: This function can be used to

88-00-88-00-88-00 configure the physical
addresses for sending PTP
and SSM packets so that
fields can be filled in to the
sent packets based on the
requirements of the
downstream equipment,
improving the configuration
flexibility for
interconnection with third-
party equipment.
NOTE
Value range for each octet: 00-
FF (Special characters are not
supported.)
NOTE
Only the following boards
support this parameter:
l OSN 8800: TN54TOA and
TN54THA.
l OSN 1832 X16:
TNF5TOA, TNF6TOA,
TNF5TQX, TNF2LDX,
TNF2ELOM (STND),
TNF6TTA, TNF1LDCA.
l OSN 1832 X8 Enhanced:
TNF2LDX, TNF2ELOM
(STND), TNF6TTA,
TNF1LDCA.
2.8.5 Configuring a IEEE 1588v2 Clock (OSN 9800 U Series:

U1CTU/S1CTU)

This topic describes how to configure an IEEE 1588v2 clock.
Figure 2-27 shows the process of configuring an IEEE 1588v2 clock.
Figure 2-27 IEEE 1588v2 clock configuration flowchart

Table 2-50 provides the detailed procedures for configuring IEEE 1588v2-compliant
frequency and phase synchronization.
NOTE
The procedures provided in Table 2-50 are only used to configure IEEE 1588v2-compliant frequency
and phase synchronization. To provide physical clock frequency synchronization and IEEE 1588v2-
compliant phase synchronization, configure the physical clock by referring to 2.7.5.1 Configuration
Process and then perform the procedures provided in Table 2-50 to configure IEEE 1588v2 packets.
Table 2-50 Procedures for configuring IEEE 1588v2-compliant frequency and phase
synchronization
Operation Remarks
2.8.5.2 Mandatory.
Enabling IEEE You must enable IEEE 1588v2 before configuring it for a NE. The
1588v2 number of available licenses is deducted by 1 each time IEEE 1588v2 is
enabled for a subrack.
NOTE
Since OSN 1832 V100R007C00, before IEEE 1588v2 is enabled, Protection
Status of SSM must be set to Start Extended SSM Protocol or Start Standard
SSM Protocol.
2.8.5.3 Mandatory.
Configuring l Set clock synchronization attributes. According to the actual
PTP NEs networking, you need to set the clock synchronization attributes of
each NE on the U2000, including setting the PTP working mode,
system time, and system time calibration parameters.
l Configure the BMC static source selection. The status of the master,
slave, and passive ports is manually set to achieve time
synchronization. The dynamic BMC automatic source selection
algorithm is not enabled. If a port is abnormal, automatic switching
is not triggered.
l Configuring clock subnets. When a physical OTN needs to be
divided into multiple clock domains, clock subnets must be
configured.
l Set the attributes of the local clock. According to the actual
networking, you must set the local clock parameters received by the
local NE, so that the clock selection module can calculate the best
master clock.
2.8.5.4 Mandatory.
Configuring l Create a clock port and set port packet attributes. The ports that
PTP Ports transmit or receive IEEE 1588v2 packets must be configured as PTP
ports to trace PTP clock sources.
l Set the Cable Transmission Warp parameter of the clock port. Set
the parameters of the cable transmission deviation according to the
actual situation to compensate for the delay generated by external
time cables.

Operation Remarks
2.8.5.5 Optional.
Configuring When an NE needs to input or output external time signals, you must
External Time enable the port cascading function and set external time interface
Ports attributes and the Cable Transmission Warp parameter.
2.8.5.6 Mandatory.
Querying the After all the clock configuration processes are completed, users need to
Clock Source query all ports for the clock synchronization status to ensure that the
Received at the port synchronization status is the same as that defined in the networking
Port diagram.
2.8.5.7 Viewing Mandatory.

the Clock Correct clock tracing relationships are critical to ensure the clock
Tracing Status synchronization within the entire network. Using the U2000, you can
monitor the clock tracing status of each NE.
2.8.5.2 Enabling IEEE 1588v2

You must enable IEEE 1588v2 before configuring it for a NE. The number of available
licenses is deducted by 1 each time IEEE 1588v2 is enabled for a subrack.
Prerequisites
l The license of IEEE 1588v2 resources is available.
l The corresponding subrack must be created.
Procedure
Step 1 Change the 1588V2 attribute to Enabled.

NOTE
ITU-T G.8275.1 and IEEE 1588v2 share the same license resources. ITU-T G.8275.1 is enabled after
IEEE 1588v2 is enabled on the U2000.
----End
2.8.5.3 Configuring PTP NEs

To ensure normal operation of the PTP clock for each NE in a network, users need to
configure PTP clock global parameter, PTP clock subnet, local clock attributes for the NE.
Prerequisites

Configuring PTP Clock Global Parameter

Based on the actual networking situation, you need to set the clock synchronization attributes
of each NE on the U2000. The attributes include PTP work mode, PTP system time, and static
BMC.
Step 1 Configuring Ptp Profile:
Step 2 Optional: Change PTP System Time.
NOTE
The PTP System Time can be set only when the NE traces the local clock source.
Step 3 Configure Ne Clock Type, Static BMC, Slave Only, Packet Multicast Mode, Protocol
Packet Format, Correct UTC Time and select the required value from the drop-down list
respectively. For parameter details, see 2.8.5.8.1 Parameters: Clock Synchronization
Attribute.

NOTE
The Slave Only parameter is available only when Ne Clock Type is set to OC.
----End
Configuring a PTP Clock Subnet

Network planning personnel need to divide the entire network into different clock subnets in
planning the clock network depending on the scheme for the site. Within each subnet, time
synchronization can be implemented for all clocks.
The calculation of the PTP clock source is based on the clock subnet. Each clock subnet
calculates its own current clock source separately. For an NE, only one time domain is
supported at a time. Each BC or OC equipment can only be configured with one clock subnet.
The clock source should be selected from within the same clock subnet. The packets sent
from different clock subnets are discarded by the NE.
Step 1 Configure Clock Subnet No.. For parameter details, see 2.8.5.8.3 Parameters: Clock
Subnet.

NOTE
l The NEs that have the same subnet number belong to the same clock subnet.
----End
Configuring the Local Clock Attributes

Depending on the networking scheme for the site, users need to set the clock attributes of the
local clock sources received at the NE, so that the best master clock can be calculated by the
clock selection module.
Step 1 Configure Time Quality Level, Time Precision, Clock Source Type, Clock Source Priority
1, Clock Source Priority 2 fields. Then configure the settings for each parameter. For the
details about these parameters, see 2.8.5.8.4 Parameters: BMC (Clock Subnet).

----End
2.8.5.4 Configuring PTP Ports

To ensure that precision time protocol (PTP) ports of every NE on a network work correctly,
users need to create logical PTP ports, configure attributes of PTP packets, and specify the
cable transmission deviation of PTP clock ports.
Prerequisites
l The corresponding board must be created.
Configuring a Clock Port

l A clock port can be used to trace the PTP clock source. Clock ports are created to enable
a PTP clock port so that PTP packets can be received.
l The clock port is used to synchronize the time between two clock nodes. Depending on
the scheme for the site, several clock ports can be created for a board to connect to other
clock nodes.
Step 1 Configure a clock port. For parameter details, see 2.8.5.8.1 Parameters: Clock
Synchronization Attribute.

NOTICE
For a port on each 10GE LAN tributary board installed on an OSN 9800 of V100R001C00 or
V100R001C01, Port Mapping can be set to MAC Transparent Mapping (10.7G). After the
OSN 9800 is upgraded to V100R001C20, configuring the port as a PTP port to support IEEE
1588v2 interrupts traffic on the port. The traffic is restored automatically after the
configuration is completed.
NOTE
In the OC work mode, only one clock port can be created.
----End
Configuring the Clock Source Priority Table

Configuring the clock source priority table specifies the priority of each required clock
switching occurs.
Step 1 Configure Clock Source WTR Time(min).

NOTE
You can set any integer from 0 to 12 for Clock Source WTR Time(min), with a step of 1. The default
value is 5.
Step 2 Configure Port, Clock Source No and Clock Source PortNo.

1
5
3
2

----End
Configuring the PTP Packet Attributes

To ensure the normal operation of the PTP clock for each NE in the network, users need to set
the corresponding PTP packet attributes based on the work mode of each NE.
Step 1 Configure P/E Mode, SYNC Packet Period(s), DELAY Packet Period(s), PDELAY
Packet Period(s), ANNOUNCE Packet Period(s), and ANNOUNCE Packet Timeout
Coefficient. For parameter details, see 2.8.5.8.1 Parameters: Clock Synchronization
Attribute.
NOTE
The DELAY Packet Period(s) field is available only when the P/E Mode is set to E2E; the PDELAY
Packet Period(s) field is available only when the P/E Mode is set to P2P.
----End

Configuring the Cable Transmission Deviation for the Clock Port

When the transmission time and length of a cable in the receive and transmit directions are
not consistent, the transmission deviation of a cable needs to be set to rectify the PTP clock
synchronization process.
The transmission deviation of a cable means the time difference of the clock signals in the
cable transmission in the receiving and sending directions between two NEs. Generally, the
actual time difference of cable transmission for the two directions is calculated by GPS in the
deployment. The cable transmission deviation can be represented by time or by length.
Step 1 Configure Warp Direction, Warp Mode, Warp Length(m), and Warp Time(ns). For
parameter details, see 2.8.5.8.1 Parameters: Clock Synchronization Attribute.
NOTE
l The value Positive of the Warp Direction field specifies that transmission distance through the
receiving direction is longer than the distance through the sending direction, or the transmission time
of the receiving direction is longer than the time of the sending direction; the value Negative
specifies just the opposite.
l The Warp Length(m) field is available only when the Warp Mode is set to Length; the Warp
Time(ns) field is available only when the Warp Mode is set to Time.
l The values of the Warp Length(m) and Warp Time(ns) are set according to the networking
scheme for the site.
----End
2.8.5.5 Configuring External Time Ports

When there are external clock sources for an NE, users need to configure the clock attributes
of the external clock sources, such as configuring attributes of external time ports, and
configuring the cable transmission distance permitted by an external time port. Based on the
configured clock attributes, the clock selection module can compute which clock is best to use
as the best master clock.

Prerequisites
l The CTU board has been created.
Configuring External Time Ports

When there are external clock sources for an NE, users need to set the attributes of the
external time ports so that the NE can use the correct external clock.
Step 1 Select an external time interface and configure the settings in the following fields: External
Time Interface Direction, and Interface Protocol Type. For parameter details, see 2.8.5.8.5
Parameters: Basic Attribute.
Step 2 Configure Bits Type, Bits Clock Class Level, Bits Precision, Bits Time Source, Bits
Priority 1, Bits Priority 2 fields. Then configure the settings for each parameter. For
parameter details, see 2.8.5.8.6 Parameters: BMC (External Time Interface).

----End
Configuring Cable Transmission Distance Permitted by an External Time Port

Users need to set the cable transmission distance based on the actual length of an external
time cable to facilitate the recovery and transmission of time signals.
Step 1 Select an external time interface and configure settings in the following fields: Input Warp
Mode, Input Warp Length(m), Input Warp Time(ns), Output Warp Mode, Output Warp
Length(m), Output Warp Time(ns). For parameter details, see 2.8.5.8.7 Parameters: Cable
Transmitting Distance.

NOTE
l The Input Warp Length(m) field is available only when the Input Warp Mode is set to Length;
the Input Warp Time(ns) field is available only when the Input Warp Mode is set to Time.
l The Output Warp Length(m) field is available only when the Output Warp Mode is set to
Length; the Output Warp Time(ns) field is available only when the Output Warp Mode is set to
Time.
l The values of the Input Warp Length(m), Output Warp Length(m), Input Warp Time(ns), and
Output Warp Time(ns) are set depending on the networking scheme for the site.
----End
2.8.5.6 Querying the Clock Source Received at the Port

The U2000 supports the function of querying the clock source received at the port. By using
this function, you can query the tracing status of the NE time.
Prerequisites
l The clock port has been created.
Procedure
Step 1 Query the information about the clock source received at the port is displayed.
----End

Prerequisites

Context
Procedure
queried, click OK.
----End
2.8.5.8 Parameters: IEEE 1588v2 (OSN 9800 U Series: U1CTU/S1CTU)

2.8.5.8.1 Parameters: Clock Synchronization Attribute

In this user interface, you can configure and query the NE and port attributes, such as the PTP
system time, working mode, packet transmission period on the port, and transmission
deviation of the cable, in the PTP clock system.
Navigation Path
Clock Synchronization Attribute from Function Tree.
Parameters
Table 2-51 Clock Synchronization Attribute

PTP System Time For example: 2009-02-01 Displays the PTP system
01:01:01 time. You can manually
modify this parameter.

Ne Clock Type OC, TC, BC, TC+BC, TC The NE Clock Type

+OC parameter provides an
Default: BC option to set the working
mode (OC, TC, BC, TC
+BC, or TC+OC) of the
node that adopts the IEEE
1588v2 clock. According to
the network planning, an NE
on the network must work in
the OC, TC, BC, TC+BC,
TC+OC mode. The specific
mode of the NE must be
determined in the network
planning phase.
Static BMC Enable, Disable NOTE

Static BMC can be set to
Default: Disable either Enable or Disable to
enable or disable the IEEE
1588v2 protocol. When it is
set to Enable, users can
manually configure the port
status as master or slave.
Slave Only Yes, No The Slave Only parameter

Default: No provides an option to set the
Slave_Only attribute for an
OC port. This attribute
determines whether the OC
port works only as a slave
clock port.
NOTE
only when NE Clock Type is
set to OC.
Enable Automatic Enable, Disable On a ring network, if a fiber

Compensation Default: Disable is cut over or adjusted, the
Measurement NE automatically computes
fiber length variation. In this
course, users do not need to
manually measure the fiber
length variation, but only
need to set compensation
parameters. In this manner,
the NE can maintain time
synchronization with GPS.
NOTE
The WDM/OTN equipment
does not support setting
Enable Automatic
Compensation
Measurement.

Packet Multicast Mode Multicast, Partly-Multicast In multicast mode, SYNC,

Default: Multicast ANNOUNCE, and DELAY
packets are multicasted. In
part multicast mode, SYNC
and ANNOUNCE packets
are multicasted, whereas
DELAY packets are
unicasted.
Inpartly-multicast mode,
Delay_Req and Delay_Resp
packets are unicasted. In
E2E TC scenarios, this
avoids transmission of delay
Req packets between slave
equipment.
Protocol Packet Format NMEA, UBX Configures and queries the

Default: UBX protocol packet format.
The Protocol Packet
Format is valid only when
Interface Protocol Type of
the external time interface is
set to 1PPS+Time.
Local Clock Source No. For example: Displays the clock number
00259e30007d0050 of the local clock source of
the NE.
Current Master Clock No. For example: Displays the master clock
00259e30007d0050 number that the NE traces.
Ingress of Current Master For example: PTP Displays the local clock
Clock input interface of the master
clock that the NE traces
after you specify the clock
source for the NE.
Hops of Current Master For Example: 3 Indicates the number of

Clock hops for transmitting clock
signals from the master
clock to the current NE.
For example, the signal
route is NE A (master
clock)->NE B->NE C->NE
D. For NE D, Hops of
Current Master Clock is 3.
Correct UTC Time 0 to 255 Correct the UTC time.

Default: 35
Ptp Profile IEEE 1588v2, G.8275.1 Indicates the PTP protocol

Default: IEEE 1588v2 type used by the NE.

Table 2-52 Port Status

Port For example: Otn0/12/255/1 Displays the name of the

ports where the PTP clocks
are synchronized.
PTP Packet VLAN 0 to 4094 The PTP Packet VLAN

option to set the VLAN IDs
with the PTP packets at a
port. In the scenario of
interconnection with other
client-side equipment, the
transmitted PTP packets
must contain VLAN IDs.
PTP Packet VLAN 0 to 7 Sets the VLAN priority of a

Priority Default: 7 port PTP packet.
PTP Packet DSCP Priority 0 to 63 Sets the DSCP prior

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Huawei Technologies Co., Ltd.

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. i

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. ii

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. iii

2.7.6.1.3 OSN 9800 M Series Hardware and Version Support.........................................................................................110

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. iv

2.8.4.8.7 Parameters: Basic Attribute............................................................................................................................... 189

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. v

2.9.2.4 ITU-T G.8275.1 Frequency Synchronization Principles......................................................................................260

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. vi

2.9.5.9.6 Parameters: Basic Attribute............................................................................................................................... 328

3 L1 Service Encryption Feature.................................................................................................352

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. vii

3.7.3.2 Creating and Logging In to an NE........................................................................................................................384

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. viii

3.8.2.4 Encryption Capability of the OSN 1832...............................................................................................................425

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. ix

Updates in Issue 01 (2018-08-30)

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. 1

2 WDM/OTN Clock Feature

About This Chapter

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. 2

2.1 About This Document

Product Name Initial Version

OSN 9800 V100R001C20

OSN 8800 V100R002C00

OSN 6800 V100R005C00

OSN 1832 V100R003C05

l Network planning and design engineers

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. 3

Indicates a hazard with a high level of risk, which if not

Indicates a hazard with a medium or low level of risk, which

Indicates a potentially hazardous situation, which if not

Indicates a tip that may help you solve a problem or save

Provides additional information to emphasize or supplement

Boldface Buttons, menus, parameters, tabs, window, and dialog titles

> Multi-level menus are in boldface and separated by the ">"

Updates in Issue 01 (2018-08-30)

2.2 Why Does the WDM/OTN Network Need Clock

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. 4

Mobile Backhaul Network Requires the WDM/OTN Network to Implement

SDH Modernization Requires the WDM/OTN Network to Implement Clock

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. 5

Architecture of a WDM/OTN Clock Synchronous Network

Figure 2-1 Architecture of the clock synchronous network

2.3 Clock Synchronization Requirements of Service

l Frequency Synchronization: Frequency synchronization means that different signals

Issue 01 (2018-08-30) Copyright © Huawei Technologies Co., Ltd. 6

Figure 2-2 Frequency synchronization and Phase Synchronization

Table 2-1 Clock synchronization requirements of mobile communication networks

Wireless Required Required Recommended Synchronization Mode

GSM 0.05 ppm Phase Physical clocks

WCDMA 0.05 ppm Phase Physical clocks

TD-SCDMA 0.05 ppm ±1.5 µs Physical clocks+IEEE 1588v2/ITU-T G.