November 2015

Chapter 4 Microelectronic Devices & Circuits (ECEg4261) Class Notes

4. NMOS and PMOS Transistors Operating Principle

4.1 Operation of MOSFETs
Transistors are active devices with highly nonlinear characteristics. Thus, to analyze and design a
transistor circuit, we need models of transistors. Creating accurate models requires detailed
knowledge of the physical operation of transistors and their parameters as well as a powerful
analytical technique.

A circuit can be analyzed easily using simple models, but there is generally a trade-off between
accuracy and complexity. A simple model, however, is always useful to obtain the approximate
values of circuit elements for use in a design exercise and the approximate performance of the
elements for circuit evaluation. In this chapter, we will consider the operation and external
characteristics of field-effect transistors using simple linear models.

The basic concept of field-effect transistors (FETs) has been known since the 1930s; however,
FETs did not find practical applications until the early 1960s. Since the late 1970s, MOSFETs
have become very popular; they are being used increasingly in integrated circuits (ICs). The
manufacturing of MOSFETs is relatively simple. A MOSFET device can be made small, and it
occupies a small silicon area in an IC chip. MOSFETs are currently used for very-large-scale
integrated (VLSI) circuits such as microprocessors and memory chips.

A metal oxide semiconductor field-effect transistor (MOSFET) is a unipolar device. The current
flow in a MOSFET depends on one type of majority carrier (electrons or holes). The output
current of MOSFETs is controlled by an electric field that depends on a gate control voltage.
There are two types of MOSFETs: enhancement MOSFETs and depletion MOSFETs.

4.1.1 Enhancement MOSFETs

There are two types of enhancement MOSFETs: n-channel and p-channel. An n-channel
enhancement MOSFET is often referred to as an NMOS. The physical structure of an NMOS
showing its terminal is illustrated in Figure 4.1(a); a schematic appears in Figure 4.1(b). Since the
p-type substrate and the two -type junctions are reverse biased, there will be a depletion region
as shown in Figure 4.1(b) by shaded lines. Two -type regions act as low-resistance connections
to the source and the drain. An insulating layer of silicon dioxide is formed on top of the p-type
substrate by oxidizing the silicon. Ohmic contacts are provided to the -regions for connection to
the external circuit by leaving two windows on the silicon dioxide and depositing a layer of
aluminum. The substrate B is normally connected to the source terminal. An n-channel is induced
under the influence of an electric field; there is no physical n-channel between the drain and the
source of an NMOS, as shown by the darker shade in Figure 4.1(b). The symbol for an NMOS is
shown in Figure 4.1(c), where the arrow points from the p-type region to the n-type region. An
NMOS is often represented by the abbreviated symbol shown in Figure 4.1(d) in which the
arrowhead indicates the direction of the current.

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A p-channel enhancement-type MOSFET, often referred to as a PMOS, is formed by two -type

regions on top of the n-type substrate, as shown in Figure 4.2[(a) and (b)]. The p-regions offer low
resistances. The symbol for a PMOS is the same as that for an NMOS, except that the direction of the
arrow is reversed, as shown in Figure 4.2(c). The abbreviated symbol is shown in Figure 4.2(d).

Figure 4.1 Structure and symbols of an n-channel enhancement MOSFET

Figure 4.2 Structure and symbols of a p-channel enhancement MOSFET

i. Operation
An NMOS is operated with positive gate and drain voltages relative to the source, as shown in Figure
4.3(a), whereas a PMOS is operated with negative gate and drain voltages relative to the source, as shown
in Figure 4.3(b). Their substrates are connected to the source terminal. The NMOS can operate in any of
the four operating regions: cutoff region, linear ohmic, nonlinear ohmic, and saturation.

Figure 4.3 Biasing of an NMOS and a PMOS

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ii. Complementary MOS (CMOS)

The complementary metal oxide semiconductor (CMOS) consists of an n-channel enhancement-
mode device > 0 in series with a p-channel enhancement-mode device < 0 . The cross-
section of a CMOS is shown in Figure 4.4. The NMOS transistor is implemented directly in the p-
type substrate, while the PMOS transistor is fabricated in a specially created n-region, known as
an n-well. The two devices are isolated from each other by a thick region of oxide that functions as
an insulator. An external body terminal is also made from the p-type body and the n-well. Due to
their unique advantages, such as very low power consumption, CMOS circuits are commonly used
in integrated circuits. The CMOS inverter, which is the basis of CMOS digital electronics, is
covered in detail in section 4.3. CMOS technology has taken over many IC applications and
continues to grow.

Figure 4.4 Cross section of a CMOS

4.1.2 Depletion MOSFETs
The construction of an n-channel depletion MOSFET is very similar to that of an NMOS. An
actual channel is formed by adding n-type impurity atoms to the p-type substrate, as shown in
Figure 4.5(a). The symbol for an n-channel depletion MOSFET is shown in Figure 4.5(b); this
symbol is often abbreviated to the one shown in Figure 4.5(c). Note that the vertical line is bold or
darker. An n-channel depletion MOSFET is normally operated with a positive voltage between the
drain and the source terminals. However, the voltage between the gate and the source terminals
can be positive, zero, or negative, whereas in an NMOS is positive.

Figure 4.5 Schematic and symbols of an n-channel depletion MOSFET

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The operation of an n-channel depletion MOSFET is similar to that of an NMOS. A depletion

NMOS is off when its gate-to-source voltage is less than − , whereas an NMOS is off when
≤ . The channel is fully established at = 0 for a depletion NMOS and at = for
an NMOS. Let us assume that the gate-to-source voltage is zero: = 0. If is increased from
zero to some small value (≈ 1 ), the drain current follows Ohm’s law ( = ⁄ ) and is
directly proportional to . Any increase in the value of beyond , known as the pinch-
down voltage, does not increase the drain current significantly. The region beyond pinch-down is
called the saturation region. The value of the drain current that occurs at = (with
= 0) is termed the drain-to-source saturation current .

4.2 Modeling of MOS transistors

Since the drain currents of the enhancement and depletion MOSFETs depend on the gate–source
voltage, they are known as voltage-dependent devices and exhibit similar output characteristics
and, the same model can be applied to both of them with reasonable accuracy. An NMOS circuit
with the transistor biased to operate in the saturation region is shown in Figure 4.6(a). Using KVL
around the drain-to-source loop gives
= +
" #
= !
− !
(4.1)
which describes the load line, and intersects the -axis at ⁄ and the -axis at as
shown in Figure 4.6(b).

Figure 4.6 NMOS with a small-signal input voltage $

The intersection of this load line with the - characteristic gives the operating (or quiescent)
point for a given value of . Let us assume that the drain current, drain-to-source voltage, and
gate-to source voltage have initial quiescent values of , , and , respectively. In a
MOSFET amplifier, an AC input signal is normally superimposed on the gate voltage. If a small
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AC signal $% is connected in series with , it will produce a small variation in the drain-to-
source voltage and the drain current . That is, if the gate-to-source voltage varies by a small
amount, such that = + $% , there will be corresponding changes in the drain current and
drain-to-source voltage such that = + &% and = + & . This situation is shown in
Figure 4. 6(b). The small variations of the drain current , as & , and the drain-to-source voltage
, as &% , around the operating point are shown in Figure 4.6(b). The drain-to-source variation
&% will equal the voltage gain times $% . If the values of & , $% , and &% are small, Figure 4.6(b)
can be represented by the small-signal circuit shown in Figure 4.6(c). Therefore, we need two
types of models for MOSFETs: a DC model and a small-signal model.

4.2.1 DC Models
The large-signal (DC) models of MOSFETs are nonlinear. The drain characteristics of as a
function of for different values of describe the large-signal model of a MOSFET. Since
the gate-channel has an oxide layer, the gate current will be negligibly small. Thus, MOSFETs can
be represented by the simple DC model of Figure 4.7.

Figure 4.7 Large-signal model of n-channel MOSFETs

4.2.2 Small-Signal AC Models

The small-signal behavior of the MOSFET in Figure 4.7 can be represented by a small-signal AC
equivalent circuit consisting of a voltage-dependent current source '( $% in parallel with an
output resistance ) representing a finite slope of the - characteristic. This circuit is shown in
Figure 4.8(a). Since the gate current $ of MOSFETs is very small, tending to zero, the gate-to-
source terminals are open circuits.

Figure 4.8 Small-signal model of MOSFETs

Applying the relations between Norton’s and Thevenin’s theorems, we can represent the current
source in Figure 4.8(a) by a voltage source, as shown in Figure 4.8(b). We find &% from
&% = & ) − ) '( $% = & ) − *$ $% (4.2)
where *$ is the open-circuit voltage gain of the MOSFETs and is given by

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*$ = ) '( (4.3)
The circuits of Figure 4.8[(a) and (b)] are referred to as the Norton and Thevenin circuits,
respectively, and they are equivalent. ) is the small-signal output resistance, and '( is the trans-
conductance gain of the MOSFET. Their values are dependent on the operating point and are
quoted at a specified operating point ( , ).

The small-signal output resistance is the inverse slope of the - characteristic in the pinch-
down or saturation region. The output resistance ) is given by
+ &. /
= &" =| =2 for all MOSFETs (4.4)
,- # 1|
Here 3 is called the channel modulation voltage and 2 = 1⁄| 3 | is called the channel
modulation length. The parameter 3 is positive for a p-channel device and negative for an n-
channel device. Its typical magnitude is 100 V. 3 is analogous to the Early voltage 4 of bipolar
transistors.

The trans-conductance is the slope of the transfer characteristic ( versus ) and is defined as
the change in the drain current corresponding to a change in the gate-to-source voltage. It is
expressed by
5
'( = ⃒" # 78)9% :9
5
Assuming ≈ , ≈ , and ≈ , the small-signal trans-conductance of an NMOS is
given by
;.
'( = ;" = 2>9 − = '() ?1 − <#
A for enhancement MOSFETs (4.5)
<# @
where '() = −2>9 (4.6)
The small-signal trans-conductance of a depletion MOSFET is given by
;. "<#
'( = = 2>9 B − C = '() D1 − F for depletion MOSFETs (4.7)
;"<# E

where '() = −2>9 = −2 ⁄ (4.8)

'() is the trans-conductance corresponding to = 0, and it varies linearly with , as shown
in Figure 4.9. For = 0, the device is cut off; thus it is never operated with a value of '() . The
pinchdown voltage can be determined experimentally by plotting '( versus and then
extrapolating to the -axis. This is a very useful method for determining and for a
MOSFET.

Figure 4.9 Variation of gm with for MOSFETs

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4.2.3 PSpice Models

The symbol for a MOSFET is M. The statements have the following general forms:
M<name> ND NG NS NB MMOD for MOSFETs
where ND, NG, NS, and NB are the drain, gate, source, and bulk (or substrate) nodes,
respectively. MMOD is the model name. The model statement has the following general forms:
.MODEL MMOD NMOS (P1=A1 P2=A2 P3=A3 ...PN=AN) for n-channel MOSFETs
.MODEL MMOD PMOS (P1=A1 P2=A2 P3=A3 ...PN=AN) for p-channel MOSFETs
Here NMOS and PMOS are the type symbols for n-channel and p-channel MOSFETs,
respectively; and P1, P2, . . . , PN and A1, A2, . . . , AN are the parameters and their values,
respectively.

Consider the NMOS of type 2N4351, whose parameters are = 1 GH 5 , and '( = 1 JK⁄
at = 2 JK and at = 10 . Taking the geometric mean value, we get = √1 × 5 =
2.24 , which is specified in PSpice/SPICE by PQ = 2.24 . The constant >9 can be found
from the following equations:
= >9 − R

'( = 2>9 −
These equations can be written in the form of a ratio as
'(R
4 >9R − R
4>9
= =
>9 − R 1
which, for '( = 1 JK⁄ and = 2 JK, gives >9 = 125 *K⁄ R . The ratio S ⁄T can be found
as
S 2>9 2 × 125 × 10WX
= = = 11.8
T *: U)V 600 × 3.54 × 10W[
Assume T = 10 *J; then S = 118 *J. Also assume | 3 | = 1⁄2 = 200 and 2 = 5 J W+.
Then NMOS 2N4351 can be specified in PSpice/SPICE by the following statements:
M1 ND NG NS NB M2N4351
.MODEL M2N4351 NMOS (KP=125U VTO=2.24 L=10U W=118U LAMBDA=5M)
The MOS transistor has a length of 0.6 *J at minimum and can be expanded by integer
increments of 0.3 *J. The minimum width is 0.9 *J and can be expanded by integer increments
of 0.3 *J. Generally, attributes of an NMOS are T = 6 GH 10 *J, S = 118 *J, K^ =
720 GH 283.2 *J, K` = 720 *J, a^ = 302.4 GH 120.4 *J, and a` = 302.4 GH 120.4 *J.
Generally, K` = K^ = 2.4 *J × S , and a` = a^ = 2.4 *J + S .

Example 7.1: Finding the small-signal parameters of an NMOS amplifier

The amplifier in Figure 4.6(a) has = 2 , = 15 , and = 3.5 bc. The NMOS
parameters are = 1 , >9 = 3.25 JK⁄ , and 3 = 1⁄2 = 100 .
R

(a) Find the DC biasing point , , and .

(b) Find the small-signal transistor model parameters ) and '(
(c) Find the small-signal amplifier parameters . , ) , and K")

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(d) Use PSpice to plot the small-signal AC output voltage for 1-mV sinusoidal input signal at
1 kHz. The NMOS parameters are >a = 6.5d, PQ = 1 , T = 1f, S = 1f, and
TKdg^K = 0.01. Note: PSpice uses > = >( = 2>9 .
Solution
a >( = > = 6.5 × 10Wi for S = T.
= >9 − R
= 3.25 × 10Wi 2 − 1 = 3.25 JK
= − = 15 − 3.5 × 10i × 3.25 × 10Wi = 3.625
b ) = 3 ⁄ = 100⁄ 3.25 × 10Wi = 30.77 bc
'( = 2 × >9 − = 2 × 3.25 × 10Wi × 2 − 1 = 6.5 JK⁄
c ) = ) ‖ =m30.77b‖3.5b = 3.143 bc m
n() = '( = 6.5 JK⁄
K") = −'( × ) = −6.5 JK⁄ × 3.143 bc = −20.426 ⁄
d Figure 4.10(a) shows the PSpice schematic and the PSpice plot for small-signal output
voltage is shown in Figure 4.10(b). The capacitor UR blocks the DC and passes the small-
signal output, which shows a voltage of -19.84; this is close to the calculated value of -20.42.

Figure 4.10 (a) PSpice schematic (b) plot of small-signal output voltage for example 4.1

4.3 Design and simulation of CMOS inverter

Complementary, or CMOS, circuits use both n-channel and p-channel enhancement-type
MOSFETs in the same circuit. Because of their very low power consumption, CMOS circuits are
commonly used in ICs. A CMOS inverter is shown in Figure 4.11(a). Transistor MP is a p-channel
device, and transistor MN is an n-channel device. Each substrate is tied to its source. The input
signal is connected to both transistor gates, and the output terminal is common to both drain
terminals. The load characteristics of two CMOS devices are shown in Figure 4.11(b) for two
extreme inputs: / = 0 and / = . For / = 0, MN is off and its drain current is zero. MP has
the characteristic corresponding to = . For / = , MP is off and its drain current is
zero. MN has the characteristic corresponding to = . Thus, their drain currents are zero at
these inputs, and the current drawn from the supply is zero.

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Figure 4.11 CMOS inverter

As the input voltage / is varied from zero to the maximum value VDD, the output voltage vO falls
from VDD to zero. The transfer characteristic is shown in Figure 4.11(c). Depending on the input
voltage / , the VTC can be divided into five regions.

In region I, 0 ≤ / ≤ , where is the threshold voltage of transistor MN. Since = /<

, MN remains off. At a low value of / , = − / is high and positive. MP is turned on,
and it is driven into the non-saturation (ohmic) region. Since the channel resistance of the off-
transistor MN is very much greater than that of the on-transistor MP and since MN and MP form a
voltage divider, the output voltage is p ≈ , as shown in Figure 4.11(c). The various voltages
are = /, =− + / , and p = .

In region II, ≤ / ≤ 3 = / G q 1 and = − + / < , where is the

threshold voltage of transistor MP and / G q 1 will be defined below. As / becomes greater
than or equal to , MN conducts and operates in the saturation region, for which is
described by < = / < + .

For < , MP remains in the ohmic region. With MN in the saturation region and MP in the
ohmic region, the two drain currents must be equal; that is, = . Applying the expressions
for the saturation and ohmic regions gives
>9 − R
= > r2 + − R s
where >9 and > are the constants for n-type and p-type transistors, respectively.
Substituting = /, = − / , and = − p into the above equation, we get
the relationship between / and p as
>9 / − R
= > r2 − /+ − p − − p Rs (4.9)
/t can be found by differentiating Eq. (4.9) and setting u p ⁄u / = −1 to solve for / = /t . If vI
is increased further, increases and decreases. Both MN and MP operate in the saturation
region. At the transition point from the ohmic to the saturation region for MP, we get
= −
Substituting the values for = − / and = − p , we get

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− /= − p−
which gives the input voltage at the first transition as
/ G q 1 = / = p +
The corresponding output voltage is
p G q 1 = p = / −
whose plot is a straight line that intercepts the output axis at − (a positive quantity), as shown
in Figure 4.11(c). The intersection with the transfer characteristic gives / G q 1 and
p G q 1 . To solve for the value of / G q 1 or p G q 1 , one of these quantities must be
known.
In region III, / = / G q 1 . Both MN and MP operate in the saturation region. Since the two
drain currents must be equal, = , or
>9 − R
=> + R

Substituting = / and = − / , we get the input voltage at the transition of MP from

the ohmic to the saturation region:
@v @w xyz ⁄yE
@w {y|
/ G q 1 = 3 = = @v
+ {y|
(4.10)
+ xyz ⁄yE

which is independent of output voltage p. For identical transistors, >9 = > and =| |, and
Eq. (4.10) is reduced to
/ G q 1 = 3 = (4.11)
R
which is desirable to maximize the noise immunity of the circuit. Once we determine the value of
/ G q 1 from Eq. (4.11), we can find the output voltage at the edge of the transition of MP from
p G q 1 = p = / G q 1 −
This segment ends when MN enters the ohmic region, which is defined by
= +
Substituting = / and = p into the preceding equation yields
/ = p +
which gives the input voltage at the transition of MN from the saturation region to the ohmic
region as
/ G q 2 = / = p +
The corresponding output voltage is given by
p = / −
which intercepts the input axis at , as shown in Figure 4.11(c). The intersection with the
transfer characteristic gives / G q 2 and p G q 2 . Since / G q 1 is independent of p
and / = / G q 1 = / G q 2 , the quantities p G q 1 and p G q 2 must be different.
There will be two transitions: the first for MP from the ohmic region to the saturation region at an
output voltage of p = / + and then the second for MN from the saturation region to the
ohmic region at an output voltage of p G q 2 = / G q 1 − .

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In region IV, / G q 1 = / G q 2 ≤ / ≤ + . MN goes into the ohmic region, and

MP still operates in the saturation region. Since the two drain currents must be equal, = ,
which, for MP in the saturation region and MN in the ohmic region, gives
>9 r2 − − R s=> + R

Substituting = /, = p , and = − / , we can express the relationship

between p and / as
>9 r2 / − p − ps = >
R
− /+ R
(4.12)
/} can be found by differentiating Eq. (4.12) and setting u p ⁄u / = −1 to solve for / = /} .

In region V, / > + . MP is in the cutoff region, and MN is in the ohmic region. There
will be virtually no current through the transistors, and the output voltage will be zero; that is,
= = 0, p = 0

Example 4.2: Designing a CMOS inverter

Design a CMOS inverter, as shown in Figure 4.11(a), to operate at a transition voltage 3 =
2.5 . The threshold voltages are = −1 , = 1 , and > = 20 *K⁄ R . The supply
voltage is = 5 . Assume /} = p} = 5 , load capacitance Ut = 0.5 ~, and frequency
~8•€ = 5 d•‚.
(a) Find the design parameter >! = >9 ⁄> , neglecting the body effect.
(b) Calculate NML and NMH.
(c) Calculate the propagation delay G & .
(d) Calculate the delay-power product (DP).
(e) Use PSpice/SPICE to verify your results.
Solution
(a) Solving Eq. (4.10) for >! , we have
S ⁄T + − 3 R
>! = =ƒ „
S ⁄T 3 −
which, for 3 = 2.5 , gives >! = 1. Thus >9 = > = 20 *K⁄ R
(b) p} = = 5 . Then
p ,:9 + = 3 − = 2.5 + 1 = 3.5 , p ,:9 R = 3 − = 2.5 − 1 = 1.5
Substituting numerical values of , , , >9 , and > in Eq. (4.9), we get
20 / − 1 R = 20r2 5 − / − 1 5 − p − 5 − p R s ↔ /R = 14 − 8 / + 2 p + 2 / p − pR
which, at u p ⁄u / = −1, gives p = / + 2.5. Solving these two equations, we get /t = / =
2.13 at p = 4.63 .
Substituting numerical values of , , , >9 , and > in Eq. (4.12), we get
Rs
20r2 / − 1 p − p = 20 5 − / − 1 R ↔ 16 − 8 / + /R = 2 / p − 2 p − pR
which, at u p ⁄u / = −1, gives / = p + 2.5. Solving these two equations, we get /} = / =
2.88 at p = 0.38 .
At / = + = 5 − 1 = 4, MP turns off and pt = p = 0. Thus,
†dt = /t − pt = 2.13 − 0 = ‡. ˆ‰ Š, †d} = p} − /} = 5 − 2.88 = ‡. ˆ‡ Š
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(c)The inverter with a load capacitor CL has an arrangement similar to Figure 4.12. As / goes low
to pt , MN turns off immediately, and capacitor CL is charged up by the drain current .
Since MP is in saturation and pt = p = 0, the output voltage is related to the charging
current by
u p
Ut = => − / + R
uG
which, after integration between and ⁄2, gives G t} as
Ut 0.5 ~ × 5
G t} = = = ‰. ‹ˆ Œ•
2> − | | R 2 × 20 *K⁄ R × 5 − 1 R
Because of the topology of the CMOS inverter, G }t will have the same
value as G t} . Thus, the propagation time G & ≈ G t} = 3.91 Ž. In
practice, a symmetric CMOS does not occupy the minimum chip area,
and thus not all CMOS designs are symmetric. Figure 4.12 Depletion load inverter
(d) A CMOS inverter draws a negligible current (on the order of nano-amperes) from the power
supply in both high and low states. Hence, the static power dissipation is almost zero: a% : .8 =
0. This is a distinct advantage for portable CMOS equipment because standby operation of the
equipment will not discharge the battery. We have
a&•9:(.8 = •8•€ Ut R = 5 d•‚ × 0.5 ~ × 5R = 62.5 *S
so a = a% : .8 + a&•9:(.8 = 0 + 62.5 *S = 62.5 *S
Therefore, the delay-power product is
^a = a × G & = 62.5 *S × 3.91 Ž = ‘. ‡’’ “”
(e) The PSpice schematic is shown in Figure 4.13. The PSpice plot of the VTC is shown in Figure
4.14(a), which gives /t = 2.1245 (expected value is 2.13 V), /} = 2.8755 (expected
value is 2.88 V), pt = 0 (expected value is 0) at p} = 5 , and / ,:9+ = 2.5
(expected value is 2.5 V). The VTC values are very close to the hand calculations, as expected.
The transient response is shown in Figure 4.14(b), which gives G }t = 4.18 Ž and G t} =
4.255 Ž (for T = 50 *J and S = 100 *J). The transient performance, however, will
depend on the values of length (L) and width (W). A typical value of the trans-conductance
parameter for the NMOS process is *9 • ⁄G)V = 40 *K⁄ R . [Note: We can find u p ⁄u / =
−1points by plotting dv(2) in Probe.]

Figure 4.13 Pspice Schematic for example 4.2

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Figure 4.14 PSpice plots for CMOS inverter (using transistor circuit model) for Example 4.2

4.4 BJT models

The purpose of an amplifier is to convert an input signal of small amplitude into an output signal
of different amplitude while minimizing any distortion introduced by the amplifier. If the input is
a sine wave, the output should also be a sine wave. If an AC small-signal –— is superimposed on
the DC biasing voltage ˜™ at the base of the transistor, the base current ˜ will change by a small
amount – , thereby causing an amplified change 8 (≈ – times the current gain) in the collector
current š . This change will cause the operating point to move up and down along the load line
around the Q-point. Too large an AC signal, however, will drive the transistor both into the
saturation region (to the left of the š™ -axis) and into the cutoff region (to the right of the š™ -
axis). Therefore, the design and analysis of an amplifier involves two signals: a DC signal and an
AC signal. The DC analysis finds the Q-point defined by š , ˜ , and š™ . For an AC analysis, a
small-signal AC model of a BJT around the Q-point is required.

4.4.1 Linear DC Model

Linear DC models are used for determining the operating point (or Q-point) of a BJT. The B-E
junction, which is forward biased in the active region, can be represented by a forward-biased
diode, as shown in Figure 4.15(a). The C-B junction, which is reverse biased, can be represented
by an open circuit. The base current varies with the base-to-emitter voltage. The input
characteristic is replaced by a piecewise linear model with resistance RBE in series with a voltage
source ˜™ whose value ranges from 0.5 V to 0.8 V, as shown in Figure 4.15(b). The finite slope
of the output characteristic can be represented by adding an output resistor ) between the
collector and emitter terminals. For most applications, this model can be approximated by Figure
4.15(c) by assuming ˜™ = 0 and ) = ∞. It is commonly used for obtaining quick results.

Figure 4.15 Linear DC models of bipolar transistors

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Chapter 4 Microelectronic Devices & Circuits (ECEg4261) Class Notes

4.4.2 Small-Signal AC Model

Linear DC models are used for determining the Q-point; however, an AC model is used for
determining the voltage or power gain when the transistor is operated as an amplifier in the active
region. If we apply a small sinusoidal input voltage –— = ( sin ŸG while operating in the active
region, the base potential will be ˜™ = ˜™ + –— , and the corresponding base current will be
˜ = ˜ + – . The corresponding collector current will be š = š + 8 , as shown in Figure 4.16(a).
The small-signal AC resistance seen by –— will be the inverse slope of the ˜ − ˜™
characteristic at the Q-point ( ˜ , ˜™ ), as shown in Figure 4.16(b). That is, we can obtain by
differentiating ˜ :
= ¢ =m ¤¦
+ . &. / /¤
= ¤= (4.13)
,¡ "¢£ &"¤¥ : §W ).9 ¨ R©.[ (

Figure 4.16 BJT with a small-signal input voltage

If the base current ˜ swings between ˜ + – —:€ and ˜ − – —:€ , the collector current š will
swing between š + 8 —:€ and š − 8 —:€ . The C-E voltage š™ will vary accordingly from
š™ + 8— —:€ to š™ − 8— —:€ , as illustrated also in Figure 4.16(b). The small-signal collector
current 8 will depend on the small-signal AC current gain ª« , defined by
ª« = ¬ = m ® ¦
. ∆.
(4.14)
.¢ ∆.¤ : §W ).9

which may be considered approximately equal to the DC current gain ª¯ for most applications.
That is, ª¯ = ª« . We will make this assumption throughout.

The collector current can be related to the B-E voltage by trans-conductance '( , defined by
'( = " ¬ = m &"
. °± &.¤ ° /¤ / °
¦ = ² = ® = ,² (4.15)
¢£ ¤¥ : §W ).9 ¨ ¨ ¡

where the derivative is evaluated at the Q-point. The output characteristic in the active region
exhibits a finite slope representing an output resistance defined by
= " ¬ = m&" ® ¦
+ . &. /® /
= = ® for 4 >> š™ (4.16)
,- ¬£ ®¥ : §W ).9 ³ ®¥ ³

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Chapter 4 Microelectronic Devices & Circuits (ECEg4261) Class Notes

where 4 is a constant called the Early voltage whose value ranges from 100 V to 200 V,
depending on the transistor. The value of ) is large (on the order of 50 kΩ) and can be neglected
for most analyses.

Any increase in š™ will increase the width of the collector depletion layer; consequently, the
effective base width will be reduced, causing a reduction in ˜ . The decrease in ˜ due to an
increase in š™ can be modeled by a C-B resistance ´ . The value of ´ can be approximated by
´ = 10 ) ª« , which is very large compared to and ) and is not normally included in the
transistor model, especially for hand calculations.

Thus, the small-signal behavior of a transistor can be modeled by an input resistance , a base
current–dependent collector current 8 = ª« – along with an output resistance ) , and a C-B
resistance ´ . Since the C-B junction is reverse biased, ´ can be neglected by assuming ´ = ∞.
This model, shown in Figure 4.17(a), can be approximated by Figure 4.17(b). The trans-
conductance representations are shown in Figure 4.17[(c) and (d)]. If Norton’s current source is
converted to Thevenin’s voltage source, Figure 4.17(c) can be represented by Figure 4.17(e),
where *$ = '( ) . Note that the units of the model parameters in Figure 4.17(a) are different.

Figure 4.17 Small-signal AC model of a BJT

Note: is the small-signal base–emitter resistance –— . It uses the subscript µ because it is the
input resistance of the model, which looks like the symbol µ and is also known as the µ model.

4.4.3 Small-Signal Hybrid Model

The manufacturers of BJTs usually specify the common-emitter hybrid parameters corresponding
to the hybrid model shown in Figure 4.17(f). The parameters are as follows:
ℎ.— ≡ is the short-circuit input resistance (or simply the input resistance).
ℎ«— ≡ ª« is the short-circuit forward-transfer current ratio (or small-signal current gain).

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Chapter 4 Microelectronic Devices & Circuits (ECEg4261) Class Notes

ℎ,— is the open-circuit reverse-voltage ratio (or voltage-feedback ratio), which takes into account
the effect of š™ on ˜ . This ratio is very small; its value is typically 0.5 × 10W¸ . ´ represents the
effect of ℎ,— .
ℎ)— ≡ 1⁄ ) is the open-circuit output admittance (or simply the output admittance) of the C-E
junction. It is also very small; its value is typically 10WX ℧.

Often ℎ,— and ℎ)— can be omitted from a circuit model without significant loss of accuracy,
especially in hand calculations. The subscript e on the h parameters indicates that these hybrid
parameters are derived for a common-emitter configuration.

4.4.4 PSpice/SPICE Model

PSpice/SPICE generates a complex BJT model, provided a number of physical parameters are
given. The symbol for a BJT is Q, and it is described by the statement
Q<name> NC NB NE QMOD
where NC, NB, and NE are the collector, base, and emitter nodes, respectively. QMOD is the
model name, which can be up to eight characters long. The model statement for an npn transistor
has the general form
.MODEL QMOD NPN (P1=A1 P2=A2 P3=A3 .......PN=AN)
The model statement for a pnp transistor has the general form
.MODEL QMOD PNP (P1=A1 P2=A2 P3=A3 .......PN=AN)
In these model statements, NPN and PNP are the type symbols for npn and pnp transistors,
respectively. P1, P2, . . ., PN & A1, A2, . . ., AN are the parameters and their values, respectively.

As an example, let us derive two parameters, and ª¯ , for transistor Q2N2222. Reading from the
plot of ˜™ versus š on the data sheet for Q2N2222, we get ˜™ = 0.7 at š = 20 JK. Using
these values, we have
0.7
20 JK = exp D F
25.8 J
which gives = 3.295 × 10W+¸ K. The DC gain ª¯ for š = 150 JK can vary between 100 and
300. This variation is not defined, however, and can change randomly from one transistor to
another of the same type. As a working approximation, the geometric mean value is usually used;
that is, ª¯ = √100 × 300 = 173. Since the value for Early voltage is not given, let us assume that
4 = 200 . With these values of , ª¯ , and 4 , the transistor Q2N2222 can be specified in
PSpice/SPICE by the following statements:
Q1 NC NB NE QMOD
.MODEL Q2N2222 NPN (IS=3.295E-14 BF=173 VA=200)

4.5 Advantages and limitations of the simulation models

In recent years there has been much pressure placed on system designers to verify their designs
with computer simulations before committing to actual printed circuit board layouts and hardware.
Simulating complex digital designs is extremely beneficial, and very often, the prototype phase
can be eliminated entirely. The same is not true for most analog circuits. While simulation can
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Chapter 4 Microelectronic Devices & Circuits (ECEg4261) Class Notes

give a greater degree of confidence in the final design, completely bypassing the prototype phase
in high-speed/high-performance analog or mixed-signal circuit designs can be very risky. For this
reason, simulation should be accompanied with some amount of prototyping when dealing with
analog circuits.

The most popular analog circuit simulation tool is SPICE (Simulation Program with Integrated
Circuit Emphasis), which is available in multiple forms for various computer platforms. However,
to achieve meaningful simulation results, designers need accurate models of many system
components. The most critical of these are realistic models for integrated circuits.

For analog applications, a distinction is usually made between a behavioral model and a
macromodel. A macromodel is composed of components and elements. Sometimes these
components are blocks of circuitry or function blocks. A macromodel is made by combining
models of the individual components or elements. The components in turn can be other
macromodels, behavioral models, or a combination of them. We can then say that we can model
and simulate the internal behavior of macromodels. In contrast the behavioral model is concerned
with the behavior presented to the outside world at the input-output ports of a component.

Digital components have an abstracted model that describes their logic functions. But that does not
describe their electrical analog I/O performance. The IBIS behavioral model is used to model the
analog behavior of digital parts. However, this too simplistic distinction does not always describe
the interactions between digital and analog. First, consider that the analog performance of a digital
circuit affects its digital logic performance. Second, logic functions are now used to control analog
switching behavior.

As the simulation conditions and the model data approach a true reflection of the actual
conditions, the accuracy of a measured behavioral model can approach or even exceed that of a
physical SPICE model. This statement is especially true if too little care was exercised in
generating the SPICE model. It is also true when the SPICE model is used outside of its
assumptions and limitations.

A behavioral model becomes inaccurate when bias conditions, temperature, voltage, and
frequency differ significantly from model measurement conditions for the application being
simulated. Many behavioral models do not account for variables like temperature and voltage that
change the behavior.

Measurement is usually taken as the most accurate data. But, be careful in such judgments. There
is no question that measurement is used to catch modeling and manufacturing mistakes or verify
that everything is as expected. But measurement, especially high-speed Signal Integrity and
RF/EMI measurements can be full of mistakes. Performing them is a science in itself
Measurement should verify that the design came out as intended. If environmental factors (like
temperature or EMI, or the statistical variations of components and boards) are not appropriately
accounted for, it's trusting in luck that the simulation or the measurements will be correct.

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By Hailay Berihu (M.Sc.)