DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

CHAPTER 1
INTRODUCTION

Demand for usage of batter based portable electronic system is increasing day by
day as the devices are portable they need battery for driving them so power consumption
and speed becomes the main concern in designing of devices such as laptops, tablets,
mobile phones, notebooks, and many other personal communication devices. the power
consumption leads to more heating which results in decreasing battery life and also needs
cooling fan to cool the circuitry. therefore power consumption affects the battery life and
the cost of the hole system. mostly all digital communication devices and the devices
about which we have discussed above are used in the applications like digital signal
processing, image and video processing, microcontroller and this applications uses
various arithmetic and logic operation to perform additions, addition is one of the
fundamental arithmetic operations and is used extensively in many VLSI systems. in
addition to its main task, that is adding two binary numbers is the nucleus of the many
different applicable operations like subtraction, multiplications, divisions, address
calculations, etc...
That's why enhancing the performance of the one bit full adder cell is taken into
account of a major goal.

1.2 SCOPE

The full adder circuit is functional basic building block and most critical
component of arithmetic circuit like microprocessor, digital signal processor or any
ALU's. Almost every complex computational circuit requires a full adder circuit. The
entire computational block and power consumption can be reduced by implementing the
low power techniques on full adder circuit.

In the Nanometer technology regime, leakage power as become a major

component of total power. The full adder is the basic function unit of an ALU. The power
consumption of a processor is reduced by lowering the power consumption of an ALU.
And power consumption of an ALU can be reduced by lowering the power consumption
of full adder. So the full adder design and analysis with low power characteristic are
becoming more popular in these days. Our project is helping to illustrate the design of the
low power and less transistor full adder design using cadence virtuoso environment in
180nm technology.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 1

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

1.3 OBJECTIVE

 To reduce the number of transistors in the circuit.

 To analyze the power losses in the circuit.

1.4 PROBLEM DEFINITION

In the Nanometer technology regime, leakage power as become a major

component of total power. The full adder is the basic function unit of an ALU. The power
consumption of a processor is reduced by lowering the power consumption of an ALU.
And power consumption of an ALU can be reduced by lowering the power consumption
of full adder. So the full adder design and analysis with low power characteristic are
becoming more popular in these days. Our project is helping to illustrate the design of the
low power and less transistor full adder design using cadence virtuoso environment in
180nm technology.

1.5 METHODOLOGY

The basic design flow of an analog IC design, together with the Cadence tools
required in each step.
First, a schematic view of the circuit is created using the Cadence Virtuoso
Schematic Editor. Alternatively, a text netlist input can be employed.
Then, the circuit is simulated using the Cadence Affirma analog simulation
environment. Different simulators can be employed, some sold with the Cadence software
(e.g., Spectre).
Once circuit specifications are fulfilled in simulation, the circuit layout is created
using the Virtuoso Layout Editor.
The resulting layout must verify some geometric rules dependent on the
technology (design rules). For enforcing it, a Design Rule Check (DRC) is performed.
Optionally, some electrical errors (e.g. shorts) can also be detected using an Electrical
Rule Check (ERC). Then, the layout should be compared to the circuit schematic to
ensure that the intended functionality is implemented. This can be done with a Layout
Versus Schematic (LVS) check. All these verification tools are included in the Assura
software in Cadence. Finally, a netlist including all layout parasitics should be extracted,
and a final simulation of this netlist should be made. This is called a Post-Layout
simulation, and is performed with the same Cadence simulation tools.

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 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

1.5.1 FLOWCHART

Specification

Schematic Entry Virtuoso

Simulation Spectre

ok

Layout Design Virtuoso

Layout verification Assura

ok

Post-Layout Simulation Spectre

ok

Format conversion(GDSII)

Fabrication

Measurements

Figure 1. Analog IC design flow and Cadence tools involved

1.6 SOFTWARE REQUIRED

 Cadence Virtuoso Tool

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 3

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

CHAPTER 2

LITRATURE SURVEY

[1] A. Benjamin Franklin, T. Sasilatha."Design and Analysis of low power Full Adder
for Portable and Wearable Applications." International Journal of Recent
Technology and Engineering , volume-7, Issue-5s3, ISSN:2277-3878, Feb 2019.

There are standard implementations with various logic style that have been used in the
past to design full adder cells like CPL,( complimentary past-transistor logic) which uses
32 transistors, CPL produces several intermediate nodes and there compliment to form
the outputs. another adder. the complementary CMOS full adder(C-CMOS) is based on a
regular CMOS structure with conventional pull-up and pull-down transistors and has 28
transistors. the input capacitance of a static CMOS gate is large because each input is
connected to the gate of at least a pmos and nmos device. this design does not uses
compliment of input signals and therefore the short circuit current is reduced and the most
important advantage of this circuit is it produces full output voltage swing, thus this
circuit has high noise margin that is why it is reliable to operate at the low voltages.

[2] Aneela Achu Mathew, Sreesh P R."Comparative Analysis Of Full Adder Circuits."
material science and engineering, DOI:10.1088, Jan 2018.

In this paper comparison of full adder circuits is analyzed, full adder circuits are
extensively used in digital design, here different types of full adder such as conventional
CMOS, based on XOR/XNOR, past transistor logic(PTL) and gate diffusion input (GDI)
technique are done among this GDI technique take less number of transistor and therefore
consumes less power in GDI 14T, 12T which is based on mux and proposed 10T is
implemented, the better power consumption is obtained for 10T compared with 12T,
SIMULATION RESULT ARE obtained in 180nm technology using mentor graphics
tool, this proposed full adder widely used in DSPs, as ASICs and multipliers.

[3] K.Paramasivam, Suresh Kumar N. "Design and Analysis of Low Power Full
Adder using 65nm Technology."International Journal of Recent Technology and
Engineering, Volume-7, Issue-4S, ISSN:2277-3878, Nov 2018.

This paper deals with low-power full adder taking merits of existing full-adders.the
proposed one-bit full adder has least power consumption. the proposed adder compared
and then analyzed average power, area and max power with existing full adder. the

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 4

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

designs have been simulated shown results using tanner EDA tool. the proposed low-
power full adder in ALU has good performance in terms of average-power and maximum
power reduction compared with classical full-adder. this approach archives high power
minimization.

[4] Omnia A. Badry, M.A. Abdelghany."Low Power 1-Bit Adder Using Full-Swing
Gate Diffusion Input Technique." International Conference On Innovative Trends In
Computer Engineering (ITCE), Dec 2018.

This paper presents a design which provides full swing output for logic 1 and logic 0 for
full adder cell and reduces power consumption, delay, and area. in this design full adder
consists of two XOR gate cells and one cell of 2*1 multiplexer (MUX). the performance
of the proposed design compared with the different logic style for full adders through
cadence virtuoso simulation based on TSMC models with a supply voltage of 1v and
frequency 125Mhz. the simulation results showed that the proposed full adder design
dissipates low power, while improving delay and area among all the design taken for
comparison.

[5] Sathaporn Lueangsongchai, Siraphop Tooprakai," Design high speed and low
power hybrid full adder circuit." International Symposium on Communications and
Information Technologies (ISCIT), DOI: 10.1109/ISCIT.2018.8587979, Sept 2018.

This paper presents 1-bit hybrid full adder cells circuit scheme that high speed and low
power consumption. This Full adder cells circuit is designed utilization of XOR gate,
XNOR gate, pass logic gate and transmission gate. Result of simulation by HSPICE
program based on 16 nm CMOS technology with 0.9V power supply voltage and
maximum frequency at 8GHz.in this paper we get know about that different circuit
having the variation in speed and power consumption and also the capacity also being
compared.

[6] Anjali Arora, Vandana Niranjan, "A New 16-bit High Speed and Variable Stage
Carry Skip Adder" Computational Intelligence & Communication Technology
(CICT), DOI: 10.1109/CIACT.2017.7977359, Feb 2017.

In this paper, fixed stage and variable stage carry skip adder configurations have been
analyzed and then a new 16-bit high speed variable stage carry skip adder is proposed by
modifying the existing structure. The proposed adder has seven stages where first and last
stage are of 1 bit each, it keeps increasing steadily till the middle stage which is the

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 5

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

bulkiest and hence is the nucleus stage. The delay and power consumption in the
proposed adder is reduced by 61.75% and 8% respectively. The proposed adder is
implemented and simulated using 90 nm CMOS technology in Cadence Virtuoso. It is
pertinent to mention that the delay improvement in the proposed adder has been achieved
without increase in any power consumption and circuit complexity. The adder proposed
in this work is suitable for high speed and low power VLSI based arithmetic circuits.

[7] Ashish Kumar Yadav, Bhavana P.Shrivatva,Ajay Kumar Dadoriya. "Low Power
High Speed 1-Bit Fill Adder Circuit Design at 45nm CMOS Technology." IEEE
Journal Of Recent Innovations Is Signal Processing And Embedded Systems(RISE).
ISBN:978-1-5090-4760, Oct 2017.

Till now in digital world different types of full adder cells are designed with different
logic styles. some of them are good for low power applications, some of them for high
speed according to requirement of applications using static energy recovery full adder
cell(SERF) requires ten transistors(10-T) to implement it can be implemented by using
XOR or XNOR gates implementation of SERF with the help of XOR gates. to produce
sum output it uses two cascaded XOR gates. gate diffusion input full adder cell(GDI)
consists of two XOR/XNOR gates, GDI full adder cell requires ten transistor, which is
very less in number as compared to conventional CMOS design and the speed is also
more as compared conventional CMOS design.

[8] Manoj Kumar, R.K Baghel “Ultra Low-Power High-Speed Single-Bit Hybrid Full
Adder Circuit.” Institute of Electrical and Electronics Engineers (IEEE), July 2017.

In this paper a low power hybrid 1-bit full adder circuit is designed and extended for 4 bit
ripple carry adder (RCA). A new XNOR logic is designed using complimentary metal-
oxide semiconductor (CMOS) logic and Pass transistor logic. CMOS weak inverters
improve the power consumption while pass transistors overcome voltage degradation
problem. Carry logic is designed using transmission gates which reduces the carry
propagation path. A 4-Bit RCA is also designed using the proposed single bit full adder.
The proposed full adder and RCA are designed in 180nm technology and post layout
simulations are done using Cadence Virtuoso. Power, delay, power delay product (PDP)
and area are performance parameters of the proposed full adder which are calculated
using umc technology.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 6

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

[9] Shailesh Dwivedi, Dr. Kavita Khare, Ajay Kumar Dadoria, ”Low-Power high
Speed 1-bit Full Adder Circuit Design.” Association for Computing Machinery
(ACM), March 2016.

In this paper, they presented a new 13T full adder design based on hybrid-CMOS logic
design style. Adders are one of the most basic building blocks in digital components
present in the Arithmetic Logic Unit (ALU). The performance of an adder have a
significant impact on the overall performance of a digital system. The new design is
compared with some existing designs for power consumption, delay, PDP at various
frequencies. the simulations are carried out on Cadence Virtuoso at 180nm CMOS
technology, Maximum saving of power delay product is at low frequency by proposed
circuit is 96.8% with respect to C-CMOS and significant improvement is observed at
other frequencies also.

[10] P. Kiran Kumar, P. Srikanth," Design of Low Power High Speed Hybrid Full
Adder." International Journal of electronics & communication technology IJECT
vol:6, Issue 4 ,ISSN : 2230-7109, Dec 2015.

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate
logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The
design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit
Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm
technology. The performance parameters such as delay, area, total power dissipation and
power delay product (PDP) were compared with the existing designs such as
Conventional CMOS full adder (CMOS), In comparison with the previous full adder
designs, the hybrid adder offers significant improvement in terms of power, area and
speed.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 7

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

CHAPTER 3

EXPECTED OUTCOME

 Number of transistors has to be reduce.

 Analyze the power and delay for different number of transistors.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 8

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

REFERENCES

[1] A. Benjamin Franklin, T. Sasilatha."Design and Analysis of low power Full Adder
for Portable and Wearable Applications." International Journal of Recent
Technology and Engineering , volume-7, Issue-5s3, ISSN:2277-3878, Feb 2019.

[2] Aneela Achu Mathew, Sreesh P R."Comparative Analysis Of Full Adder Circuits."
material science and engineering, DOI:10.1088, Jan 2018.

[3] K.Paramasivam, Suresh Kumar N. "Design and Analysis of Low Power Full
Adder using 65nm Technology."International Journal of Recent Technology and
Engineering, Volume-7, Issue-4S, ISSN:2277-3878, Nov 2018.

[4] Omnia A. Badry, M.A. Abdelghany."Low Power 1-Bit Adder Using Full-Swing
Gate Diffusion Input Technique." International Conference On Innovative Trends In
Computer Engineering (ITCE), Dec 2018.

[5] Sathaporn Lueangsongchai, Siraphop Tooprakai," Design high speed and low
power hybrid full adder circuit." International Symposium on Communications and
Information Technologies (ISCIT), DOI: 10.1109/ISCIT.2018.8587979, Sept 2018.

[6] Anjali Arora, Vandana Niranjan, "A New 16-bit High Speed and Variable Stage
Carry Skip Adder" Computational Intelligence & Communication Technology
(CICT), DOI: 10.1109/CIACT.2017.7977359, Feb 2017.

[7] Ashish Kumar Yadav, Bhavana P.Shrivatva,Ajay Kumar Dadoriya. "Low Power
High Speed 1-Bit Fill Adder Circuit Design at 45nm CMOS Technology." IEEE
Journal Of Recent Innovations Is Signal Processing And Embedded Systems(RISE).
ISBN:978-1-5090-4760, Oct 2017.

[8] Manoj Kumar, R.K Baghel “Ultra Low-Power High-Speed Single-Bit Hybrid Full
Adder Circuit.” Institute of Electrical and Electronics Engineers (IEEE), July 2017.

[9] Shailesh Dwivedi, Dr. Kavita Khare, Ajay Kumar Dadoria, ”Low-Power high
Speed 1-bit Full Adder Circuit Design.” Association for Computing Machinery
(ACM), March 2016.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA 9

 DESIGN AND ANALYSIS OF FULL ADDER USING CADENCE VIRTUOSO PLATFORM

[10] P. Kiran Kumar, P. Srikanth," Design of Low Power High Speed Hybrid Full
Adder." International Journal of electronics & communication technology IJECT
vol:6, Issue 4 ,ISSN : 2230-7109, Dec 2015.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING, BCE, SHRAVANABELAGOLA

10