Motorola w208

W208
Level 3
Circuit Description
22 September 2006
V1.0
W208 Level 3 Circuit Description
Index
1 Receive .................................................................................................... 4
1.1 Band selection........................................................................................... 4
1.2 Demodulation............................................................................................ 5
1.3 Audio Codec.............................................................................................. 6
1.3.1 Voice Downlink Patch..................................................................................................7
1.4 Earpiece Receiver ...................................................................................... 7
1.5 Headset .................................................................................................... 7
1.6 Speaker Phone .......................................................................................... 7
1.7 Data Download Receive Path ...................................................................... 8
2 Transmit .................................................................................................. 8
2.1 Audio (Voice uplink Patch).......................................................................... 9
2.2 Data Download Transmit Path .................................................................... 9
2.3 Stereo Audio Path...................................................................................... 9
2.4 Modulation................................................................................................................... 10
2.5 RF TX PA ............................................................................................... 12
2.6 TX PA Power Control in SKY77318 .......................................................... 13
3 Triton-Lite Monitoring ADC ....................................................................14
4 Baseband Serial Port (BSP) ....................................................................15
5 Microcontroller Serial Port (USP) ...........................................................15
6 General purposes I/O (GPIO).................................................................15
7 TFT LCD Display......................................................................................17

7.1 Display Backlights.................................................................................... 18
8 32kHz RTC ..............................................................................................18
9 SIM Card Circuit .....................................................................................18

9.1 SIM Card Supply Voltage Generation ......................................................... 18
10 Keypad....................................................................................................19
10.1 Keypad Matrix ......................................................................................... 19
11 Vibrator circuit .......................................................................................20
12 Memory ..................................................................................................20
13 Power .....................................................................................................21
Service Engineering & Optimization
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13.1 Low-Dropout Voltage Regulators............................................................... 21
13.2 Power Down Methods .............................................................................. 22
14 Sleep Module ..........................................................................................22

14.1 Sleep Up Sequence.................................................................................. 23
14.2 Sleep off Sequence .................................................................................. 23
15 Power Tree .............................................................................................24
16 Charging Circuit and External Power .....................................................24

16.1 Battery Support ....................................................................................... 24
16.2 Charger Support...................................................................................... 24

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1 Receive
1.1 Band selection

The radio frequency signal is received from internal PIFA-type antenna. Received
GSM RF signal enters to PCB through the RF switch JP201. At this moment the T/R switch
SW201 is switched to RX mode to let the signal input to next stage. Then the signal goes
into SAW filter, BF201 and BF202 , which reject out-band signal and transfer the signal
from single-end to balanced. And the matching circuits between T/R switch and SAW
filter reduce the unwanted RF signal reflection and provide a flat frequency response in the
operation band. Finally the received signal will fed into Locosto Plus U101 DRP core
through a balanced MLCC matching network. The following table describes the control
voltages of T/R switch and PA:
SW_LO_TX SW_HI_TX VAPC
PA_EN BS1
W375 EU PIN 5 PIN 2 PIN 20
TP201 TP202
of T201 of T201 of U201
Standby Low x Low Low x
RX EGSM900 Low Low Low Low Low
RX DCS1800 Low Low Low Low High
TX GSM900 High High High High Low
TX DCS1800 High High High High High
The RF signal is received by internal antenna or by RF plug, and the signal is passing
through the RF switch JP201 and then fed into T/R switch. The low band (GSM900) RX
received signal is transmitted from SW201 (Pin 11) and input to low-band SAW filter
BF201, while the high band (DCS1800) RX received signal from SW201 (Pin 1) and then
input to high-band SAW filter BF202. The last stage of RX on PCB is Locosto U101
(Loocsto-Plus), and the DRP process will make the signal into binary data.
Figure 1: Locosto TX/RX Paths Description

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1.2 Locosto RX Mode
Figure 2: Locosto RX Signal Process
As described in Figure 2, when the RF signal is input to Locosto, it will be amplified by

a differential LNA in advance, in order to obtain a better NF in the last receiving stage.
And then it will be turned into discrete IF signal by a high-speed mixer. After passing
through a filter and an A/D converter, the discrete signal will become digital signal and
then input to Locosto core to do DSP process. The detail RX signal route is depicted as
below:

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Figure 3: Baseband Downlink Block Diagram
Figure 3: Audio Codec Block Diagram
1.3 Audio Codec

The Audio codec consist of a voice codec dedicated to GSM application and an audio stereo
line. The voice codec circuitry processes analog audio components in the uplink path and
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applies this signal to the voice signal interface for eventual baseband modulation. In the
downlink path, the codec circuitry changes voice component data received from the voice
serial interface into analog audio. The voice codec support an 8/16 kHz sampling
frequency. The stereo audio path converts audio component data received from the I2S
serial interface into analog audio. The following paragraphs describe these
uplink/downlink and audio stereo functions in more details.
1.3.1 Voice Downlink Patch

The VDL path receives speech samples at the rate of 8 kHz from the Locosto-Plus IC U101
(DSP) via the VSP and converts them to analog signals to drive the external speech
transducer.
The digital speech coming from the Locosto-Plus IC U101 (DSP) is first fed to a speech
digital filter that has two functions. The first function is to interpolate the input signal and
to increase the sampling rate from 8 kHz up to 40 kHz to allow the digital-to-analog
conversion to be performed by an over-sampling digital modulator. The second function is
to band-limit the speech signal with both low-pass and high-pass transfer functions. The
filter, the PGA gain, and the volume gain can be bypassed by programming.
The interpolated and band-limited signal is fed to a second order Σ-∆ digital modulator
sampled at 1 MHz to generate a 4-bit (9 levels) over-sampled signal. This signal is then
passed through a dynamic element-matching block and then to a 4-bit digital-to-analog
converter (DAC).
Due to the over-sampling conversion, the analog signal obtained at the output of the 4–bit
DAC is mixed with a high frequency noise. Because a 4–bit digital output is used, a
first–order RC filter (included in the output stage) is enough to filter this noise.
The volume control and the programmable gain are performed in the TX digital filter.
Volume control is performed in steps of 6 dB from 0 dB to -24 dB. In mute state,
attenuation is higher than 40 dB. A fine adjustment of gain is possible from -6 dB to +6 dB
in 1–dB steps to calibrate the system depending on the earphone characteristics. The
earphone amplifier provides a full differential signal on the terminals EARP Triton-Lite Pin
J2 and EARN Triton-Lite Pin H2. The 8Ohm speaker amplifier provides a differential
signal on the terminals SPKP Triton-Lite Pin L6, K6 and SPKN Triton-Lite Pin M6, M7.
1.4 Earpiece Receiver

The Receiver J10 is connected to EARP Triton-Lite Pin J2 and EARN Triton-Lite Pin H2.
1.5 Headset
The headset uses a standard 2.5mm phone jack. The headset circuit contains analog
switches (U602 and U605), which are normally switched to receiver earpiece after power
on. When system turns on, the signal HS_EN (U101 Pin T3) are applied. When earphone
plug in, the phone will detect this action and make an appropriate response to answer a
call while incoming call occur. The interrupt for the headphones is detected on the
HS_DETECT (U101 Pin C6) line from Pin 6 of Headset Jack J602. This signal will be
pulled to high when the headset is connected.
1.6 Speaker Phone

When the handset set the hand-free mode, the Triton-Lite will switch from EARP/EARN
to SPKP/SPKN trace and receiver signal will be through Audio amplifier U601 to Speaker.

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1.7 Data Download Receive Path
The External download cable is connected to the Earphone Jack J602, the headset
connector of the mobile phone. The download path is routed from J602 Pin 2 via U602
Pin 1 and U607 Pin C1 to RX_Modem. The RX_Modem signal connects to
Locosto-Plus IC U101 Pin L7 to provide this capability. When software is set to download
mode, the signal HS_EN (U101 Pin T3) is applied high, the phone will entered to
download state till download cable pulls out.
Figure 4: Voice Codec Downlink Patch
2 Transmit
2.1 Audio (Voice uplink Patch)

The VUL path includes two input stages. The first stage is a microphone amplifier,
compatible with electric microphones containing a FET buffer with open drain output. The
microphone amplifier has a gain of typically 25.6 dB (±1 dB) and provides an external
voltage of 2.5V to bias the microphone (HS_BIAS Locosto-Plus Pin K8).
The auxiliary audio input can be used as an alternative source for higher-level speech
signals. This stage performs single-ended conversion and provides a programmable gain
of 4.6 dB or 28.2 dB. The third stage is a headset microphone amplifier, compatible with
electric microphones. The headset microphone amplifier has a gain of typically 18 dB and
provides an external voltage of 2.0V or 2.5V to bias the headset microphone (HS_BIAS
Locosto-Plus Pin K8). When one of the input stages (HSMIC) is in use, the other input
stages are disabled and powered down.
The resulting fully differential signal is fed to the analog-to-digital converter (ADC). The
ADC conversion slope depends on the value of the internal voltage reference.
Analog-to-digital conversion is performed by a third-order Σ-∆ modulator with a sampling
rate of 1 MHz. Output of the ADC is fed to a speech digital filter, which performs the
decimation down to 8 kHz and band-limits the signal with both low-pass and high-pass
transfer functions. Programmable gain can be set digitally from –12 dB to +12 dB in 1-dB
steps. The speech samples are then transmitted to the Locosto-Plus IC U101 via the VSP
at a rate of 8 kHz. There are 15 meaningful output bits.
Programmable functions of the VUL path, power-up, input selection, and gain are
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controlled by the Baseband serial port (BSP) or the MCU serial port (USP) via the serial
interfaces. The VUL path can be powered down by Program.
Figure 5: Voice Uplink Paths
2.2 Data Download Transmit Path

The External download cable is connected to the Earphone Jack J602 Pin 3, the headset
connector of the mobile phone. The download path is routed from J602 Pin 3 via U605
Pin 1 and U608 (Level shifter) Pin C2 to TX_Modem. The TX_Modem signal connects
to Locosto-Plus IC U101 Pin P3 to provide this capability. When software is set to
download mode, the signal HS_EN (U101 Pin T3) is applied low, the phone will entered to
download state till download cable pull out.
2.3 Stereo Audio Path

The stereo audio path receives Left and right signal samples at the rate of a programmable
frequency, from 8kHz to 48kHz, via the I2S serial interface and converts them to analog
signals to drive the external audio signal or speech transducers.
The digital audio signal is first fed to an audio digital filter that has two functions. The first
function is to interpolate the input signal and to increase the sampling rate to allow the
digital–to–analog conversion to be performed by an over-sampling digital modulator. The
second function is to band–limit the audio signal with a low–pass transfer functions. The
interpolated and band–limited signal is fed to a second order Σ-∆ digital modulator
sampled at fS1 frequency to generate a 4–bit (9 levels) over-sampled signal. This signal is
then passed through a dynamic element matching block and then to a 4–bit
digital–to–analog converter (DAC).
Due to the over-sampling conversion, the analog signal obtained at the output of the 4–bit
DAC is mixed with a high frequency noise. Because a 4–bit digital output is used, a
first–order RC filter (included in the output stage) is enough to filter this noise.
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The volume control is performed in the audio digital filter. Volume control is performed in
steps of 1 dB from 0 dB to -30 dB. In mute state, attenuation is higher than 40 dB. The
gain is independently programmable on the Left and Right channels, using the same
register VAUSCTRL. A common adjustment of gain is possible at 0dB or +6dB. A digital
Left/Right summer and 6dB attenuator allows output of a mono audio path. These
configurations are programmed with the register VAUDCTRL.
The Left and right head set amplifiers provide the stereo signal on terminals HSOL (U103
Pin G1) and HSOR (U103 Pin F1). The mono audio signal may be provided on the Right
or the Right and Left headset outputs. The mono audio signal may be sum to the speech
signal and provided on the Auxiliary, Earphone and/or 8Ohm Speaker outputs. The Audio
Stereo/Mono path can be powered down and configure with the PWDNG, VAUDCTRL and
VAUDPLL registers.
Figure 6: Stereo Audio Path
2.4 Modulation
As illustrated in Figure 8, GMSK 0.3 is generated with Gaussian low-pass filtered

bipolar data, applied to a DC coupled FM modulator, set to a modulation index of 0.5.
Figure 7: GMSK Modulation
2.4.1 Transmit Section

As compared with a traditional VCO, TI takes advantage of DCO scheme to design the
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main TX oscillator in Locosto. DCO stands for “digitally controlled oscillator”, which uses
some digital switched capacitances to do frequency tuning, but it should be noticed that
the oscillator core is still analog. And Locosto DRP uses ADPLL (all digital phase lock loop)
architecture to design a digital synthesizer, and its reference frequency is provided by
26MHz DXCO. The ADPLL output signal will be pre-amplified by a digital controlled
pre-PA and then fed into PA module. The TX signals output at TXLB Locosto Plus Pin
F17 (low-band) and TXHB Locosto Plus Pin G17 (high-band).
Figure 9: Locosto Transmit Block Diagram
2.4.2 Digitally- Controlled Crystal Oscillator (DCXO)

The DCXO system comprises an external crystal Y101, DCXO core based on Colpitts
oscillator, a switching capacitor array, amplitude control loop and a current DAC. It also
includes a startup system to control the startup sequence of the bandgap reference and
the LDO voltage regulator for the DCXO that is based on a 32 KHz clock. DCXO (Digitally
Controlled Crystal Oscillator) is a digitally tunable crystal oscillator centered at 26MHz for
GSM applications with the step size of ~0.01ppm of the 26MHz. Both the amplitude and
the frequency of oscillation are digitally controllable. Figure 10 shows the top level
schematic of DCXO. Major components of DCXO includes a Colpitts oscillator core with
negative resistance, 14-bit AFC fine frequency control capacitor DAC, plus an 10-bits
coarse frequency control capacitor DAC; an 8-bit programmable current source (IDAC), a
peak detector circuit, an ADC, a digital amplitude control loop, and an output buffer.

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Figure 80: DCXO Block Diagram
The DCXO system is shown in Figure 10 including the power management. VR2 (from
Triton/Triton-Lite) is used to power this system. At the heart of the DCXO system is the
DCXO core that consists of a Colpitts oscillator with an 8-bit current DAC that can be used
to change the loop gain of the DCXO core. The oscillator frequency can be tuned by
controlling a bank of capacitors organized as an array in a very similar fashion to the
construction of D/A converters. By selecting more capacitance, the oscillator frequency
can be reduced and vice versa. The capacitors are selected by independently controlling
rows and columns of the array through a thermometer encoded row/column selection.
The smallest capacitor is dithered with first order sigma-delta modulation to achieve
fractional resolution. The output of DCXO is available to the external world through the
FREF buffer.
The system level control of DCXO basically can be separated by two categories:
Frequency control and amplitude control. Frequency control is accomplished in three
steps:
Coarse frequency control using segmented feedback capacitor inside the Colpitts
oscillator
Fine Frequency Control using 1024 unit tuning capacitors
Fractional Fine Frequency control using Sigma-Delta Dithering of FFC unit capacitor
LDOX: Because of the low phase noise requirements, DCXO is provided with its own
LDO voltage regulator (LDOX)
Oscillation Amplitude Control is accomplished by varying the current to the Colpitts Gm
transistor. This functionality is implemented using a current DAC (IDAC block)
2.5 RF TX PA
The TX signal outputs at TXLB Locosto Plus Pin F17 (low-band) and TXHB Locosto
Plus Pin G17 (high-band). The high-band signal passes through R202, and the low-band
signal passes through R201. The SKY77318 PA IC U201, has two independent paths (one
for the high-band signal and one for the low-band signal). A linear power amplifier in
each path. The SKY77318 U201 also contains band-select switch circuitry to select GSM
(logic0) or DCS/PCS (logic1) as determined from the Band Select(BS) Pin 1 signal. The
module consists of separate GSM850/900 PA and DCS1800/PCS1900 PA blocks,
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impedance-matching circuitry for 50 Ω input and output impedances, and a Power
Amplifier Control (APC SKY77318 Pin 20) block with an internal current-sense resistor.
The amplified RF output signal feeds out of SKY77318 from Pin 15 for high-band and Pin
11 for low-band. The high-band signal enters the T/R Switch SW201 Pin 3, and the
low-band signal enters the Antenna Switch U700 Pin 5. The T/R Switch provides
isolation between the various receiver and transmitter paths as they connect to the RF
switch JP201 Pin 1. For Antenna Switch settings, see Section 1.1: Band Selection.
Figure 11: Power Amplifier and Antenna Switch
2.6 TX PA Power Control in SKY77318 U201

Figure 13 shows the Integrated Power Amplifier Control (iPAC) function along with
SKY77318 proven quad-band PA architecture and BiCMOS current buffering bias scheme.
The iPAC circuitry generally operates independently of other device subcircuits and serves
to make the RF output power a predictable function of the APC SKY77318 Pin 20 (VAPC)
control voltage over variations in supply, temperature, and process. Top-level
performance specifications, with exception of those directly associated with power control
(or the range of APC control voltage), are not altered by placing the device into internal
closed loop operation with the PAENA (PAC Enable) signal. Thus, the iPAC function of the
SKY77318 can be analyzed separately from the general power amplifier performance.

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Figure 12: Skyworks 77318 Function Block Diagram
3 Triton-Lite Monitoring ADC

The monitoring section includes a 10-bit ADC and 10-bit/9-word RAM. The ADC monitors:
z Four internal analog values:
– Battery voltage (VBAT)
– Battery charger voltage (VCHG)
– Current charger (current-to-voltage (I-to-V) converter) (ICHG)
– Backup battery voltage (VBACKUP)
z Five external analog values:
– ADIN3: MODE_DETECT Triton-Lite Pin B7 for detect download cable or headset.
– ADIN4: not used
– ADIN5: BAT_TEMP Triton_Lite Pin F8 for monitor the battery temperature.
Figure 13: Baseband interface
4 Baseband Serial Port (BSP)

The baseband serial port (BSP) is a bidirectional (transmit/receive) serial port. Both
receive and transmit operations are double-buffered and permit a continuous
communication stream. Format is a 16-bit data packet with frame synchronization.
The CK13M master clock is used as a clock for both transmit and receive. The BSP allows
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read and write access of all internal registers under the arbitration of the internal bus
controller. But its transmit path is allocated to the BDL path during burst reception for I
and Q data transmissions.
5 Microcontroller Serial Port (USP)

The microcontroller serial port (USP) is a synchronous serial port. It consists of three
terminals: data transmit (MCUDI Syren Pin K3), data receive (MCUDO Syren Pin L3),
and port enable (MCUEN0 Syren Pin M2). The clock signal is the CK13M master clock.
Transfers are initiated by the external microcontroller, which pushes data into the USP via
the MCUDO, while synchronous data contained in the transmit buffer of the USP is
pushed out via the MCUDI. The USP allows read and write access of all internal registers
under the arbitration of the internal bus controller.
6 General purposes I/O (GPIO)

LOCOSTO-Plus provides 47 GPIOs in read or write mode by internal registers.
GPIO Pin Used As. Description

GPIO0 HS_HOOK Pin M6 Headset Hook
GPIO1 HS_BIAS Pin K8 Enable Headset BIAS
GPIO2 HS_EN Pin T2 Enable analog switch in data cable or headset MIC
GPIO3 USB_Boot Pin T10 Connect to R112 0Ohm PD resister
GPIO4 CDI Pin R9 Used as Stereo I/F signal
GPIO5 TSPACT8 Pin N9 Used as Triton-Lite STARTADC
GPIO6 A21 Pin F3 Used as Memory I/F A21
GPIO7 BYPASS Pin G6 Reserve as W215 Back-end IC BYPASS signal
GPIO8 KBR4 Pin F10 Used as Key board I/F KBR4
GPIO9 KBC4 Pin B12 Used as Key board I/F KBC4
GPIO10 nEMU0 Pin C11 No Use
GPIO11 nEMU1 Pin D10 No Use
GPIO12 KEY_BL Pin B11 Keypad LED enable signal
GPIO13 LCD_nCS_0 Pin E10 No Use
GPIO14 LCD_STB Pin B10 No Use
GPI015 AUDAMP_SD Pin F9 Enable Audio Amplifier shutdown pin
GPI016 LCM_ID Pin D9 LCM_ID signal
GPI017 LCD_nCS_1 Pin B9 No Use
GPI018 ND_WE Pin A6 Connect to a PU resister R119
GPI019 Pin F8 No Use
GPI020 SIM_IO Pin E7 To control transistor T703 for solving SIM initial issue
GPI021 LEDLCM_EN Pin A5 For controller the LCD Back Light Driver
GPI022 HS_DETECT Pin C6 Headset plug-in detection
GPI023 SPI_CLK Pin G9 Used as SPI I/F SPI_CLK
GPI024 SPI_SOMI Pin F7 Used as SPI I/F SPI_SOMI
GPI025 SPI_SIMO Pin C5 Used as SPI I/F SPI_SIMO
GPI026 Charging_end Pin E6 To control transistor T502

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GPI027 SPI_nCS Pin G8 Used as SPI I/F SPI_nCS
GPI028 Pin C4 No Use
GPI029 Charge_Protect Pin G7 U501 alert signal when OCP/OVP event happened
GPI030 Pin B3 Connect to a PD resister R124
GPI031 ND_WE Pin C3 No Use
GPI032 ND_CLE Pin F6 Connect to a PU resister R133
GPI033 FM_RESET Pin H8 FM IC enable pin
GPI034 ND_RnB Pin C2 Connect to a PD resister R122
GPI035 Pin F5 No Use
GPI036 Pin D2 No Use
GPI037 A23 Pin H7 Used as Memory I/F A23
GPI038 nCS0 Pin E3 Used as Memory I/F nCS0
GPI039 A22 Pin G5 Used as Memory I/F A22
GPI040 WAIT Pin M3 Used as Memory I/F WAIT
GPI041 nFADV Pin J7 Used as Memory I/F nFADV
GPI042 CKM Pin L6 Used as Memory I/F CLM
GPI043 MCSI_CK Pin N3 Connect to a PD resister R108
GPI044 HS_MIC_OFF Pin M5 To turn OFF headset MIC
GPI045 MCSI_TX Pin K7 Connect to a PD resister R110
GPI046 MCSI_RX Pin P2 Connect to a PD resister R111
GPI047 BE_NRESET Pin N5 Reserve for W215 Back-end IC
7 TFT LCD Display

The 1.5” (3.8608cm) LCD module is an active matrix color TFT LCD module. LTPS (Low
Temperature Poly Silicon) TFT technology is used. Vertical drivers are built on the panel.
The following is general specifications of Toppoly TFT LCD. (Model name is TD015THEA6)
1. Display Size (Diagonal) : 1.52 (3.8608) Inch (cm)
2. Display Type : Transmissive
3. Active Area (HxV) : 27.264 x 27.264 mm
4. Number of Dots (HxV) : 128 x RGB x 128 dot
5. Dot Pitch (HxV) : 0.071 x 0.213 mm
6. Color Arrangement : RGB Stripe
7. Color Numbers : 65 K
8. Outline Dimension (HxVxT) : 35.4 x 40.3 x 2.95 mm
9. Weight : 5.85 +/- 0.5 g
For W208, the 65K TFT LCD display is controlled by the micro wire (uWire) and GPIO
interface of Locosto-Plus. Figure shows the pin connections between TFT LCD and
Locosto-Plus. And the functions of those pins are described as the following:
LCD_SDATA – LCD serial data bus from Locosto-Plus
LCD_SCLK – LCD serial clock derived from reference 13MHz clock
LCM_nCS – This is used as Chip Enable for the LCD.
LCM_RESET – LCD reset
VCCIO – LCD driver IC power supply
LED+ – LCD backlight LED power supply

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Figure 14: The pin connections of TFT LCD and U101 Locosto-Plus
7.1 Display Backlights

The Display backlights are provided by the control signal LEDLCM_EN Locosto-Plus Pin
A5. After LEDLCM_EN Locosto-Plus Pin A5 control signal turned on, Charge Pump U701
will charge the flying capacitor (C702) to supply 5V for two shunt LEDs in LCM. On another
side, when LEDLCM_EN Locosto-Plus Pin B11 control signal is high, the keypad light will
be turned on.
8 32kHz RTC
The Real-time Clock Interface is part of the Triton-Lite U103 in use with the crystal Y102.
The clock signal is running on 32kHz as reference for the clock module and as deep sleep
clock.
9 SIM Card Circuit

To allow the use of both 1.8V and 2.8V SIM card types, there is a SIM level-shifter module
in the Locosto-Plus U101. The SIM card digital interface ensures the translation of logic
levels between the Locosto-Plus U101 device and the SIM card J701 for the transmission
of three different signals:
USIM_IO – Data Communications path between SIM connector J701 Pin 2 and
Locosto-Plus Pin P11
USIM_CLK – SIM data Clock from Locosto-Plus Pin P10
USIM_RST – SIM Reset from Locosto-Plus Pin N11
VRSIM is an LDO voltage regulator providing the power supply to the SIM card driver of
the Triton-Lite device.

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VRSIM
From Triton-Lite VCC
SIM-IO
SIMIO I/O
SIM-CLK
SIMCK CLK
SIM-RST
SIMRST RST
GND
Locost-Plus SIM Connecter
Figure 15: SIM interface
9.1 SIM Card Supply Voltage Generation

To accommodate the 1.8V or 2.9V SIM cards, the Triton-Lite includes an LDO voltage
regulator that delivers supply voltage Pin A3 to the SIM module.
The LDO voltage regulator is configured to generate the 1.8V or 2.9V (VRSIM U103 Pin
A3) supply. The VRSIM J701 Pin 4 and 5 terminals are decoupled by a capacitor (C709).
10 Keypad
The keyboard is connected to the chip using:
ROW0-ROW4 (KBR[0:5]) input pins for row lines
COL0-COL4 (KBC[0:5]) output pins for column lines
If a key button of the keyboard matrix is pressed, the corresponding row and column lines
are shorted.
To allow key press detection, all input pins (KBR[0:5]) are pulled up to VCC and all output
pins (KBC[0:5]) are driving a low level. Any action on a button will generate an interrupt
to the microcontroller which will, as answer, scan the column lines with the sequence
describe below.
This sequence is written to allow detection of simultaneous press actions on several key
buttons.
Figure 16: Keyboard scanning sequence

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Figure 97: Keyboard connection
10.1 Keypad Matrix

The keypad matrix is as follow:
Function Key Col 0 Col 1 Col 2 Col 3 Col 4 Row 0 Row1 Row 2 Row 3 Row 4
1 S10 V V
2 S11 V V
3 S12 V V
SEND S13 V V
4 S14 V V
5 S15 V V
6 S16 V V
UP S17 V V
7 S18 V V
8 S19 V V
9 S20 V V
DOWN S21 V V
* S22 V V
0 S23 V V
# S24 V V
LEFT S25 V V
SOFT-L S26 V V
MENU S27 V V
SOFT-R S28 V V
RIGHT S29 V V
POWER/END S30 V
11 Vibrator circuit
Triton-Lite U103 Pin U12 is used to control the vibrational level. D708 is used to
protection the vibrator. The DAC output voltage is 2.7V and drain current is around 80mA.
12 Memory
The W208 portable will be using the stacked combination memory parts that include flash
die and PSRAM die. The Flash memory is 64Mbit size and the PSRAM memory is 16Mbit
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size.
ADD [1:23] – Address Bus for Flash memory/PSRAM.
DATA [0:15] – Data Bus for Flash memory/PSRAM
F1_VCC – This is provided Flash memory I/O voltage.
RnW – Read and Write allows information to be written or read from the memory devices.
nFOE – Flash and PSRAM output enable (Active Low).
FDP – The Flash reset/deep power-down mode control.
nCS3 – This is used as Chip Enable for the Flash Memory.
nCS0 – This is used as Chip Enable for the PSRAM Memory.
nBHE – Enable to address High Byte Information.
nBLE – Enable to address Low Byte Information.
VCCQ – This provides PSRAM memory power supply
Figure 108: Memory interface
13 Power
13.1 Low-Dropout Voltage Regulators

The voltage regulation block consists of seven subblocks.
Several low-dropout (LDO) regulators perform linear voltage regulation. These regulators
supply power to internal analog and digital circuits, to the Locosto-Plus IC U101 (DSP)
processor, and to external memory.
The first LDO (VRPLL Triton-Lite Pin T12) is a programmable regulator that generates
the supply voltages 1.3 V for Locosto-Plus IC U101.
The second LDO (VRABB Triton-Lite Pin B2) generates the supply voltage (2.8 V) for the
Triton-Lite analog part.
The third LDO (VRRTC Triton-Lite Pin N17) is a power rail for embedded 32K real time
clock used.
The fourth LDO (VREXTH Triton-Lite Pin I17) is a programmable regulator that
generates the supply voltages 2.8 V for supplying an external peripheral to Locosto-Plus
U101.
The fifth LDO (VREXTL Triton-Lite Pin G17) generates the supply external peripheral
- 20 -
voltage (1.3 V) Triton-Lite U101.
The sixth LDO (VRMMC Triton-Lite Pin T10) is a programmable regulator that generates
the supply an external MMC device voltages (2.8V).
The seventh LDO (VRSIM Triton-Lite Pin A3) is a programmable regulator for supply
SIM-card and SIM-card device (2.8V).
The eighth LDO (VRIO Triton-Lite Pin J16) is a programmable regulator for supplying
the I/O of the system (1.8V).
The ninth LDO (VRMEM Triton-Lite Pin U11) is a programmable regulator for supplying
the external Flash memory (1.8V).
The Triton-Lite U103 allows three operating modes for each of these voltage regulators:
1. ACTIVE mode during which the regulator is able to deliver its full power.
2. SLEEP mode during which the output voltage is maintained with very low power
consumption but with a low current capability (1mA).
3. OFF mode during which the output voltage is not maintained and the power
consumption is null.
The regulators rise up in ACTIVE mode only and each of them has a regulation ready
signal RSU. In switched-off and backup states of the mobile phone, the voltage regulators
will be set to a SLEEP or OFF mode depending on the system requirements. The regulator
voltages are decoupled by a low ESR capacitor connected across the corresponding VCC
and ground terminals. Besides its voltage filtering function, this capacitor also has a
voltage storage function that could give a delay for data protection purposes when the
main battery is unplugged.
The third LDO (VRRTC Triton-Lite Pin N17) is a programmable regulator that generates
the supply voltages 1.8 V for the real-time clock and the 32kHz oscillator located in the
Locosto-Plus IC U101 (DSP) device during all modes. The main or backup battery supplies
VRRTC.
13.2 Power Down Methods

The phone is disabled by one of the following conditions:
1. Software-initiated power down.

When the user requests to turn the phone off by pressing the POWER/END key, or
put RPWON TP11 to GND, or when a low battery voltage is detected by software
through VBATS Syren Pin K8 (typical value is 3.53V) measurement and therefore
the phone turns off.
2. Hardware-initiated power down.
On main battery remove or deep discharge, when the main battery voltage is lower
than 2.8V.
14 Sleep Module
The Sleep Module allowed for optimal power savings in idle modes. Triton-Lite U103
internal LDOs (VRIO, VRMAM, VRSIM, VRABB, VREXTL, VRPLL) have very low current
consumption and can provide 1mA current.

- 21 -
14.1 Sleep Up Sequence
14.2 Sleep off Sequence

- 22 -
15 Power Tree
Figure 119: Power Distribution Tree
16 Charging Circuit and External Power

We can obtain power from battery and external charger. Power source via the accessory
connector are not supported.
16.1 Battery Support

The Battery connecter J700 is made up of 4 contacts, these are
♦ Pin 1 – VBAT- (BATTGND)
♦ Pin 2 – BAT_TEMP is used to measure the Battery temperature during charging,
fed from the battery connector to Triton-Lite U103 Pin F8
♦ Pin 3 – DATA-EPROM for charge/discharge control (No Used for W370/
W375)
♦ Pin 4 – VBAT+
16.2 Charger Support

When the battery voltage is less than 3.2V, and adapter is inserted, the charging system
will enter the ‘Pre-CHARGE’ mode. The pre-charging current will pass through Triton-Lite
pre-charge path and charger IC U501 (ISL9200). The current limit resisters, (R511), are
set the safe magnitude of pre-charging current.
When a charger is plugged in and VAC is less than 6.85V, the Triton-Litw will enable U502
(P-MOSFET) to start charging process. The process starts charge state until VAC is full.
When the battery voltage is less than 3.2V (deeply discharged), the Battery Charge
Interface (BCI) of Triton-Lite will enter the pre-charge mode (charging current is under
100mA) as soon as the charger is plugged-in. At this moment, software cannot control the
charging process. Until battery voltage VBAT is larger than 3.2V, Triton-Lite will wake up
and then enter to normal charging status. The normal charge will start as constant current
mode (MAX current is 450mA). When the battery voltage is reach 4.15V, charging system
will enter the constant voltage mode till minimum current is less than 50mA, then the
charge process finishes. When the battery voltage VBAT is higher than 4.2V, U502
- 23 -
(P-MOSFET) will be turned off and stop charging.

- 24 -
5 4 3 2 1
S403 S404 S405 S406

1 1 1 1
Keypad Circuit 2 2 2 2
1 8 R807 (1) (2) (3) (SEND)
LCM Hot Bar
2 7
C 40 6 1uF ; 06 03 Y 5U
3 6
4 5 DGND DGND DGND
W208 E U
C 40 1 1 00nF _N M
1u F, 0 603
R405 1K C806 S407 S408 S409 S400
N.M 1 1 1 1
CON2 33pF
C 40 2
RPWON R104 100K VBAT
DGND 2 2 2 2
LCM_ID 10 R808 R105 100K
GND (4) (5) (6) (UP) PWON
VR2V8 9 VCC
8 VSS 1K S410 S411 S412 S413
C807
VRIO 7 VCCIO 1 1 1 1 VCHG VCHG
33pF
LCD_SDATA R401 100R 6 VBAT
SDA VBAT
LCD_SCLK R402 100R 5 DGND 2 2 2 2 VRIO
SCL VRIO
R403 10K R809
LCM_RESET 4 /RES (7) (8) (9) (DOWN) VRMEM VRMEM
R404 200R 3 VR2V8
LCM_nCS /CS VR2V8
1K C808 S414 S415 S416 S417
LED+ 2 LED(+) VREXTH VREXTH
D 1 1 1 1 D
1 33pF
LED(-)
C408 DGND 2 2 2 2
100nF 070_LCM R810

(*) (0) (#) (LEFT)
C407 C403 C404 C405
100nF 22pF 22pF 22pF 1K C809 S806 S811 S816 S821

1 1 1 1
DGND 33pF
DGND DGND DGND DGND DGND

DGND 2 2 2 2
R811 (SOFT-L) (MENU) (SOFT-R) (RIGHT)
1K 1K 1K 1K
1K C810
LCDBACK LIGHTDRIVER
33pF
R801 R803 R804 R805
L701
0ohm,0603
DGN D
DGN D
VBAT
DGN D
DGN D
DGND
33pF 33pF
U701 C801 33pF 33pF C804
1 VOUT 6 C802 C803 DGND
LED+ C+
R806
2 VIN 5 C702
DG ND
GND
3 /SHDN* C- 4 0.1uF,0603
FM Circuit Speaker Circuit
25
24
23
22
21
20
19
2
1K U202
RT9361APESOT-26 C805 D801
B_ GN D
GN D
NC
NC
GP I O1
GP I O2
GP I O3
DGND
C703 C713 33pF 1PS79SB30 AUDAMP_SD
R719 R607 40K_NM DGND DGND DGND DGND
10uF0805 100k0402 10uF0805 R802 S402 C222 1 GND VA 18
1
DGND 100pF ( 1.8V )
C7 05
C7 06
C7 07
C7 08
1 2 FMIP GND 17 C289 C152 R608
R71210K RPWON R219 1k 27pF C612 C614 C647
3 RFGND LOUT 16 47nF 100nF C150 200K U601 VR605
DGND DGND DGND 1K TPA6204A1DRBR 12pF 47pF 270pF L60168nH,0603 TVM0G180M03018V
2 2pF
3 3pF
9pF
2 2pF
J10 2 4 FMIN ROUT 15 100nF C149 1 SHUTDOWN VO- 8
R714 39R C290 SpeakerCON
(POWER/END)
DGN D
R715 39R 5 GND GND 14 R220 1k 2 BYPASS GND 7 1
R716 39R 47nF C151 C6130.22uF R60940.2K 2
6 13 27pF 3 6 VBAT
C709 VRSIM DGND GND VD VBAT R61040.2K IN+ VDD L60268nH,0603
S CL K
R C LK
J603
S DI O
GN D
V IO
S EN
R ST
C226 C231 Close to Triton C615 4 IN- VO+ 5
100nF
5
R72410KNM 22nF 27pF 0.22uF C616 C617 C631 C648 VR606
10
11
12
9
Close to VD TVM0G180M03018V
V CC
CL K
RS T
Close to Locosto
SIM Circuit
220nF C618 12pF 47pF 270pF
GND 7 SCL1 R103 2.2K VRIO 1uF;0603Y5U
SP I _SOMI
8 SDA1 R127 2.2K R207 DGND

H S _DE TE C T
GND 9 R725 0 SCL2 R128 2.2K 100K C233 DGND DGND DGND DGND DGND
GND SDA2 R129 2.2K R611 40K_NM
GND 10 DGND
S I M_I O
BOTTOM R208 0R 100nF
GN D
SIMCON FM_RESET
V PP
VCLKRX R102 10K
I/O
VIEW
3
R726 R216 0R VRIO
T703 SCL2
C TS_ MOD EM
1 SIM_IO DGND
6
T X_MODE M
R X_MODE M
B E_ NR ES ET
PDTC144EEEMT3 47K C102 SDA2 R217 0R

47K 0
VRIO
MIC Circuit
100nF U102 CLK32K R215 2k R602
R601270 2K
2
R727 VBAT 4 VDD VOUT 3 VR2V8 VRIO
NM
R 107 N M
Active High 150mA C103 C602 C630

10 k
10 k
56pF
10K
10K
1 CE GND 2 Close to Triton

REGEN 1uF;0603Y5U 10uF,0805
DG ND
R1114Q281D
MLV S- 040 2- M0 4 20A 5 . 5V

S C L2
S DA 2
DGND DGND
R11 2
R11415K C10547nFKX7R 33pF NM
Receiver Circuit
R 108
R 109
R 110
R 111
C646
K BC 0
K BC 1
K BC 2
K BC 3
K BC 4
K BR 0
K BR 1
K BR 2
K BR 3
K BR 4
U S B_D M
US B _DP
C107
C 10 6
VR 60 1
0R
VBUS
C C603 C643 C
C606 C605 C604 C644
T 10
G11
C 16
E 13
C 15
B 12
F 11
E 11
C 12
F 10
B 16
A 16
+ C6071uF;0603Y5U
F8
E7
C6
A5
C5
F7
G9
E6
G8
C4
P3
R2
R3
N5
M6
N3
M5
K7
P2
H9
U2
U1
R4
N6
L1 2 120 K, 1% R 116
4.7nF VR602 J604
L7
5
C109 12pF 47pF MLVS-0402-M0420A5.5V 12pF 47pF 12pF 47pF MicrophoneCON
68pFNM
10 nF
C 159
22uF , 0 805
1
GP I O4 7/ DS R_ RX I R
GPI O0/ DC D _TX I R
GP I O24 / SPI _S OMI
GPI O23/ S PI _C LK I
GPI O21/ C AM_L CK / DT P
TX
RX
CT S
RT S_S D I RD A
GPI O4 3/ MCS I _CK / CS CL K
GPI O46/ MC SI _R X
F OR C E
S EN S E
S DA
GP I O19 / CA M_ HS / CK P/ N D_D T 3/ CA M_DT 3
GP I O20 / CA M_ VS / CK N/ N D_D T 3/ CA M_DT 3
GPI O22/ CA M_X CK / DT N/ N D_D T 3/ CA M_DT 3
GPI O26/ SP I EN _0
GPI O27/ SP I EN _1
GPI O28/ SP I EN _2/ N D_D T 7/ CA M_DT 7
KB C _0
KB C _1
KB C _2
KB C _3
K BC _4/ GPI O9
KB R _0
KB R _1
KB R _2
KB R _3
K BR _4/ GPI O8
SP AR E _2
SP AR E _3
SC L
EF1
GP I O25 / SPI _S I MO
T X/ C DO
U SB - Boo t /G PI O3/ LPG

GP I O4 4/ MC S I _FS/ C SY NC
100nF C110 C1
T DO
LCM_RESET C10 LCD_nRst nBSCAN T1 2
B10 LCD_STB/GPIO14 TDI B1 TDI C601 5 O1 I1 1
DGN D
AUDAMP_SD F9 JTAG/ Emulation B2 10uF,0805 ReceiverCON 2
GP I O4 5/ MC S I _
6
LCM_ID D9 LCD_RnW/GPIO15 TDO A2 TMS R6440 1 1uF;0603Y5U 4 GND 3
LCD_RS/GPIO16 TMS O2 I2
Interface A1 TCK 2
G12
F1 6
R 17
M17
M16
TCK 33pF NM SMT bottom hole port type
U2
B9
A5
A7
A8
P2
E1
E10 GPIO13/LCD_nCS_0 nEMU0/GPIO10 C11
J601 C645 NZF220DFT1
B9 GPIO17/LCD_nCS_1 LCD VDD-IOs nEMU1/GPIO11 D10
T2 TRSTN G1 R6430 VR604
A U DV MI D
H SD E T
I RE F
D M_T XD _S PK R_ L
F I LTE RA PL L
TRSTN HSOL
T DO
V BG
RE GEN
D P_ RX D _MI C_R
R EF GND
VB US
I D_U SB
V BA CK UP
Interface
Cam ara Ctr l I/ F
E9 U1 J6 C608 C611 MLVS-0402-M0420A5.5V

B8 LCD/CAM/ND_DT_0 R1 TDI HSOVMID F1
LCD/CAM/ND_DT_1 TMS HSOR 12pF 47pF
C8 LCD/CAM/ND_DT_2 T1 TCK AUXI_FMR C1
Se ria l Po rt
E8 N11 K12 C2
LCD/CAM/ND_DT_3 MCU Ap p I2 C USIM_RST 1 TESTRESET VRIO FML
B7 LCD/CAM/ND_DT_4 USIM USIM_IO R11 EARN H2
In ter face
D8 P10 TP114 B17 J2
VRV BUS
LCD/CAM/ND_DT_5 USIM_CLK TESTV EARP
UART MODEM
Card
Int erf ace
C7 M10
Test ctrl
VRABB
Key Boa rd
VBA CKU P
LCD/CAM/ND_DT_6 USIM_PW_CTL
(BTVoice)
B6 VDD-IOs T11 VBAT JTAG TEST K6

LCD/CAM/ND_DT_7 SIM_PBIAS SPKPA
DSP MCSI
M10 L6 47pF_nm
Mis c
SIMDTC SPKPA
Device
VDD-USIM SIM I/F K1 C158 C156 VRIO

VDD -IO s
VDD -IO s
VDD -IO s
VDD -IO s
/IRDA
VRIO SPKPD
VDD -IO s
VDD -IO s
RX_EGSMP M17 RXGSMP SPKPD K2 220nF_nm
Detection
RX_EGSMM N17 RXGSMM USB_RCV/UART_CTS T4 F6 RCV/TEST4 SPKNA M6
MCU L8 B6 Audio M7 VR612
REF SYS
USB_SE0/UART_TX SE0_VM_TXD/TEST3 SPKNA 220nF_nm 1uF0603 R631 NM
GPIO
L16 R5 B4 Drivers M1
M16 RXEGSMP
RXEGSMM USB I/F USB_DAT/UART_RX
USB_TXEN/UART_RTS M7 B3 DAT_VP_RXD/TEST2
OE_INTN/TEST1
SPKND
SPKND M2 C157 47K
USB
R617
U101
IF
SPKVDD L1
RX_DCSP L17 RXDCSP VDD-IOs USB DBB IF SPKVDD L2 C111 R131 4.7K L604
VCC 5
VBA T
VRU SB
VRIO VBAT
VRA BB
RX_DCSM K17 RXDCSM SPKGND H1 HS_DETECT
SPKGND N1 0R BLM18BD252SN1D0603
SCL1 Ctrl SPKVDD C642
K16
J16 RXPCSP MCU&DSP SCL_TriTon N7
R6 SDA1
T8
U7 SCL1 Serial U103 F2 1uF,0402 C624
RXPCSM SDA_TriTon SDA1 MICIN
I2C Port
VRIO Audio MICIP G2 MLVS-0402-M0420A5.5V
TXHB G17 TXHB TP116 1 HSMIC D2 R139
TXLB F17 Input G6 0R
TXLB MICBIAS
LOCOSTO Lite
VCLKRX R7 VCLKRX T3 VSP_VCK HSMICBIAS H6 C1121uF;0603Y5U
VAPC M11 T6 VDX T4 Voice VRABB C623 R632
APC_OUT VDX VSP_VDR
DSP Voice VDR M8 VDR
VFSRX
T2 VSP_VDX I/F 10uF 0805 7.5
R12 APC_LDO_FILTER VFSRX K9 U3 VSP_VFS Vibrator VIBDR U12
VIBDR C113 VR611
R13 APC_REF RF VDD-IOs TP117 TP118 VRIO TRITON-LITE LED LED_A C16 DGND
TVM0G180M03018V
1
L9 E17 33pF
RF
DGND
APCSPARE1 1 LED_B
C101 C114 N13 VSSAPC DRP2.0 CSYNC M9 CSYNC U6 I2S_WS Stereo
Drivers
LED_C F17 DGND
100nF 100nF CODEC Audio CSCLK P9 CSCLK
CDO
T7 I2S_SCK VRWLED LED_x, ADCINx: connect to
ground if not used.
CDO T9 T6 I2S_SDR I/F
SW_HI_TX F12 R9 CDI U5 TWL3031 Monitor
RX _MODE M_ 2V8
TSPACT11 GPIO4/CDI/LT2/TSPACT9 I2S_SDX
SW_LO_TX H10
C14
TSPACT12 DBB VDD-IOs TP119 VRIO DonainVoltage(V) Current(mA)
ADC ADCIN3 B7
F7 R623
TSPACT13 1 1 ADCIN4 U603
E12 TPU TP120 ------------------------------------ F8 100K R624
Tr it on I/ F
PA_EN TSPACT14 TSPACT8 VRPLL 1.3/1.4/1.05 10

VRABB ADCIN5 R1170R_NM 1K
BS1 G10 TSPACT15 GPIO5/TSPACT8 N9 M9 STARTADC VRIO 1 OUT NC 3
T17
TPU Port ADC VRDBB
VRMEM
VRIO
1.4~0.95 850
1.8
1.8
200
200
VAC BM_PRECH B16
B11
CHARGER U604 R640
0R
XANATST1 VDD-IOs VRIO VRABB VAC
DGN D
U17 XANATST2 2.8 80
VAC PCHGAC A12 VR2V8 4 VDD VOUT 3 2 Vin GND 4
VRRTC 1.8 20
U15 XANATST3 Interrupt VRUSB 3.3 15
VRVBUS PCHGUSB A11 Active High
U16 XANATST4 MCU IRQ ABB_IRQ P8 R2 P1_INT2 Handling
VRWLED 20 20
VCCS A10 VCCS C637 HS_BIAS
150mA C619
10uF,0805
R613
2.2K
R625
10K
R3111N231A
T16 XANATST5
VRSIM 1.8/2.85 15
VRIO VREXTH 1.8/2.8 200/100 VBAT VBAT B12 VBAT 1 CE GND 2
R17 XANATST6 VDD-IOs TP121 1 VBATS B10 VBATS 100nF C634 C636
Battery
VDD_RF VREXTL 1.3/1.05 200 VCCS
A13 R1114Q251D 100nF 4.7uF,0603
Charge
1.8/2.8 100
VRVBUS ICTLUSB1
H17 VDDRF Domain | Block | Voltage
----------------------------- Reset ctrl On_nOFF N10 U15 ONNOFF VRMMC
VRVBUS
1.8/2.85 100
5 60
VCCS ICTLUSB2 B15
U607 VR2V8 D3157DFT2
G16 VDDRF1 VAC ICTLAC1 F11
TVM0 G1 80M030 18 V
TVM0 G1 80M030 18 V
1uF,0603 M15 VSSRF VDD-IOs I/O CELL 1.8V VDD-RST TP122 1 VCCS ICTLAC2 F12 RX_MODEM C1 A B C2 DGND DGND
Close toG16 pin C115 H14 VDD-MIF MEMORY 1.8V R8 WakeUp_Req M12 Y102 R618
VSSRF1 Wake_Up_Req WAKEUP1 VRIO
DG ND
DGN D
G15 VSSRF1 VDD-RST INPUT RESET 1.3V Power CKout_13MHz N8 CLK13M M11 MCLK1 VRIO VRIO OSC32KIN R16 1 4 B1 GND DIR B2 100K,1%
VDD-USIMSIM CARD 2.85V &Clocks VRIO OSC32KOUT T16
C116 P15 VDDA CK13MHz_En T7 H12 CKEN PWON T14 PWON 32.768kHz A1 VCCA VCCB A2
1uF,0603 P16 T8 CLK32K P16 Power Ctrl& System Clock VCC2 U13 R1261K Low : Bo<-->A VR2V8
C1171uF,0402 D16 VDDA VDD-IOs CKin_32KHz CLK32KOUT VCC2 RPWON T15 RPWON R1300R SN74AVC1T45YZPR
C15410nF VDDX VRIO PCLKREQ High : B1<--> A C627 R620
GP I O7/ nF WP/ L1 / TSP AC T7 / ND _DT 2/ CA M_D T2
VR 607
VR 608
VDD-MIF 1 VRRTC VRRTC BM_SEL M8 R633
E17 VREF VDD-IOs VDD-IOs VSS_PBIAS U11 R138 VRRTC 100nF 100K,1% R641
Trace shortand wide B14 27R TP124 VRRTC U606 1M U602 6.2K
VSSPLL VRRTC
R16 ARM Memory Interface Nand Flash PWM’s E15 C120 C121 1 6 1 6 C621
CL K13 M
DGN D
n CS 0/ GPI O38/ LT1 / TSP AC T7 / ND _D T0
VREF1 VSSX B1 S B1 S
C122
0.47uF C162 R101 Ctrl I/F Output Power supply VSSA N15 C119
10pF_NM 22pF 22pF
100nF
DG ND
DG ND
R15 IREF VSSA M13 A3 VRSIM 2 GND VCC 5 2 GND VCC 5 DGND 6
GP I O30 / LT3/ N D_ DT 5/ CA M_D T5
1.5pF L13 T14 J12 L606 1

C K EN
C LK 32K
GP I O29 / BU / ND _DT 6/ CA M_D T6
45.3K,1% VSSRF VSS GND_DBB DGND

DRP VSS
N D _nWP / ND _D T4 / CAM_ DT 4
K14 VSSRF C17 3 B0 A 4 3 B0 A 4 2

K15 VSSRF VSS A12 C165 R615 BLM18BD252SN1D0603 4 J602
Close toE17 pin 10nF 100R D3157DFT2
GP I O12 / LPG/ TS PA CT 10
L15 VSSRF VSS A10 A1 N/C GND_PWR1 T9 3

Power Management
GP I O39 / AD 22/ ND _D T0
GP I O37 / AD 23/ ND _D T1
GP I O36 / nCS 1N D_ DT 2
GP I O35 / nCS 2N D_ DT 3
A7 A2 C17 5 LGK2409-1070E-041001
GP I O2/ P WL/ PC M_C K
VSS N/C GND_PWR2

H16 C1 A16 D16
T X_MODE M_2V 8
VDDOSC VSS N/C GND_PWR2
TV M0 G1 80M030 1 8V
DRP H1 A17 U8 C640 C620
GP I O32 / ND _C LE
GP I O33 / ND _AL E
GP I O34 / ND _R nB
VSS N/C GND_PWR3 4 3 6

GP I O18 / ND _WE
GP I O31 / ND _R E
n RD Y M/ GPI O40
100nF 47pF
A D D/ D AT A_1 0
A D D/ D AT A_1 1
A D D/ D AT A_1 2
A D D/ D AT A_1 3
A D D/ D AT A_1 4
A D D/ D AT A_1 5
J14 R1 B1 A6
A D D2 1/ GP I O6
VSSOSC VSS N/C GND_PWR4

GP I O42 / CK M
B B
Headset Circuit
A D D/ D AT A_0
A D D/ D AT A_1
A D D/ D AT A_2
A D D/ D AT A_3
A D D/ D AT A_4
A D D/ D AT A_5
A D D/ D AT A_6
A D D/ D AT A_7
A D D/ D AT A_8
A D D/ D AT A_9
A D V/ GPI O41
J15 U5 T17 G16

GP I O1/ P WT
VSSOSC VSS N/C GND_PWR5

V D D_ US I M
C123
V D D_ AP C
DB B
DB B
DB B
DB B
DB B
DB B
DB B
DB B
V D DR 1T X
V D DR 1R X
RS T
H15 U8 U16 F9
V D D_ MI F
V D D_ MI F
V D D_ PLL
I Os
I Os
I Os
I Os
I Os
VSSOSC VSS N/C GND_VBUS
TVM0 G1 80M030 18 V
A D D_ 16
A D D_ 17
A D D_ 18
A D D_ 19
A D D_ 20
N D _C E1
10uF,0805 U12 U17

V D DR 2
VSS N/C DGND

n BH E
n BL E
n MOE
n CS 3
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
V D D_
VR 610
VR 609
F DP
VPP
VPP
R nW
D15 XTAL L603 1 2 5

VR E XT H
VR WL ED
VR WL ED
VR E XT L
VR ME M
VR MMC
VR R TC
VR U SB
VR A BB
VR P LL
VC C 1
VC C 2
VC C 2
VC C 3
VC C 4
VC C 4
VC C 5
VC C 5
VC C 6
U608 BLM18BD252SN1D0603
VR I O
K4
L2
K5
K3
K2
J5
J3
J2
J4
J6
H2
H3
H5
G2
G1
H4
G3
F1
F2
H6
J8
F3
G5
H7
E3
D2
F5
L5
L1
L3
M2
M1
K6
M3
J7
L6
G6
E5
D3
A6
C3
F6
H8
C2
B 11
G7
B3
K8
T3
A 17
B 17
A 11
U6
R 10
B 15
A 13
A8
B4
N1
U 10
F 16
T 15
F 15
U 13
U3
U7
A 15
C9
A3
E1
K1
C 13
T 12
LOCOSTOLITE C2 C1 R619
TX_MODEM B A 1K U605 C625 1 4
DGN D
100nF C622
DG ND
B2 B1 1 6 Mic R L GND
L1 6
T1 1
U1 0
C3
K1 6
K1 7
H1 6
H1 7
F1 0
T1 2
U1 1
J1 6
l 7
G1 7
T1 0
B8
N1 7
B2
A1 5
Y101 C124 B1 4 DIR GND B1 S MLVS-0402-M0420A5.5V 2 3 6 5
1
Di t her i ng
DG ND
A/ D 10
A/ D 11
A/ D 12
A/ D 13
A/ D 14
A/ D 15
A 16
A 17
A 18
A 19
A 20
A 21
A 22
A 23
1 00n F C 125
1 00n F C 126
1 00n F C 127
1 00n F C 128
2 1 VBAT A2 VCCB VCCA A1 2 5

A/ D 0
A/ D 1
A/ D 2
A/ D 3
A/ D 4
A/ D 5
A/ D 6
A/ D 7
A/ D 8
A/ D 9
GND VCC
C12 9
DGND
1nF SN74AVC1T45YZPR 3 4
3 4 R137 B0 A
10 0nF
1.5M 10uF D3157DFT2

Di t her in g
TP127 C626 R616

26MHz 120K C641
100pFN.M.
VR2V8
FM_ RE SE T
VRSIM
WA I T
Rn W
C163
nB HE
n BLE
nF OE
F DP
nF AD V
VRPLL VRABB
nC S3
C KM
HS _B I AS
R140 0.5pF VRMEM R144 0R VRMEM_Out VRRTC

VRIO R143 0R VRIO_Out VRUSB L605
nC S 0
VREXTH R634 220nH0805

680K1% 100K
A [ 16. . 23]
VREXTL
R141 R142 VRMMC
47R 100K DGND
VR2V8
6
C164
B Y PA SS
R 132
100 K
R1 19
R1 36
C1 61
C1 30
C1 31
C1 32
C1 33
C1 34
C1 35
C1 36
C1 37
C1 38
C1 39
C1 40
C1 41
C1 42
C1 48
C1 45
C1 46
C1 47
100pF
100K NM
47K 2.2K
R627 T601 R614
100 K R 133
R 125
100 K
R1 24
C143 C155 C144 100K EMH10(EMT6) 1M

1nF 33pF 10uF,0805
10 0nF
10 0nF
10 0nF
10 0nF
10 0nF
10 0nF
10 0nF
10 0nF
1u F, 0 603
1u F, 0 603
1u F, 0 603
1u F, 0 603
1u F, 0 603
1u F, 0 603
470n F, 0 603
1u F, 0 603
1u F, 0 603
1u F, 0 603
100 K
100 K
R1 22
R1 23
100K NM
10 0K_ NM
2.2K 47K
1
R642 DGND
VRIO
VRIO DGND
A/D0
A/D1
G1
F1
A0
A1
DQ0
DQ1
H2
H3
A/D0
A/D1
VRIO VRIO VRIO
POWER 10K
A/D2 E1 A2 DQ2 G3 A/D2
A/D3 D1 H4 A/D3
A/D4 B1 A3 DQ3 J5 A/D4
A/D5 A4 DQ4 A/D5
C1 A5 DQ5 G5
A6 0: H83 1: H85
Vibrator Circuit
A/D6 F2 A6 DQ6 J6 A/D6
A/D7 E2 H7 A/D7 VRMEM
A/D8
A/D9
F6 A7
A8
DQ7
DQ8 G2 A/D8
A/D9 TP301
B3 0: no DSC 1: with DSC
D7 J3
A/D10 E7 A9
NOR FLASH:64Mbit
A10
DQ9
DQ10 G4 A/D10 F6 Low: No FM, High: Has FM
1
A/D11 A/D11 VBAT J9

C2 Low: 850 band, High: 900 band
Test Point
B8 A11 DQ11 J4
A/D12
A/D13 MOBILE PSRAM:16Mbit
C8 A12 DQ12 H5 A/D12
A/D13
R302 BATTCONN4P_ACON
Keypad Backlight
D8 A13 DQ13 G6 BATT- 1 R713
A/D14 F7 A14 DQ14 H6 A/D14 100K VCHG 1
A/D15 E8 J7 A/D15 TP7 F701 2 BAT_TEMP
A[16..23] A16 F8 A15 U301 DQ15 SGM20F1E104-2A THERM
A16 M36W0R6040U3ZAME VBAT 1
1
A17 D2 VBAT TP9 3 1K

A18 B2 A17 K1 DATA
I /O 1
A19 A18 F1_CE nCS3 C701 TP701 1 TP10

B3 A19 F2_CE G8 BATT+ 4 VBAT
A20 E6 A20 F3_CE K3 1 RPWON 1 4 G G 3
A21 B7 J2 ROE TP104
A21 F1_OE
I / O2
A22 C7 A22 F2_OE H8 TX_MODEM_2V8 1

A23 RnW 100nF TP3 C711 C714 C712 D902
Charging Circuit
C3 (A23) F_WE F5
D3 C6 R3010R CKM RX_MODEM_2V8 DGND DGND R501 BAT_TEMP BAT_TEMP MLVS-0402-M0720A9V
2
(A24) CLK 1
R 701
R 702
R 703
R 704
R 705
R 706
E3 (A25) WAIT G7 WAIT TP4 U502 47R,1206 100nF 22pFnm 100nF

F_WP E4 CTS_MODEM 1
ADV E5 nFADV TP1 FDG326P
VRMEM J8 VCCQ F4 FDP BAT_TEMP 6 0.15R,1%,0805 DGND
F_RST 1 U501
Battery Connector
K7 VCCQ TP12 5 D502 R503
R707
47R
47R
47R
47R
47R
47R
L3 VCCQ PWON 1 1 VIN NC 12 4 2 2 1 VBAT

TP11 VCHG 2 VIN OUT 11 1
TP302 R135 22R R502 RB160M-30
DG ND
USB_DM 1 3 GND OUT 10
L4 F1_VCC TP126 4 WRN ILIM 9 R504200K
1
3
B5 F1_VCC USB_DP R134 22R 12R 5 8 51R C503
GN D
2
B6 F2_VCC 1 TP125 6 NC VB 7 VBAT

NC EN
3
K6 D702 D703 D704 D705 D706 D707 R70868

D4 F2_VCC D6 LED LED LED LED LED VBUS 1 TP128 1 ISI9200 22nF
F_VPP/F_VPEN P1_CS nCS0 LED
13
T702 R506 C501
Adapter Connector
P2-CS K2 TP702
S_CS1 J1 MMBT2222AT-7-F
2
K4 S_VCC C5 C153 TDO TDO R709 1uF;0603Y5U R5051M

1
S_CS2 1
1
K5 P_VCC R_OE H1 ROE R3030R nFOE 1uF;0603 TP109 200

A
D5 TMS TMS 30K DGND DGND A
R_WE RnW CHGLED 1
VC C S
VB AT S
R_UB F3 nBHE TP110
C2 T701 TCK TCK
R_LB nBLE 1
MLV S- 040 2- K14 2 0A 18 V

C3 01
C3 02
C3 03
C3 04
P_MODE K8 A23 MMBT2222AT-7-F TP111 DGND DGND DGND DGND

1 TDI TDI
1 TP112 DGND
1K R710 TRSTN C710
10 0nF
10 0nF
10 0nF
10 0nF
B4 A1 TRSTN
2
C4 VSS DU A2 C305 C704 1 TP113
1u F; 0 603 Y 5U
1
VSS DU
V R 501
L1 VSS DU A7 100nFNM R711
L2 A8 100nF
VSS DU 10K
C H GL ED
C 502
L5 VSS DU M1 D708 J501
L6 M2 BAS516SOD523 1
L7 VSS DU M7 100nF JA1001 J704 2 GND
VSS DU GND
2
L8 M8 VIBRATORCON VIBRATORCON 3
VSS DU -
VA C
VRMEM VRMEM VCHG 4 +
R512 DCJACK
Memory Circuit
DGND
47R
R507 DGND
J702 J704 6.8K

R510
3
0R
T501 1
With Camera V MMBT2222ATT1G T502
3
MMBT2222ATT1G R508 10K
2
1
Without Camera V
R511
2
47k R509
100K
2006.09.08
DGND
Level3Schematics Rev.1.0
DGND
DGND DGND W208 EU
HansonKo Page1of2
5 4 3 2 1
5 4 3 2 1
W208 E U
D D
VBAT VBAT
Antenna Matching
C202 C203
PA Matching
1
ANT201 ANTGND
ANT ANT
VDD_RF L20133nH 33pF 0R
3
DGND
G
DGND DGND
L202 L203 L204 L205
RX/ TX
I NT
DGN D
C205
DG ND
5 6
47pF NM NM 22nH NM
C
C281 C282 C283
DGND NM 1pF DGND DGND JP201
C201 R201 DGND
DGND
TXLB 2 1 5.6nH DGND
4 2 1 3 MM8430-2604RB36PIN
C207 47pF 4 3
NM U201
21
19
16
14
13
12
10
11
9
8
7
5
L20615nH PAT1010-3dB SKY77318
GS M850/ 90 0_OU T
GND
R SV D _GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DGND DGND DGND
C208 DGND DGND LB_IN 4 GSM850/900_IN SAW Matching

12pF R218
47R
R202
SAW Matching C209
DGND BF201
3 3 4 4 RX_EGSMM
TXHB 1 2 HB_IN 3 5 4
1 2 DCS/PCS_IN SW201 C212 GND OUT 2.2pF
DC S/ P CS _OU T
8
C21012pF EZFL897DF11S 1 L209
PA C_ EN AB LE
PAT1010-3dB IN 22nH
AN T
L215 2.7nH C213
2 GND OUT 3
4.7nH
VC C1 A
VC C1 B
VB AT T
L210 L211 RX_EGSMP
VA PC
5 FUJITSU_900 2.2pF
BS
LB_GSM_Tx NM NM
LB_GSM_Rx 11
18
20
17
15
DGND C285 DGND DGND DGND
3 HB_PCS_Tx
TP202 C206 C214 C284 3.9nH C286 C215
10nF 10nF NM 0.5pF BF202
1
HB_PCS_Rx 1 RX_DCSP
BS1 5 GND OUT 4
V C _HB _T x
C216 1.5pF
V C _LB _Tx
DGNDDGND DGND DGND 1 IN L213
TP201 6.8nH
GN D
GN D
GN D
GN D
GN D
C217
1
2 GND OUT 3
12pF
PA_EN
PA Matching L214 FUJITSU_1800
RX_DCSM
10
4
6
7
9
12
1.5pF
NM
DGND DGND DGND

VAPC R206 1K APC
C C
C218
680pF C287 C288
33pF 12pF
DGND
DGND DGND
VBAT
C224 C223 C219 C220 C232 +

C221
10nF 33pF 10pF 33pF 10uF,0805 47uF,B-CASE
DGND DGND DGND

DGND DGND DGND
VRMMC
R211
47K
T201 T202
1 6 1 6 VC2_GSMTX
DG ND
VRMMC
R212
47 k
47 k
10 k
10 k
1K
SW_HI_TX TSPACT11 2 5 T SP A C T1 2 SW_LO_TX 2 5
10 k
10 k
47 k
47 k
R21347K DGND
DGN D
VRMMC 3 4 3 4 VRMMC
PEMH9SOT666(EMT6) PEMB9SOT666(EMT6)
VC1_DCSTX
R214
1K
DGND
B B
A A
2006.09.08
Level3Schematics Rev.1.0
W208 EU
HansonKo Page2of2
5 4 3 2 1
2006.09.08
Page 1 of 2
Rev.1.0
Vibrator
Level 3 Schematics
Hanson Ko
W208 Top
DC Jack
Audio Jack
SIM
connector
FM IC
Memory
Backend IC
TI Locosto
TI Triton
Lite
Crystal
SAW filter
PA
T/R Switch
Batt
connector
W208 Top
Function
Keypad
W208 Bottom
2006.09.08
Level 3 Schematics Rev.1.0
W208 Bottom
Hanson Ko Page 2 of 2

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W208

3 Triton-Lite Monitoring ADC ....................................................................14

4 Baseband Serial Port (BSP) ....................................................................15

5 Microcontroller Serial Port (USP) ...........................................................15

6 General purposes I/O (GPIO).................................................................15

7 TFT LCD Display......................................................................................17

8 32kHz RTC ..............................................................................................18

9 SIM Card Circuit .....................................................................................18

11 Vibrator circuit .......................................................................................20

14 Sleep Module ..........................................................................................22

15 Power Tree .............................................................................................24

16 Charging Circuit and External Power .....................................................24

Service Engineering & Optimization

1.1 Band selection

Figure 1: Locosto TX/RX Paths Description

Service Engineering & Optimization

1.2 Locosto RX Mode

Figure 2: Locosto RX Signal Process

As described in Figure 2, when the RF signal is input to Locosto, it will be amplified by

Service Engineering & Optimization

Figure 3: Baseband Downlink Block Diagram

Figure 3: Audio Codec Block Diagram

1.3 Audio Codec

1.3.1 Voice Downlink Patch

1.4 Earpiece Receiver

1.6 Speaker Phone

Service Engineering & Optimization

Figure 4: Voice Codec Downlink Patch

2.1 Audio (Voice uplink Patch)

Figure 5: Voice Uplink Paths

2.2 Data Download Transmit Path

2.3 Stereo Audio Path

Figure 6: Stereo Audio Path

As illustrated in Figure 8, GMSK 0.3 is generated with Gaussian low-pass filtered

Figure 7: GMSK Modulation

2.4.1 Transmit Section

Figure 9: Locosto Transmit Block Diagram

2.4.2 Digitally- Controlled Crystal Oscillator (DCXO)

Service Engineering & Optimization

Figure 80: DCXO Block Diagram

Figure 11: Power Amplifier and Antenna Switch

2.6 TX PA Power Control in SKY77318 U201

Service Engineering & Optimization

3 Triton-Lite Monitoring ADC

Figure 13: Baseband interface

4 Baseband Serial Port (BSP)

5 Microcontroller Serial Port (USP)

6 General purposes I/O (GPIO)

GPIO Pin Used As. Description

Service Engineering & Optimization

7 TFT LCD Display

Service Engineering & Optimization

7.1 Display Backlights

9 SIM Card Circuit

Service Engineering & Optimization

Locost-Plus SIM Connecter

Figure 15: SIM interface

9.1 SIM Card Supply Voltage Generation

Figure 16: Keyboard scanning sequence

Service Engineering & Optimization

Figure 97: Keyboard connection

10.1 Keypad Matrix

Figure 108: Memory interface

13.1 Low-Dropout Voltage Regulators