Beruflich Dokumente
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TAREFA 02 – PARTE 01
IJUÍ
1. Projete e implemente via FPGA e programação em VHDL um multiplexador
que tenha as mesmas características do multiplexador lógico de oito
entradas 74ALS151 (74HC151).
--TRABALHO_02
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
A, B, C, D, E, F, G, H, I, J, K, L: in BIT;
X, Z: out BIT;
end atividade2;
begin
X <= ((E and not(A) and not(B) and not(C) and not(D))+(F and not(A) and not(B) and C
and not(D))+(G and not(A) and B and not(C) and not(D))+(H and not(A) and B and C and
not(D))+(I and A and not(B) and not(C) and not(D))+(J and A and not(B) and C and
not(D))+(K and A and B and not(C) and not(D))+(L and A and B and C and not(D)));
Z <= NOT ((E and not(A) and not(B) and not(C) and not(D))+(F and not(A) and not(B)
and C and not(D))+(G and not(A) and B and not(C) and not(D))+(H and not(A) and B and
C and not(D))+(I and A and not(B) and not(C) and not(D))+(J and A and not(B) and C
and not(D))+(K and A and B and not(C) and not(D))+(L and A and B and C and not(D)));
end ativ2;
2. Estudo do Artigo:
METODOLOGIA DE PROJETO DE RETIFICADORES COM FILTRO
CAPACITIVO. Autor: Clovis Antônio Petry. Disponível no Portal do Aluno. Trata-
se de uma metodologia para projetar retificadores monofásicos.
2.1. Leia o artigo e elabore um resumo para ser entregue apontando os
principais pontos de análise.
RESUMO:
METODOLOGIA DE PROJETO DE RETIFICADORES COM FILTRO CAPACITIVO
Valor
Variável
Calculado
VC1max 311,126 V
ΔVC1 31,112
VC1min 280,147 V
tc 0,0683
VC1med 295,636 V
Io 2,367 A
Po=Pf 700 W
R1 124,90 ohms
C1 636,92 uF