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> Manuscript No: TIE-0754-2008.R3<

Experimental Design of a Nonlinear Control


Technique for Three-Phase Shunt Active Power
Filter
S. Rahmani, N. Mendalek and K. Al-Haddad, Fellow, IEEE

high efficiency. However, the performance of the passive scheme has


Abstract—This paper presents a nonlinear control technique a limitation, since the addition of the passive filter interfaces with the
for a three-phase Shunt Active Power Filter (SAPF). The method system impedance and causes resonance with other network [1]-[5].
provides compensation for reactive, unbalanced, and harmonic Numerous active solutions which are becoming a more effective
load current components. A proportional-integral control law is means to meet the harmonic standards by overcoming the drawback
derived through linearization of the inherently nonlinear SAPF of the passive filter have been proposed [6]-[12]. The SAPF operates
system model, so that the tasks of current control dynamics and by injecting the reactive, unbalanced, and harmonic load current
dc capacitor voltage dynamics become decoupled. This components into the utility system with the same magnitudes as the
decoupling allows us to control the SAPF output currents and the non-active load currents demanded by a given nonlinear load, but
dc bus voltage independently of each other, providing thereby with opposite phases [13]. Among the subjects related to the active
either one of these decoupled subsystems has a dynamic response filter's design and applications, the methods for extraction of the
significantly slower than the other. To overcome the drawbacks harmonic load currents and determination of the filter reference
of the conventional method, a computational control delay current play an important and crucial role. Indeed, accuracy and
compensation method, which generates the SAPF reference speed of the SAPF response are related to this point [14]-[16]. The
currents delaylessly and accurately, is proposed. The first step is methods of reference current generation are categorized into two
to extract the SAPF reference currents from the sensed nonlinear main fields; time domain and frequency domain methods [17]-[20].
load currents by applying the synchronous reference frame Time domain methods such as d-q transformation (or synchronous
method, where a three-phase diode bridge rectifier with R-L load rotating reference frame), p-q transformation (or instantaneous
is taken as the nonlinear load, and then the reference currents reactive power), symmetrical components transformation etc., are
are modified so that the delay will be compensated. The based on measurements and transformation of three-phase quantities.
converter which is controlled by the described control strategy The main advantage of these time domain control methods compared
guarantees balanced overall supply currents, unity displacement to the frequency domain methods based on the Fast Fourier
power factor, and reduced harmonic load currents in the Transformation (FFT) is the fast response obtained. On the other
common coupling point. Various simulation and experimental side, frequency domain methods provide accurate individual and
results demonstrate the high performance of the nonlinear multiple harmonic load currents detection. The compensation method
controller. presented in this paper is time domain control type of compensation
where all harmonic load current components are targeted and
Index Terms—Power quality, active power filter, modeling, compensated. A SAPF offers different options of compensation such
nonlinear control, control delay compensation, non-active load as harmonic attenuation, load balancing, resonance elimination, and
current compensation. displacement power factor improvement. Thus, the control strategy
and the method for extracting the non-active load currents references
will depend on the compensation objectives [13]-[20].
Although conventional linear controllers may fulfill certain
I. INTRODUCTION
compromises between steady state performance, and harmonic load

N ONLINEAR loads such as Adjustable speed drives, power


supplies for various electronic equipments used in both
domestic and industrial applications are the origin of both
currents compensation and dc bus voltage regulation, they remain
unable to compensate the inherent nonlinearity of such circuits,
generated by the switching process. This manifests with important
current and voltage harmonics production in the distribution system. overshoots and long settling times, during transients from both ac or
Such harmonics are the cause of transformer extra heating losses, dc side. On the other hand, most of the techniques mentioned in the
marginalized use of existing power distribution installation, and literature assume sinusoidal supply voltages when compensating
cause power quality deterioration. In response to the power quality unbalanced nonlinear load currents [13]. However, in reality, the
concerns of typical power distribution systems in terms of harmonic utility voltage available at the downstream end is nonsinusoidal due
current distortion and power factor, IEEE 519 and IEC EN 61000-3 to the harmonic load currents. A thorough investigation of the
standards specify regulations governing harmonic compliance. experimental results reported in [2], reveals that the total demand
Passive filter has been a viable approach because of low cost and distortion (THD) in the supply currents cannot be brought down
below 5% to satisfy the IEEE-519 standard. This is due to the
presence of notches in the supply currents, while feedforward control
Copyright (c) 2009 IEEE. Personal use of this material is permitted. methods are used. The drawbacks can be eliminated by using
However, permission to use this material for any other purposes must be
nonlinear control theory, ideally without exaggerating computational
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.

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> Manuscript No: TIE-0754-2008.R3< 2

and implementation complexities. Also authors of [21] have from the distorted waveform without harmful phase shift, even when
implemented very useful advanced non linear control technique to the frequency and amplitude altered simultaneously. The drawback
active rectifiers with active filtering function. The control technique of this technique is the difficulty to design the DC-link voltage and
can be applied to active filtering technology. In [22], a nonlinear the current regulators.
control strategy of a SAPF based on the internal model principle is In this paper, the authors propose a detailed nonlinear control
proposed. The stabilization of the DC-link voltage dynamics is technique uses a computational control delay compensation method
addressed along with the fulfillment of the harmonic load currents to overcome the conventional method drawbacks. The first step is to
compensation objective. The two-time scale behaviour of the SAF is extract the SAPF reference current, then the phase shift of the
exploited to apply the averaging theory in the control design. In [23], reference current are modified so that the delay will be compensated.
a non-linear control strategy for an active filter is proposed. It is In addition, the nonlinear control is theoretically established and
based on the input-output linearization method implemented on a dq0 experimentally validated using both simulations and experiments.
rotating current reference frame. The structure balances the load Consequently, the currents track very closely their references. The
currents, obtains unity displacement power factor, and reduces the SAPF compensates for unwanted reactive, unbalanced, and harmonic
harmonic load currents in arbitrary loads. In [24], the current loop load current components under nonsinusoidal supply voltage
dynamics in the synchronous d-q frame are controlled using conditions. The SAPF performance, during both nominal and severe
Multiple-Input Multiple-Output (MIMO) Optimal Control based on operating conditions, is then evaluated in real-time using the
Predictive Control approach. The non-Linear control strategy does dSPACE DS1104 controller board, supported by a Matlab/Simulink
not require on-line optimization and it overcomes the aforementioned Real-Time Workshop environment.
difficulties by ensuring fast current tracking, current loop stability,
and compensation robustness under non-ideal load and/or supply II. THREE-PHASE SHUNT ACTIVE FILTER TOPOLOGY
conditions.
A shunt active power filter configuration is considered in this paper
In this work the theoretical development of the SAPF is based on the
in order to avoid harmonic pollution along the power line caused by a
work done in [25]. However, no experimental validation for the
three-phase diode bridge rectifier load followed by inductor LL in
proposed control was conducted. It was shown by simulations that
series with a resistor RL. The SAPF acts as a controlled current
the nonlinear control technique enhances the dynamic performance
source connected in parallel with the nonlinear load. It has the
of the SAPF modeled in the synchronous orthogonal 'dq' frame. The
structure illustrated in Fig. 1. It consists of a full-bridge voltage
exact feedback linearization theory was applied in the design of the
source PWM inverter, a dc side capacitor Cdc and ac-side high
controller. This control strategy allowed the decoupling of the
frequency inductors Lc that are required to shape the compensator
currents and enhanced their tracking behaviour and improved the dc
input currents i1, i2 and i3.
voltage regulation. The reference signals were obtained by extracting
the harmonic currents from the measured load currents. In the
orthogonal frame the fundamental current component can be seen as
a dc component, and as a consequence, the harmonic load currents
can be extracted with high pass filters (HPF). The HPFs were based
on a fourth order Butterworth low pass filters. The main problem
with this method is the delay which occurs when the control system
is implemented digitally. Even if the HPF would perform perfectly,
not all the harmonic load currents could be filtered. In addition, the
system cannot completely compensate load currents unbalance,
because of the phase shift caused by the filter.
The studies on active power filters which appeared in the literature
[1-20], [25] all ignore the delay time such as current response delay
generated by the boost inductors and DC-link voltage feedback delay
due to the detection circuits.
The delay time caused by the filter control algorithm is due to
lowpass filter used for reference current calculation, and the active
filter natural response determined by boost inductors and DC-link
voltage capacitors [26]. To simplify the current control plant to a
first-order delay type, voltage decouplers, rotating frame
transformation and pole-zero cancellation techniques were used in
current regulators. In [27] the concept of delay time was discussed.
The method considered the instantaneous power delay caused by the
current regulators and DC-link voltage feedback circuit, and
presented load power estimation method to improve the dynamic
response of input power regulation.
A computational control delay compensation method was also
presented in [28], where only the feedforward control of the load
current was used. The method is very effective for decreasing the
magnitudes of the lower order harmonic load currents, but cannot Fig. 1. Basic circuit of shunt active power filter
fully compensate the fast load current transients. The high pass filter
time constant is about 8 ms. It is reported that in the case of load A. Modeling of shunt active filter
current step changes, the system takes about 19ms to reach steady
state. Also, a multistage adaptive filter was discussed in [29]. This Kirchoff’s rules for voltages and currents as applied to this system
method combines a low-pass filter and an adaptive predictive filter, provide us with the three differential equations in the stationary abc
making it possible to extract the sinusoidal active current component frame:

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> Manuscript No: TIE-0754-2008.R3< 3

di1 did
v1 = v1N = Lc + Rc i1 + v1M + vMN Lc + Rc id = Lcωiq − vdc d nd + vd
dt dt
di diq (7)
v2 = v2 N = Lc 2 + Rc i2 + v2M + vMN (1) Lc + Rc iq = − Lcωid − vdc d nq + vq
dt dt
di Let us define the equivalent inputs as:
v3 = v3N = Lc 3 + Rc i3 + v3M + vMN
dt ud = Lcωiq − vdc d nd + vd
Where v1 , v2 , v3 denote the line to ground voltages of the three uq = − Lcωid − vdc d nq + vq (8)
phase balanced system measured at the PCC. The currents id and iq can be controlled independently by acting
Using the following assumptions: upon inputs ud and uq, respectively. By using the error signals
v1 + v2 + v3 = 0 %id = i*d − id and %iq = i*q − iq , and applying proportional integral
i1 + i2 + i3 = 0
compensation, one can choose d nd and d nq such that:
The following relation is obtained:

1
3 ∫
ud = k p%id + ki %id dt
vMN =− ∑
3 m =1
vmM (2)
uq = k p%iq + k ∫%i dt
i q
(9)

The switching function ck of the kth leg of the converter (for k = 1, 2, The transfer function of the proportional-integral compensator is:
3) is defined as: ki
⎧ 1, if Sk is On and Sk' is Off s+
ck = ⎨ (3) Uq ( s ) d U (s) kp
Gi ( s ) =
%I ( s ) = %I ( s ) = k p
' (10)
⎩0, if Sk is Off and Sk is On s
q d
Thus, vkM = ck vdc . The phase k dynamic equation of the filter’s
The closed loop transfer function of the current loop is:
model is given by the following equation: ki
s+
1 ⎛ ⎞
3
dik R 1 v
dt
= − c ik − ⎜ ck −
Lc Lc ⎜⎝ ∑
cm ⎟ vdc + k
3 m =1 ⎟⎠ Lc
(4)
Iq ( s )
I *q ( s )
=
Id ( s )
I *d ( s )
=
kp
Lc
kp
( Rc + k p ) ki
(11)
s2 + s+
A switching state function d nk is defined as: Lc Lc
⎛ 1
3 ⎞ For the optimal value of the damping factor ζ = 2 / 2 , the
d nk = ⎜ ck −
⎜ ∑
cm ⎟
3 m =1 ⎟⎠
(5) theoretical overshoot is 20.79%. Nevertheless, in order to eliminate
⎝ n the zero in the closed loop transfer function, a prefilter G p ( s ) is
The value of d nk depends on the switching state n and on the phase added as shown in Fig. 2.
k . In other words, d nk depends simultaneously on the switching 1
functions of the three legs of the SAPF. This shows the interaction
Gp ( s ) = (12)
1 + ( k p / ki )s
between the three phases.
The resulting transformed model in the synchronous orthogonal The response of the current loops becomes that of a second order
rotating frame is as follows [25]: transfer function with no zero; hence, the following design relations
2
can be easily derived: k p = 2ζωni Lc − Rc and ki = Lcωni .
⎡ Rc ⎤
d nd The control law is given by the equations:
⎢− ω − ⎥ vd + Lcωiq − ud
⎡ ⎤ ⎢ Lc Lc
⎥⎡ i ⎤ ⎡v ⎤ d nd = (13)
d ⎢ id ⎥ ⎢ R d nq
⎥⎢ d ⎥ 1 ⎢ d ⎥ vdc
iq = −ω − c − i + vq (6)
dt ⎢ v ⎥ ⎢ Lc ⎥ ⎢ v ⎥ Lc ⎢ 0 ⎥
q
Lc vq − Lcωid − uq
⎣ dc ⎦ ⎢ d d nq ⎥ ⎣ dc ⎦ ⎣ ⎦
d nq = (14)
⎢ nd 0 ⎥ vdc
⎢⎣ Cdc Cdc ⎥⎦
The inner control loop of the current iq is shown in Fig. 2.

B. Harmonic current control


i*q i q~ uq
1 iq
A proportional-integral control law was derived through Lc s + R c
linearization of the inherently nonlinear SAPF system model, thereby
decoupling the tasks of harmonic load currents tracking and dc Gp ( s )
capacitor voltage regulation. This decoupling allows the SAPF to
compensate for the ac currents and the dc-bus voltage independently
of each other, but results in either one of these decoupled subsystems Fig. 2 The inner control loop of the current iq
to have a dynamic response significantly slower than the other. In
order to obtain a fast dynamic response of harmonic load currents C. Dc voltage regulation
compensation, the structure of a fast inner loop (current tracking
loop), and a slow outer loop (dc voltage regulation loop), is adopted. To maintain some vdc level across the dc capacitor of the SAPF,
The dynamics of the ac currents in (6) can be rewritten as follows: the losses through the active power filter’s resistive-inductive

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> Manuscript No: TIE-0754-2008.R3< 4

branches can be compensated by acting on the supply current. algorithms fix the minimum sampling period of the DSP. The delay
Ideally, it must act on the active current component id : Tcirc brought by the digital circuit is thus equal to Ts. The delivered
dvdc signal by the numerical system has pace in stairs of width Ts. By
Cdc = d nd id + d nq iq (15) carrying out the average over each sampling period, one obtains the
dt
signal s3 . The delay Tsamp resulting from this average over one
An equivalent input udc is defined as:
udc = d nd id + d nq iq (16) sampling period is equal to Ts/2. The delay Tcomp due to the
discretization and the computing time is equal to 3Ts/2. The sampling
To regulate the dc voltage vdc , the error %vdc = v*dc − vdc is passed period for program execution is Ts =52 μ s . Thus, the total delay
through a PI type controller given by: Td is approximately equal 178 µs.

udc = k1%vdc + k2 %vdc dt (17)
The transfer function of the PI compensator is:
k2 s1 s2
s+ s3
U dc ( s ) k1
Gv ( s ) = = k1 (18)
V% dc ( s ) s

The resulting closed loop transfer function is:


ωnv
s+
Vdc ( s ) 2ζ
*
= 2ζωnv 2 2
(19)
Vdc ( s ) s + 2ζωnv s + ωnv
where the proportional and integral gains are:
2
k1 = 2ζωnv Cdc and k2 = ωnv Cdc
Ts
Tsens Tcirc = Ts Tsamp =
2
Fig. 3 illustrates the outer control loop of the dc voltage.
Tcomp

~ Td
v *dc v dc u dc Vdc
1 Fig. 5 Delays generated by the system
C dc s
Where s1: signal without delay, s2: signal at the output of the sensor,
s3: signal at the output of the DSP.

Fig. 3 Dc-bus voltage control loop.


The delay Td involves a dephasing angle θ d 1 = 3.8 degrees at
60Hz, between the reference current and the current injected by the
The control effort of this outer loop is given by the following: SAPF. The proposed strategy consists of creating a phase lead at 60
Hz on the reference currents to compensate for the total delay.
2 vdc Therefore, from the measured voltages vs (θ ) at the PCC, the Phase
i*do = udc (20)
3 Vˆ locked Loop rebuilds the voltages by integrating desired dephasings
( θ sens and θ comp ). Consequently, the reference currents are corrected
The i*do is added to the harmonic reference current of id loop, it and the filter currents behave as desired.
will force the SAPF to generate or to draw a small current at the Where θ sens is the delay caused by boost inductors and DC-link
fundamental frequency. Further, by designing the dc voltage loop capacitor, θ comp is the delay caused by discrete digital
much slower than the current loops, there would not be any implementation and the computing time.
interaction between the two loops. Fig. 4 represents the nonlinear
control of the SAPF.
A. Current controller performance
III. CONTROL DELAY COMPENSATION Fig.6 shows test results of the current controller without control
In this paper, the analytical model and design methods are delay compensation. The d-axis id, the q-axis iq and the phase ‘1’
described in continuous time. In practice, DC-link voltage regulator, active filter current in steady state operation superposed with their
current regulators and lowpass filter are implemented by a PC-based respective references are shown. The results show the appearance of
discrete system. A computational control delay compensation method a time delay between the reference currents and the sensed currents.
is used. The following figure illustrates the total delay resulting from Fig.7 shows the test results of the nonlinear control with the proposed
the chain of acquisition and the real time controller which uses control delay compensation method. The results clearly show that the
oscillating current harmonics injected by the filter track their
sampling period named Ts. The delay time Tsens caused by boost
reference templates with high accuracy. It demonstrates that the
inductors and DC-link capacitor is approximated to 100µs, which computational control delay compensation method performs very
corresponds to a dephasing angle θ sens of 2 degrees at 60 Hz. well.
Moreover, interface communication and computing time of the

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> Manuscript No: TIE-0754-2008.R3< 5

i1 ( θ + θsens ) i 2 ( θ + θsens )

sin ( θ + θsens )

cos ( θ + θcomp + θsens )


cos ( θ + θsens )
sin ( θ + θcomp + θsens )

id
i *d i *d ud d nd
∑ ∑ ∑
i *d 0 Gp ( s ) G i (s)
iq
i *q uq d nq

Gp ( s )
G i (s)

u dc v
dc

G v (s)
v *dc

Fig. 4 Nonlinear control scheme of the shunt active power filter

The system parameters used in these simulations are given in Table I:


IV. SIMULATION RESULTS
TABLE I
The nonlinear control scheme and compensation by SAPF is
SPECIFICATION PARAMETERS
simulated under MATLAB/Simulink and PSB environment to
estimate its performance. The nonlinear load consists of one three-
Line voltage and frequency Vs=50 V (Peak), fs= 60 Hz
phase and one single-phase diode rectifiers so that the effectiveness
Line impedance Ls=0.5 mH
of the nonlinear control scheme to compensate for unbalanced load Three-phase diode rectifiers LL=10mH,
can be tested. The rectifiers are feeding R-L type circuits. The source parameters RLmin=8Ω, RLmax=17Ω
current waveforms of the simulation results have been analyzed to Single-phase diode rectifiers LL=10 mH, RL=40 Ω
obtain their total harmonic distortion (THD) under varying load parameters
conditions. The main purpose of the simulation is set to study three Shunt active power filter parameters Lc= 5 mH, Rc= 0.1 Ω,
different aspects: a) reactive and harmonic load currents Cdc= 1600 μF, Vdc= 200 V
compensation, b) dynamic response of the SAPF to load variations, Switching frequency fsw= 1920 Hz
and c) compensation of non-active load currents.

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Therefore, the maximum rating of the SAPF to achieve non-active


4 load currents compensation represent 37% of the load nominal
power.
id1,id1* (A),
2
0
-2
-4 A. Reactive and harmonic currents compensation of a nonlinear load
0.4 0.402 0.404 0.406 0.408 0.41 0.412 0.414 0.416
The simulation results of the SAPF system are presented in Fig.8.
5
The supply voltage (vs1), load currents (iL123), supply currents (is123),
iq1,iq1* (A)

SAPF currents (ic123) and the dc voltage (vdc) are depicted there. The
0
THD of the current generated by the nonlinear load is observed to be
-5 approximately 25.8%, whereas the compensated supply current has a
0.4 0.402 0.404 0.406 0.408 0.41 0.412 0.414 0.416 THD of approximately 2.62% at steady state. A graphical
representation of the load current (top plot) and the supply current
5 (bottom plot) after SAPF connection appears in Fig.9.a and Fig.9.b.
ic1,ic1* (A)

0 The results presented in Figs. 8 and 9 coincide with the included in


subsection V.A. Figures 13 and 14.
-5

0.4 0.402 0.404 0.406 0.408 0.41 0.412 0.414 0.416 50

v (V)
Time(S) 0

s1
-50
Fig.6 Current controller performance without control delay compensation 0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28

(A)
10
0

L123
-10
4

(A) i
0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28
10
id1,id1* (A),

2 0

s123
-10
0

i
10 0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28
-2

i (A)
0

1
-4 -10
0.384 0.386 0.388 0.39 0.392 0.394 0.396 0.398 0.4 i (A) 10 0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28
0
2

5 -10
iq1,iq1* (A)

0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28
10
i (A)

0 0
3

-10
0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28
-5
202
v (V)

200
dc

0.4 0.402 0.404 0.406 0.408 0.41 0.412 0.414 0.416 198
0.235 0.24 0.245 0.25 0.255 0.26 0.265 0.27 0.275 0.28
Time(S)
5
Fig. 8 Steady state response of the SAPF
ic1,ic1* (A)

0
12
-5
10
0.4 0.402 0.404 0.406 0.408 0.41 0.412 0.414 0.416 8
Time(S)
(A)

6
L1

Fig.7 Waveforms showing the tracking performances of the inner loop


i

4
2

0
One can read, for the case of balanced load, the following main 5 10 15 20 25 30
power magnitudes (active power, reactive power, distortion power, Harmonic order

apparent power) and power factor: PL=818.6W; QL=162VAR; (a)


DL=207.4VAR; SL=859.9VA; PF=95.2%; 12
The SAPF power magnitudes (active power, reactive power,
10
distortion power, apparent power) are: Pc=6.6W; Qc=159VAR; Dc=
8
226.6VAR; Sc= 276.9VA;
is1 (A)

6
The source power magnitudes (active power, reactive power,
4
apparent power) and power factor are: Ps=825.2W; Qs=3VAR;
2
Ss=826.2VA; PF=99.88%;
0
One can deduce that SAPF power rating to compensate reactive and 5 10 15 20 25 30
Harmonic order
harmonic load current components is 32.2% (Sc=32.2%SL) of the
load nominal power. (b)
Fig. 9 Spectrum of phase 1: (a) load current; (b) source current after
For the case of unbalanced nonlinear loads, the fundamental positive-
compensation
sequence active power, reactive power and apparent power are:
PL1+=503.8W; QL1+=65.55VAR; SL=532.1VA.
The SAPF fundamental positive-sequence active power, positive- B. Response of the SAPF to nonlinear load variation
sequence reactive power and apparent power are: Pc1+=8.22W; In practice, nonlinear loads are usually time-varying in nature.
Qc1+=60.8VAR; Sc= 197VA. Therefore, it is necessary to study the dynamic performance of the
The source fundamental positive-sequence active power, positive- SAPF when variations in the nonlinear loads are considered. The
sequence reactive power and apparent power are: Ps1+=512W; nonlinear load current was subjected to 100% step decrease at
Qs1+=4.75VAR; Ss=513VA. t=366.7ms and to 100% step increase at t=483.3ms. In other terms,
the value of the load resistance is changed from 16Ω to 8Ω at t =

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366.7ms, and then changed from 8Ω to 16Ω at t = 483.3ms. The after compensation are balanced. Further, the spectrum analysis of
relevant waveforms are depicted in Fig. 10. These results confirm the load and line currents depicted in Fig. 12 indicates that the SAPF can
good dynamic performance of the SAPF for a rapid change in the largely improve the THD of supply currents while feeding
nonlinear load current. The waveforms presented in Fig. 10 coincide unbalanced load. The THD of the source currents (is123) are reduced
with the included in subsection V.B. As shown in Fig. 15. The respectively from 15.91%, 22.12% and 25.76% before compensation
settling time of DC-link voltage vdc and line current is are less than to 1%, 1.27% and 1.27% after compensation. These results confirm
3ms. Nevertheless, the results show that the computational control the capability of the algorithm to balance the line currents while
delay compensation possesses good dynamic response for both compensating for reactive and harmonic load current components
harmonic current compensation and DC-link voltage regulation. It is simultaneously. The waveforms presented in this subsection and
important to note that the THD of the supply currents are largely showed in Figs. 11 and 12 coincide with those included in subsection
reduced, which is well below the IEEE-519 standard requirement. V. C. Figures 16 and 17. The harmonic contents (peak) of the main
50
load and source currents along with %THD are shown in Table II.
vs1(V)

0
8
-50
6
0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
6
205
vdc(V)

iS1 (A)
iL1 (A)
200 4
195
2 2
0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
10 0 0
is1(A)

5 10 15 20 25 30 5 10 15 20 25 30
0 Harmonic order Harmonic order
-10
0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 8
6
10 6
iL1(A)

0
4

iS2 (A)
i L2 (A)
-10 4

0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 2


2
10
ic1(A)

0 0 0
5 10 15 20 25 30 5 10 15 20 25 30
-10 Harmonic order Harmonic order
0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 ( )
Time(S)
6 6

Fig. 10 Dynamic response of SAPF under varying distorted nonlinear load


4 4

iS3 (A)
iL3 (A)

conditions
2 2
50
is123(A) iL123(A) vs1(V)

0
-50 0
5 10 15 20 25 30
0
5 10 15 20 25 30
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 Harmonic order Harmonic order
10
0 Fig. 12 Spectrum of load currents and source currents after compensation for
-10
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 asymmetrical load conditions
10
0
-10
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18
V. EXPERIMENTAL RESULTS
5
The nonlinear control method is tested on a laboratory prototype of
ic1(A)

0
-5
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18
a SAPF. The SAPF consists of six IGBT modules GA100TS60U of
5 IR. The peak load power is 3.5 kW. The maximum rating of the
ic2(A)

0
-5 SAPF is 1 kVA. The real-time performance of SAPF system with
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 developed algorithm was tested in the laboratory for several different
5
ic3(A)

0 operating conditions such as – steady-state, transient condition, and


-5
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 under unbalanced nonlinear load. The experimental results are
205
presented in Figs. 13 – 17 and discussed in the following subsections.
vdc(V)

200
195
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18
Time(S)
A. Steady state performance of the nonlinear control scheme with
Fig. 11 Steady state response of SAPF with nonlinear load unbalances. SAPF harmonic load currents compensation
Experimental results aimed to validate the simulation results of the
C. Compensation of non-active load currents nonlinear control have been obtained for steady state operation mode
With the adopted control algorithm, this test aims to evaluate the as shown in Fig.13. These results show the effectiveness of the SAPF
capability of the SAPF to compensate for non-active load currents. to compensate harmonic currents created by three-phase diode
To carry out this, the load consists of a three-phase diode rectifier rectifier type of load. In this figure, the supply voltage (vs1) in phase-
1, the load currents (iL123), the supply currents (is123) and the
followed by inductor LL = 10mH in series with a resistor
compensating currents of the SAPF (ic123) are presented. The
RL = 16 Ω and a single-phase diode rectifier followed by inductor harmonic spectrums of load and source currents have been given in
LL = 10mH in series with a resistor RL = 40Ω . The single-phase Figs.14a-b, respectively. The compensated source current profile
shows that the SAPF was working effectively, thus reducing the
rectifier is connected between phases 1 and 2 as shown in Fig. 1. The source current THD from 26 % to 3.1 %. This significant reduction
supply voltage (vs1), unbalanced three phase load currents (iL123), occurred when the utility voltage measured THD is 8.8 %;
supply currents (is123), SAPF currents (ic123), and dc bus voltage of consequently, the SAPF system is able to reduce the source current
the SAPF are shown in Fig. 11. One notes that these supply currents THD (3.1%) well below the IEEE-519 standard requirement.

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> Manuscript No: TIE-0754-2008.R3< 8

TABLE II
MAIN HARMONIC CONTENTS OF SIMULATED SOURCE CURRENTS

Before Compensation After Compensation


Peak current Is1 Peak current Is2 Peak current Is3 Peak current Is1 Peak current Is2 Peak current Is3
(A) (A) (A) (A) (A) (A)
Fundamental 7.02 7.00 5.17 6.76 6.77 6.68
3rd 0.01 0.01 0.01 0.08 0.05 0.05
5th 1.07 1.09 1.09 0.01 0.04 0.03
7th 0.61 0.6 0.62 0.01 0.02 0.02
9th 0.00 0.01 0.01 0.04 0.02 0.03
11th 0.41 0.42 0.42 0.01 0.01 0.02
13th 0.32 0.31 0.33 0.01 0.02 0.01
15th 0.00 0.01 0.01 0.01 0.02 0.02
17th 0.23 0.24 0.23 0.00 0.02 0.02
19th 0.19 0.19 0.20 0.02 0.00 0.02
21st 0.00 0.01 0.01 0.01 0.01 0.01
THD 19.81% 20.01% 27.41% 1.74% 1.69% 1.65%

B. Dynamic performance of the active power filter


Fig. 15 shows the transient response of the SAPF during sudden
variations in nonlinear load. It also shows SAPF dc-bus voltage,
phase 1 supply, load and the filter currents. The load current is
abruptly decrease from 7.85A (rms) to 3.8A (rms) and then increased
from 3.8A (rms) to 7.85A (rms). As viewed from the experimental
results, the changeover from one operating condition to the other is
quite smooth, therefore maintaining excellent compensation. The
increase of load current will be supplied immediately from the SAPF
resulting in decreased energy storage of dc bus capacitor. This
reduction in dc bus voltage of the SAPF will activate the dc voltage
controller to increase the supply current. This increased source
current tries to restore the stored energy of the capacitor in addition
to increased load active power. Within one cycle, supply current
settles to steady state value. Similarly, the reverse action takes place
as the load current decreases from 7.85A (rms) to 3.8A (rms),
causing the DC link to increase slightly, as shown in Fig. 15. This
will decrease supply current momentarily to reduce the capacitor
voltage at set reference value. Within one cycle of ac source, the
supply current settles to steady-state value. Since the corrective
action of the voltage controller is taken within a half cycle of the ac
Fig. 13 Steady state response of the SAPF with diode rectifier load mains it results in fast response of the scheme. It was observed that
this dip in DC link voltage was around 7V for 200V DC link (3.5%).
Nevertheless, the conditions discussed above prove that the APF
system compensates the reactive and harmonic load current
components during steady-state as well as during transient operating
conditions.

C. Compensation of reactive, unbalanced, and harmonic load current


components
(a) The SAPF consists of six IGBT ( S1 ,S 2 S3 ,S1' ,S 2' ,S3' ). The load
8
consists of a three-phase and single-phase diode rectifiers followed
is1(A)
6 by inductor LL in series with a resistor RL. The single-phase rectifier
is connected between phases 1 and 2 by closing the switch SW as
rms 4
shown in Fig. 1. The global load currents containing asymmetrical
2
components are shown in Fig. 16. This Figure illustrates the supply
0
DC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
voltages (vs1) of phase 1, the unbalanced three phase load currents
Harmonic (iL123), the supply currents (is123) and the SAPF currents (ic123). One
(b)
can note that supply currents after compensation are balanced. The
Fig. 14 Spectrum of the supply current in phase 1: (a) before compensation, spectral analysis of load and line currents is performed, using Fluke
(b) after compensation Model 41B Power Harmonics Analyzer. The results depicted in Fig.
17. shows the ability of the SAPF to improve the THD of supply
currents with unbalanced load. The RMS source currents before

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> Manuscript No: TIE-0754-2008.R3< 9

compensation was I s1 = 4.31 A , I s 2 = 4.64 A and I s3 = 3.23 A ;


I S1 RMS = 4.56 A
therefore, after compensation these currents after compensation I L1 RMS = 4.31 A

iL1 (A)

is1 (A)
become equals I s1 = I s 2 = I s3 = 4.56 A . The THD of the source THD = 13.6% THD = 2.9%

currents (is123) are reduced respectively from 13.6%, 14% and 21%
before compensation to 2.9%, 3% and 2.3% after compensation. The
SAPF system works as expected. The compensated source currents,
as viewed from Fig. 16, are sinusoidal and close to balanced. The I L2 RMS = 4.64 A I S2 RMS = 4.56 A
filter currents suggest that the SAPF system inject different currents

iL2 (A)

is2 (A)
THD = 14% THD = 3%
to compensate non-active load current demands in each phase. This
proves that the control approach with SAPF system can handle the
most critical situation in power distribution system quite effectively.

I L3 RMS = 3.23 A I S3 RMS = 4.56 A


vdc

iL3 (A)

is3 (A)
THD = 21% THD = 2.3%
is1

iL1 Fig. 17 Harmonic spectra of load currents and supply currents

i1 VI. CONCLUSION
The nonlinear control algorithm of a SAPF has been implemented
to enhance its response for compensation of non-active load
currents. The nonlinear control technique of the SAPF has been
designed which is based on two inner current loops and an outer dc
bus voltage regulator loop. It has been observed that there is no
interaction between inner and outer loops in addition to good
performance in both steady state and transient operations. Simulation
and experimental results have validated the nonlinear control
approach of the SAPF. It has been shown that the system has a 1.5
cycles for outer voltage loop and 0.5 cycles for inner current loop
and is able to keep the THD of the supply current below the limits
specified by the IEEE-519 standard. The obtained results have
demonstrated the high performance of the SAPF.
Fig. 15 Dynamic response of the SAPF under varying distorted nonlinear load
conditions

ACKNOWLEDGMENT
The authors gratefully thank Canada Research Chair in Energy
v s1 Conversion and Power Electronics at the École de Technologie
Supérieure for their financial support.

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Copyright (c) 2009 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on July 04,2010 at 17:25:20 UTC from IEEE Xplore. Restrictions apply.
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> Manuscript No: TIE-0754-2008.R3< 10

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> Manuscript No: TIE-0754-2008.R3< 11

Kamal Al-Haddad (S’82–M’88–SM’92–F’07)


was born in Beirut, Lebanon, in 1954. He
received the B.Sc.A. and M.Sc.A. degrees from
the University of Québec à Trois-Rivières,
Trois-Rivières, QC, Canada, in 1982 and 1984,
respectively, and the Ph.D. degree from the
Institut National Polythechnique, Toulouse,
France, in 1988.
From June 1987 to June 1990, he was a
Professor with the Engineering Department,
Université du Québec à Trois Rivières. Since
June 1990, he has been a Professor with the
Electrical Engineering Department, École de
Technologie Supérieure (ETS), Montreal, QC, where he has been the holder of
the Canada Research Chair in Electric Energy Conversion and Power
Electronics since 2002. He has supervised more than 60 Ph.D. and M.Sc.A.
students working in the field of power electronics. He was the Director of
graduate study programs at the ETS from 1992 to 2003. He is a Consultant
and has established very solid link with many Canadian industries working in
the field of power electronics, electric transportation, aeronautics, and
telecommunications. He is the Chief of ETS-Bombardier Transportation North
America division, a joint industrial research laboratory on electric traction
system and power electronics. He is the Coauthor of the Power System
Blockset software of Matlab. He has coauthored more than 250 transactions
and conference papers. His fields of interest are in high efficient static power
converters, harmonics and reactive power control using hybrid filters, switch
mode and resonant converters including the modeling, control, and
development of prototypes for various industrial applications in electric
traction, power supply for drives, telecommunication, etc.
Prof. Al-Haddad is a fellow member of the Canadian Academy of
Engineering, a life member of the Circle of Excellence of the University of
Quebec and received the outstanding researcher award from ETS in 2000. He
is active in the IEEE Industrial Electronics society where he is Vice President
for Publication, an AdCom member and serves as an Associate Editor of the
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS.

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