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D Q
combinatorial output
input0 logic cloud
input0
reset
D Q
clk
-But the added combinatorial logic grows and may cancel out the benefit.
-Synchronous resets provide some filtering for the reset line such that
it is not effected by glitches unless they occur right at the clock edge.
-The reset buffer tree may be pipelined to keep all the resets occurring
within the same clock cycle.
-Unless care is taken with logic synthesis, the reset signal may take the fastest path to the
D input making worse case timing hard to meet.
logic
cloud
D Q
logic output
input0 cloud’
input0
reset D Q
clk
-No filtering of reset line is available for inputs coming directly from
Vdd
D Q D Q master_reset_n
reset_n_dly R R
clk
delay flt_reset_n
reset_n
reset glitch filter
-However the allowed skew is greater because it is only necessary for reset
to be removed sometime prior to the next clock edge.