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ENGINEERING COLLEGES

2016 – 17 Odd Semester


COMMON MINIMUM STUDY MATERIAL (MSM)
Department of ECE

SUBJECT CODE: EC6013

SUBJECT NAME: ADVANCED MICROPROCESSOR AND MICROCONTROLLERS

Regulation: 2013 Year and Semester: IV/VII

Prepared by
Sl.
Name of the Faculty Designation Affiliating College
No.
1 Mr. V. Parvathinathan AP/ ECE SCADCET

2 Mrs. M. Maryam Sumaya AP/ ECE SCADCET

3 Mr. B. Sweetlinson AP/ ECE SMTEC

4 Mrs. S. Josethana AP/ ECE SMTEC

Verified by DLI, CLI and Approved by the Centralized Monitoring Team dated
_________________.

1
EC6013 ADVANCED MICROPROCESSORS AND MICROCONTROLLERS L T P C
3003

OBJECTIVES:

 To expose the students to the fundamentals of microprocessor architecture.


 To introduce the advanced features in microprocessors and microcontrollers.
 To enable the students to understand various microcontroller architectures.

UNIT I HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUM 9


CPU Architecture- Bus Operations – Pipelining – Brach predication – floating point
unit- Operating Modes –Paging – Multitasking – Exception and Interrupts –
Instruction set – addressing modes – Programming the Pentium processor.

UNIT II HIGH PERFORMANCE RISC ARCHITECTURE – ARM 9


Arcon RISC Machine – Architectural Inheritance – Core & Architectures - Registers –
Pipeline - Interrupts – ARM organization - ARM processor family – Co-processors -
ARM instruction set- Thumb Instruction set - Instruction cycle timings - The ARM
Programmer’s model – ARM Development tools – ARM Assembly Language
Programming - C programming – Optimizing ARM Assembly Code – Optimized
Primitives.

UNIT III ARM APPLICATION DEVELOPMENT 9


Introduction to DSP on ARM –FIR filter – IIR filter – Discrete fourier transform –
Exception handling – Interrupts – Interrupt handling schemes- Firmware and
bootloader – Embedded Operating systems – Integrated Development Environment-
STDIO Libraries – Peripheral Interface – Application of ARM Processor - Caches –
Memory protection Units – Memory Management units – Future ARM Technologies.

UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS 9


Instruction set addressing modes – operating modes- Interrupt system- RTC-Serial
Communication Interface – A/D Converter PWM and UART.
100
UNIT V PIC MICROCONTROLLER 9
CPU Architecture – Instruction set – interrupts- Timers- I2C Interfacing –UART- A/D
Converter –PWM
and introduction to C-Compilers.

TOTAL: 45 PERIODS
OUTCOMES:
 The student will be able to work with suitable microprocessor / microcontroller
for a specific real world application.
TEXT BOOK:
1. Andrew N.Sloss, Dominic Symes and Chris Wright “ ARM System Developer’s
Guide : Designing and Optimizing System Software” , First edition, Morgan
Kaufmann Publishers, 2004.
2
REFERENCES:
1. Steve Furber , “ARM System –On –Chip architecture”, Addision Wesley, 2000.
2. Daniel Tabak , “Advanced Microprocessors”, Mc Graw Hill. Inc., 1995
3. James L. Antonakos , “ The Pentium Microprocessor”, Pearson Education, 1997.
4. Gene .H.Miller, “Micro Computer Engineering”, Pearson Education , 2003.
5. John .B.Peatman , “Design with PIC Microcontroller”, Prentice Hall, 1997.
6. James L.Antonakos, “An Introduction to the Intel family of Microprocessors”,
Pearson
Education, 1999.
7. Barry.B.Brey,“The Intel Microprocessors Architecture, Programming and
Interfacing”,
PHI,2002.
8. Valvano, "Embedded Microcomputer Systems", Thomson Asia PVT LTD first
reprint 2001.
Readings: Web links www.ocw.nit.edu www.arm.com

3
EC6013 ADVANCED MICROPROCESSORS AND MICROCONTROLLERS L T P C
3003
1. Aim and Objective of the Subject
The student should be made
 To expose the students to the fundamentals of microprocessor architecture.
 To enable the students to understand various microcontroller architectures.
 To introduce the advanced features in microprocessors and
microcontrollers.
 To enable the students to understand various microcontroller architectures.
 To expose the students to the applications of microprocessors and
microcontrollers.

2. Need and Importance for Study of the Subject


 The student will be able to work with suitable microprocessor /
microcontroller for a specific real world application.

3. Industry Connectivity and Latest Developments

Industry Connectivity:
 The following companies (Industries) are linked to Advanced Microprocessor
and Microcontroller:
C-DAC, NIELIT and Bharat Electronics Ltd (BEL),

Latest Developments:
 Application class processors are finding their way into the embedded sector
as system complexity increases

 ARM-processor tool-chains accelerate safety-critical compliance

 The launch of the AMD Opteron 6200 and 4200 Series Embedded Processors
has delivers better performance, efficiency and scalability.

4. Industrial Visit (Planned if any): -Nil-

4
SCAD GROUP OF INSTITUTIONS
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Detailed Lesson Plan

Name of the Subject & Code: EC6013 ADVANCED MICROPROCESSORS AND


MICROCONTROLLERS
Name of the Faculty:
1. Mr. Parvathinathan V, AP/ECE, SCADCET
2. Mrs. Maryam Sumayal, AP/ECE, SCADCET
3. Mr. B. Sweetlinson AP/ECE, SMTEC
4. Mrs. S. Josethana, AP/ECE, SMTEC

TEXT BOOK:
1. Andrew N.Sloss, Dominic Symes and Chris Wright “ ARM System Developer’s
Guide : Designing and Optimizing System Software” , First edition, Morgan
Kaufmann Publishers, 2004.

REFERENCES:
1. Steve Furber , “ARM System –On –Chip architecture”, Addision Wesley, 2000.
2. Daniel Tabak , “Advanced Microprocessors”, Mc Graw Hill. Inc., 1995
3. James L. Antonakos , “ The Pentium Microprocessor”, Pearson Education, 1997.
4. Gene .H.Miller, “Micro Computer Engineering”, Pearson Education , 2003.
5. John .B.Peatman , “Design with PIC Microcontroller”, Prentice Hall, 1997.
6. James L.Antonakos, “An Introduction to the Intel family of Microprocessors”,
Pearson Education, 1999.
7. Barry.B.Brey,“The Intel Microprocessors Architecture, Programming and
Interfacing”,
PHI,2002.
8. Valvano, "Embedded Microcomputer Systems", Thomson Asia PVT LTD first
reprint 2001. Readings: Web links www.ocw.nit.edu www.arm.com

5
S. WEEK TOPIC NAME NO. OF TEXT BOOK PAGE NO.
NO. HOURS

UNIT I HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUM


1 WEEK 1 CPU Architecture- Bus 1 R7 51-57
Operations
2 Pipelining – Brach 1 R1 22-24
predication
3 floating point unit- 1 R7
Operating
WEEK 2 Modes
Paging 296
4 1 T1
Multitasking – Exception and 389 -393
5 1 R1
Interrupts
6 Instruction set 2 R7 883-894

7 WEEK 3 addressing modes 2 R7 78-103

Programming the Pentium


8 1 Notes
processor
UNIT II HIGH PERFORMANCE RISC ARCHITECTURE – ARM

WEEK 4 Acorn RISC Machine – 37


9 1 R1
Architectural Inheritance
Core & Architectures 34
10 1 T1
Registers – Pipeline- 21
11 1 T1
Interrupts
WEEK 5 ARM processor family – Co- 36
12 2 T1
processors
ARM instruction set- Thumb 47
13 2 T1
Instruction set
WEEK 6 The ARM Programmer’s 39
14 2 T1
model – ARM Development
ARM
tools Assembly Language 157
15 1 T1
Programming
Optimizing ARM Assembly 207
16 1 T1
Code-Optimized Primitives
UNIT III ARM APPLICATION DEVELOPMENT

WEEK 7 Introduction to DSP on ARM 269


17
1 T1
–FIR filter

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18 IIR filter – Discrete fourier 294
transform 1 T1
19 Exception handling – 317
Interrupts – Interrupt 1 T1
20 Firmware and boot loader –
handling schemes 367
Embedded Operating 1 T1
21 WEEK 8 Integrated
systems Development
Environment- STDIO 1 Notes
22 Peripheral
Libraries Interface
1 Notes
23 ARM Processor - Caches 403
2 T1
24 WEEK 9 Memory protection Units 461
1 T1
25 Memory Management units 491
2 T1
26 Future ARM Technologies. 1 T1 549

UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS

27
WEEK Instruction set 2 Notes
10
28 addressing modes 2
Notes
29 operating modes- Interrupt 1
system Notes
30 RTC-Serial Communication 1
Interface Notes
31
WEEK A/D Converter 1
11 Notes
32 PWM 1
Notes
33 UART. 1
Notes
UNIT V PIC MICROCONTROLLER

34 WEEK CPU Architecture 27


1 R5
12
35 Instruction set 38
2 R5
36 interrupts- Timers 1 72
R5
37 I2C Interfacing 1 176
R5

7
38 WEEK UART- A/D Converter 1 206,195
R5
13
39 PWM 1 126
R5
40 introduction to C-Compilers 2
Notes

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TABLE OF CONTENT
S.No TITLE PAGE NO
UNIT 1 - HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUM
PART A 1
PART B
1 Pentium Processor architecture 3
2 Pentium Special registers 6
3 Paging mechanism in Pentium Processor 7
4 Addressing modes of Pentium Processor 10
5 Instruction set of Pentium processor 15
UNIT 2 - HIGH PERFORMANCE RISC ARCHITECTURE – ARM
PART A 18
PART B
1 Arm instruction set 20
2 Thumb instruction set 25
3 Architecture of arm processors 28
4 Pipe line 31
5 Interrupts 32
UNIT 3 - ARM APPLICATION DEVELOPMENT
PART A 34
PART B
1 Interrupt handling schemes 36
2 FIR and IIR filters on ARM 38
3 Memory Management Unit (MMU) of Arm 41
4 Embedded operating system 44
5 Cache Memory of ARM Processor 46
UNIT 4 - MOTOROLA 68HC11 MICROCONTROLLERS
PART A 50
PART B
1 Block diagram of 68HC11. MODEL 52
2 Addressing modes of 68 HC 11 micro controllers 55
3 UART interface with Motorola micro controller 58
4 A/D conversion process in 68HC11 microcontrollers 62
5 Instruction set of 68HC11 microcontroller 64
UNIT 5 - PIC MICROCONTROLLER
PART A 70
PART B
1 Interrupts handing in PIC micro controller 72
2 Architecture of PIC micro controllers. 75
Features of UART and A/D converter in PIC micro
3 78
controller
5 I2C interfacing with PIC micro controller 81
6 Program and data memory of PIC microcontrollers 84

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UNIT 1 HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUM

PART A

1. What are the features of Pentium Microprocessor?


• The Pentium microprocessor is almost identical to the earlier 80386 and 80486
microprocessors.
• The main difference is that the Pentium has been modified in-ternally to contain a
dual cache (instruction and data) and a dual integer unit.
• The Pentium also operates at a higher clock speed of 66 MHz.
• The data bus on the Pentium is 64 bits wide and contains eight byte-wide memory
banks selected with bank enable signals.
• The superscalar structure of the Pentium contains three independent process-ing
units: a floating-point processor and two integer processing units labeled U and V by
Intel.
• The cache structure of the Pentium is modified to include two caches.
• A new mode of operation called the system memory-management (SMM) mode has
been added to the Pentium.
• The built-in self-test (BIST) allows the Pentium to be tested when power is first
applied to the system.
• The pin-out of the Pentium processor, packaged in a huge 237-pin PGA (pin grid
array)
• Pentium is available in two versions:
i. the full-blown Pentium
ii. P24T version called the Pentium Overdrive
• P24T version contains a 32-bit data bus, for insertion into 80486 machines which
contain the P24T socket
• Memory system for the Pentium is 4G bytes.
– just as in 80386DX and 80486 processors
• It has Built In Self Test (BIST) feature.

2. What is a Superscalar processor?


The ability to process more than one instruction per clock. The Pentium processor
has two execution pipes (U and V) so it is superscalar level 2. The P6 can dispatch and
retire 3 instructions per clock so it is superscalar lever 3.

3. Name few special Pentium registers.


 Control Reg. 4
 EFLAG Reg. bit pattern
 Machine Check type Reg.

4. Define: Pipeling (or) Pipeline processing.


A micro architecture design technique that divides the execution of an instruction
into sequential steps, using different resources at each step. Pipelined machines have
multiple IA instructions executing at the same time, but at different stages in the

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machine. For example, while one instruction is being executed, the computer is
decoding the next instruction.

5. What are the stages of Pentium Pipeline?


Pre-fetch/Fetch : Instructions are fetched from the instruction cache and aligned in
pre-fetch buffers for decoding.
Decode1 : Instructions are decoded into the Pentium's internal instruction format.
Branch prediction also takes place at this stage.
Decode2 : Same as above, and microcode ROM kicks in here, if necessary. Also, address
computations take place at this stage.
Execute : The integer hardware executes the instruction.
Write-back : The results of the computation are written back to the register file.

6. Define: Dynamic pipeline.


A parallel pipeline that supports out of Order execution is called dynamic pipeline.
It is used in the superscalar architecture.

7. What is branch prediction?


A branch predictor is the part of a processor that determines whether a
conditional branch (jump) in the instruction flow of a program is likely to be taken or
not. This is called branch prediction.

8. What are the main purposes of branch prediction?


The main purpose of branch prediction is to minimize branch penalty and maximize the
Throughput when a branch is encountered in pipeline. Two fundamental components of
branch prediction are i) branch target speculation and ii) branch condition
speculation.

9. Define: Selector and Descriptor.


Selector: A selector that selects a descriptor from a descriptor table.
Descriptor: The descriptor is located in the segment register & describes the location,
length, and access rights of the segment of memory.

10. What are the primary operating modes of Pentium Processor?


Protected Mode - In this mode all instructions and architectural features are available,
providing the highest performance and capability.
Real-Address Mode - This mode provides the programming environment of the Intel
8086 processor, with a few extensions.

11. Define: Multitasking


Multitasking refers to the ability of the operating system to run multiple tasks
concurrently. True multitasking can only be achieved on a multiprocessor machine
where each task is scheduled for execution on a different processor.

2
12. Define: Paging
paging is a memory management scheme by which a computer stores and retrieves
data from secondary storage. In this scheme, the operating system retrieves data from
secondary storage in same-size blocks called pages. Paging is an important part
of virtual memory implementations in modern operating systems

13. What is exception handling?


Exceptions are situations where the processor needs to stop executing current code
because of an error. In these cases the processor typically begins running an exception
handling routine to resolve the error and then returns to the normal program flow. The
exceptions can be internal or external.

14. What are the components used for page address translation?
Three components are used in page address translation:
- the page directory
- the page table
- the actual physical memory page

15. Compare RISC and CISC.

RISC CISC
Small Number of instructions(not exceed More no. of instructions
128)
Single cycle execution of all instructions. Instructions may require more than one cycle
for execution
Small no. of instruction formats (not exceed More no. of instruction formats
about 4)
Small no. of addressing modes (not exceed More addressing modes are available
about 4)

PART B
1. Explain in detail about Pentium Processor architecture (or) Explain the features
of Pentium Processor.
Features of Pentium Processor:
• The Pentium microprocessor is almost identical to the earlier 80386 and 80486
microprocessors.
• The main difference is that the Pentium has been modified in-ternally to contain a
dual cache (instruction and data) and a dual integer unit.
• The Pentium also operates at a higher clock speed of 66 MHz.
• The data bus on the Pentium is 64 bits wide and contains eight byte-wide memory
banks selected with bank enable signals.

3
• The superscalar structure of the Pentium contains three independent process-ing
units: a floating-point processor and two integer processing units labeled U and V by
Intel.
• The cache structure of the Pentium is modified to include two caches.
• A new mode of operation called the system memory-management (SMM) mode has
been added to the Pentium.
• The built-in self-test (BIST) allows the Pentium to be tested when power is first
applied to the system.
• The pin-out of the Pentium processor, packaged in a huge 237-pin PGA (pin grid
array)
• Pentium is available in two versions:
i. the full-blown Pentium
ii. P24T version called the Pentium Overdrive
• P24T version contains a 32-bit data bus, for insertion into 80486 machines which
contain the P24T socket
Memory system for the Pentium is 4G bytes.
b. just as in 80386DX and 80486 processors
It has Built In Self Test (BIST) feature.

Branch Prediction Logic:


• Used by Pentium to reduce time required for a branch caused by internal delays.
• Delays are minimized when a branch is encountered, because the processor begins
prefetch instruction at the branch address.
• If the branch prediction logic errs, the branch requires an extra three clocking
periods to execute.
– in most cases, branch prediction is correct and no delay ensues.

Cache Structure:
• Pentium contains two 8K-byte cache memories instead of one as in 80486.
– one 8K-byte instruction cache stores only instructions
– another 8K-byte cache stores data used by instructions
• In the 80486 unified cache, a data-intensive program quickly filled the cache, and
slowed execution speed.
– this cannot occur in Pentium separate caches.

Superscalar Architecture:
• Pentium has three execution units.
– One executes floating-point instructions
– the other two (U-pipe and V-pipe) execute integer instructions

This means it is possible to execute three instructions simultaneously. Pentium can


simultaneously execute two integers and one MMX instruction.

4
Fig. Superscalar Architecture of Pentium

5
2. Explain in detail about Pentium Special registers (or) Explain in detail about
Pentium control registers
Pentium is essentially the same as 80386 and 80486
a. except some additional features and changes to the control register set have
occurred.

Control Registers :

– a new control register, CR4, has been added to the control register array .

PG Selects page table translation of linear addresses into physical addresses when
PG = 1. Page table translation allows any linear address to be assigned any physical
memory location.
ET Selects the 80287 coprocessor when ET _ 0 or the 80387 coprocessor when
ET.
TS switched tasks (in protected mode, changing the contents of TR places a 1 into
TS). If TS 1, a numeric coprocessor instruction causes a type 7 (coprocessor not
available) interrupt.
EM The emulate bit is set to cause a type 7 interrupt for each ESC instruction.
MP is set to indicate that the arithmetic coprocessor is present in the system.

PE Is set to select the protected mode of operation


NW Not write-through selects the mode of operation for the data cache. If NW = 1,
the data cache is inhibited from cache write-through.
AM Alignment mask enables alignment checking when set. Note that alignment
checking only occurs for protected mode operation when the user is at privilege
level 3.
WP Write protect protects user-level pages against supervisor-level write
operations. When WP = 1, the supervisor can write to user-level segments.

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NE Numeric error enables standard numeric coprocessor error detection. If NE = 1,
the pin FERR becomes active for a numeric coprocessor error. If NE = 0, any
coprocessor error is ignored.
VME Virtual mode extension enables support for the virtual interrupt flag in
protected mode. If VME = 0, virtual interrupt support is disabled.
PVI Protected mode virtual interrupt enables support for the virtual interrupt
flag in protected mode.
TSD Time stamp disable controls the RDTSC instruction.
DE Debugging extension enables I/O breakpoint debugging extensions when set.
PSE Page size extension enables 4M-byte memory pages when set.
MCE Machine check enable enables the machine checking interrupt.

EFLAG Register

- The extended flag (EFLAG) register has been changed in the Pentium
microprocessor
– four new flag bits have been added to control or indicate conditions about
some of the new features in the Pentium

ID The identification flag is used to test for the CPUID instruction. If a program can set
and clear the ID flag, the processor supports the CPUID instruction.

VIP Virtual interrupt pending indicates that a virtual interrupt is pending.

VIF Virtual interrupt is the image of the interrupt flag IF used with VIP.

AC Alignment check indicates the state of the AM bit in control register 0.

Built-In Self-Test (BIST):


The built-in self-test (BIST) is accessed on power-up by placing a logic 1 on INIT while the
RESET pin changes from 1 to 0.

3. Explain in detail the Paging mechanism in Pentium Processor. (or) Explain in


detail about the Memory Management Unit (MMU) of Pentium.

The memory paging mechanism located within the 80386 and above allows any
physical memory location to be assigned to any linear address.
The linear address is defined as the address generated by a program. The physical
address is the actual memory location accessed by a program.

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With the memory paging unit, the linear address is invisibly translated to any
physical address, which allows an application written to function at a specific address to be
relocated through the paging mechanism. It also allows memory to be placed into areas
where no memory exists.

Paging Registers
 The paging unit is controlled by the contents of the microprocessor’s control registers.
 Beginning with the Pentium, an additional control register labeled CR4 controls
extensions to the basic architecture provided in the Pentium or newer microprocessor.
One of these features is a 2M- or a 4M-byte page that is enabled by controlling CR4.
 The registers important to the paging unit are CR0 and CR3. The leftmost bit (PG)
position of CR0 selects paging when placed at a logic 1 level. If the PG bit is cleared (0),
the linear address generated by the program becomes the physical address used to
access memory.
 If the PG bit is set (1), the linear address is converted to a physical address through the
paging mechanism.
 The paging mechanism functions in both the real and protected modes.
 CR3 contains the page directory base or root address, and the PCD and PWT bits.

Structure of Control Register

The linear address, as it is generated by the software, is broken into three sections that are
used to access the page directory entry, page table entry, and memory page offset
address. Figure 2–12 shows the linear address and its makeup for paging.

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The Page Directory and Page Table
Figure 2–13 shows the page directory, a few page tables, and some memory pages. There is
only one page directory in the system. The page directory contains 1024 double word
addresses that locate up to 1024 page tables. The page directory and each page table are 4K
bytes in length.

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Paging in Pentium

To fully re-page 4G bytes of memory, the microprocessor requires slightly over 4M


bytes of memory just for the page tables. In the Pentium, with the new 4M-byte paging
feature, this is dramatically reduced to just a single page directory and no page tables. The
new 4M-byte page sizes are selected by the PSE bit in control register 0.
The main difference between 4K paging and 4M paging is that in the 4M paging
scheme there is no page table entry in the linear address.

Memory-Management Mode
The system memory-management mode (SMM) is on the same level as protected
mode, real mode, and virtual mode, but it is provided to function as a manager.
Access to the SMM is accomplished via a new external hardware interrupt applied to
the SMI’ pin on the Pentium. When the SMM interrupt is activated, the processor begins
executing system-level software in an area of memory called the system management RAM,
or SMMRAM, called the SMM state dump record.
The SMI’ interrupt disables all other interrupts that are normally handled by user
applications and the operating system. A return from the SMM interrupt is accomplished
with a new instruction called RSM.

4. Explain in detail about the addressing modes of Pentium Processor.

Addressing Modes

• Addressing mode refers to the specification of the location of data required by an


operation
• Pentium supports three fundamental addressing modes:

10
* Register mode
* Immediate mode
* Memory mode
• Specification of operands located in memory can be done in a variety of ways
* Mainly to support high-level language constructs and data structures

Pentium Addressing Modes (32-bit Addresses)

Addressing Modes

Register Immediate Memory

Direct Indirect
[disp]

Register Indirect Based Indexed Based-Indexed


[Base] [Base + disp] [(Index * scale) + disp]

Based-Indexed Based-Indexed
with no scale factor with scale factor
[Base + Index + disp] [Base + (Index * scale) + disp]

Simple Addressing Modes


--Register Addressing Mode--
• Operands are located in registers
• It is the most efficient addressing mode
* No memory access is required
* Instructions tend to be shorter
» Only 3 bits are needed to specify a register as opposed to at least 16 bits for a
memory address
• An optimization technique:
* Place the frequently accesses data (e.g., index variable of a big loop) in registers

--Immediate Addressing Mode--


• Operand is stored as part of the instruction
• This mode is used mostly for constants
• It imposes several restrictions:
Typically used in instructions that require at least two operands (exceptions like

11
push exist)
* Can be used to specify only the source operands (not the destination operand)
* Another addressing mode is required for specifying the destination operand
• Efficient as the data comes with the instructions (instructions are generally pre
fetched)
--Memory Addressing Modes--
• Pentium offers several addressing modes to access operands located in memory
» Primary reason: To efficiently support high-level language constructs and data
structures.
• Available addressing modes depend on the address size used
16-bit modes (shown before)
» same as those supported by 8086
* 32-bit modes (shown before)
» supported by Pentium
» more flexible set

32-Bit Addressing Modes


• These addressing modes use 32-bit registers
Segment + Base + (Index * Scale) + displacement
CS EAX EAX 1 no displacement
SS EBX EBX 2 8-bit displacement
DS ECX ECX 4 32-bit displacement
ES EDX EDX 8
FS ESI ESI
GS EDI EDI
EBP EBP
ESP
Differences between 16- and 32-bit Modes

16-bit addressing 32-bit addressing

Base register BX, BP EAX, EBX, ECX,


EDX, ESI, EDI,
EBP, ESP
Index register SI, DI EAX, EBX, ECX,
EDX, ESI, EDI,
EBP
Scale factor None 1, 2, 4, 8

Displacement 0, 8, 16 bits 0, 8, 32 bits

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16-bit or 32-bit Addressing Mode?
• Uses the D bit in the CS segment descriptor
D=0
» default size of operands and addresses is 16 bits
D=1
» default size of operands and addresses is 32 bits
• We can override these defaults
Pentium provides two size override prefixes
66H operand size override prefix
67H address size override prefix
• Using these prefixes, we can mix 16- and 32-bit data and addresses

--Direct Addressing--

• Offset (i.e., effective address) is specified as part of the instruction


» The assembler replaces variable names by their offset values during the
assembly process
» Useful to access only simple variables
Example
total_marks =
translated assign_marks + test_marks + exam_marks
into
mov EAX,assign_marks
add EAX,test_marks
add EAX,exam_marks
mov total_marks,EAX

-- Register Indirect Addressing--

• Effective address is placed in a general-purpose register


• In 16-bit segments
* only BX, SI, and DI are allowed to hold an effective address
add AX,[BX] is valid
add AX,[CX] is NOT allowed
• In 32-bit segments
* any of the eight 32-bit registers can hold an effective address
add AX,[ECX] is valid
Default Segments
• 16-bit addresses
BX, SI, DI : data segment BP, SP : stack segment

• 32-bit addresses

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* EAX, EBX, ECX, EDX, ESI, EDI: data segment
* EBP, ESP : stack segment

• Possible to override these defaults


* Pentium provides segment override prefixes

--Based Addressing--

• Effective address is computed as


base + signed displacement
* Displacement:
– 16-bit addresses: 8- or 16-bit number
– 32-bit addresses: 8- or 32-bit number
• Useful to access fields of a structure or record
» Base register ==> points to the base address of the structure
» Displacement ==> relative offset within the structure
• Useful to access arrays whose element size is not 2, 4, or 8 bytes
» Displacement ==> points to the beginning of the array
Base register ==> relative offset of an element within the array

--Indexed Addressing--

• Effective address is computed as


(Index * scale factor) + signed displacement
* 16-bit addresses:
– displacement: 8- or 16-bit number
– scale factor: none (i.e., 1)
* 32-bit addresses:
– displacement: 8- or 32-bit number
– scale factor: 2, 4, or 8
• Useful to access elements of an array (particularly if the element size is 2, 4, or 8 bytes)
» Displacement ==> points to the beginning of the array
» Index register ==> selects an element of the array (array index)
» Scaling factor ==> size of the array element

--Based-Indexed Addressing--
Based-indexed addressing with no scale factor
• Effective address is computed as
Base + Index + signed displacement
• Useful in accessing two-dimensional arrays
» Displacement ==> points to the beginning of the array
» Base and index registers point to a row and an element within that row

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• Useful in accessing arrays of records
» Displacement ==> represents the offset of a field in a record
» Base and index registers hold a pointer to the base of the array and the offset of
an element relative to the base of the array.
-- PC relative mode –-

The effective address is the sum of the contents of the PC and a constant contained within
the instruction.
Example instruction:

jmp a_label

The contents of the program counter is added to an offset that is within the machine
code for the instruction. The resulting sum is placed back into the program counter. Note
that from the assembly language it is not clear that a PC relative addressing mode is used.
It is the assembler that generates the offset to place in the instruction.

5. Explain in detail about Instruction set of Pentium processor.

Integer Instructions
Integer instructions perform the integer arithmetic, logic, and program flow control
operations

1. Data Transfer Instructions


The data movement instructions move bytes, words, doublewords, or quadwords
both between memory and the processor’s registers and between registers. These
instructions are divided into four groups: • General-purpose data movement. •
Exchange. • Stack manipulation. • Type-conversion.
MOV Move
CMOVC Conditional move if carry
CMOVE/CMOVZ Conditional move if equal/Conditional move if zero
IN Read from a port
OUT Write to a port
PUSH Push onto stack
POP Pop off of stack
2. Binary Arithmetic Instructions
The binary arithmetic instructions operate on 8-, 16-, and 32-bit numeric data
encoded as signed or unsigned binary integers. Operations include the add, subtract,
multiply, and divide as well as increment, decrement, compare, and change sign
(negate). The binary arithmetic instructions may also be used in algorithms that
operate on decimal (BCD) values.
ADD Integer add
ADC Add with carry
SUB Subtract
SBB Subtract with borrow

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IMUL Signed multiply
MUL Unsigned multiply
DIV Unsigned divide
INC Increment
DEC Decrement
NEG Negate
3. Decimal Arithmetic
Decimal arithmetic can be performed by combining the binary arithmetic
instructions ADD, SUB, MUL, and DIV (discussed in “Binary Arithmetic Instructions”)
with the decimal arithmetic instructions.
DAA Decimal adjust after addition
DAS Decimal adjust after subtraction
AAA ASCII adjust after addition
4. Logic Instructions
The logical instructions AND, OR, XOR (exclusive or), and NOT perform the standard
Boolean operations for which they are named. The AND, OR, and XOR instructions
require two operands; the NOT instruction operates on a single operand.
AND And
OR Or
XOR Exclusive or
NOT Not
5. Shift and Rotate Instructions
The shift and rotate instructions rearrange the bits within an operand. These
instructions fall into the following classes: • Shift. • Double shift • Rotate
SAR Shift arithmetic right
SHR Shift logical right
SAL/SHL Shift arithmetic left/Shift logical left
6. Bit and Byte Instructions
The bit and byte instructions operate on bit or byte strings. They are divided into
four groups: • Bit test and modify instructions. • Bit scan instructions. • Byte set on
condition. • Test.
BT Bit test
BTS Bit test and set
BTR Bit test and reset
SETS Set byte if sign (negative)
SETNS Set byte if not sign (non-negative)
SETO Set byte if overflow
SETNO Set byte if not overflow
7. Control Transfer Instructions
The processor provides both conditional and unconditional control transfer
instructions to direct the flow of program execution. Conditional transfers are taken
only for specified states of the status flags in the EFLAGS register. Unconditional
control transfers are always executed.
JMP Jump
JE/JZ Jump if equal/Jump if zero
JNE/JNZ Jump if not equal/Jump if not zero
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JC Jump if carry
JNC Jump if not carry
JO Jump if overflow
MMX Technology Instructions
1. MMX Data Transfer Instructions
MOVD Move doubleword
MOVQ Move quadword
2. MMX Packed Arithmetic Instructions
PADDB Add packed bytes
PADDW Add packed words
PADDD Add packed doublewords
PSUBB Subtract packed bytes
PSUBW Subtract packed words
PSUBD Subtract packed doublewords
3. MMX Comparison Instructions
PCMPEQB Compare packed bytes for equal
PCMPEQW Compare packed words for equal
PCMPEQD Compare packed doublewords for equal
4. MMX Logic Instructions
PAND Bitwise logical and
PANDN Bitwise logical and not
POR Bitwise logical or
PXOR Bitwise logical exclusive or
5. MMX State Management
EMMS Empty MMX state
Floating-Point Instructions
1. Data Transfer
FLD Load real
FST Store real
FILD Load integer
FIST Store integer
2. Basic Arithmetic
FADD Add real
FIADD Add integer
FSUB Subtract real
FISUB Subtract integer FSUBR Subtract real reverse
3. Comparison
FCOM Compare real
FCOMP Compare real and pop
FICOM Compare integer
FICOMP Compare integer and pop
4. FPU Control
FFREE Free floating-point register
FNINIT Initialize FPU without checking error conditions
FFREE Free floating-point register
FINCSTP Increment FPU register stack pointer
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UNIT 2 HIGH PERFORMANCE RISC ARCHITECTURE – ARM

1. Define Pipelining.
Starting the execution of next instruction before the current instructionexecution is
finished with the available hardware resources is calledpipelining. This is achieved by
splitting the execution of each instruction formore than one stage and allocating
appropriate hardware for each stage. Toimprove the utilization of hardware resources, and
also the processorthroughput, pipelining organization is implemented.

2. What are the sequences of steps in pipelining?


A typical pipelining sequence may be as follows:
• Fetch – fetch instruction from memory.
•Decode – generating control signals for that instruction.
•Register – accessing any operands from register.
•ALU – combine the operands to produce results or memory address.
•Memory – access memory for a data operand.
•Result – write the result back to the register bank.

3. What are the hazards occur in pipelining?


Read-after-write pipeline hazard – occurs when an instruction waits for an operand
which is the result of the previous instruction. Branching hazards – since branch instructions
modify the flow of program, it flush and refill the pipeline.

4. List the features of RISC architecture.


•Fixed 32-bit instruction size with predefined formats.
•Load - store architecture.
•Large register bank of 32–bit registers.

5. Mention the advantages and drawbacks of RISC.


Advantages:
•Smaller die size.
•Shorter development time.
•Higher performance.
•Higher clock rate with single cycle execution.
Drawbacks:
•RISCs generally have poor code density.
•RISCs don’t execute x86 code.

6. Mention the features of RISC which are used and rejected in ARMprocessors.
Features used:
Load store architecture2. Fixed-length 32-bit instructions3. 3-address instruction
formats.
Features rejected:
Register windows2. Delayed branches3. Single cycle execution of all instructions.

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7. List the types of ARM instructions.
All ARM instructions fall into one of the following three categories:1.
Data processing instructions.2. Data transfer instructions3. Control flow instructions
8. Define supervisor mode.
The ARM processor supports a protected supervisor mode. The
protectionmechanism ensures that user code cannot gain supervisor privileges
withoutappropriate checks being carried out to ensure that the code is notattempting
illegal operations. These functions generally include any accessesto hardware peripheral
registers, and to widely used operations such ascharacter input and output.

9. List the features of ARM instruction set.


The most notable features of the ARM instruction set are:
•The load-store architecture;
•3-address data processing
•Conditional execution of every instruction;
•load and store multiple register instructions;
•Single instruction that executes in a single clock cycle;
•Open instruction set extension through the coprocessor instruction set
•Highly dense 16-bit compressed representation of the instruction setin the Thumb
architecture.

10. Mention the development tools available for ARM.


•ARM C compiler.
•ARM assembler.
•The linker.
•ARM symbolic debugger.
•ARMulator.

11. Give the steps in exception handling.


The current state is saved by copying the PC into rl4_exc and the CPSR intoSPSR_exc
(where exc stands for the exception type). The processoroperating mode is changed to the
appropriate exception mode. The PC isforced to a value between 0016 and 1C16,
the particular value depending onthe type of exception.

12. What are the factors considered to view breaks in ARM pipeline.
The simplest way to view breaks in the ARM pipeline is to observe that:
• All instructions occupy the data-path for one or more adjacent cycles.
• For each cycle that an instruction occupies the data-path, it occupies thedecode
logic in the immediately preceding cycle.
• During the first data-path cycle each instruction issues a fetch for thenext
instruction but one.
• Branch instructions flush and refill the instruction pipeline

13. List the features of co-processor architecture.


The coprocessor’s most important features are:
• Support for up to 16 logical coprocessors.
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• Each coprocessor can have up to 16 private registers of any reasonablesize; they are
not limited to 32 bits.
• Coprocessors use load-store architecture, with instructions to performinternal
operations on registers, instructions to load and save registersfrom and to memory, and
instructions to move data to or from an ARMregister.

14. What is a co-processor?


The ARM architecture supports a general mechanism for extending theinstruction
set through the addition of coprocessors. The most commonuse of a coprocessor is the
system coprocessor used to control on-chipfunctions such as the cache and memory
management unit on theARM720.

15. What are the signals used in ARM bus transactions?


The memory bus interface signals include the following:
• A 32-bit address bus, A [31:0], which gives the byte address of the datato be
accessed.
• A 32-bit bidirectional data bus, D [31:0], along which the data istransferred.
• Signals that specify whether the memory is needed (mreq) and whetherthe address is sequential
(seq); these are issued in the previous cycle sothat the memory control logic can prepare
appropriately.
• Signals that specify the direction (r/w) and size (b/w on earlierprocessors; mas[1:0] on later
processors) of the transfer
.• Bus timing and control signals (abe, ale, ape, dbe, lock, bl[3:0]).

PART B

1. Explain in detail about ARM instruction set?


ARM instructions process data held in registers and only access memory with load
and store instructions. ARM instructions commonly take two or three operands. For
example ,the ADD instruction adds the two values stored in registers r1 and r2 (the source
registers). It stores the result to register r3 (the destination register). ADD r3, r1, r2
ARM instructions are classified into data processing instructions, branch
instructions, load-store instructions, software interrupt instruction, and program status
register instructions.

Data Processing Instructions :


The data processing instructions manipulate data within registers. They are move
instructions, Arithmetic instructions, logical instructions, comparison instructions, and
multiply instructions. Most data processing instructions can process one of their operands
using the barrel shifter.

Barrel Shifter:
Data processing instructions are processed within the arithmetic logic unit (ALU). A
unique and powerful feature of the ARM processor is the ability to shift the 32-bit binary
pattern in one of the source registers left or right by a specific number of positions before it

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enters the ALU. This shift increases the power and flexibility of many data processing
operations.
There are data processing instructions that do not use the barrel shift, for example,
the MUL (multiply), CLZ (count leading zeros), and QADD (signed saturated 32-bit add)
instructions.

i) Move Instructions : Move instruction copies R into a destination register Rd, where R
is a register or immediate value. This instruction is useful for setting initial values and
transferring data between registers.

Example1 : PRE r5 = 5
r7 = 8
MOV r7, r5 ;
POST r5 = 5
r7 = 5
The MOV instruction takes the contents of register r5 and copies them into register r7.
Arithmetic Instructions : The arithmetic instructions implement addition and subtraction
of 32-bit signed and unsigned values. the various addition and subtraction instructions are
given in table below.

SUB r0, r1, r2 ; This subtract instruction subtracts a value stored in register r2 from a
value stored in register r1. The result is stored in register r0.

RSB r0, r1, #0 ; This reverse subtract instruction (RSB) subtracts r1 from the constant
value #0, writing. the result to r0. You can use this instruction to negate numbers.

SUBS r1, r1, #1 ; The SUBS instruction is useful for decrementing loop counters. In this
example we subtract the immediate value one from the value one stored in
register r1. The result value zero is written to register r1.

Logical Instructions : These Logical instructions perform bitwise logical operations on the
wo source registers.

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BIC r0, r1, r2 ; BIC, carries out a logical bit clear. register r2 contains a binary pattern
where every binary 1 in r2 clears a corresponding bit location in register r1. This
instruction is particularly useful when clearing status bits and is frequently used to change
interrupt masks in the cpsr.

Comparison Instructions : The comparison instructions are used to compare or test a


register with a 32-bit value. This instruction affects only CPSR register flags.

Branch Instructions: A branch instruction changes the normal flow of execution of a main
program or is used to call a subroutine routine. This type of instruction allows programs
to have subroutines, if-then-else structures, and loops. The change of execution flow forces
the program counter pc to point to a new address.

Example 1: B forward ; (unconditional branch to forward)

ADD r1, r2, #4 ;


ADD r0, r6, #2 ;
ADD r3, r7, #4 ;
forward SUB r1, r2, #4 ;

Similarly Backward branch :

backward : ADD r1, r2, #4 ;


SUB r1, r2, #4 ;
ADD r4, r6, r7 ;
B backward ; branch to the target backward.

The branch with link, or BL, instruction is similar to the B instruction but overwrites
the link register lr with a return address. It performs a subroutine call.

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BL subroutine ; branch to subroutine
CMP r1, #5 ; compare r1 with 5
MOVEQ r1, #0 ; if (r1==5) then r1 = 0 :
Subroutine
MOV pc, lr ; return by moving pc = lr

The Branch Exchange (BX) and Branch Exchange with Link (BLX) are the third type of
branch instruction. The BX instruction uses an absolute address stored in register Rm. It is
primarily used to branch to and from Thumb code. The T bit in the cpsr is updated by the
least significant bit of the branch register. Similarly the BLX instruction updates the T bit of
the cpsr with the least significant bit and additionally sets the link register with the return
address.

The details of the branch instructions are given in the table above.

Load-Store Instructions : Load-store instructions transfer data between memory and


processor registers. There are three types of load-store instructions:

 Single-register transfer
 Multiple-register transfer, and
 Swap.

Single-Register Transfer : These instructions are used for moving a single data item in
and out of a register. The data types supported are signed and unsigned words (32-bit),
half-words (16-bit), and bytes. Ex1: STR r0, [r1] ; = STR r0, [r1, #0] ; store the contents
of register r0 to the memory address pointed to by register r1.

Multiple-Register Transfer : Load-store multiple instructions can transfer multiple


registers between memory and the processor in a single instruction. The transfer occurs
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from a base address register Rn pointing into memory. Multiple-register transfer
instructions are more efficient than single-register transfers for moving blocks of data
around memory and saving and restoring context and stacks.

Load-store multiple instructions can increase interrupt latency. ARM


implementations do not usually interrupt instructions while they are executing. For
example, on an ARM7 a load multiple instruction takes 2 + N.t cycles, where N is the
number of registers to load and t is the number of cycles required for each sequential
access to memory. If an interrupt has been raised, then it has no effect until the load-store
multiple instruction is complete.

Example 1: LDMIA r0!, {r1-r3} ; In this example, register r0 is the base register Rn and is
followed by !, indicating that the register is updated after the instruction is executed. In this
case the range is from register r1 to r3.

Stack Operations : The ARM architecture uses the load-store multiple instructions to
carry out stack operations. The pop operation (removing data from a stack) uses a load
multiple instruction; similarly, the push operation (placing data onto the stack) uses a store
multiple instruction.

A stack is either ascending (A) or descending (D). Ascending stacks grow towards
higher memory addresses; in contrast, descending stacks which grow towards lower
memory addresses. When a full stack (F)is used , the stack pointer sp points to an address
that is the last used or full location (i.e., sp points to the last item on the stack). In contrast,
if an empty stack (E) is used , the sp points to an address that is the first unused or empty
location (i.e., it points after the last item on the stack).

Swap Instruction :

The Swap instruction is a special case of a load-store instruction. It swaps (Similar


to exchange) the contents of memory with the contents of a register. This instruction is an
atomic operation—it reads and writes a location in the same bus operation, preventing any
other instruction from reading or writing to that location until it completes.Swap cannot be
interrupted by any other instruction or any other bus access. So, the system “holds the bus”
until the transaction is complete.

Ex 1: SWP : Swap a word between memory and a register tmp = mem32[Rn]


mem32[Rn] =Rm
Rd = tmp

Software Interrupt Instruction : A software interrupt instruction (SWI) is used to


generate a software interrupt exception, which can be used to call operating system
routines.When the processor executes an SWI instruction, it sets the program counter pc to
the offset 0x8 in the vector table. The instruction also forces the processor mode to SVC,
which allows an operating system routine to be called in a privileged mode. Each SWI
instruction has an associated SWI number, which is used to represent a particular function
call or feature.

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Program Status Register Instructions : There are two instructions available to directly
control a program status register (PSR). The MRS instruction transfers the contents of
either the CPSR or SPSR into a register.Similarly the MSR instruction transfers the contents
of a register into the CPSR or SPSR .These instructions together are used to read and
write the CPSR and SPSR.
MRS : copy program status register to a general-purpose register , Rd= PSR
MSR : move a general-purpose register to a program status register, PSR[field]=Rm
MSR : move an immediate value to a program status register, PSR[field]=immediate

Loading Constants : In ARM instruction set there are no instructions to move the 32-bit
constant into a register. Since ARM instructions are 32 bits in size, they obviously cannot
specify a general 32-bit constant. To overcome this problem .two pseudo instructions are
provided to move a 32-bit value into a register.
LDR : load constant pseudo instruction Rd= 32-bit constant.
ADR : load address pseudo instruction Rd=32-bit relative address.
The first pseudo instruction writes a 32-bit constant to a register using whatever
instructions are available.
The second pseudo instruction writes a relative address into a register, which will be
encoded using a PC -relative expression.

2) Explain in detail about Thumb instruction set?


Thumb encodes a subset of the 32-bit ARM instructions into a 16-bit instruction set
space. Since Thumb has higher performance than ARM on a processor with a 16-bit data
bus, but lower performance than ARM on a 32-bit data bus, use Thumb for memory-
constrained systems. Thumb has higher code density—the space taken up in memory by an
executable program—than ARM. For memory-constrained embedded systems, for example,
mobile phones and PDAs, code density is very important. Cost pressures also limit memory
size, width, and speed.
Thumb execution is flagged by the T bit (bit [5] ) in the CPSR. A Thumb
implementation of the same code takes up around 30% less memory than the equivalent
ARM implementation. Even though the Thumb implementation uses more instructions ; the
overall memory footprint is reduced. Code density was the main driving force for the
Thumb instruction set. Because it was also designed as a compiler target, rather than for
hand-written assembly code. Below example explains the difference between ARM and
Thumb code

25
From the above example it is clear that the Thumb code is more denser than the
ARM code.
Exceptions generated during Thumb execution switch to ARM execution before
executing the exception handler . The state of the T bit is preserved in the SPSR, and the LR
of the exception mode is set so that the normal return instruction performs correctly,
regardless of whether the exception occurred during ARM or Thumb execution.
In Thumb state, all the registers can not be accessed . Only the low registers r0 to r7 can be
accessed. The higher registers r8 to r12 are only accessible with MOV, ADD, or CMP
instructions. CMP and all the data processing instructions that operate on low registers
update the condition flags in the CPSR.The list of registers and their accessibility in Thumb
mode are shown in the following table..

S.No Registers Access


1 r0 – r7 Fully accessible
2 r8 – r12 Only accessible by MOV ,ADD &CMP
3 r13SP Limited accessibility
4 r14 lr Limited accessibility
5 r15 PC Limited accessibility
6 CPSR Only indirect access
7 SPSR No access

Form the above discussion, it is clear that there are no MSR and MRS equivalent
Thumb instructions. To alter the CPSR or SPSR , one must switch into ARM state to use
MSR and MRS. Similarly, there are no coprocessor instructions in Thumb state. You need to
be in ARM state to access the coprocessor for configuring cache and memory management.

ARM-Thumb interworking is the method of linking ARM and Thumb code together
for both assembly and C/C++. It handles the transition between the two states. To call a
Thumb routine from an ARM routine, the core has to change state. This is done with the T
bit of CPSR . The BX and BLX branch instructions cause a switch between ARM and Thumb

26
state while branching to a routine. The BX lr instruction returns from a routine, also with a
state switch if necessary.

The data processing instructions manipulate data within registers. They include
move instructions, arithmetic instructions, shifts, logical instructions, comparison
instructions, and multiply instructions. The Thumb data processing instructions are a
subset of the ARM data processing instructions.

Exs : ADC : add two 32-bit values and carry Rd = Rd + Rm + C flag


ADD : add two 32-bit values Rd = Rn + immediate
Rd = Rd + immediate
Rd = Rd + Rm

AND : logical bitwise AND of two 32-bit values Rd = Rd & Rm


ASR : arithmetic shift right Rd = Rm_immediate,
C flag= Rm[immediate − 1]
Rd = Rd_Rs, C flag = Rd[Rs - 1]
BIC : logical bit clear (AND NOT) of two 32-bit Rd = Rd AND
NOT(Rm)values
CMN : compare negative two 32-bit values Rn + Rm sets flags
CMP : compare two 32-bit integers Rn−immediate sets flags Rn−Rm sets
flags
EOR : logical exclusive OR of two 32-bit values Rd = Rd EOR Rm

LSL : logical shift left Rd = Rm_ immediate,


C flag= Rm[32 − immediate]
Rd = Rd_Rs, C flag = Rd[32 − Rs]
LSR : logical shift right Rd = Rm_ immediate,
C flag = Rd [immediate − 1]
Rd = Rd_ Rs, C flag = Rd[Rs − 1]

MOV : move a 32-bit value into a register Rd = immediate


Rd = Rn
Rd = Rm
MUL : multiply two 32-bit values Rd = (Rm * Rd)[31:0]
MVN : move the logical NOT of a 32-bit value into a register Rd = NOT(Rm)
NEG : negate a 32-bit value Rd = 0 − Rm
ORR : logical bitwise OR of two 32-bit values Rd = Rd OR Rm
ROR : rotate right a 32-bit value Rd = Rd RIGHT_ROTATE Rs,
C flag= Rd[Rs−1]
SBC : subtract with carry a 32-bit value Rd = Rd − Rm − NOT(C flag)
SUB : subtract two 32-bit values Rd = Rn − immediate
Rd = Rd − immediate
Rd = Rn − Rm
sp = sp − (immediate_2)
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TST : test bits of a 32-bit value Rn AND Rm sets flags.

Note : Thumb deviates from the ARM style in that the barrel shift operations (ASR, LSL,
LSR, and ROR) are separate instructions.

3. Expain in detail about ARM processor architecture?


The ARM 7 processor is based on Von Neman model with a single bus for both data
and instructions..( The ARM9 uses Harvard model).Though this will decrease the
performance of ARM, it is overcome by the pipe line concept. ARM uses the Advanced
Microcontroller Bus Architecture (AMBA) bus architecture. This AMBA include two
system buses: the AMBA High-Speed Bus (AHB) or the Advanced System Bus (ASB), and
the Advanced Peripheral Bus (APB).
The ARM processor consists of
 Arithmetic Logic Unit (32-bit)
 One Booth multiplier(32-bit)
 One Barrel shifter
 One Control unit
 Register file of 37 registers each of 32 bits.
In addition to this the ARM also consists of a Program status register of 32 bits,
Some special registers like the instruction register, memory data read and write
register and memory address register ,one Priority encoder which is used in the
multiple load and store instruction to indicate which register in the register file to be
loaded or stored and Multiplexers etc.

ARM Registers : ARM has a total of 37 registers .In which - 31 are general-purpose
registers of 32-bits, and six status registers .But all these registers are not seen at once.
The processor state and operating mode decide which registers are available to the
programmer. At any time, among the 31 general purpose registers only 16 registers are
available to the user. The remaining 15 registers are used to speed up exception
processing. there are two program status registers: CPSR and SPSR (the current and saved
program status registers, respectively

In ARM state the registers r0 to r13 are orthogonal—any instruction that you can apply to
r0 you can equally well apply to any of the other registers.The main bank of 16 registers is
used by all unprivileged code. These are the User mode registers. User mode is different
from all other modes as it is unprivileged. In addition to this register bank ,there is also one
32-bit Current Program status Register(CPSR)

28
In the 15 registers ,the r13 acts as a stack pointer register and r14 acts as a link
register and r15 acts as a program counter register.
Register r13 is the sp register ,and it is used to store the address of the stack top.
R13 is used by the PUSH and POP instructions in T variants, and by the SRS and RFE
instructions from ARMv6.

Register 14 is the Link Register (LR). This register holds the address of the next
instruction after a Branch and Link (BL or BLX) instruction, which is the instruction used to
make a subroutine call. It is also used for return address information on entry to exception
modes. At all other times, R14 can be used as a general-purpose register.
Register 15 is the Program Counter (PC). It can be used in most instructions as a pointer to
the instruction which is two instructions after the instruction being executed.

29
The remaining 13 registers have no special hardware purpose.

CPSR : The ARM core uses the CPSR register to monitor and control internal operations.
The CPSR is a dedicated 32-bit register and resides in the register file. The CPSR is divided
into four fields, each of 8 bits wide : flags, status, extension, and control. The extension and
status fields are reserved for future use. The control field contains the processor mode,
state, and interrupt mask bits. The flags field contains the condition flags. The 32-bit CPSR
register is shown below.

Processor Modes: There are seven processor modes .Six privileged modes abort, fast
interrupt request, interrupt request, supervisor, system, and undefined and one non-
privileged mode called user mode.The processor enters abort mode when there is a failed
attempt to access memory. Fast interrupt request and interrupt request modes correspond
to the two interrupt levels available on the ARM processor. Supervisor mode is the mode
that the processor is in after reset and is generally the mode that an operating system
kernel operates in. System mode is a special version of user mode that allows full read-
write access to the CPSR. Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the implementation. User mode is used
for programs and applications.

Banked Registers : Out of the 32 registers , 20 registers are hidden from a program at
different times. These registers are called banked registers and are identified by the
shading in the diagram. They are available only when the processor is in a particular
mode; for example, abort mode has banked registers r13_abt , r14_abt and spsr _abt.
Banked registers of a particular mode are denoted by an underline character post-fixed to
the mode mnemonic or _mode.
When the T bit is 1, then the processor is in Thumb state. To change states the core
executes a specialized branch instruction and when T= 0 the processor is in ARM state and
executes ARM instructions. There are two interrupt request levels available on the ARM
processor core—interrupt request (IRQ) and fast interrupt request (FIQ).

V, C , Z , N are the Condition flags .


V (oVerflow) : Set if the result causes a signed overflow
C (Carry) : Is set when the result causes an unsigned carry
Z (Zero) : This bit is set when the result after an arithmetic operation is zero,
frequently

30
used to indicate equality
N (Negative) : This bit is set when the bit 31 of the result is a binary 1.

4)Explain in detail about pipeline Structure in ARM Processor?


PIPE LINE : Pipeline is the mechanism used by the RISC processor to execute
instructions at an increased speed. This pipeline speeds up execution by fetching the next
instruction while other instructions are being decoded and executed. During the execution
of an instruction ,the processor Fetches the instruction .It means loads an instruction from
memory.And decodes the instruction i.e identifies the instruction to be executed and
finally Executes the instruction and writes the result back to a register.

The ARM7 processor has a three stage pipelining architecture namely Fetch , Decode and
Execute.And the ARM 9 has five stage Pipe line architecture.The three stage pipelining is
explained as below.

To explain the pipelining ,let us consider that there are three instructions Compare,
Subtract and Add.The ARM7 processor fetches the first instruction CMP in the first cycle
and during the second cycle it decodes the CMP instruction and at the same time it will
fetch the SUB instruction. During the third cycle it executes the CMP instruction , while
decoding the SUB instruction and also at the same time will fetch the third instruction ADD.
This will improve the speed of operation. This leads to the concept of parallel processing
.This pipeline example is shown in the following diagram.

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As the pipeline length increases, the amount of work done at each stage is reduced, which
allows the processor to attain a higher operating frequency. This in turn increases the
performance. One important feature of this pipeline is the execution of a branch
instruction or branching by the direct modification of the PC causes the ARM core to flush
its pipeline.

5) Briefly Discuss about Interrupts in ARM Processor?


Exceptions are generated by internal and external sources to cause the ARM
processor to handle an event, such as an externally generated interrupt or an attempt to
execute an Undefined instruction. The processor state just before handling the exception is
normally preserved so that the original program can be resumed after the completion of
the exception routine. More than one exception can arise at the same time.ARM exceptions
may be considered in three groups.
1. Exceptions generated as the direct effect of executing an instruction.Software
interrupts, undefined instructions (including coprocessor instructions where the
requested coprocessor is absent) and prefetch aborts (instructions that are invalid
due to a memory fault occurring during fetch) come under this group.
2. Exceptions generated as a side-effect of an instruction.Data aborts (a memory fault
during a load or store data access) are in this group.
3. Exceptions generated externally, unrelated to the instruction flow.Reset, IRQ and
FIQ are in this group.
The ARM architecture supports seven types of exceptions.
1. Reset
2. Undefined Instruction
3. Software Interrupt(SWI)
4. Pre-fetch abort(Instruction Fetch memory fault)
5. Data abort (Data access memory fault)
6. IRQ(normal Interrupt)
7. FIQ (Fast Interrupt request).
When an Exception occurs , the processor performs the following sequence of actions:
• It changes to the operating mode corresponding to the particular exception.
• It saves the address of the instruction following the exception entry instruction in
r14 of
the new mode.
• It saves the old value of the CPSR in the SPSR of the new mode.
• It disables IRQs by setting bit 7 of the CPSR and, if the exception is a fast interrupt,
disables
further fast interrupts by setting bit 6 of the CPSR.
• It forces the PC to begin executing at the relevant vector address

Excdption / Interrupt Name Address High Address


Reset RESET 0X00000000 0Xffff0000
Undefined Instruction UNDEF 0X00000004 0Xffff0004

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Software Interrupt SWI 0X00000008 0Xffff0008
Pre-fetch Abort PABT 0X0000000C 0Xffff000c
Data Abort DABT 0X00000010 0Xffff0010
Reserved --- 0X00000014 0Xffff0014
Interrupt Request IRQ 0X00000018 0Xffff0018
Fast Interrupt Request FIQ 0X0000001C 0Xffff001c

The exception Vector table shown above gives the address of the subroutine
program to be executed when the exception or interrupt occurs. Each vector table entry
contains a form of branch instruction pointing to the start of a specific routine.Reset vector
is the location of the first instruction executed by the processor when power is applied.
This instruction branches to the initialization code.Undefined instruction vector is used
when the processor cannot decode an instruction.

Software interrupt vector is called when you execute a SWI instruction. The SWI
instruction is frequently used as the mechanism to invoke an operating system routine.Pre-
fetch abort vector occurs when the processor attempts to fetch an instruction from an
address without the correct access permissions. The actual abort occurs in the decode
stage.

Data abort vector is similar to a prefetch abort but is raised when an instruction
attempts to access data memory without the correct access permissions.Interrupt request
vector is used by external hardware to interrupt the normal execution flow of the
processor. It can only be raised if IRQs are not masked in the CPSR

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UNIT III ARM APPLICATION DEVELOPMENT

PART A

1. What is Firmware?
The firmware is the deeply embedded, low-level software that provides an interface
between the hardware and the application/operating system level software. It resides in
the ROM and executes when power is applied to the embedded hardware system.

2. What is Bootloader?
The bootloader is a small application that installs the operating system or application
onto a hardware target. The bootloader only exists up to the point that the operating
system or application is executing, and it is commonly incorporated into the firmware.

3. Define Interrupt Latency.


The interval of time from an external interrupt request signal being raised to the first
fetch of an instruction of a specific interrupt service routine (ISR). Interrupt latency
depends on a combination of hardware and software.

4. Name few Interrupt handling schemes.


 Non-nested interrupt handler
 Nested interrupt handler
 Reentrant interrupt handler
 Prioritized simple interrupt handler
 Prioritized standard interrupt handler
 Prioritized direct interrupt handler
 Prioritized grouped interrupt handler

5. When an FIQ and IRQ exceptions occur?


A Fast Interrupt Request (FIQ) exception occurs when an external peripheral sets
the FIQ pin to nFIQ. An FIQ exception is the highest priority interrupt.
An Interrupt Request (IRQ) exception occurs when an external peripheral sets the
IRQ pin to nIRQ. An IRQ exception is the second-highest priority interrupt.

6. What is an Exception?
An exception is any condition that needs to halt the normal sequential execution of
instructions.

7. Define Vector Table.


vector table—a table of addresses that the ARM core branches to when an
exception is raised. These addresses commonly contain branch instructions

8. What is the function of TLB?


A translation lookaside buffer (TLB) is a memory cache that stores recent
translations of virtual memory to physical addresses for faster retrieval.

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9. Define: Virtual Memory?
virtual memory is a memory management technique that is implemented using
both hardware and software. It maps memory addresses used by a program, called virtual
addresses, into physical addresses in computer memory.

10. What is Page Table Walk?


The search for valid translations in the page tables is known as a page table walk.

11. What are the functions of Memory Protection Unit (MPU)?


Memory protection is a way to control memory access rights on a computer. The
main function of memory protection unit is to prevent a process from accessing memory
that has not been allocated to it.

12. What are the functions of MMU?


The functions of an ARM MMU are to:
 read level 1 and level 2 page tables and load them into the TLB
 store recent virtual-to-physical memory address translations in the TLB
 perform virtual-to-physical address translation
 enforce access permission and configure the cache and write buffer

13. State the difference between logical and physical cache memories.
A logical cache stores data in a virtual address space. A logical cache is located
between the processor and the MMU. The processor can access data from a logical cache
directly without going through the MMU. A logical cache is also known as a virtual cache.
A physical cache stores memory using physical addresses. A physical cache is
located between the MMU and main memory. For the processor to access memory, the
MMU must first translate the virtual address to a physical address before the cache
memory can provide data to the core.

14. Mention the development tools available for ARM.

• ARM C compiler.
• ARM assembler.
• The linker.
• ARM symbolic debugger.
• ARMulator.

15. List the features of ARM instruction set.


The most notable features of the ARM instruction set are:
• The load-store architecture;
• 3-address data processing
• Conditional execution of every instruction;
• load and store multiple register instructions;
• Single instruction that executes in a single clock cycle;
• Open instruction set extension through the coprocessor instruction set

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• Highly dense 16-bit compressed representation of the instruction setin the Thumb
architecture.

PART B

1. What is an interrupt? and explain the interrupt handling schemes of ARM


processor.

An event external to the currently executing process that causes a change in the normal
flow of instruction execution; usually generated by hardware devices external to the CPU is
known as interrupt.

Interrupt handling schemes

 Non-nested interrupt handling:


A non-nested interrupt handler handles and services individual interrupts sequentially.
It is the simplest interrupt handler. Interrupts are disabled until control is returned
back to the interrupted task. So only one interrupt can be served at a time and that is
why this scheme is not suitable for complex embedded systems which most probably
have more than one interrupt source and require concurrent handling. The steps taken
to handle an interrupt:

Disable interrupt/s—When the IRQ exception is raised, the ARM processor will disable
further IRQ exceptions from occurring.
Save context—On entry the handler code saves a subset of the current processor mode
nonbanked registers.
Interrupt handler—The handler then identifies the external interrupt source and executes
the appropriate interrupt service routine (ISR).

36
Interrupt service routine—The ISR services the external interrupt source and resets the
interrupt.
Restore context—The ISR returns back to the interrupt handler, which restores the
context.
Enable interrupts—Finally, to return from the interrupt handler, the spsr_{interrupt
request mode} is restored back into the cpsr.

Non-nested interrupt handling summery:


• Handle and service individual interrupts sequentially.
• High interrupt latency.
• Relatively easy to implement and debug.
• Not suitable for complex embedded systems.
 Nested interrupt handling:
 A nested interrupt handler handles multiple interrupts without a priority
assignment. This is achieved by re-enabling interrupts before the handler has fully
served the current interrupt.
 This feature increases the complexity of the system but improves the latency. The
scheme should be designed carefully to protect the context saving and restoration
from being interrupted.
 The goal of nested handling is to respond to interrupts quickly and to execute
periodic tasks without any delays.
 The main disadvantage of this interrupt handling scheme is that it doesn’t differ
between interrupts by priorities, so lower priority interrupt can block higher
priority interrupts.

37
Nested interrupt handling summery:
• Handle multiple interrupts without a priority assignment.
• Medium or high interrupt latency.
• Enable interrupts before the servicing of an individual interrupt is complete.
• No prioritization, so low priority interrupts can block higher priority interrupts.

 Prioritized simple interrupt handling:


It handles prioritized interrupts. In this scheme the handler will associate a priority
level with a particular interrupt source. A higher priority interrupt will take precedence
over a lower priority interrupt. Handling prioritization can be done by means of software
or hardware.
When an interrupt signal is raised, a fixed amount of comparisons with the available set
of priority levels is done, so the interrupt latency is deterministic but at the same point this
could be considered a disadvantage because both high and low priority interrupts take the
same amount of time.

Prioritized simple interrupt handling summary:


• Handle multiple interrupts with a priority assignment mechanism.
• Low interrupt latency.
• Deterministic interrupt latency.
• Time taken to get to a low priority ISR is the same as for high priority ISR.

 Re-entrant interrupt handler:


A reentrant interrupt handler handles multiple interrupts that can be prioritized. The basic
difference between this scheme and the nested interrupt handling is that interrupts are re-
enabled early on the re-entrant interrupt handler which can reduce interrupt latency. This
is done by a using a mask in the interrupt controller.
 Prioritized standard interrupt handler:
It handles higher-priority interrupts in a shorter time than lower-priority interrupts. It is
the alternative approach of prioritized simple interrupt handler; it has the advantage of low
interrupt latency for higher priority interrupts than the lower priority ones. But the
disadvantage now is that the interrupt latency in nondeterministic.
 Prioritized grouped interrupt handler:
It is a mechanism for handling interrupts that are grouped into different priority levels. The
way of grouping reduces the complexity of the handler since it doesn’t scan through every
interrupt to determine the priority.

2. Explain the implementation of FIR and IIR filters on ARM in detail.


FIR filters
The finite impulse response (FIR) filter is a basic building block of many DSP applications.
It is used to remove unwanted frequency ranges, boost certain frequencies, or implement
special effects. The FIR filter is the simplest type of digital filter. The filtered sample yt
depends linearly on a fixed, finite number of unfiltered samples xt . Let M be the length of
the filter. Then for some filter coefficients, ci :

38
the coefficients ci are referred as the impulse response. If you feed the impulse signal x =
(1, 0, 0, 0, . . .) into the filter, then the output is the signal of filter coefficients y = (c0, c1, c2, .
. .).

We implement the filter by calculating accumulated values A[t ]:

Block FIR filters

Generally X[t ] and C[i] are k-bit integers and A[t ] is a 2k-bit integer, where k = 8, 16, or 32.
For a long filter, each result A[t ] depends on M data values and M coefficients that we must
read from memory. These loads are time consuming, and it is inefficient to calculate just a
single result A[t ]. While we are loading the data and coefficients, we can calculate A[t + 1]
and possibly A[t + 2] at the same time.
An R ×S block filter is an R-way block filter where we read S data and coefficient
values at a time for each iteration of the inner loop. On each loop we accumulate R × S
products onto the R accumulators.
Figure 8.3 shows a typical 4 × 3 block filter implementation. Each accumulator on
the left is the sum of products of the coefficients on the right multiplied by the signal value
heading each column. The diagram starts with the oldest sample Xt−M+1 since the filter
routine will load samples in increasing order of memory address. Each inner loop of a 4 × 3
filter accumulates the 12 products in a 4 × 3 parallelogram. We’ve shaded the first
parallelogram and the first sample of the third parallelogram.

39
Summary Writing FIR Filters on the ARM
 If the number of FIR coefficients is small enough, then hold the coefficients and history
samples in registers. Often coefficients are repeated. This will save on the number of
registers you need.
 If the FIR filter length is long, then use a block filter algorithm of size R × (R − 1) or R ×R.
Choose the largest R possible given the 14 available general purpose registers on the
ARM.
 Ensure that the input arrays are aligned to the access size. This will be 64-bit when
using LDRD. Ensure that the array length is a multiple of the block size.
 Schedule to avoid all load-use and multiply-use interlocks.

IIR Filters
An infinite impulse response (IIR) filter is a digital filter that depends linearly on a finite
number of input samples and a finite number of previous filter outputs. In other words, it
combines a FIR filter with feedback from previous filter outputs. Mathematically, for some
coefficients bi and aj :

If you feed in the impulse signal x = (1, 0, 0, 0, . . .), then yt may oscillate forever. This is why
it has an infinite impulse response. However, for a stable filter, yt will decay to zero.
an IIR filter with M = L = 2:

We can implement any IIR filter by repeatedly filtering the data by a number of biquads. To
see this, we use the z-transform. This transform associates with each signal xt ,
a polynomial x(z) defined as

If we transform the IIR equation into z-coordinates, we obtain

Equivalently,

Next, consider H(z) as the ratio of two polynomials in z−1

In other words, we perform the feedback part of the filter before the FIR part of the filter.
Equivalently we apply the denominator of H(z) before the numerator. Now each biquad
filter requires a state of only two values, st−1 and st−2. we have reduced an IIR to filtering
by a series of biquads of the form

40
Summary Implementing 16-bit IIR Filters
 Factorize the IIR into a series of biquads. Choose the data precision so there can be no
overflow during the IIR calculation. To compute the maximum gain of an IIR, apply the
IIR to an impulse to generate the impulse response.
 Use a block IIR algorithm, dividing the signal to be filtered into large frames.
 On each pass of the sample frame, filter by M biquads. Choose M to be the largest
number of biquads so that you can hold the state and coefficients in the 14 available
registers on the ARM. Ensure that the total number of biquads is a multiple of M.
 As always, schedule code to avoid load and multiply use interlocks.

3. Explain in detail about Memory Management Unit (MMU) of Arm.


Details of the ARM MMU:
The main software configuration and control components in the MMU are
 Page tables
 The Translation Look aside Buffer (TLB)
 Domains and access permission
 Caches and write buffer
 The CP15:c1 control register
 The Fast Context Switch Extension

Page Tables
The ARM MMU hardware has a multilevel page table architecture. There are two
levels of page table: level 1 (L1) and level 2 (L2).

Level 1 Page Table Entries


The level 1 page table accepts four types of entry:
 A 1 MB section translation entry
 A directory entry that points to a fine L2 page table
 A directory entry that points to a coarse L2 page table
 A fault entry that generates an abort exception

Level 2 Page Table Entries


There are four possible entries used in L2 page tables:
 A large page entry defines the attributes for a 64 KB page frame.
 A small page entry defines a 4 KB page frame.
 A tiny page entry defines a 1 KB page frame.
 A fault page entry generates a page fault abort exception when accessed.

The Translation Lookaside Buffer


The TLB is a special cache of recently used page translations. The TLB maps a virtual
page to an active page frame and stores control data restricting access to the page. The TLB
is a cache and therefore has a victim pointer and a TLB line replacement policy. If the TLB
does not contain a valid translation, it is a TLB miss. The MMU automatically handles TLB

41
misses in hardware by searching the page tables in main memory for valid translations and
loading them into one of the 64 lines in the TLB. The search for valid translations in the
page tables is known as a page table walk.

Single-Step Page Table Walk:


If the MMU is searching for a 1 MB section page, then the hardware can find the
entry in a single-step search because 1 MB page table entries are found in the master L1
page table.

Two-Step Page Table Walk:


If the MMU ends its search for a page that is 1, 4, 16, or 64 KB in size, then the page table
walk will have taken two steps to find the address translation.
The two-stage process for a translation held in a coarse L2 page table. Note that the virtual
address is divided into three parts.

Domains and Memory Access Permission


There are two different controls to manage a task’s access permission to memory: The
primary control is the domain, and a secondary control is the access permission set in the
page tables.

42
Domains control basic access to virtual memory by isolating one area of memory from
another when sharing a common virtual memory map. There are 16 different domains that
can be assigned to 1 MB sections of virtual memory and are assigned to a section by setting
the domain bit field in the master L1 PTE

Page-Table-Based Access Permissions


The AP bits in a PTE determine the access permission for a page. In addition to the
AP bits located in the PTE, there are two bits in the CP15:c1 control register that act
globally to modify access permission to memory: the system (S) bit and the rom (R) bit.
These bits can be used to reveal large blocks of memory from the system at different times
during operation.

The Caches and Write Buffer


A cache is a small, fast array of memory placed between the processor core and
main memory that stores portions of recently referenced main memory. The processor
uses cache memory instead of main memory whenever possible to increase system
performance.
Often used with a cache is a write buffer—a very small first-in-first-out (FIFO) memory
placed between the processor core and main memory. The purpose of a write buffer is to

43
free the processor core and cache memory from the slow write time associated with
writing to main memory.

4. Explain in detail about embedded operating system.


Fundamental Components OF Embedded operating systems and Simple Little
Operating System (SLOS):

There is a common set of low-level components, each carrying out a prescribed


action, that form an operating system. It is how these components interact and function
that determines the characteristics of a specific operating system.
Initialization is the first code of the operating system to execute and involves
setting up internal data structures, global variables, and the hardware. Initialization starts
after the firmware hands over control.
Memory handling involves setting up the system and task stacks. The positioning of
the stacks determines how much memory is available for either the tasks or the system.
A static task is defined at build time and is included in the operating system image.
For these tasks the stack can be set up during operating system initialization.
A dynamic task loads and executes after the operating system is installed and
executing and is not part of the operating system image. The stack is set up when the task is
created. Memory handling varies in complexity from one operating system to another. It
depends upon a number of factors, such as the ARM processor core selected, the
capabilities of the microcontroller, and the physical memory layout of the end target
hardware. The method for handling interrupts and exceptions is part of the architecture
design of the operating system.
A preemptive operating system like SLOS requires a periodic interrupt, which is
normally produced by a counter/timer device on the target hardware. As part of the
initialization stage, an operating system sets the periodic interrupt frequency.
In contrast, a non preemptive operating system does not require a periodic
interrupt and will use a different technique, for example, polling—the continuous checking
for a state change in a device. If the device state changes, then a specific action can be
connected to a particular state change.
The scheduler is an algorithm that determines which task is to be executed next.
There are many scheduling algorithms available. One of the simplest is called a round-
robin algorithm—it activates tasks in a fixed cyclic order. Scheduling algorithms have to
balance efficiency and size with complexity.
Once the scheduler is complete, the new and old tasks have to be swapped with a
context switch. A context switch saves all the old task registers from the processor into a
data structure.
The last component is the device driver framework—the mechanism an operating
system uses to provide a consistent interface between different hardware peripherals.

Simple Little Operating System : SLOS is a preemptive operating system. A periodic


interrupt activates a dormant task. For simplicity, all the tasks and device drivers are static;
that is, they are created at build time and not while the system is running. SLOS also
provides a device driver framework.

44
SLOS is designed to execute on an ARM7TDMI core with no memory management
unit or protection unit. It is assumed that the memory map has already been configured by
the initialization code. SRAM is required to be located between 0x00000000 to
0x00080000, and the base configuration registers must be set to address 0x03ff0000. SLOS
is loaded at address 0x00000000, where the vector table is located. This is the same
address as the entry point into SLOS.
In this current configuration, SLOS includes three tasks and two service routines.
Tasks 1 and 2 provide an example of mutual exclusion using a binary semaphore. The two
service routines implemented are the periodic timer (which is essential) and a push-button
interrupt (which is optional). Task 3 provides a simple command line interface through one
of the ARM Evaluator-7T’s serial ports.

Initialization
There are three main stages of initializing SLOS—startup, executing process control
block (PCB) setup code, and executing the C initialization code. The startup code sets up the
FIQ registers and the system, SVC, and IRQ mode stacks. In the next stage, the PCB, which
contains the state of each task, is set up, including all the ARM registers. It is used to store
and restore task state during a context switch. The setup code sets the process control
block to an initial start state. The final C initialization stage calls the device driver, event
handler, and periodic timer initialization routines. Once complete, the first task can be
invoked.

Memory Model
We have adopted a simple memory model for SLOS. Figure 11.2 shows that the code
portion of SLOS, including the tasks, are located in low memory, and the stacks for the IRQ
and for each task are located in higher memory.

45
Interrupts and Exceptions Handling
In this implementation of the operating system only three exceptions are actually
used. The other exceptions are ignored by going to specific dummy handlers, which for
safety reasons are implemented as infinite loops.

Scheduler
The low-level scheduler, or dispatcher, used in SLOS is a simple static round-robin
algorithm as illustrated in the following pseudocode. “Static” in this case means that the
tasks are only created when the operating system is initialized.

Context Switch
Using the updated information produced by the scheduler, the context switch then
swaps the active task t with the next task t _. To achieve this, a context switch splits the
activity into two stages, as shown in Figure 11.4. The first stage involves saving the
processor registers into the current task t PCB pointed by PCB_PtrCurrentTask. The second
stage loads the registers with data from the next t_ PCB pointed by PCB_PtrNextTask.

5. Explain in detail about Cache Memory of ARM Processor.


A cache is a small, fast array of memory placed between the processor core and main
memory that stores portions of recently referenced main memory.
The L1 cache is an array of high-speed, on-chip memory that temporarily holds code
and data from a slower level. A cache holds this information to decrease the time required
to access both instructions and data.
An L2 cache is located between the L1 cache and slower memory. The L1 and L2
caches are also known as the primary and secondary caches.

46
Relationship that a cache has with main memory system and the processor core

Physical and Logical Caches:

47
If a cached core supports virtual memory, it can be located between the core and the
memory management unit (MMU), or between the MMU and physical memory.
A logical cache stores data in a virtual address space. A logical cache is located
between the processor and the MMU. The processor can access data from a logical cache
directly without going through the MMU. A logical cache is also known as a virtual cache.
A physical cache stores memory using physical addresses. A physical cache is
located between the MMU and main memory. For the processor to access memory, the
MMU must first translate the virtual address to a physical address before the cache
memory can provide data to the core.
Cache Architecture
ARM uses two bus architectures in its cached cores, the Von Neumann and the
Harvard. The Von Neumann and Harvard bus architectures differ in the separation of the
instruction and data paths between the core and memory.
In processor cores using the Von Neumann architecture, there is a single cache used
for instruction and data. This type of cache is known as a unified cache. A unified cache
memory contains both instruction and data values.
The Harvard architecture has separate instruction and data buses to improve
overall system performance, but supporting the two buses requires two caches.
In processor cores using the Harvard architecture, there are two caches: an
instruction cache (I-cache) and a data cache (D-cache). This type of cache is known as a
split cache.
We introduce the basic architecture of caches by showing a unified cache in Figure
12.4. The two main elements of a cache are the cache controller and the cache memory.
The cache memory is a dedicated memory array accessed in units called cache lines.

Basic Architecture of a Cache Memory

48
A simple cache memory is shown on the right side of Figure 12.4. It has three main
parts: a directory store, a data section, and status information. All three parts of the cache
memory are present for each cache line.
The cache must know where the information stored in a cache line originates from
in main memory. It uses a directory store to hold the address identifying where the cache
line was copied from main memory. The directory entry is known as a cache-tag.
The cache must know where the information stored in a cache line originates from
in main memory. It uses a directory store to hold the address identifying where the cache
line was copied from main memory. The directory entry is known as a cache-tag.
The size of a cache is defined as the actual code or data the cache can store from
main memory. Not included in the cache size is the cache memory required to support
cache-tags or status bits.
There are also status bits in cache memory to maintain state information. Two
common status bits are the valid bit and dirty bit.
A valid bit marks a cache line as active, meaning it contains live data originally taken
from main memory and is currently available to the processor core on demand.
A dirty bit defines whether or not a cache line contains data that is different from
the value it represents in main memory.

Basic Operation of a Cache Controller


The cache controller is hardware that copies code or data from main memory to
cache memory automatically. It performs this task automatically to conceal cache operation
from the software it supports.
The controller then checks the valid bit to determine if the cache line is active, and
compares the cache-tag to the tag field of the requested address. If both the status check
and comparison succeed, it is a cache hit. If either the status check or comparison fails, it is
a cache miss.

49
UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS

PART A

1. What are the features of Motorola 68HC11?


 The HCMOS MC68HC11 is an advanced 8-bit MCU with numerous on-chip
peripheral capabilities.
 Up to 10MIPS Throughput at 10MHz
 256 Bytes of RAM , 512 Bytes of In-System Programmable EEPROM.
 Eight channel 8-bit Analog to Digital Convertor
 One serial peripheral interface, with a speed up to 1M (baud rate)
 The MC68HC11 is available in two packages .
 One is 48-pin dual inline package (DIP) and the other is the 52 Pin Plastic Leaded
Chip Carrier(PLCC) known as Lead quad pack.
 In the 48 pin DIP package 38 pins are available for I/O functions.(34 I/O lines+ 2
interrupt lines + 2 hand shake control lines).
 Similarly in a 52 PLCC pack 42 pins are meant for different I/O functions, and the
remaining are used for interrupt and handshake signals.
 MC68HC11 has one universal Asynchronous Serial Communications Interface
(UART)
 Six powerful addressing modes (Immediate, Extended, Indexed, Inherent and
Relative)
 Power saving STOP and WAIT modes
 Memory mapped I/O and special functions

2. State the different operating modes of MC68HC11.


The 6811 can operate in one of the four modes:
• Single-chip mode: uses internal memory for program & data.
• Expanded mode :allows for use of external memory.
• Bootstrap mode: used to load programs into RAM.
• Test mode : used by Motorola to test the chip is operation

3. What is the function of CCR in 68HC11 Microcontrollers?


CCR- condition code register. It is an 8-bit register used to keep track of the program
execution status , control the execution of conditional branch instructions and
enable/disable the interrupt handling.

4. Define special bootstrap mode.


The special variation of single-chip mode is called special bootstrap mode. The
special bootstrap mode allows programs to be downloaded through the on-chip serial
communications interface (SCI) into internal random-access memory (RAM) to be
executed.

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5. Define Special test mode.
The special variation of the expanded mode is called special test mode. The special
test mode, which is intended primarily for factory testing, is seldom chosen by the
user except for emulation, development, or in other rare circumstances.

6. When conversion complete flag set in 68 HC 11 microcontroller?


During the A/D conversion, the conversion complete flag is set to indicate that the
conversion is finished and the A/D result register can be used.

7. List the different types of addressing modes supported by Motorola 68HC11.


 Immediate (IMM)
 Extended (EXT)
 Direct (DIR)
 Indexed (INDX and INDY)
 Inherent (INH)
 Relative (REL)

8. List the different types of instruction sets available in Motorola 68HC11.


 Accumulator and Memory Instructions: Loads, stores, and transfers,
arithmetic operations, Multiply and divide, Logical operations, Data testing and
bit manipulation, Shifts and rotates
 Stack and Index Register Instructions
 Condition Code Register Instructions
 Program Control Instructions

9. What are the built-in peripherals in 68HC11?


 8-channel analog-to-digital (A/D) converter
 Asynchronous serial communications interface (SCI)
 synchronous serial peripheral interface (SPI)
 8-bit pulse accumulator
 On-chip memory systems: 8 Kbytes of ROM; 256 bytes of RAM; 512 bytes of
EEPROM

10. Define Interrupt Service Routine.


The instructions executed in response to an interrupt are called the interrupt service
routine. These routines are much like subroutines except that they are called through
the automatic hardware interrupt mechanism rather than by a subroutine call
instruction.

11. What is the function of XIRQ’?


The XIRQ pin provides a means for requesting non-maskable interrupts after reset
initialization. XIRQ’ is often used as a power loss detect interrupt.

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12. What is the function of IRQ’?
The IRQ input provides a means for requesting asynchronous interrupts to the
MC68HC11. IRQ’ is program selectable (OPTION register), having a choice of either
level-sensitive or falling-edge-sensitive triggering.

13. What is meant by UART?


UART stands for universal Asynchronous Receiver/Transmitter.
· UART is a hardware component for translating the data between parallel and
serial interfaces.
· UART does convert bytes of data to and from asynchronous start stop bit.
· UART is normally used in MODEM.

14. Define: NMI


NMI- Non Maskable Interrupt, is a hardware interrupt that cannot be ignored by
standard interrupt-masking techniques in the system.

15. Give the structure of System CONFIG register of MC 68HC11.

PART B

1. Explain the architecture of Motorola 68HC11 in detail.

Features:
• It is a CISC microcontroller, optimized for low power consumption and high-
performance operation.
• The 68HC11 chip has built-in EEPROM/ROM, RAM, digital I/O, timers, A/D converter,
PWM (Pulse width modulator) generator, and synchronous and asynchronous
communications channels.
• The HCMOS MC68HC11 is an advanced 8-bit MCU with numerous on-chip peripheral
capabilities.
• Up to 10MIPS Throughput at 10MHz
• 256 Bytes of RAM , 512 Bytes of In-System Programmable EEPROM.
• Eight channel 8-bit Analog to Digital Convertor
• One serial peripheral interface, with a speed up to 1M (baud rate)
• The MC68HC11 is available in two packages .
• One is 48-pin dual inline package (DIP) and the other is the 52 Pin Plastic Leaded Chip
Carrier(PLCC) known as Lead quad pack.

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• In the 48 pin DIP package 38 pins are available for I/O functions.(34 I/O lines+ 2
interrupt lines + 2 hand shake control lines).
• Similarly in a 52 PLCC pack 42 pins are meant for different I/O functions, and the
remaining are used for interrupt and handshake signals.
• MC68HC11 has one universal Asynchronous Serial Communications Interface (UART)
• Six powerful addressing modes (Immediate, Extended, Indexed, Inherent and Relative)
• Power saving STOP and WAIT modes
• Memory mapped I/O and special functions

Fig. Motorola 68HC11 Architecture

From the figure , we see that the 68HC11 has a number of pins. Some of these pins are used
to control the micro-controller's operating mode, clock logic, special interrupts, or power.
The majority of the pins, however, have been organized into four 8-bit input/output ports.
These ports have the logical names PORTA, PORTB , PORTC, and PORTD. It is through these
four ports that the 68HC11 channels most of its interactions with the outside world.
The I/O ports and other device pins are connected to special subsystems in the 68HC11.

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 EPROM: Some versions of the 68HC11 have as much as 4 kilo-bytes of internal
EEPROM. If your program is sufficiently small, then your micro-controller system would
not need external memory chips and could be operated in single-chip mode.
 RAM: The version of the 68HC11 in your MicroStamp11 has 256 bytes of internal RAM.
As mentioned above, some of these bytes are mapped into hardware registers that are
used to control the micro-controller. In reality the MicroStamp11 programmer only has
192 bytes of RAM that can be used for program variables.
 Serial Peripheral Interface (SPI): This subsystem allows the 68HC11 to communicate
with synchronous serial devices such as serial/parallel slave devices.
 Serial Communication Interface (SCI): This subsystem allows the 68HC11 to
communicate with asynchronous serial devices. The SCI interface is used to
communicate with laptop computers.
 Parallel I/O Interface: There are 5 on chip I/O ports. They are: Port A , Port B , Port C,
Port D and Port E
Port A (8 bits): 1 bidirectional pin, 4 output pins, 3 input pins , Also used for timer.
Port B (8 bits): 8 output pins with optional handshaking , Also used as address in
expanded mode (replaced by PRU).
Port C (8 bits): 8 bidirectional pins with optional handshaking and wired-or mode
Also used as data/address in expanded mode (replaced by PRU).
Port D (6 bits): 6 bidirectional pins (controlled by direction register), Also used for
asynchronous (SCI) and synchronous serial (SPI) I/O.
Port E (8 bits): 8 input pins, Also used for A/D converter.

 Mode Selection System:


The 6811 can operate in one of the four modes:
16. Single-chip mode: uses internal memory for program & data.
17. Expanded mode :allows for use of external memory.
18. Bootstrap mode: used to load programs into RAM.
19. Test mode : used by Motorola to test the chip is operation

This subsystem selects whether the 68HC11 runs in expanded or single-chip mode.
Clock logic: An important feature of micro-controllers is that they work in real-time.
The clock logic subsystem provides the real-time clock for the 68HC11. The rate of the
clock is determined by a crystal that is connected to the clock logic pins. Interrupt
Logic: The interrupt logic subsystems provides three pins that can be used to trigger
hardware interrupts. A hardware interrupt automatically transfers software execution
to a specified memory address in response to the hardware event (such as the pin's
logic state going low).

 Timer Interrupts: This subsystem generates interrupts that are associated with an
internal timer. Remember that the 68HC11 executes instructions in step with a clock
tick provided by the clock logic subsystem. With each tick of the clock, an internal
register called a timer is incremented. This timer is memory mapped to an address in

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RAM with the logical name TCNT. SO at any instant you can fetch the current count
(time) on the timer by simply reading TCNT.

There are two types of interrupts associated with TCNT. An input-compare (IC)
interrupt is generated with a specified input pin changes state. When the IC interrupt
occurs, then the value in TCNT is stored in an input-compare register.

The other type of timer interrupt is called an output compare (OC) interrupt. The
output compare event occurs when TCNT matches the value stored in an output compare
register.

2. Explain the addressing modes of Motorola 68 HC 11 micro controllers with


suitable examples.

In the M68HC11 CPU, six addressing modes can be used to reference memory:
 Immediate
 Direct
 Extended
 Indexed (With Either Of Two 16-Bit Index Registers And An 8-Bit Offset),
 Inherent
 Relative

IMMEDIATE ADDRESSING MODES (IMM):


 In immediate addressing the instruction itself contains the data to be loaded into the
destination.
 Consider the instruction
LDAA #15 This instruction will load $0F into Accumulator A

For example:
Load Immediate
LDAA #10 Loading a decimal value Loads the binary for 10, i.e., a value of
$0A into accumulator A
LDAA #$1C Loads the hexadecimal value $1C in A
LDAA #@03 Loads the octal value 3 into A
LDAA #%11101100 Loads a binary value
LDAA #’C’ Loads the ASCII code for the letter C
EXTENDED ADDRESSING MODE (EXT):
 This addressing mode introduces the concept of the effective address of an
operand.
 The effective address of an operand is the address in memory of the operand and
is usually a calculated value.
 This mode also introduces the use of an instruction prebyte in the machine code
of the 68HC11. Instructions that require a prebyte take 4 bytes of memory.
Prebytes are either $18, $1A, or $CD Machine code and effect

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DIRECT ADDRESSING (DIR):
In direct addressing the least significant byte of the 16-bit address of the operand is
in the instruction. The high order byte is taken to be $00. This is how you access the
256 bytes of RAM.

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INHERENT (INH) ADDRESSING MODE:
In this addressing mode all the information required for execution is contained in
the instruction. No other operand is required.
Examples:
Increment an Accumulator (either A or B)
Accumulator A+Accumulator B  Accumulator A
RELATIVE ADDRESSING MODE (REL):
Relative addressing is much like it sounds. The address is relative to something else.
In the case of the 68HC11 relative addressing mode is used only for branch instructions.
It is a 2 byte instruction with the second byte being the offset (-128 to +127) to take if
the condition is TRUE. When the condition is not met, execution continues with the next
instruction.

INDEXED ADDRESSING MODE:


 There are two index address registers, X and Y, providing two indexed addressing
modes, INDX and INDY.

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 The value in the indexed register is added to an offset contained in the instruction to
obtain the effective address of the operand.
 This is best seen by an example

3. Explain the UART interface with Motorola micro controller.

The universal asynchronous receiver transmitter (UART) type serial


communications interface (sci) system, which is one of two independent serial
input/output (i/o) subsystems in the M68HC11 Family.
The SCI is a full-duplex UART-type asynchronous system, using standard non-
return-to-zero (NRZ) format (one start bit, eight or nine data bits, and a stop bit). The
SCI transmitter and receiver are functionally independent but use the same data format
and baud rate.
The block diagram of the transmitter section of the SCI subsystem is shown in the
following figure.
The heart of the transmitter is the transmit serial shift register near the top of the
figure. Usually, this shift register gets its data from the write-only transmit buffer. Data
gets into the transmit buffer when software writes to the SCI data register (SCDR).

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Fig: SCI Transmitter Block Diagram

59
Whenever data is transferred into the shifter from the transmit buffer, a 0 is loaded into
the least significant bit (LSB) of the shifter to act as a start bit, and a logic 1 is loaded into
the last bit position to act as a stop bit. In the case of a preamble, the shifter is jammed to all
1s, including the bit position usually holding the logic 0 start bit.

A preamble is jammed each time the transmit enable bit is written from 0 to 1. In the
case of a send break command,the shifter is jammed to all 0s, including the last bit position
usually holding the logic 1 stop bit. enable bit is written from 0 to 1. In the case of a send
break command, the shifter is jammed to all 0s, including the last bit position usually
holding the logic 1 stop bit.
The T8 bit in SCI control register 1 (SCCR1) acts like an extra high-order bit (ninth bit)
of the transmit buffer register. This ninth bit is only used if the M bit in SCCR1 is 1 to select
the 9-bit data character format. The M bit also controls the length of idle and break
characters. The R8 and WAKE bits in SCCR1 are associated with the SCI receiver.

The TDRE and TC status flags in the SCI status register (SCSR) are automatically set by
the transmitter logic. These two bits can be read at any time by software. The transmit
interrupt enable (TIE) and transmit complete interrupt enable (TCIE) interrupt control bits
enable the TDRE and TC bits, respectively, to generate SCI interrupt requests.

SCI Receiver
The block diagram of the receiver section of the SCI subsystem is shown in the
figure below. SCI receive data comes in the RxD pin, is buffered, and drives the data
recovery block. The data recovery block is actually a high-speed shifter operating at 16
times the bit rate; whereas, the main-receive serial shifter operates at one times the bit
rate. This higher speed sample rate allows the start-bit leading edge to be located more
accurately than a 1×clock would allow. The high-speed clock also allows several samples to
be taken within a bit time so logic can make an intelligent decision about the logic sense of
a bit (even in the presence of noise). The data recovery block provides the bit level to the
main receiver shift register and also provides a noise flag status indication.
The heart of the receiver is the receive serial shift register. This shifter is enabled by
the receive enable (RE) bit from the SCI control register 2 (SCCR2). The M bit from the
SCCR1 register determines whether the shifter will be 10 or 11 bits long. After detecting
the stop bit of a character, the received data is transferred from the shifter to the SCDR, and
the receive data register full (RDRF) status flag is set. When a character is ready to be
transferred to the receive buffer but the previous character has not yet been read, an
overrun condition occurs. In the overrun condition, data is not transferred and the overrun
(OR) status flag is set to indicate the error.
The wakeup block uses the WAKE control bit from SCCR1 to decide whether to use
the most significant bit (MSB) signal (address mark) or the ALL 1s signal (idle line) to wake
up the receiver. When the selected condition is detected, the wakeup logic clears the
receiver wake-up (RWU) bit in SCCR2, which wakes up the receiver.

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Fig: SCI Receiver Block Diagram

There are three receiver-related interrupt sources in the SCI. These flags can be
polled by software or optionally cause an SCI interrupt request. The receive interrupt
enable (RIE) control bit enables the RDRF and the OR status flags to generate hardware
interrupt requests. The idle line interrupt enable (ILIE) control bit allows the IDLE status
flag to generate SCI interrupt requests.

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SCI Registers and Control Bits
The SCI system is configured and controlled by five registers (BAUD, SCCR1, SCCR2,
SCSR, and SCDR). In addition, the port D register, data direction register for port D (DDRD),
and the port D wired-OR mode bit in the SPI control register (SPCR) are secondarily related
to the SCI system.

4. Discuss about the A/D conversion process in 68HC11 microcontrollers. (Or)


Explain ADC unit features in 68HC11.
ANALOG-TO-DIGITAL CONVERTERS

 MC68HC11 has an 8 channel, multiplexed- input, successive approximation,


analog-digital (A/D) convertor with sample and hold to minimize conversion
errors caused by rapidly changing input signals.
 The 68HC11 has an 8 bit A/D converter which results in 256 possible digital
output values.
 The resolution = FSR /256
 The FSR of the 68HC11 is 0 to 5.12V so the resolution is 20mV/1bit
 68HC11 has 4 A-to-D conversion registers
 When a conversion is done, result is placed in one of the ADRx registers, where x is
1 to 4.

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The ideal transfer function of a 3-bit ADC
 Full-scale (input voltage) range (FSR)
 Analog signal is continuous
 Digital – finite and discrete
 In general n-bit converter
 Total of 2n output codes

A/D CONVERSION SEQUENCE:

ADCTL register:

CCF: Conversions Complete Flag- This read-only status indicator is set when all four A/D
result registers contain valid conversion results. Each time the ADCTL register is written,
this bit is automatically cleared, and a new conversion sequence is started immediately.
Bit 6: Not implemented; always reads 0
SCAN: Continuous Scan Control Bit- When this bit is 0, the four requested conversions are
performed, once each, to fill the four result registers. When this bit is 1, conversions
continue in a round-robin fashion with the result registers being updated as new data
becomes available.
MULT: Multiple-Channel/Single-Channel Control Bit- When this bit is 0, the A/D system is
configured to perform four consecutive conversions on the single channel specified by the
four channel-select bits (CD:CA of the ADCTL register). When this control bit is 1, the A/D
system is configured to perform conversions on each

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channel in the group of four channels specified by the CD and CC channel-select bits. In this
multiple-channel mode, each channel is associated with a specific result register.
CD, CC, CB, and CA — Channel Select Bits.

Channel Selection When Bit 4=1

A/D PIN:
The below figure shows a model of an A/D input pin, which is useful in planning
external circuitry and connections.

5. Discuss about the different types of instruction available in Motorola micro


controller. (Or) Explain in detail the instruction set of 68HC11 microcontroller
with examples.

 Accumulator and Memory Instructions


 Stack and Index Register Instructions
 Condition Code Register Instructions
 Program Control Instructions

Accumulator and Memory Instructions

 Loads, stores, and transfers


 Arithmetic operations
 Multiply and divide
 Logical operations
 Data testing and bit manipulation
 Shifts and rotates

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loads, stores, and transfer instruction:

Arithmetic operations:

65
Multiply and divide:

Data testing and bit manipulation:

66
Data testing and bit manipulation:

Shifts and rotates:

67
PROGRAM CONTROL INSTRUCTIONS:
 Branches
 Jumps
 Subroutine calls and returns
 Interrupt handling
 Miscellaneous

Branch instructions:

Jump instructions:

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Subroutine calls and returns:

Interrupt handling instructions:

Miscellaneous instructions:

69
UNIT V PIC MICROCONTROLLER

PART A

1. What is watchdog timer in PIC microcontroller?


A watch dog timer (user programmable) resets the processor if the
software/program ever malfunctions and deviates from its normal operation.

2. Show the status register format in PIC micro controller.


The STATUS register is a 8-bit register that stores the status of the processor. This
also stores carry, zero and digit carry bits.

C = Carry bit
DC = Digit carry
Z = Zero bit NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0 = Register bank select bit used in conjunction with direct addressing mode.

3. Name the different interrupt sources present in PIC micro controller.


 External interrupt. This is the only external interrupt input. It shares a pin with
Port B, bit 0.It is edge triggered.
 Timer overflow. This is an interrupt caused by the Timer 0 module. It occurs
when the timer’s 8-bit counter overflows.
 Port B interrupt on change. This interrupts when a change is detected on any of
the higher 4 bits of Port B.
 EEPROM write complete. This interrupts when a write instruction to the
EEPROM memory is completed.

4. What is the function of CCP module in PIC microcontrollers?


A register that can record the time of an event is called a ‘Capture’ register. One that
can generate an alarm does this by holding a preset value and comparing it with the
value of a running timer (as we have seen already with PR2). The alarm occurs when
the two are equal. Such registers are called ‘Compare’ registers. The CCP modules are
very versatile, and interact with both Timer 1 and Timer 2.

5. What is meant by UART?


UART stands for universal Asynchronous Receiver/Transmitter.
· UART is a hardware component for translating the data between parallel and serial
interfaces.
· UART does convert bytes of data to and from asynchronous start stop bit.
· UART is normally used in MODEM.

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6. Define Real Time Clock (RTC)?
Real time clock is a clock which once the system stats does not stop and can’t be
reset and its count value can’t be reloaded.

7. Define INTCON & ADCON register.


INTCON:

ADCON:

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8. What does UART contain?
· A clock generator.
· Input and Output start Registers
· Buffers.
· Transmitter/Receiver control.

9. What is PIC?
PIC refers to Programmable Intelligent Computer. PIC is microprocessor lies inside a
personal computer but significantly simpler, smaller and cheaper. It can be used for
operating relays, measuring sensors etc.

10. What are the main elements inside a PIC?


Processing engine, Program memory, data memory and Input/output.

PART B

1. Explain interrupts handing in PIC micro controller. (or) Describe the interrupt
structure of PIC microcontrollers.
If an interrupt occurs, it sets an S-R bistable. The occurrence of the interrupt,
even if it is only momentary, is thus recorded. The output of the bistable, the latched
version of the interrupt, is called the interrupt flag. This is then gated with an enable
signal, Interrupt X Enable. If this is high, then the interrupt signal progresses to an OR
gate. If it is low, the interrupt signal gets no further. If enabled, it is ORed with other
enabled interrupt inputs of the microcontroller. The OR gate output will go high if any
interrupt input is high. There is then a further gating of the OR gate output, this time
with a Global Interrupt Enable. Only if that value is high can any interrupt signal reach
the CPU. The action of disabling an interrupt is sometimes called masking.

Figure: A simple generic interrupt structure


The 16F84A interrupt structure
The 16F84A has four interrupt sources, all of which can be individually enabled or
disabled:

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• External interrupt. This is the only external interrupt input. It shares a pin with Port B, bit
0.
It is edge triggered.
• Timer overflow. This is an interrupt caused by the Timer 0 module. It occurs when the
timer’s 8-bit counter overflows.
• Port B interrupt on change. This interrupts when a change is detected on any of the
higher 4 bits of Port B.
• EEPROM write complete. This interrupts when a write instruction to the EEPROM
memory is completed and the SFR that controls it, INTCON.

Figure: The 16F84A interrupt structure

Fig. The 16F84A INTCON register

GIE: Global Interrupt Enable; 1 = Enables all un‐masked interrupts


0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable; 1 = Enables all un‐masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: Overflow Interrupt Enable; 1 = Enables TMR0 overflow interrupt
0 = Disables TMR0 overflow interrupt
INTE: External Interrupt Enable; 1 = Enables INT external interrupt
0 = Disables INT external interrupt
RBIE: RB Port Change Interrupt Enable; 1 = Enables RB port change interrupt
0 = Disables RB port change interrupt
T0IF: Overflow Interrupt Flag; 1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
INTF External Interrupt Flag; 1 = INT external interrupt occurred
0 = INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag; 1 = At least one of RB7:RB4 pins changed state
0 = None of RB7:RB4 pins have changed state

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Thus, the lines TOIF, INTF and so on are actually the interrupt flags, rather than the
interrupt inputs themselves. All can be seen as bits in the INTCON register, with the
exception of the EEPROM write complete flag and enable. The external interrupt is edge
triggered. The edge it responds to is controlled by the setting of the INTEDG bit of the
OPTION register.In general interrupt structure each flag is ANDed with a corresponding
Enable input (TOIE, INTE, RBIE and EEIE).
The enable bits are located in the INTCON register and can be set by the
programmer. The outputs of the four AND gates are then ORed together, before passing on
to the Global Enable gate. Interrupt flags must be cleared by manipulating their INTCON
bits in the program. The 16F84A has no non-maskable interrupt input.
The interrupt is therefore detected by the CPU and it executes a special section of
program called the Interrupt Service Routine (ISR). The ISR must start at the interrupt
vector, program memory location 0004.Therefore, when an interrupt occurs, this value is
loaded into the Program Counter and program execution then continues from the reset
vector.
In any processor, the ISR must end with a special ‘return from interrupt’ instruction.
In the 16 Series this is the retfie instruction. When this is detected, the CPU sets the GIE to
1, loads the Program Counter from the top of the Stack and then resumes program
execution. Thus, it returns to the instruction which follows the instruction during which the
interrupt was detected.

Figure: The 16F84A interrupt response sequence of events

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2. Describe the architecture of PIC micro controllers. (Or) Discuss the core
architectural features of PIC microcontrollers.
PIC stands for Peripheral Interface Controller given by Microchip Technology to
identify its single-chip microcontrollers.
Features:
1. Speed: Harvard Architecture, RISC Architecture
1 instruction Cycle = 4 clock cycles.
For 20 MHz clock, most of the instructions are executed in 0.2μs or
five instructions per microsecond.
2. Instruction Set Simplicity:
The instruction set consists of just 35 instructions (as opposed to 111
instructions for 8051)

3. Power on reset
Power-out reset
Watch-dog timer
Oscillator Options
• low-power Crystal
• Mid-range Crystal
• High-range Crystal
• RC Oscillator
4. Programmable timer options on chip ADC
5. Up to 12 independent interrupt sources
6. Powerful output pin control
25mA (max.) current sourcing capability.
7. EPROM/OTP/ROM/Flash memory options.
8. Free assembler and simulator support from microchip

CPU Architecture:

75
The block diagram mainly consists of CPU (Central Processing Unit), containing the
8-bit ALU (Arithmetic Logic Unit), the Working register ‘WREG’(sometimes called the
accumulator) and an 8-bit × 8-bit hardware multiply unit. CPU action is determined by the
instruction received from program memory, which is transferred through the Instruction
register.

Fig: Basic Architecture of PIC 16C74A

The basic architecture of PIC16C74A is shown in the above figure. The architecture
consists of Program memory, file registers and RAM, ALU and CPU registers. The program
Counter is 13 - bit and the program memory is organized as 14 - bit word. Hence the
program Memory capacity is 8k x 14 bit. Each instruction of PIC 16C74A is 14 - bit long.
CPU registers (registers commonly used by the CPU)
W, the working register, is used by many instructions as the source of an operand. This is
similar to accumulator in 8051. It may also serve as the destination for the result of the
instruction execution. It is an 8 - bit register.

STATUS Register
The STATUS register is a 8-bit register that stores the status of the processor. This also
stores carry, zero and digit carry bits.
STATUS - address 03H, 83H

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Fig: STATUS Register
C = Carry bit
DC = Digit carry
Z = Zero bit NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0 = Register bank select bit used in conjunction with direct addressing
mode.

FSR Register
(File Selection Register, address = 04H, 84H) FSR is an 8-bit register used as data memory
address pointer. This is used in indirect addressing mode.

INDF Register
(INDirect through FSR, address = 00H, 80H) INDF is not a physical register. Accessing INDF
access is the location pointed to by FSR in indirect addressing mode.

PCL Register
(Program Counter Low Byte, address = 02H, 82H) PCL is actually the lower 8-bits of the 13-
bit program counter. This is a both readable and writable register.

PCLATH Register
(Program Counter Latch, address = 0AH, 8AH) PCLATH is a 8-bit register which can
be used to decide the upper 5bits of the program counter. PCLATH is not the upper 5bits of
the program counter. PCLATH can be read from or written to without affecting the program
counter. The upper 3bits of PCLATH remain zero and they serve no purpose. When PCL is
written to, the lower 5bits of PCLATH are automatically loaded to the upper 5bits of the
program counter, as shown in the following figure.

Figure: Schematic of how PCL is loaded from PCLATH

Program Counter Stack


An independent 8-level stack is used for the program counter. As the program
counter is 13bit, the stack is organized as 8x13bit registers. When an interrupt occurs, the
program counter is pushed onto the stack. When the interrupt is being serviced, other

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interrupts remain disabled. Hence, other 7 registers of the stack can be used for subroutine
calls within an interrupt service routine or within the mainline program.
Register File Map
Some of the special purpose registers are available both in Bank-0 and Bank-1.
These registers have the same value in both banks. Changing the register content in one
bank automatically changes its content in the other bank.

Port Structure and Pin Configuration of PIC 16C74A


PIC 16C74A has 5 I/O Ports. Each port is a bidirectional I/O port. In addition, they have the
following alternate functions.
In addition to I/O pins, there is a Master clear pin (MCLR) which is equivalent to
reset in 8051. However, unlike 8051, MCLR should be pulled low to reset the micro
controller. Since PIC16C74Ahas inherent power-on reset, no special connection is required
with MCLR pin to reset the micro controller on power-on.
There are two VDD pins and two VSS pins. There are two pins (OSC1 and OSC2) for
connecting the crystal oscillator/ RC oscillator. Hence the total number of pins with a
16C74A is 33+7=40. This IC is commonly available in a dual-in-pin (DIP) package.

3. Describe the features of UART and A/D converter in PIC micro controller. Analog-
to-Digital Converter
Features (16C7X)

• Eight input channels


• An analog multiplexer
• A track and hold circuit for signal on the selected input channel
• Alternative clock sources for carrying out the conversion.
• An adjustable autonomous sampling rate.
• The choice of an internal or external ref. voltage.
• 8-bit conversion
• Interrupt response when conversion is completed.

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Port A and Port E pins are used for analog inputs/ Reference voltage for ADC.
Port A pins
RA0/AN0 - Can be used as analog input-0
RA1/AN1 - Can be used as analog input-1
RA2/AN2 - Can be used as analog input-2
RA3/AN3/VREF - RA3 can be used as analog input 3 or analog reference voltage
RA4/TOCKI - RA4 can be used as clock input to Timer-0
RA5/SS/AN4 - RA5 can be used as analog input 4 or the slave select for the sync serial port
Port E pins
RE0/RD/AN5 - Can be used as analog input 5
RE1/WR/AN6 - Can be used as analog input 6
RE2/CS/AN7 - Can be used as analog input 7

PIC microcontroller has internal sample and hold circuit. The input signal should be
stable across the capacitor before the conversion is initiated.

After waiting out the sampling time, a conversion can be initiated. The ADC circuit will
open the sampling switch and carry out the conversion of the input voltage as it was at the

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moment of opening of the switch. Upon completion of the conversion, the sampling switch
is closed and VHOLD again tracks VSOURCE.
Registers ADCON1, TRISA, and TRISE must be initialized to select the reference
voltage and the input channels. The first step selects the ADC clock source from among four
choices (OSC/2, OSC/8, OSC/32, and RC).
The A/D modules has three registers. These registers are
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCONO)
• A/D Control Register 1 (ADCON1)
The ADCONO register as shown here, controls the operation of A/D module.

Fig.: ADCON0 Register

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Fig.: ADCON1 Register

4. Explain I2C interfacing with PIC micro controller (or) Explain the data
communication protocol of I2C bus.
I2C is Inter Integrated Circuit which requires two open-drain I/O pins. Port-C of PIC
IC can be used for I2C communication.
SCL (Serial Clock) RC3/SCK/SCL
SDA (Serial Data) RC4/SDI/SDA

Low output on SCL or SDA I/O pin set to be an output with ”0” written to it.
High output on SCL or SDA I/O pin set to be an input.
Transfers on the I2C bus take place a bit at a time.

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The clock line, SCL, is driven by the PIC chip, which server as bus master. The open drain
feature of every chip’s bus driver can be used by the receiver to hold the clock line low,
there by signaling the transmitter to pause until the clock line is released by the receiver.
The open drain feature is also needed if this PIC will ever become an I2C slave to another
PIC, in which it must relinquish control of the SCL line. The last figure illustrates that the
first eight bits on the SDA line are sent by the transmitter whereas the ninth bit is the
acknowledgment bit which is sent by the receiver in response to the byte sent by the
transmitter.
When the PIC sends out a chip address, it is the transmitter, while every other chip
on the I2C bus is a receiver. During the acknowledgment bit time, the addressed chip is the
only one that drives the SDA line, pulling it low in response to the masters pulse on SCL,
acknowledging the reception of its chip address.
When the data transfer direction is reversed that is form a peripheral chip to the
PIC, which is the master, the peripheral chip drives the eight data bits in response to the
clock pulse from PIC.
In this case, the acknowledge bit is driven in a special way by the PIC, which is
serving as receive but also as bus master. If the peripheral chip is one that can send the
contents of successive internal address back to the PIC, then PIC completes the reception of
each byte and signals a request for the next byte by pulling SDA line low in
acknowledgment.
After any number of bytes have been received by the master from the peripheral,
the PIC can signal the peripheral to stop any further transfers by not pulling the SDA line
low in acknowledgment.
SDA line should be stable during high period of the clock (SCL). When the slave
peripheral is driving SDA line , either as transmiter or acknowledge, it initiates the new bit
in response to the falling edge of SCL, after a specified time. It maintains that bit on SDA line
until the next falling edge of SCL, again after a specified hold time.
I2C bus transfers consist of a number of byte transfers framed between a START
condition and either another START condition or a STOP condition. Both SDA and SCL lines
are released by all drives and float high when bus transfers are not taking place. The PIC
(I2C bus controller) initiates a transfer with a START condition by first pulling SDA low and
then pulling SCL as shown in the figure.

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The PIC terminates a multiple byte transfer with the STOP condition. With both SDA
and SCL initially low, it first releases SCL and then SDA. Both then occurrences are easily
recognized by I2C hardware in each peripheral chip since they both consist of a chage in
SDA line which SCL is high, a condition that never happens in the middle of a byte transfer.

I2C Bus Subroutines:


I2C bus fast-mode timing constraints

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5. ii. Discuss in detail the organization of program and data memory of PIC
microcontrollers? PIC Memory Organisation:
Program Memory:
PIC microcontroller has 13 bits of program memory address. Hence it can address
up to 8k of program memory. The program counter is 13-bit. PIC 16C6X or 16C7X program
memory is 2k or 4k. While addressing 2k of program memory, only 11- bits are required.
Hence two most significant bits of the program counter are ignored. Similarly, while
addressing 4k of memory, 12 bits are required. Hence the MSB of the program counter is
ignored.
The program memory map of PIC16C74A is shown in Fig.2. On reset, the program
counter is cleared and the program starts at 00H. Here a 'go to' instruction is required that
takes the processor to the mainline program.
When a peripheral interrupt, that is enabled, is received, the processor goes to
004H. A suitable branching to the interrupt service routine (ISR) is written at 004H.

Figure: Program memory map

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Data memory (Register Files):
Data Memory is also known as Register File. Register File consists of two components.

1. General purpose register file (same as RAM).


2. Special purpose register file (similar to SFR in 8051).

The special purpose register file consists of input/output ports and control
registers. Addressing from 00H to FFH requires 8 bits of address. However, the instructions
that use direct addressing modes in PIC to address these register files use 7 bits of
instruction only. Therefore the register bank select (RP0) bit in the STATUS register is used
to select one of the register banks.
In indirect addressing FSR register is used as a pointer to anywhere from 00H to FFH in the
data memory.

Figure: Data memory map

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