®

CA3130, CA3130A

Data Sheet August 1, 2005 FN817.6

15MHz, BiMOS Operational Amplifier with Features

MOSFET Input/CMOS Output • MOSFET Input Stage Provides:
CA3130A and CA3130 are op amps that combine the - Very High ZI = 1.5 TΩ (1.5 x 1012Ω) (Typ)
advantage of both CMOS and bipolar transistors. - Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
Gate-protected P-Channel MOSFET (PMOS) transistors are . . . . . . . . . . . . . . . . . . . . . .= 2pA (Typ) at 5V Operation
used in the input circuit to provide very-high-input • Ideal for Single-Supply Applications
impedance, very-low-input current, and exceptional speed • Common-Mode Input-Voltage Range Includes
performance. The use of PMOS transistors in the input stage Negative Supply Rail; Input Terminals can be Swung 0.5V
results in common-mode input-voltage capability down to Below Negative Supply Rail
0.5V below the negative-supply terminal, an important
• CMOS Output Stage Permits Signal Swing to Either (or
attribute in single-supply applications.
both) Supply Rails
A CMOS transistor-pair, capable of swinging the output • Pb-Free Plus Anneal Available (RoHS Compliant)
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the Applications
output circuit.
• Ground-Referenced Single Supply Amplifiers
The CA3130 Series circuits operate at supply voltages
• Fast Sample-Hold Amplifiers
ranging from 5V to 16V, (±2.5V to ±8V). They can be phase
compensated with a single external capacitor, and have • Long-Duration Timers/Monostables
terminals for adjustment of offset voltage for applications
• High-Input-Impedance Comparators
requiring offset-null capability. Terminal provisions are also (Ideal Interface with Digital CMOS)
made to permit strobing of the output stage.
• High-Input-Impedance Wideband Amplifiers
• The CA3130A offers superior input characteristics over
those of the CA3130. • Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)
Ordering Information • Voltage Regulators (Permits Control of Output Voltage
PART NO. TEMP. PKG. Down to 0V)
(BRAND) RANGE (oC) PACKAGE DWG. #
• Peak Detectors
CA3130AE -55 to 125 8 Ld PDIP E8.3
CA3130AM -55 to 125 8 Ld SOIC M8.15 • Single-Supply Full-Wave Precision Rectifiers
(3130A)
CA3130AM96 -55 to 125 8 Ld SOIC M8.15
• Photo-Diode Sensor Amplifiers
(3130A) Tape and Reel
CA3130AMZ -55 to 125 8 Ld SOIC M8.15 Pinout
(3130AZ) (Note) (Pb-free) CA3130, CA3130A
CA3130AMZ96 -55 to 125 8 Ld SOIC M8.15 (PDIP, SOIC)
(3130AZ) (Note) Tape and Reel (Pb-free) TOP VIEW
CA3130E -55 to 125 8 Ld PDIP E8.3
CA3130EZ -55 to 125 8 Ld PDIP* E8.3 OFFSET 1 8 STROBE
(Note) (Pb-free) NULL
CA3130M -55 to 125 8 Ld SOIC M8.15 INV. 2 7 V+
INPUT -
(3130) +
NON-INV. 3 6 OUTPUT
CA3130M96 -55 to 125 8 Ld SOIC M8.15 INPUT
(3130) Tape and Reel V- 4 5 OFFSET
CA3130MZ -55 to 125 8 Ld SOIC M8.15 NULL
(3130MZ) (Note) (Pb-free)
CA3130MZ96 -55 to 125 8 Ld SOIC M8.15
(3130MZ) Tape and Reel (Pb-free)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not
intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 CA3130, CA3130A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V PDIP Package*. . . . . . . . . . . . . . . . . . . 115 N/A
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions (SOIC - Lead Tips Only)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC *Pb-free PDIPs can be used for through hole wave solder process-
ing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

CA3130 CA3130A
TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Input Offset Voltage |VIO| VS = ±7.5V - 8 15 - 2 5 mV

Input Offset Voltage ∆VIO/∆T - 10 - - 10 - µV/oC

Temperature Drift

Input Offset Current |IIO| VS = ±7.5V - 0.5 30 - 0.5 20 pA

Input Current II VS = ±7.5V - 5 50 - 5 30 pA

Large-Signal Voltage Gain AOL VO = 10VP-P 50 320 - 50 320 - kV/V

RL = 2kΩ
94 110 - 94 110 - dB

Common-Mode CMRR 70 90 - 80 90 - dB
Rejection Ratio

Common-Mode Input VICR 0 -0.5 to 12 10 0 -0.5 to 12 10 V

Voltage Range

Power-Supply ∆VIO/∆VS VS = ±7.5V - 32 320 - 32 150 µV/V

Rejection Ratio

Maximum Output Voltage VOM+ RL = 2kΩ 12 13.3 - 12 13.3 - V

VOM- RL = 2kΩ - 0.002 0.01 - 0.002 0.01 V

VOM+ RL = ∞ 14.99 15 - 14.99 15 - V

VOM- RL = ∞ - 0 0.01 - 0 0.01 V

Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA

IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA

Supply Current I+ VO = 7.5V, - 10 15 - 10 15 mA

RL = ∞

I+ VO = 0V, - 2 3 - 2 3 mA
RL = ∞

2
 CA3130, CA3130A

Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified

CA3130,
PARAMETER SYMBOL TEST CONDITIONS CA3130A UNITS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or ±22 mV
4 and 1

Input Resistance RI 1.5 TΩ

Input Capacitance CI f = 1MHz 4.3 pF

Equivalent Input Noise Voltage eN BW = 0.2MHz, RS = 1MΩ 23 µV

(Note 3)

Open Loop Unity Gain Crossover Frequency CC = 0 15 MHz

(For Unity Gain Stability ≥47pF Required.) fT
CC = 47pF 4 MHz

Slew Rate: SR

Open Loop CC = 0 30 V/µs

Closed Loop CC = 56pF 10 V/µs

Transient Response: CC = 56pF,
CL = 25pF,
Rise Time tr 0.09 µs
RL = 2kΩ
Overshoot OS (Voltage Follower) 10 %

Settling Time (To <0.1%, VIN = 4VP-P) tS 1.2 µs

NOTE:
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC
Unless Otherwise Specified (Note 4)

PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS

Input Offset Voltage VIO 8 2 mV

Input Offset Current IIO 0.1 0.1 pA

Input Current II 2 2 pA

Common-Mode Rejection Ratio CMRR 80 90 dB

Large-Signal Voltage Gain AOL VO = 4VP-P, RL = 5kΩ 100 100 kV/V

100 100 dB

Common-Mode Input Voltage Range VICR 0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V

NOTE:
4. Operation at 5V is not recommended for temperatures below 25oC.

3
 CA3130, CA3130A

Schematic Diagram

CURRENT SOURCE FOR “CURRENT SOURCE 7 V+

BIAS CIRCUIT Q6 AND Q7 LOAD” FOR Q11

Q1 Q2 Q3

D1
Z1 D2
8.3V Q4 Q5
D3

R1 D4

40kΩ R
2

5kΩ SECOND
STAGE

INPUT STAGE

NON-INV. D5 D6 (NOTE 5) D7 D8
INPUT

3 OUTPUT
+ STAGE Q8
INV.-INPUT Q6 Q7 OUTPUT
2
- 6
R3 R4
1kΩ 1kΩ
Q9 Q10
Q12
Q11

R5 R6
1kΩ 1kΩ

5 OFFSET NULL 1 COMPENSATION 8 STROBING 4 V-

NOTE:
5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.

Application Information
Circuit Description the output stage under the strobed “OFF” condition can only
Figure 1 is a block diagram of the CA3130 Series CMOS be achieved when the ohmic load resistance presented to
Operational Amplifiers. The input terminals may be operated the amplifier is very high (e.g.,when the amplifier output is
down to 0.5V below the negative supply rail, and the output used to drive CMOS digital circuits in Comparator
can be swung very close to either supply rail in many applications).
applications. Consequently, the CA3130 Series circuits are Input Stage
ideal for single-supply operation. Three Class A amplifier
The circuit of the CA3130 is shown in the schematic diagram.
stages, having the individual gain capability and current
It consists of a differential-input stage using PMOS field-effect
consumption shown in Figure 1, provide the total gain of the
transistors (Q6, Q7) working into a mirror-pair of bipolar
CA3130. A biasing circuit provides two potentials for
transistors (Q9, Q10) functioning as load resistors together
common use in the first and second stages.
with resistors R3 through R6.
Terminal 8 can be used both for phase compensation and to
The mirror-pair transistors also function as a differential-to-
strobe the output stage into quiescence. When Terminal 8 is
single-ended converter to provide base drive to the second-
tied to the negative supply rail (Terminal 4) by mechanical or
stage bipolar transistor (Q11). Offset nulling, when desired,
electrical means, the output potential at Terminal 6
can be effected by connecting a 100,000Ω potentiometer
essentially rises to the positive supply-rail potential at
across Terminals 1 and 5 and the potentiometer slider arm to
Terminal 7. This condition of essentially zero current drain in
Terminal 4.

4
 CA3130, CA3130A

sources for both the first and second amplifier stages,

V+
CA3130 respectively.
7
200µA 1.35mA 200µA 8mA At total supply voltages somewhat less than 8.3V, zener
(NOTE 5)
BIAS CKT. 0mA diode Z1 becomes nonconductive and the potential,
(NOTE 7)
developed across series-connected R1, D1-D4, and Q1,
+
varies directly with variations in supply voltage.
OUTPUT Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in
3
AV ≈ AV ≈ accordance with supply-voltage variations. This variation
INPUT AV ≈ 5X 6000X 30X 6
2
results in deterioration of the power-supply-rejection ratio
- V-
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
4
degraded performance.
CC
5 1 8 STROBE Output Stage
COMPENSATION
OFFSET (WHEN REQUIRED) The output stage consists of a drain-loaded inverting
NULL amplifier using CMOS transistors operating in the Class A
NOTES: mode. When operating into very high resistance loads, the
6. Total supply voltage (for indicated voltage gains) = 15V with input output can be swung within millivolts of either supply rail.
terminals biased so that Terminal 6 potential is +7.5V above Because the output stage is a drain-loaded amplifier, its gain
Terminal 4. is dependent upon the load impedance. The transfer
7. Total supply voltage (for indicated voltage gains) = 15V with characteristics of the output stage for a load returned to the
output terminal driven to either supply rail.
negative supply rail are shown in Figure 2. Typical op amp
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES loads are readily driven by the output stage. Because large-
Cascade-connected PMOS transistors Q2, Q4 are the signal excursions are non-linear, requiring feedback for good
constant-current source for the input stage. The biasing circuit waveform reproduction, transient delays may be
for the constant-current source is subsequently described. encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
The small diodes D5 through D8 provide gate-oxide protection
against high-voltage transients, including static electricity NOTE:
during handling for Q6 and Q7. 8. For general information on the characteristics of CMOS
transistor-pairs in linear-circuit applications, see File Number
Second-Stage 619, data sheet on CA3600E “CMOS Transistor Array”.
Most of the voltage gain in the CA3130 is provided by the
OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

second amplifier stage, consisting of bipolar transistor Q11 17.5

SUPPLY VOLTAGE: V+ = 15, V- = 0V
and its cascade-connected load resistance provided by TA = 25oC
15
PMOS transistors Q3 and Q5. The source of bias potentials LOAD RESISTANCE = 5kΩ
for these PMOS transistors is subsequently described. Miller 12.5 2kΩ
Effect compensation (roll-off) is accomplished by simply 1kΩ
connecting a small capacitor between Terminals 1 and 8. A 10
500Ω
47pF capacitor provides sufficient compensation for stable
7.5
unity-gain operation in most applications.
5
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2 2.5
and zener diode Z1 serve to establish a voltage of 8.3V across
0
the series-connected circuit, consisting of resistor R1, diodes
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5
D1 through D4, and PMOS transistor Q1. A tap at the junction
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
of resistor R1 and diode D4 provides a gate-bias potential of
about 4.5V for PMOS transistors Q4 and Q5 with respect to FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
Terminal 7. A potential of about 2.2V is developed across CMOS OUTPUT STAGE
diode-connected PMOS transistor Q1 with respect to Terminal
7 to provide gate bias for PMOS transistors Q2 and Q3. It
should be noted that Q1 is “mirror-connected (see Note 8)” to
both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to
be identical, the approximately 200µA current in Q1
establishes a similar current in Q2 and Q3 as constant current

5
 CA3130, CA3130A

Input Current Variation with Common Mode Input typical variation of input bias current as a function of
Voltage temperature in the CA3130.
As shown in the Table of Electrical Specifications, the input
4000
current for the CA3130 Series Op Amps is typically 5pA at VS = ±7.5V
TA = 25oC when Terminals 2 and 3 are at a common-mode 1000
potential of +7.5V with respect to negative supply Terminal 4.

INPUT CURRENT (pA)

Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at TA = 25oC.
100
These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the
common-mode input voltage does not exceed 2V. As 10
previously noted, the input current is essentially the result of
the leakage current through the gate-protection diodes in the
input circuit and, therefore, a function of the applied voltage. 1
Although the finite resistance of the glass terminal-to-case -80 -60 -40 -20 0 20 40 60 80 100 120 140
insulator of the metal can package also contributes an TEMPERATURE (oC)

increment of leakage current, there are useful compensating FIGURE 4. INPUT CURRENT vs TEMPERATURE
factors. Because the gate-protection network functions as if In applications requiring the lowest practical input current
it is connected to Terminal 4 potential, and the Metal Can and incremental increases in current because of “warm-up”
case of the CA3130 is also internally tied to Terminal 4, input effects, it is suggested that an appropriate heat sink be used
Terminal 3 is essentially “guarded” from spurious leakage with the CA3130. In addition, when “sinking” or “sourcing”
currents. significant output current the chip temperature increases,
10 causing an increase in the input current. In such cases, heat-
TA = 25oC
sinking can also very markedly reduce and stabilize input
current variations.
15V
7.5 V+ Input Offset Voltage (VIO) Variation with DC Bias
INPUT VOLTAGE (V)

TO
5V
and Device Operating Life
7 It is well known that the characteristics of a MOSFET device
5 2
PA CA3130 6 can change slightly when a DC gate-source bias potential is
3 applied to the device for extended time periods. The
2.5
8 magnitude of the change is increased at high temperatures.
VIN 4 0V Users of the CA3130 should be alert to the possible impacts
TO
-10V of this effect if the application of the device involves extended
0 V- operation at high temperatures with a significant differential
-1 0 1 2 3 4 5 6 7 DC bias voltage applied across Terminals 2 and 3. Figure 5
INPUT CURRENT (pA)
shows typical data pertinent to shifts in offset voltage
FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE
encountered with CA3130 devices (metal can package)
Offset Nulling during life testing. At lower temperatures (metal can and
plastic), for example at 85oC, this change in voltage is
Offset-voltage nulling is usually accomplished with a
considerably less. In typical linear applications where the
100,000Ω potentiometer connected across Terminals 1 and
differential voltage is small and symmetrical, these
5 and with the potentiometer slider arm connected to
incremental changes are of about the same magnitude as
Terminal 4. A fine offset-null adjustment usually can be
those encountered in an operational amplifier employing a
effected with the slider arm positioned in the mid-point of the
bipolar transistor input stage. The 2VDC differential voltage
potentiometer’s total range.
example represents conditions when the amplifier output
Input-Current Variation with Temperature stage is “toggled”, e.g., as in comparator applications.
The input current of the CA3130 Series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate-protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the
leakage current approximately doubles for every 10oC
increase in temperature. Figure 4 provides data on the

6
 CA3130, CA3130A

increased and current flow through Q8 (from the positive

o

7
TA = 125oC FOR TO-5 PACKAGES supply) decreases correspondingly. When the gate terminals
OFFSET VOLTAGE SHIFT (mV)

6 of Q8 and Q12 are driven increasingly negative with respect

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V to ground, current flow through Q8 is increased and current
5 OUTPUT STAGE TOGGLED flow through Q12 is decreased accordingly.
4
Single-supply Operation: Initially, let it be assumed that the
3 value of RL is very high (or disconnected), and that the input-
terminal bias (Terminals 2 and 3) is such that the output
2 terminal (No. 6) voltage is at V+/2, i.e., the voltage drops
DIFFERENTIAL DC VOLTAGE
1 (ACROSS TERMINALS 2 AND 3) = 0V across Q8 and Q12 are of equal magnitude. Figure 20 shows
OUTPUT VOLTAGE = V+ / 2 typical quiescent supply-current vs supply-voltage for the
0 CA3130 operated under these conditions. Since the output
0 500 1000 1500 2000 2500 3000 3500 4000 stage is operating as a Class A amplifier, the supply-current
TIME (HOURS) will remain constant under dynamic operating conditions as
FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE long as the transistors are operated in the linear portion of
SHIFT vs OPERATING LIFE
their voltage-transfer characteristics (see Figure 2). If either
V+ Q8 or Q12 are swung out of their linear regions toward cut-off
7
(a non-linear region), there will be a corresponding reduction
CA3130 in supply-current. In the extreme case, e.g., with Terminal 8
3 +
Q8 swung down to ground potential (or tied to ground), NMOS
6 transistor Q12 is completely cut off and the supply-current to
Q12
RL series-connected transistors Q8, Q12 goes essentially to zero.
2 -
The two preceding stages in the CA3130, however, continue
4 to draw modest supply-current (see the lower curve in Figure
8 V- 20) even though the output stage is strobed off. Figure 6A
shows a dual-supply arrangement for the output stage that
FIGURE 6A. DUAL POWER SUPPLY OPERATION can also be strobed off, assuming RL = ∞ by pulling the
potential of Terminal 8 down to that of Terminal 4.
7 V+ Let it now be assumed that a load-resistance of nominal
CA3130 value (e.g., 2kΩ) is connected between Terminal 6 and
3 +
Q8 ground in the circuit of Figure 6B. Let it be assumed again
6 that the input-terminal bias (Terminals 2 and 3) is such that
Q12 the output terminal (No. 6) voltage is at V+/2. Since PMOS
RL
2 -
transistor Q8 must now supply quiescent current to both RL
4
and transistor Q12, it should be apparent that under these
conditions the supply-current must increase as an inverse
8
function of the RL magnitude. Figure 22 shows the voltage-
drop across PMOS transistor Q8 as a function of load
FIGURE 6B. SINGLE POWER SUPPLY OPERATION current at several supply voltages. Figure 2 shows the
FIGURE 6. CA3130 OUTPUT STAGE IN DUAL AND SINGLE voltage-transfer characteristics of the output stage for
POWER SUPPLY OPERATION several values of load resistance.

Power-Supply Considerations
Because the CA3130 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single-and dual-supply service. Figures 6A and 6B show the
CA3130 connected for both dual-and single-supply
operation.
Dual-supply Operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q8 and Q12 are driven
increasingly positive with respect to ground, current flow
through Q12 (from the negative supply) to the load is
Wideband Noise
From the standpoint of low-noise performance
considerations, the use of the CA3130 is most advantageous
in applications where in the source resistance of the input
signal is on the order of 1MΩ or more. In this case, the total
input-referred noise voltage is typically only 23µV when the
test-circuit amplifier of Figure 7 is operated at a total supply
voltage of 15V. This value of total input-referred noise
remains essentially constant, even though the value of
source resistance is raised by an order of magnitude. This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for

7
 CA3130, CA3130A
values of source resistance very much greater than 1MΩ,
the total noise voltage generated can be dominated by the
thermal noise contributions of both the feedback and source
resistors.
+7.5V
0.01µF
Rs 7
3 + NOISE
1MΩ 6 VOLTAGE
2 - OUTPUT
4
8 30.1kΩ
1
0.01
µF
47pF -7.5V
BW (-3dB) = 200kHz 1kΩ
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23µV (TYP)
FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED
FOR WIDEBAND NOISE MEASUREMENTS
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like
the CA3130, are particularly suited to service as voltage
followers. Figure 8 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA3130 in a split-supply configuration.
A voltage follower, operated from a single supply, is shown in
Figure 9, together with related waveforms. This follower
circuit is linear over a wide dynamic range, as illustrated by
the reproduction of the output waveform in Figure 9A with
input-signal ramping. The waveforms in Figure 9B show that
the follower does not lose its input-to-output phase-sense,
even though the input is being swung 7.5V below ground
potential. This unique characteristic is an important attribute
in both operational amplifier and comparator applications.
Figure 9B also shows the manner in which the CMOS output
stage permits the output signal to swing down to the
negative supply-rail potential (i.e., ground in the case
shown). The digital-to-analog converter (DAC) circuit,
described later, illustrates the practical use of the CA3130 in
a single-supply voltage-follower application.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 10. This system combines the concepts of
multiple-switch CMOS lCs, a low-cost ladder network of
discrete metal-oxide-film resistors, a CA3130 op amp
connected as a follower, and an inexpensive monolithic
regulator in a simple single power-supply arrangement. An
additional feature of the DAC is that it is readily interfaced
8
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 10.
The circuit uses an R/2R voltage-ladder network, with the
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power-supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive
or negative power-supply terminal. The resistor ladder is an
assembly of 1% tolerance metal-oxide film resistors. The five
arms requiring the highest accuracy are assembled with
series and parallel combinations of 806,000Ω resistors from
the same manufacturing lot.
A single 15V supply provides a positive bus for the CA3130
follower amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line-
voltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
Single-Supply, Absolute-Value, Ideal Full-Wave
Rectifier
The absolute-value circuit using the CA3130 is shown in
Figure 11. During positive excursions, the input signal is fed
through the feedback network directly to the output.
Simultaneously, the positive excursion of the input signal
also drives the output terminal (No. 6) of the inverting
amplifier in a negative-going excursion such that the 1N914
diode effectively disconnects the amplifier from the signal
path. During a negative-going excursion of the input signal,
the CA3130 functions as a normal inverting amplifier with a
gain equal to -R2/R1. When the equality of the two equations
shown in Figure 11 is satisfied, the full-wave output is
symmetrical.
Peak Detectors
Peak-detector circuits are easily implemented with the
CA3130, as illustrated in Figure 12 for both the peak-positive
and the peak-negative circuit. It should be noted that with
large-signal inputs, the bandwidth of the peak-negative
circuit is much less than that of the peak-positive circuit. The
second stage of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion requires a
positive-going signal excursion at the collector of transistor
Q11, which is loaded by the intrinsic capacitance of the
associated circuitry in this mode. On the other hand, during
a negative-going signal excursion at the collector of Q11, the
transistor functions in an active “pull-down” mode so that the
intrinsic capacitance can be discharged more expeditiously.
 CA3130, CA3130A

+7.5V +15V

0.01µF 0.01µF
7 7
3 +
3 + 10kΩ
10kΩ 6 6
2 - 2 -
4 2kΩ
4
8
5
1 1
0.01µF 25pF 100kΩ
8
-7.5V
CC = 56pF 56pF OFFSET
2kΩ ADJUST
2kΩ

BW (-3dB) = 4MHz
SR = 10V/µs 0.1µF
0.1µF

Top Trace: Output

Center Trace: Input
FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV., FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL
200ns/DIV.) RAMPING (2V/DIV., 500µs/DIV.)

Top Trace: Output Signal; 2V/Div., 5µs/Div.

Top Trace: Output; 5V/Div., 200µs/Div.
Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
Bottom Trace: Input Signal; 5V/Div., 200µs/Div.
Bottom Trace: Input Signal; 2V/Div., 5µs/Div.
FIGURE 9B. OUTPUT WAVEFORM WITH GROUND
FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
REFERENCE SINE-WAVE INPUT
SETTLING TIME (MEASUREMENT MADE WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER) FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS. (E.G., FOR USE IN
FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH
SINGLE-SUPPLY D/A CONVERTER; SEE FIGURE 9
ASSOCIATED WAVEFORMS
IN AN6080)

9
 CA3130, CA3130A

10V LOGIC INPUTS

+10.010V
REQUIRED
LSB MSB BIT RATIO-MATCH
14
9 8 7 6 5 4 3 2 1 STANDARD
1
6 3 10 11
6 3 10 6 3 10 2 ±0.1%
3 ±0.2%
2 4 ±0.4%
CD4007A CD4007A CD4007A 5 ±0.8%
“SWITCHES” “SWITCHES” “SWITCHES” 6-9 ±1% ABS
NOTE: All resistances are in ohms.
9
13 1 13 1 12 13 1
7 12 806K 12
8 5 8 5 8 5
1% (2) (4) (8)
4
806K 402K 200K 100K 806K 806K 806K 806K 806K
1% 1% 1% 1% 1% 1% 1% 1% 1%

806K 750K
806K 1% 1%
1% PARALLELED
RESISTORS
10K
+15V
VOLTAGE
REGULATOR 62
+15V 7

1 + 3
OUTPUT
2 +10.010V CA3130 VOLTAGE
6 FOLLOWER
CA3085 8
- 2
3 LOAD 4
22.1k 5
6 1% 1
7 8
+ REGULATED
2µF 4 56pF
1K VOLTAGE 100K
- 25V ADJ
0.001µF OFFSET
3.83k NULL 2K
1%

0.1µF
FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130

R2

2kΩ +15V
0.01
R1 µF
2 - 7
4kΩ CA3130 6
3 + 1N914 0V
4 5.1kΩ
5
1
8 R3
PEAK
20pF 100kΩ ADJUST
OFFSET 2kΩ
ADJUST
0V

R2 R3
Gain = ------- = X = -------------------------------------
R1 R1 + R2 + R3
2
2KΩ R 2
R 3 = R 1  ------------------
X+X
For X = 0.5: ------------ = -------
 1-X  4kΩ R 1 Top Trace: Output Signal; 2V/Div.
Bottom Trace: Input Signal; 10V/Div.
R 3 = 4kΩ  ----------- = 6kΩ
0.75 Time base on both traces: 0.2ms/Div.
 0.5 
20VP-P Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V
1VP-P Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV

FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

10
 CA3130, CA3130A

6VP-P INPUT;
6VP-P INPUT; +7.5V
+7.5V BW (-3dB) = 360kHz
BW (-3dB) = 1.3MHz
0.3VP-P INPUT;
0.3VP-P INPUT; 0.01µF
0.01µF BW (-3dB) = 320kHz
BW (-3dB) = 240kHz 7 -DC
7 +DC 3 + OUTPUT
3 + OUTPUT 10kΩ CA3130 6
10kΩ CA3130 6
2 -
2 - 1N914
1N914
4 -
4 + 100
100 5µF
5µF kΩ +
kΩ - 0.01µF
0.01µF
2kΩ -7.5V
2kΩ -7.5V

FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 12. PEAK-DETECTOR CIRCUITS

CURRENT
LIMIT
ADJ
3Ω
+
R2
1kΩ

IC3 1kΩ

CA3086 Q5 13

10 7 3 12 14
Q4 Q3 Q2 Q1

9 6 2 4
11 8 1 5

+ OUTPUT
20kΩ
0 TO 13V
390Ω 1kΩ AT
56pF
40mA
+
5µF
2.2kΩ 25V
0.01µF -
ERROR
1 AMPLIFIER
+
25µF 8
IC2 - 7
+20V CA3086 10 11 1, 2 - 2
INPUT Q4 Q1 6 CA3130
9 3 +
IC1 3
8, 7 5
Q2 30kΩ
Q3 Q5 14 4
6 4 100kΩ
R1
12 13 50kΩ
VOLTAGE
ADJUST 0.01
62kΩ µF
- -
REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0.02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz

FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)

11
 CA3130, CA3130A

2N3055 Q2 1Ω
+ +
10kΩ
2N2102
1kΩ CURRENT
4.3kΩ Q1 LIMIT
1W ADJUST
Q3
3.3kΩ
1W
2N5294
+
43kΩ
+ 1000pF 100µF
100µF -
- 2.2kΩ

1 ERROR OUTPUT:
+55V + AMPLIFIER
8 0.1 TO 50V
INPUT IC2 5µF
- 2N2102 7 AT 1A
+ 3
CA3086 10, 11 1, 2
10kΩ
6 CA3130
Q4 Q1
9 3 Q5 14 IC1 - 2
Q4
8, 7 5
12 13 4
Q3 Q2 8.2kΩ
6 4

1kΩ 50kΩ
VOLTAGE
62kΩ ADJUST

- -
REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT: <250µVRMS UP TO 100kHz

FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)

Error-Amplifier in Regulated-Power Supplies connected series-pass transistors Q1, Q2. Transistor Q3

The CA3130 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an error-
amplifier when the regulated output voltage is required to
approach zero. Figure 13 shows the schematic diagram of a
40mA power supply capable of providing regulated output
voltage by continuous adjustment over the range from 0V to
13V. Q3 and Q4 in lC2 (a CA3086 transistor-array lC)
function as zeners to provide supply-voltage for the CA3130
comparator (IC1). Q1, Q2, and Q5 in IC2 are configured as a
low impedance, temperature-compensated source of
adjustable reference voltage for the error amplifier.
Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086
transistor-array lC) are connected in parallel as the series-
pass element. Transistor Q5 in lC3 functions as a current-
limiting device by diverting base drive from the series-pass
transistors, in accordance with the adjustment of resistor R2.
Figure 14 contains the schematic diagram of a regulated
power-supply capable of providing regulated output voltage
by continuous adjustment over the range from 0.1V to 50V
and currents up to 1A. The error amplifier (lC1) and circuitry
associated with lC2 function as previously described,
although the output of lC1 is boosted by a discrete transistor
(Q4) to provide adequate base drive for the Darlington-
functions in the previously described current-limiting circuit.
Multivibrators
The exceptionally high input resistance presented by the
CA3130 is an attractive feature for multivibrator circuit design
because it permits the use of timing circuits with high R/C
ratios. The circuit diagram of a pulse generator (astable
multivibrator), with provisions for independent control of the
“on” and “off” periods, is shown in Figure 15. Resistors R1
and R2 are used to bias the CA3130 to the mid-point of the
supply-voltage and R3 is the feedback resistor. The pulse
repetition rate is selected by positioning S1 to the desired
position and the rate remains essentially constant when the
resistors which determine “on-period” and “off-period” are
adjusted.
Function Generator
Figure 16 contains a schematic diagram of a function
generator using the CA3130 in the integrator and threshold
detector functions. This circuit generates a triangular or
square-wave output that can be swept over a 1,000,000:1
range (0.1Hz to 100kHz) by means of a single control, R1. A
voltage-control input is also available for remote sweep-
control.

12
 CA3130, CA3130A

The heart of the frequency-determining system is an The amplifier circuit in Figure 17 employs feedback to
operational-transconductance-amplifier (OTA) (see Note 10), establish a closed-loop gain of 48dB. The typical large-signal
lC1, operated as a voltage-controlled current-source. The bandwidth (-3dB) is 50kHz.
output, IO, is a current applied directly to the integrating
NOTE:
capacitor, C1, in the feedback loop of the integrator lC2, using 9. See file number 619 for technical information.
a CA3130, to provide the triangular-wave output.
+15V
Potentiometer R2 is used to adjust the circuit for slope
symmetry of positive-going and negative-going signal
excursions. 0.01µF
ON-PERIOD OFF-PERIOD
Another CA3130, IC3, is used as a controlled switch to set the R1 ADJUST ADJUST
excursion limits of the triangular output from the integrator 100kΩ 1MΩ 1MΩ

circuit. Capacitor C2 is a “peaking adjustment” to optimize the

2kΩ 2kΩ
high-frequency square-wave performance of the circuit.
R3
Potentiometer R3 is adjustable to perfect the “amplitude 100kΩ
symmetry” of the square-wave output signals. Output from
7
the threshold detector is fed back via resistor R4 to the input 3 +
of lC1 so as to toggle the current source from plus to minus CA3130 6
in generating the linear triangular wave. 1µF S1
2 - OUTPUT
R2 4
Operation with Output-Stage Power-Booster 100kΩ 2kΩ
0.1µF
The current-sourcing and-sinking capability of the CA3130 0.01µF 0.001µF

output stage is easily supplemented to provide power-boost

capability. In the circuit of Figure 17, three CMOS transistor-
pairs in a single CA3600E (see Note 12) lC array are shown
parallel connected with the output stage in the CA3130. In the FREQUENCY RANGE:
Class A mode of CA3600E shown, a typical device consumes POSITION OF S1 PULSE PERIOD
20mA of supply current at 15V operation. This arrangement 0.001µF 4µs to 1ms
0.01µF 40µs to 10ms
boosts the current-handling capability of the CA3130 output
0.1µF 0.4ms to 100ms
stage by about 2.5X. 1µF 4ms to 1s
FIGURE 15. PULSE GENERATOR (ASTABLE MULTIVIBRATOR)
WITH PROVISIONS FOR INDEPENDENT CONTROL
OF “ON” AND “OFF” PERIODS
R4

270kΩ INTEGRATOR
VOLTAGE-CONTROLLED C1
CURRENT SOURCE THRESHOLD
+7.5V HIGH - FREQ. DETECTOR
100pF ADJUST
7 +7.5V 3 - 30pF 150kΩ
IC1
IC2 +7.5V
3 + IO 7
C2 IC3 7
3kΩ
3kΩ 6 2 -
2 - CA3080A CA3130 6 3 +
4 (NOTE 10) 3 + 39kΩ CA3130 6
+7.5V 5 -7.5V
4
2 -
10MΩ 8 4
+7.5V 1 5
R2 -7.5V 1
100kΩ SLOPE 22kΩ
R3
SYMMETRY 10kΩ 56pF
100kΩ
ADJUST
FREQUENCY
-7.5V VOLTAGE ADJUST AMPLITUDE
R1
CONTROLLED 10kΩ (100kHz MAX) SYMMETRY
INPUT ADJUST
-7.5V
-7.5V

NOTE:
10. See file number 475 and AN6668 for technical information.

FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)

13
 CA3130, CA3130A

+15V

0.01µF 14 2 11
1MΩ
1µF CA3600E
(NOTE 12) QP1 QP2 QP3

7
750kΩ
3 +
CA3130 13 1
2kΩ 6
INPUT 2 -
500µF
1µF
8 6 3 10 12
4 RL = 100Ω
(PO = 150mW
AT THD = 10%)
8 5
AV(CL) = 48dB
LARGE SIGNAL QN1 QN2 QN3
BW (-3 dB) = 50kHz

7 4 9
510kΩ

NOTES:
11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.
12. See file number 619.

FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130

Typical Performance Curves

120
AOL SUPPLY VOLTAGE: V+ = 15V; V- = 0
TA = 25oC
OPEN LOOP VOLTAGE GAIN (dB)

150

OPEN LOOP PHASE (DEGREES)

100
LOAD RESISTANCE = 2kΩ φ OL 4
-100
OPEN LOOP VOLTAGE GAIN (dB)

140 1 3
80
2
130 2 -200
60 3
120 1
-300
40 4
110

100 20

90 0
101 102 103 104 105 106 107 108
80 FREQUENCY (Hz)
-100 -50 0 50 100
1 - CL = 9pF, CC = 0pF, RL = ∞
TEMPERATURE (oC) 2 - CL = 30pF, CC = 15pF, RL = 2kΩ
3 - CL = 30pF, CC = 47pF, RL = 2kΩ
4 - CL = 30pF, CC = 150pF, RL = 2kΩ

FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE FIGURE 19. OPEN-LOOP RESPONSE

14
 CA3130, CA3130A

Typical Performance Curves (Continued)

17.5
LOAD RESISTANCE = ∞ 14
QUIESCENT SUPPLY CURRENT (mA)

TA = 25oC OUTPUT VOLTAGE = V+/2

QUIESCENT SUPPLY CURRENT (mA)

12.5 OUTPUT VOLTAGE BALANCED = V+/2 12 V- = 0 TA = -55oC
V- = 0

10
10 25oC

8 125oC
7.5

6
5
OUTPUT VOLTAGE HIGH = V+ 4
OR LOW = V-
2.5
2

0
0
4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16
TOTAL SUPPLY VOLTAGE (V) TOTAL SUPPLY VOLTAGE (V)
FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE VOLTAGE
50 50
VOLTAGE DROP ACROSS PMOS OUTPUT

NEGATIVE SUPPLY VOLTAGE = 0V

VOLTAGE DROP ACROSS NMOS OUTPUT

15V NEGATIVE SUPPLY VOLTAGE = 0V
TA = 25oC 10V TA = 25oC
15V
10 10 10V
POSITIVE SUPPLY VOLTAGE = 5V
STAGE TRANSISTOR (V)

STAGE TRANSISTOR (V)

POSITIVE SUPPLY VOLTAGE = 5V

1 1

0.1 0.1

0.01 0.01

0.001 0.001
0.001 0.01 0.1 1.0 10 100 0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA) MAGNITUDE OF LOAD CURRENT (mA)

FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q8) vs LOAD CURRENT (Q12) vs LOAD CURRENT

15
 CA3130, CA3130A

Dual-In-Line Plastic Packages (PDIP)

N
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
SEATING
B 0.014 0.022 0.356 0.558 -
PLANE L C B1 0.045 0.070 1.15 1.77 8, 10
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.355 0.400 9.01 10.16 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES: E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between
e 0.100 BSC 2.54 BSC -
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7
2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated
N 8 8 9
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru- Rev. 0 12/93
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

16
 CA3130, CA3130A

Small Outline Plastic Packages (SOIC)

N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0532 0.0688 1.35 1.75 -

1 2 3 A1 0.0040 0.0098 0.10 0.25 -

L
B 0.013 0.020 0.33 0.51 9
SEATING PLANE C 0.0075 0.0098 0.19 0.25 -
-A- D 0.1890 0.1968 4.80 5.00 3
D A h x 45°
E 0.1497 0.1574 3.80 4.00 4
-C- e 0.050 BSC 1.27 BSC -
α
H 0.2284 0.2440 5.80 6.20 -
e A1
C h 0.0099 0.0196 0.25 0.50 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 8 8 7
NOTES: α 0° 8° 0° 8° -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

17