ASSIGNMENT

Course Code ECE416A

Course Name Embedded Systems
Programme B.Tech
Department ECE
Faculty Engineering & Technology

Name of the Student Rohit Surya

Reg. No 15ETEC004039
Semester/Year 8th/4th year
Course Leader/s Dr. Sunil Y

i
 Declaration Sheet
Student Name V M Rohit Surya
Reg. No 15ETEC004039
Programme B.Tech Semester/Year 8th/4th year
Course Code ECE416A
Course Title Embedded Systems
Course Date to
Course Leader Dr. Sunil Y

Declaration

The assignment submitted herewith is a result of my own investigations and that I have
conformed to the guidelines against plagiarism as laid out in the Student Handbook. All
sections of the text and results, which have been obtained from other sources, are fully
referenced. I understand that cheating and plagiarism constitute a breach of University
regulations and will be dealt with accordingly.

Signature of the
Date 18/02/2018
Student
Submission date
stamp
(by Examination & Assessment
Section)
Signature of the Course Leader and date Signature of the Reviewer and date
<Embedded Systems> 3
Part A (5marks)

Cryptocurrency mining is a competitive endeavour. An "arms race" has been observed

through the various hashing technologies that have been used to mine cryptocurrency:
Central Processing Unit (CPU), Graphics Processing Unit (GPU), Field-Programmable Gate
Array (FPGA) and Application-Specific Integrated Circuit (ASIC) all have been used. Processor
selection is a crucial milestone in designing the mining system, each reducing the
profitability of the less-specialized technology.
In this context write an essay on the topic “Cryptocurrency Mining with ASIC architecture”

Solution to Question A:

A1.1) Cryptocurrency Mining with ASIC architecture:

Mining is a process that requires a

computer (node) to discover a number
by figuring out a mathematical
equation that includes components
from the previous and current
blocks. In the BTC network, this is
known as the proof-of-work. Once a
miner correctly answers the equation,
they are allowed to add the next block
to the blockchain and are awarded
a prize. In the case of the BTC
blockchain network, the prize is 12.5
BTC.
An ASIC miner is able to calculate these
proof-of-work equations much more
efficiently than a regular CPU. This is
because ASIC Mining hardware is
specifically designed to utilize a certain hash algorithm based on the crypto you are attempting to
mine. For example, when mining BTC, the SHA-256 hash algorithm is used and when mining
Litecoin, it is Scrypt that is employed.
An ASIC miner will allow you to mine any cryptocurrency that utilizes the same hash script as it is
programmed to mine. This means ASIC mining hardware that is configured for BTC, can also mine
numerous other cryptos including Bytecoin, PetroDollar, and Devcoin – just to name a few.
When a block is discovered, the discoverer may award themselves a certain number of bitcoins,
which is agreed-upon by everyone in the network.

<Embedded Systems> 4
Additionally, the miner is awarded the fees paid by users sending transactions. The fee is an
incentive for the miner to include the transaction in their block. In the future, as the number of new
bitcoins miners are allowed to create in each block dwindles, the fees will make up a much more
important percentage of mining income.
It is hard to say where mining technology will go next. Manufacturers are putting forth considerable
effort to create more efficient and powerful mining rigs and you can expect to see this trend
increase as the cryptomarket continues to expand. The high cost of these mining rigs has deterred
many would be miners from entering the space it and has also led to the development of new
technologies such as mining pools and proof-of-stake algorithms.

ASICs are efficient, but they can only be used to mine a singular coin.
This makes the miner to be tied to that one coin - and the investment relies entirely on the future
of that one coin.

Below is a list of advantages and disadvantages for ASIC Bitcoin mining.

ADVANTAGES DISADVANTAGES

Low Power Usage Application-specific

ASIC can consume drastically less power
compared to GPU or CPU. The H/W efficiency
of ASICs is unmatched by anything else.
Very High Hash Rates for Specific Coin
A Bitcoin ASIC will greatly outperform anything
else at mining Bitcoin.
Physical Size
ASICs are usually much smaller and lighter for
similar performance.
Higher Profit Margin
ASICs are so much more efficient and
powerful. they are much more profitable.
A Bitcoin ASIC can only mine Bitcoins. and is
completely useless for anything else.
Can Become Obsolete Overnight
A change in the hashing algorithm. can render
the ASIC useless.
Non-upgradeable
When new ASIC comes out. old ASIC becomes
obsolete. There is no way to upgrade an ASIC.
Very High Entry Point
Cost can be very high.
Low Resale Value
Unlike GPUs, ASICs are worth very little used.

There is a situation where ASICs are beneficial. If you have a large equipment budget, access to very
low cost electricity, and you are OK at sticking to one coin for the long run no matter what - ASICs
are by far the best choice for you.

<Embedded Systems> 5
B1 (10Marks)

Processes and outcomes of a team depend on its size and composition. The optimal size and
composition of teams depend on the task at hand.
Assume a designer’s productivity when working alone on a project is ‘X’ thousand transistors
per month. Assume that each additional designer reduces productivity by ‘Y’%. (And keep in
mind this is an extremely simplified model of designer productivity!)
B1.1 Plot monthly productivity versus team size ranging from 1 to 40 designers.
B1.2 Plot on the same graph the project completion time versus team size for projects
producing ‘Z’ and ‘W’ transistors.
B1.3 Provide the optimal number of designers for each of the two projects, indicating the
number of months required in each case.
Note: Contact course leader for the value of ‘X’, ‘Y’, ‘Z’, and ‘W’.

Solution to Question B1:

Roll no.: 39
It is given that,
X = 5000
Y = 5%
Z = 100,000
W = 1,000,000

For the given data, the following table shows how the productivity of one designer decreases
as the number of designers keep increasing. Also, the completion of hundred thousand and
one million transistors in months is also shown.

TRANSISTORS PER
TEAM TEAM MONTHLY COMPLETION OF COMPLETION OF
DESIGNER PER
SIZE PRODUCTIVITY 100,000 (in months) 1,000,000 (in months)
MONTH
1 5000 5000 20 200
2 4750 9500 10.52631579 105.2631579
3 4512.5 13537.5 7.386888273 73.86888273
4 4286.875 17147.5 5.8317539 58.317539
5 4072.53125 20362.65625 4.910950653 49.10950653
6 3868.904688 23213.42813 4.30785145 43.0785145
7 3675.459453 25728.21617 3.886783263 38.86783263
8 3491.68648 27933.49184 3.579931953 35.79931953
9 3317.102156 29853.91941 3.349643932 33.49643932
10 3151.247049 31512.47049 3.173346883 31.73346883
11 2993.684696 32930.53166 3.036695582 30.36695582
12 2844.000461 34128.00554 2.93014486 29.3014486
13 2701.800438 35123.4057 2.847104317 28.47104317

<Embedded Systems> 6
 TRANSISTORS PER
TEAM TEAM MONTHLY COMPLETION OF COMPLETION OF
DESIGNER PER
SIZE PRODUCTIVITY 100,000 (in months) 1,000,000 (in months)
MONTH
14 2566.710416 35933.94583 2.782883919 27.82883919
15 2438.374896 36575.62343 2.734061394 27.34061394
16 2316.456151 37063.29841 2.698086902 26.98086902
17 2200.633343 37410.76684 2.673027272 26.73027272
18 2090.601676 37630.83017 2.657395533 26.57395533
19 1986.071592 37735.36025 2.650034327 26.50034327
20 1886.768013 37735.36025 2.650034327 26.50034327
21 1792.429612 37641.02185 2.656676017 26.56676017
22 1702.808131 37461.77889 2.669387385 26.69387385
23 1617.667725 37206.35767 2.687712699 26.87712699
24 1536.784339 36882.82413 2.711289126 27.11289126
25 1459.945122 36498.62804 2.739829012 27.39829012
26 1386.947866 36060.64451 2.773106287 27.73106287
27 1317.600472 35575.21275 2.810945944 28.10945944
28 1251.720449 35048.17256 2.853215808 28.53215808
29 1189.134426 34484.89836 2.899820059 28.99820059
30 1129.677705 33890.33115 2.950694095 29.50694095
31 1073.19382 33269.00841 3.005800436 30.05800436
32 1019.534129 32625.09212 3.065125445 30.65125445
33 968.5574223 31962.39494 3.12867669 31.2867669
34 920.1295512 31284.40474 3.196480829 31.96480829
35 874.1230736 30594.30758 3.2685819 32.685819
36 830.4169199 29895.00912 3.345039957 33.45039957
37 788.8960739 29189.15474 3.42592997 34.2592997
38 749.4512702 28479.14827 3.511340966 35.11340966
39 711.9787067 27767.16956 3.60137535 36.0137535
40 676.3797714 27055.19086 3.696148385 36.96148385

Thus, as we can see the productivity of one designer has dropped exponentially when there are 40
designers in the team. There’s almost a 86% decrease in the productivity.

But other factors such as the team productivity and completion of 100,000 and 1,000,000
transistors have increased by 441%, 81.5% and 81% respectively.

The is easily visualised using graphical representation (show in the next page).

<Embedded Systems> 7
B1.1) Monthly productivity versus team size:

40000

35000

30000
Team Productivity

25000

20000

15000

10000

5000

0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Team Size

B1.2) Project completion time versus team size:

250

200
Project Completion Time

150

100

50

0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

Team Size
COMPLETION OF 100,000 (in months) COMPLETION OF 1,000,000 (in months)

<Embedded Systems> 8
B1.3) Optimal number of designers:

Therefore as we can see from the above graphs, the team productivity is highest around
when the team size is 19 or 20 and also the time for completion is at its lowest when the
team size is again, 19 or 20. So, comparing them using the below table,

TRANSISTORS PER TEAM

COMPLETION OF COMPLETION OF
TEAM SIZE DESIGNER PER MONTHLY
100,000 (in months) 1,000,000 (in months)
MONTH PRODUCTIVITY

19 1986.071592 37735.36025 2.650034327 26.50034327

20 1886.768013 37735.36025 2.650034327 26.50034327

It takes the same amount of time for a team of size 19 and 20 – 2.65 months to complete 100,000
transistors.

Hence, 19 is the optimal team size because the same amount of work is completed in the same
amount of time with one less designer/engineer.

This is also true for the completion of 1 million transistors – both the tam sizes take the same
amount of time.

Thus, 19 is the optimal number of designers.

<Embedded Systems> 9
B2. (10 Marks)
The traffic lights require the control and coordination for smooth and safe transit of vehicles
and pedestrians.
Design a traffic Light Controller for a junction of ‘K’ roads. Make the suitable assumptions
regarding traffic control and coordination. Perform the following:
B2.1 Develop a finite state machine.
B2.2 Perform state optimization for the developed finite state machine.
B2.3 Develop the finite state machine using logic circuits.

Solution to Question B2:

Assumptions for Traffic Light Controller:

1. T intersection as shown in Figure below,

2. Default to green on main road.

3. Sensor enables green for cross street.
4. Delay switching for right- turn- on- red from cross street.
5. Programmable delays.

B2.1) Finite state machine:

State machine level :

1. Stay in thru G state until
sensor is activated.
2. Wait in pause state to see
if sensor deactivates.
(right- turn- on- red).
3. Then proceed through
sequence, waiting in each
state for specified time
delay.
4. In each state, provide
appropriate control
signals for lights.
5. 5 states, so at least 3 flip-
flop.

<Embedded Systems> 10
B2.2) Optimization for the developed Finite state machine:

The figure shown

here is the general
diagram of a finite
state machine.

This figure represents the optimized

finite state machine diagram for the
required problem.

<Embedded Systems> 11
Four states are defined:

State O: goS Cars going in South Direction GREEN signal, West Direction with RED signal.

State 1: waitS Cars waiting in South Direction YELLOW signal, West Direction with RED signal.

State 2: goW Cars going in West Direction GREEN signal, South Direction with RED signal.

State 3: waitW Cars waiting in South Direction YELLOW signal, South Direction with RED signal.

<Embedded Systems> 12