Design and implementation of an efficient FIFO buffer for Network on

Chip Routers
Amardeep Chatrath, Mukul Varshney, Manoj Kumar Pandey and Sujata Pandey
Amity School of Engineering and Technology
Amity University Uttar Pradesh, Noida Uttar Pradesh

Abstract: The paper presents the an efficient first in been used to design the hardware system. The results
first out (FIFO) buffer for use in network on chip show that the designed system is working efficiently
routers. Further we have designed a heterogeneous when implemented in the Network on chip router.
router using the efficient FIFO buffer, in which each
channel can have a different buffer size. Ehen the II. SYSTEM DESIGN
FIFO of a particular channel is full it can borrow
more buffer length from neighbouring channels. In A FIFO or Queue or first-in first-out buffer is a
this new architecture read and write operations are memory in array form which is used to transfer data
managed by the FIFO and channel itself, thus between two circuits but having separate clocks.
reducing the circuitry and making the it high speed FIFO uses a dual port memory and has two pointers
router. called write (wr) pointer and read (rd) pointer. A
FIFO provides temporary storage of data, as per
Keywords: Network on Chip, FIFO buffer, Verilog need FIFO can have any size and transfer data
between devices with separate clocks. A FIFO
I. INTRODUCTION Buffer has a read pointer (RP) and a Write pointer
FIFOs are increasingly becoming important keeping (WP) as shown in Figure 1
in view of heterogeneous blocks in latest integrated
circuits. The various modules may operate at
different frequencies and data may travel at different
rates in these FIFOs. Efficient communication
among these blocks may require efficient FIFOs and
CAD designers may requires different types if
FIFOs ranging from synchronous to asynchronous
types.

In complex integrated circuits network on chip

(NOC) is considered to be significant than earlier
used bus-based network architectures. FIFO buffers
and the control circuitry occupy much of the NOC
area and hence designing efficient FIFO buffers is
Figure 1: Block diagram of FIFO buffer
of utmost importance.
Generally, FIFO’s are implemented using rotating
In a system with large number of cores interacting
pointers. A circular FIFO is normally preferred. At
with each other may require FIFO buffers operating
the starting the FIFO pointers namely read(rd) and
at different data rates. These FIFO’s may be of shift
write(wr) pointers will point to same location. In a
type or RAM type which may further be classified
FIFO with n locations, after writing data to 'n'th
as ring address RAM type, dual port RAM type,
location, write pointer points to 0th location. A
arbitration RAM type etc. Data travel in NOC’s
circular FIFO is shown in Figure 2.
through these FIFO buffers and may introduce
latency if not designed efficiently.

Apperson et.al., designed a scalable dual clock FIFO

[1], Pandes et.al., proposed a bi -synchronous FIFO
and many other types of FIFO are available in
literature [2-4]. Others showed the usage of FIFO in
UART [5], routers [6], AMBA AHB [7] and so on.
Fault detection in FIFO and its management are also
important areas of study [8].
In this paper a unique first-in first out buffer has
been designed for use in NOC router. Verilog has Figure 2: Circular FIFO
FIFO are of three kinds: Shift register FIFO has data
words which are stored as constant number. So,
there should be proper synchronisation between the
two operations as data word is read immediately
when a data word is written, Exclusive FIFO has
data word which are stored as variable number with
synchronisation is achieved due to internal structure
of FIFO and Concurrent FIFO has data word stored
as variable number.
In exclusive FIFO there is no dependency on data
read and data write. But there exists a relationship
between the clocks for read and write. So, we need
to use an external circuit for synchronisation if we
want to use such FIFO between two asynchronous
systems. But the data rate of the circuit is reduced by
this external circuit. In parallel FIFOs, writing and
reading of data is not dependent on each other. Both
writing and reading are possible in overlapping way.
In other words, FIFO can be joined to any two
systems which have different frequencies.
Synchronisation of both systems is then the sole
responsibility of FIFO. Parallel read/write in FIFOs,
which depend on control signal are of two types:
Synchronous FIFO and Asynchronous FIFO.
III. RESULTS AND DISCUSSION
Hardware description language Verilog has been
used to design the system. The flow chart of the
design is shown in Figure 3.
Figure 3: Flow chart of FIFO
Inputs used in designing FIFO
CLOCK: Clock or clk can work on positive as well
as negative edge that is posedge clk , negedge clk.if
posedge clk, then the inputs will change at every
positive edge of clock to produce outputs. A clock
generator is designed to supply a clock signal.
Clocks should have a constant frequency, pulse with
fast rising and falling edges and right logic levels.
FIFO full and FIFO empty
Two ports are available in a FIFO - one for writing
and another for reading. Both ports have their own
counter. Once a write operation is completed, the
write pointer or wr ptr = wr ptr+1. Same happens for
read operation, rd ptr = rd ptr+1. When the rd ptr=wr
ptr, that is they are equal, the FIFO has either
nothing or it is full. Read and Write Organization is
shown in Figure 4.
Figure 4: Write and read organisation
Read pointer(rd)= write pointer(wr) => FIFO empty
write pointer(wr) read pointer(rd)= => FIFO full
For proper working of pointer what can be done is
that FIFO counter can be made one bit wider than its
design. The MSB of the counter is used for array of
FIFO. Now when the FIFO is rolled that is FIFO is
full and then is equal read or when the read counter
equals write, the MSB is first checked twice.
When MSB of write counter= MSB of read counter
=> FIFO empty
When MSB of write counter != MSB of read counter
=> FIFO full
Empty flags and full flags can be easily generated
and also extra write command to a full FIFO is
avoided. In the same way read command to empty
FIFO is also avoided. This way the counter can only
go upto the depth of FIFO.
FIFO buffer
Input to the module are data_in of 10 bit for input
data, clock for synchronisation, read signal of 1 bit
for read operation, write signal of 1 bit for write
operation and reset signal of 1 bit to make buffer
reset. Outputs are data_out of 10 bit to pop the value
from the buffer. Figure 5 shows the simulation result
of the FIFO.

(a)

Figure 5: Simulation result of FIFO

The Channel
clk,rst,rd_s,rd_e,rd_w,wr_s,wr_e,wr_w,din_s,din_s
_e,din_s_w,din_e,din_w are inputs to channel. The
inputs din_s,din_s_e,din_s_w,din_e,din_w are of 4
bit each. The outputs dout_s
,dout_e_s,dout_w_s,dout_s_e,dout_s_w are also of
4 bits each. The simulation results for the channel is
shown in Figure 6.

(b)
Figure 7: Channel waveforms (a) for input, (b) for
output

In architecture of NOC router, FIFO buffer is

implement as shown in Figure 8.

Figure 6: Simulation results for the channel

The channel waveform for input and output is shown

in Figure 7(a) and (b)

Figure 8: FIFO in a NOC router

 IV. CONCLUSIONS
In this paper a novel FIFO has been designed and
implemented in the NOC router. In this new
architecture read and write operations are managed
by the FIFO and channel itself thus reducing the
circuitry. Since the circuit is reduced, the wiring for
all the connection to the multiplexers from the port
also reduces which in turn reduces the delay, thus
making the it high speed router.
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12th Latin American Theoretical Informatics
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11-15 Apr 2016