R.T.

E Society’s
RURAL ENGINEERING COLLEGE, HULKOTI.
DEPARTMENT OF ELECTRONICS &COMMUNICATION ENGINEERING
SEE- Assignment Question + VALUATION Pattern
Class:V Sem (E&C) Subject: VHDL (17EC53) Staff Incharge : Mrs Chetana Hooli
17 SCHEME – 30 MARKS (I. A.) + 10 MARKS ASSIGNMENT = 40 MARKS

Q. Assignment Module 1- Overview of digital design with Maximum Marks Submission

No verilog HDL& Hierarchical modeling concepts (CO1) Marks Obtained Date
1 a Describe the top down and bottom up design 6
methodogies.explain wit 4 bit ripple counter with 't' and 'd'd
filpflop as component in 'd' filipflop.
b What is instance?Explain odule instatiation with an example 7

c With neat diagram explain typical design flow of digital 7

31-8-19
design

2 a explain the trends in HDL language 4

b Explain top down and bottom up design methodology 06
c Explain the different levels of abstraction used for 10
programming in verilog
Q. Assignment Module 2— Basic concepts &modules and Maximum Marks
No ports(CO2) Marks Obtained
3 a Define the following and explain each with an example. 7
i)arrays ii)memories iii)parameters iv)strings
b With neat block diagram explain components of verilog 7
module
5-10-19
c Explain port connecting rules 6
4 a What are system tasks?explain the different tasks this 8
performed by verilog.
b Explain two methods of connecting ports to external signals 8
with an example
c Explain any two complier directives in VHDL 4
Q. Assignment Module 3- Gate level modeling and dataflow Maximum Marks
No modeling(CO3,CO4) Marks Obtained
5 a Explain assignment delay,implicit assignment delay and net 6
declaration delay for continous assignment statements with an
example
b Construct a XNOR module using AND/NOT/OR gates.write 6
stimulus that exercises all four combinations
c What would be the output of the following 8
a=4’b1010,b=4’b1111 5-10-19
i) a&b ii)a &&b iii)&a iv)a>>1 v)a>>>1
vi)y={2{a}} vii)a^b viii)z={a,b}
6 a Write a programme for 4:1 mux using conditional operator. 6
b Describe Rise,fall and turnoff delays in gate level description 6
and also explain min\max and typ delay of each Type
c Explain assignment delay,implicit assignment delay and net 8
declaration delay for continous assignment statements with an
example
Q. Assignment Module 4- behavioral modelling(CO5) Maximum Marks 9-11-19
No Marks Obtained
7 a Explain blocking and non blocking assignment statements 8 5
with examples
 b Explain sequentila and parallel blocks with example 8
c Explain While and forever loop with its syntax 4
8 a Write verilog program for 8:1 multiplexer using case 8
statement
b Explain different types of event based timing control in 8
verilog?
c Explain casex and casez statements in verilog. 4
Q. Assignment Module 5- Introduction to VHDL &Entities and Maximum Marks
No architecture(CO6) Marks Obtained
9 a Explain synthesis process with block diagram 8
b Explain attributes of VHDL with examples 7
c Write VHDL data flow description of 1 bit full adder 8 9-11-19
10 a Explain different scalar types in VHDL 7
b Explain the synthesis process with block diagram 7
c Write a programme for half adder in VHDL behavioural 6
descriptiom
Total Maximum Marks Staff Sign
Marks Obtained
Total 200/20
Final marks obtained 10

STAFF Dept NBA Co-ordinator HOD Dean Academic Principal

(Mrs Chetana H) (Mrs Suganda P) (Mrs Aleem S) (Dr M.D.Haralapur) (Dr V.M.Patil)