EMT 125/3

Digital Electronic Principles 1

(Prinsip-prinsip Elektronik Digit 1)

W1 – Course Briefing
 COURSE COORDINATOR/LECTURER
DR NORHAWATI AHMAD
Email: norhawati@unimap.edu.my
Room: 05-00-B

LECTURER
DR NURUL IZZA MOHD NOR
Email: izza@unimap.edu.my
Room: Level 1, Block 11

TECHNICIAN
PN. SHARIFAH SALMAH SYED MAT NOOR
Email: shsalmah@unimap.edu.my
Room: Level 0, MMBE Lab, Block 11
 Day Time Venue

Lectures, Pauh-Putra Campus

Tuesday 2.00 pm – 3.00 pm ZEMAX Tutorial Room

Thursday 2.30 pm – 4.30 pm Photonic Tutorial Room

Lab (MMBE, Level 0, Block 9, Pauh-Putra Campus)

Tuesday 10.30 am - 12.30 pm

Thursday 10.30 am - 12.30 pm

 Assessments
Examinations (70%) Continual Assessment (30%)
Program
Level of
Course Outcome, CO Outcome, Laboratory
Complexity Final Mid/End Assignments/
PO Assessment PO5
Exam Term Exam Quizzes
s (10%)
(50%) (20%) (10%)
(10%)

CO1:
Ability to apply Boolean Cognitive:C6 MTE:
Lab 1, Lab 2,
Algebra and, analyse and Evaluation Q1, Q2, Q3 Q1, Q2 Assignment/
PO1 Lab 3
construct combinational Quiz: 1
logic circuits design

CO2:
Ability to identify, Cognitive:C6 ETE:
Assignment/
illustrate, analyze and Evaluation Q4, Q5 Q1, Q2
PO2 Quiz: 2
deduce synchronous and
asynchronous sequential
circuits design
CO3:
Ability to apply
techniques and skills Psychomotor:
Rubric
using modern P4
PO5 PO5 (Lab
engineering tools for Mechanism
3)
complex engineering
practices to meet
specifications

 Course work = 30%

 Examination (FE + MTE +ETE) = 70%
o 5 Questions: Answer ALL!
 Activities Week Tentative Date
Lab 1 5 13 & 15 March 2018
Mid Term Examination 6 22 March 2018
Lab 2 7 27 & 29 March 2018
Lab 3 9 17 & 19 April 2018
End Term Examination 12 10 May 2018
LAB 1 Introduction to TTL ICs

LAB 2 Combinational System Design 1

LAB3 Combinational System Design 2

* Information will be uploaded in portal.

 Project based laboratory
◦ Preparation before labs – PreLab + Circuit
connectivity  Compulsory!
◦ Group of 2
◦ Lab Evaluation – During Labs
◦ Assessment Form – Submit immediately after
finish the labs
 Digital
Fundamentals by
Thomas L. Floyd
1 TEXT 1
Floyd, Tocci (2007). (Compiled by
Rafikha Aliana A. Raof et al.)
“Digital Electronics Design”,
Pearson/Prentice Hall, 2007
(revised).

2 TEXT 2
Tocci, R. J. et al (2006). “Digital
Systems: Prinsiples and
Applications”, 10th Edition,
Prentice Hall.
 Basic of Digital Electronic
◦ Digital Electronic, Digital vs Analog
◦ Number System & Codes
◦ Logic Circuit
◦ Boolean Function
◦ Karnaugh Map
 Combinational Logic Circuit
◦ Arithmetic (Adder, Subtractor, Multiplier)
◦ Converters
◦ Comparators
◦ Multiplexer/Demultiplexer
◦ Parity Generator/Checker
 Sequential Logic Circuit
◦ Latches
◦ Flip-flops
◦ Shift Registers
 Study Delivery Level of Psbl.
Course Content
Week Mode Complexity Asmt.
1
Number Systems and Codes
(12/2/2018
Digital Electronic, Digital vs Analog. Numbering systems &
– Assign/Quiz,
Base conversion, BCD, Gray, 1’s & 2’s complements of Lecture C4: Analysis
16/2/2018) Test, Exam
binary numbers, Signed numbers, ASCII
Dr
(3 hours)
Norhawati
2
Logic Circuits
(19/2/2018
Boolean constants & logic operations, Truth Table, Basic Assign/Quiz,
–
Logic Gates : inverter NOT, AND, OR, NAND , NOR, XOR, Lecture C5: Design Test, Exam,
23/2/2018)
XNOR , Fixed-function logic : IC Gates Lab
Dr
(3 hours)
Norhawati
Boolean Function
3
Boolean Algebra, Boolean Law & rules, De Morgan’s
(26/2/2018 Theorems, Boolean analysis of logic circuits, Simplification
Assign/Quiz,
– 2/3/2018) using Boolean Algebra, Standard forms of Boolean Lecture C4: Analysis
Test, Exam
Expressions (SOP & POS), Boolean Expressions & truth
Dr
tables
Norhawati
(3 hours)
 4
Karnaugh Map
(5/3/2018 – Assign/Quiz,
Karnaugh Map, Karnaugh Map SOP minimization Lecture C6: Evaluation
9/3/2018) Test, Exam
(3 hours)
Dr Norhawati
5
Laboratory 1 – Introduction to TTL ICs Laboratory C4: Analysis
(12/3/2018 – Lab
(2 hours) experiment; P4: Mechanism
16/3/2018)
5
Karnaugh Map
(12/3/2018 – C4: Analysis Assign/Quiz,
Karnaugh Map POS minimization, 5 Variable K-Map. Lecture
16/3/2018) C6: Evaluation Test, Exam
(3 hours)
Dr Norhawati
6 Combinational Logic Circuit
C4: Analysis Assign/Quiz,
(19/3/2018 – Binary arithmetic, 2’s complement representation, 2’s
Lecture Test, Exam,
23/3/2018) complement arithmetic.
Lab
Dr Norhawati (3 hours)
7
Laboratory C4: Analysis Lab
(26/3/2018 – Laboratory 2 – Combinational System Design 1 experiment; P4: Mechanism
30/3/2018) (2 hours)
7 Combinational Logic Circuit
Assign/Quiz,
(26/3/2018 – Combinational logic, Timing diagram, Arithmetic
Lecture C5: Design Test, Exam,
30/3/2018) circuits, Half Adders, Ripple-carry adder, Full adder.
Lab
Dr Norhawati (3 hours)
(2/4/2018 –
CUTI PERTENGAHAN SEMESTER/ MID SEMESTER BREAK
6/4/2018)
 8
Combinational Logic Circuit
(9/4/2018 – Assign/Quiz,
13/4/2018) 4-bit full-adder ICs, System design application. Lecture C5: Design Test, Exam,
Lab
Dr (3 hours)
Norhawati
9 Laborator
Laboratory 3 – Combinational System Design 2 y C4: Analysis
(16/4/2018 Lab
– (2 hours) experime P4: Mechanism
20/4/2018) nt;
9
Combinational Logic Circuit
(16/4/2018
– MSI, Converter (Encoder & Decoder), Comparators, Code Assign/Quiz,
Lecture C4: Analysis
20/4/2018) converters. Test, Exam
Dr Nurul (3 hours)
Izza
10
Combinational Logic Circuit
(23/4/2018
– Multiplexers, Demultiplexers, Parity Generator, Parity Assign/Quiz,
Lecture C4: Analysis
27/4/2018) Checker Test, Exam
Dr Nurul (3 hours)
Izza
11 Introduction to Sequential Logic Circuit I

(30/4/2018 Latches, Gated Latches and Edge triggered flip flops

Assign/Quiz,
– 4/5/2018) characteristic. Output of Latches, Gated Latches and Edge Lecture C6: Evaluation
Test, Exam
triggered flip flops. Applications of flip flops.
Dr Nurul
Izza (3 hours)
 12
Introduction to Sequential Logic Circuit II
(7/5/2018
Latches, Gated Latches and Edge triggered flip flops
– C6: Assign/Quiz,
characteristic. Output of Latches, Gated Latches and Edge Lecture
11/5/2018) Evaluation Test, Exam
triggered flip flops. Applications of flip flops.
Dr Nurul
(3 hours)
Izza
Shift Registers
13
Basic Shift Register functions. Types of Shift Register. Flip
(14/5/2018
flop in Shift Register operation. The output for Serial In
– C6:
Serial Out (SISO), Serial In Parallel Out (SIPO), Parallel In Lecture Exam
19/5/2018) Evaluation
Serial Out (PISO) and Parallel In Parallel Out (PIPO) Shift
Dr Nurul Register.
Izza
(3 hours)
14

(21/5/2018 Shift Registers

– C6:
Birectional shift register operation. Shift Register Counters. Lecture Exam
25/5/2018) Evaluation
(3 hours)
Dr Nurul
Izza
15

(28/5/2018 MINGGU ULANGKAJI / REVISION WEEK

–
1/6/2018)
16-17

(4/6/2018 PEPERIKSAAN AKHIR SEMESTER / FINAL EXAMINATION

–
15/6/2018)
 No of credits = 3
 SLT = 3.00!
◦ Assignment/Quiz = 2
◦ Lab = 3
◦ Test = MTE (1 hour)
ETE (1 hour)
 Strictly no re-test.
 DON’T FORGET ABOUT WHAT YOU HAVE
LEARNT!!!!!!!!!!!!!