Mtec Ece-Vlsi-Design 2018

SCHEME
&
SYLLABUS
M.Tech. in Electronics & Communication Engineering
(VLSI Design)
Effective from 2018-19
Department of Electronics & Communication Engineering

Deenbandhu Chhotu Ram University of Science &
TechnologyMurthal (Sonipat), Haryana, 131039
Approved in the 13th meeting of academic council held on 18/6/2018.
Mission
To facilitate and promote studies and research in emerging areas of Electronics and
Communication Engineering with focus on new frontiers of upcoming technologies
evolution of enlightened technocrats, innovators and entrepreneurs who will contribute to
national growth in particular and to the international community as a whole.
Vision
To achieve excellence in education and research in main & related areas of Electronics and
communication technologies, Sustainable growth of the students not only locally but
globally and to occupy a place of pride amongst the most eminent organizations of the world.

Programme Educational Objectives:
1. Core Competence:
 Post Graduating engineers should understand the basic concepts of Electronics and
Communication engineering fundamentals required to solve engineering problems and also to
pursue higher studies & Research.
2. Preparations:
 To prepare students for various competitive exams like NET, GRE, the entrance exam for
research organisations like DRDO, ISRO etc, for the purpose of higher studies and research
and getting better placements in PSU, MNC’s along with research organisations.
3. Application and Synthesis:
 To give more emphasis on application and synthesis in courses related to Design of Electronic
Circuits and their Simulation along with optimization. It helps in developing practical skills to
design experimentation and develop confidence for tackling a problem and initiating its
solution.
 To train students with good scientific and engineering knowledge, so as to comprehend,
analyse, design, and create novel products and solutions for the real life problems/systems.
4. Professionalism:
 To inculcate in students professional and ethical attitude, effective communication skills

teamwork skills, multidisciplinary approach, social engineering, and an ability to relate
engineering issues to broader social context.
5. Learning Environment:
 To provide students with and academic environment aware of excellence, leadership, written
ethical codes and guidelines, and the lifelong learning needed for a successful career.

Programme Outcomes:
Following are the programme outcomes:
a. an ability to apply knowledge of mathematics, science, and engineering,

b. an ability to design and conduct experiments, as well as to analyze and interpret data,
c. an ability to design a system, component, or process to meet desired needs within
realistic constraints such as economic, environmental, social, political, ethical, health
and safety, manufacturability, and sustainability,
d. an ability to function on multidisciplinary teams,
e. an ability to identify, formulate, and solve engineering problems,
f. an understanding of professional and ethical responsibility,
g. an ability to communicate effectively,
h. the broad education necessary to understand the impact of engineering solutions in a
global, economic, environmental, and societal context. To indulge in Research
and development activities that will be helpful to further technological development.
i. a recognition of the need for, and an ability to engage in life-long learning,
j. a knowledge of contemporary issues.
k. an ability to use the techniques, skills, and modern engineering tools necessary for
engineering practice.

DEENBANDHU CHHOTU RAM UNIVERSITY OF SCIENCE & TECHNOLOGY, MURTHAL
(SONEPAT)
SCHEME OF STUDIES & EXAMINATIONS
MASTER OF TECHNOLOGY IN ELECTRONICS & COMMUNICATION ENGINEERING (VLSI DESIGN)
(Choice Based Credit System w.e.f 2018-19)
SEMESTER I
SN Course No. Course Title Teaching Marks of Examination Total Credit Duration
Schedule Class Marks Marks of Exam.
Work
L P Theory Practical
1 MTVLSI501C RTL Simulation and 3 - 25 75 - 100 3 3
Core 1 Synthesis with PLDs
2 MTVLSI503C Analog and Digital 3 - 25 75 - 100 3 3
Core 2 CMOS VLSI Design
3 PE I ELECTIVE I 3 - 25 75 - 100 3 3
4 PE II ELECTIVE II 3 - 25 75 - 100 3 3
5 MTVLSI551C RTL Simulation and - 4 25 - 75 100 2 3
Lab 1 Synthesis with PLDs Lab
6 MTVLSI553C Analog and Digital - 4 25 - 75 100 2 3

Lab 2 CMOS VLSI Design Lab
7 MTEC557C Research Methodology 2 - 25 75 - 100 2 3
and IPR
8 Aud 1 Audit course 1 2 - 25 75 - 100 0 3
Total 16 08 200 450 150 800 18 -
List of Program Specific Elective I List of Program Specific Elective II Audit course 1& 2
MTVLSI511C Digital Signal MTVLSI521C Parallel Processing AUD531C English for Research
and Image Paper Writing
Processing
MTVLSI513C Programming MTVLSI523C System Design AUD533C Disaster Management
Languages for with Embedded AUD535C Sanskrit for Technical
Embedded Linux Knowledge
Software AUD537C Value Education
MTVLSI515C VLSI Signal MTVLSI525C CAD of Digital AUD539C Constitution of India
Processing System AUD541C Pedagogical Studies
MTVLSI517C IC Fabrication MTVLSI527C Introduction to AUD543C Stress Management by
Technology MEMS Yoga
MTVLSI519C Semiconductor MTVLSI529C Advanced AUD545C Personality
device modeling Computer Development through
Architecture Life Enlightenment
Skills.
Note: 1. Student can opt any two subjects for electives I & II from given list respectively and one audit course
from given list of audit course 1&2.
2. The choice of students for any elective shall not be binding on the department to offer, if the department
does not have expertise. The minimum strength of the students opting for the particular subject shall not
be less than 8.
3. The students will be allowed to use non-Programmable Scientific Calculator. However, sharing/exchange
of calculator is prohibited in the examination.

(SONEPAT)
(Choice based Credit System w.e.f. 2018-19)
SEMESTER II
S. Course No. Course TitleTeaching Marks of Examination Total Credit Duration
No. Schedule Class Marks Marks of Exam.
Work
1 MTVLSI502C Microcontrollers and 3 - 25 75 - 100 3 3
Core 3 Programmable Digital
Signal Processors
2 MTVLSI504C VLSI Design 3 - 25 75 - 100 3 3
Core 4 Verification and
Testing
3 PE III ELECTIVE III 3 - 25 75 - 100 3 3
4 PE IV ELECTIVE IV 3 - 25 75 - 100 3 3
5 MTVLSI552C Microcontrollers and - 4 25 - 75 100 2 3
Lab 1 Programmable Digital
Signal Processors Lab
6 MTVLSI554C VLSI Design - 4 25 - 75 100 2 3
Lab 2 Verification and
Testing Lab
7 MTVLSI556C MINI PROJECT 4 25 75 100 2
8 Aud 2 Audit course 2 2 - 25 75 - 100 0 3
Total 14 8 200 375 225 800 18 -
List of Program Specific Elective I List of Program Specific Elective II Audit course 1 & 2
MTVLSI510C Memory MTVLSI520 C Communication AUD531C English for Research
Technologies Buses and Paper Writing
Interfaces AUD533C Disaster Management
MTVLSI512C SoC Design MTVLSI522 C Network Security
and AUD535C Sanskrit for Technical
Cryptography Knowledge
MTVLSI514C Low Power VLSI MTVLSI524 C Physical design AUD537C Value Education
Design automation
AUD539C Constitution of India
AUD541C Pedagogical Studies
MTVLSI516C Computational MTVLSI526 C Hardware Stress Management by
AUD543C
Intelligent Software Co- Yoga
Techniques for Design AUD545C Personality Development
VLSI Design through Life
Enlightenment Skills.
MTVLSI518C VLSI for Optical MTVLSI528 C Optimization for
Interconnect VLSI Design
Note:
1. Student can opt any two subjects for electives III & IV from given list respectively and one audit
course from given list of audit course 1&2.
2. The choice of students for any elective shall not be binding on the department to offer, if the
department does not have expertise. The minimum strength of the students opting for the particular
subject shall not be less than 8.
3. The students will be allowed to use non-Programmable Scientific Calculator. However,
sharing/exchange of calculator is prohibited in the examination.

(SONEPAT)
SEMESTER III
S. Course No. Course Title Teaching Marks of Examination Total Credit Duration
No. Schedule Class Marks Marks of Exam.
Work
1 PE V ELECTIVE V 3 - 25 75 - 100 3 3
2 OE OPEN ELECTIVE 3 - 25 75 - 100 3 3
3 MTVLSI651C DISSERTATION - 20 50 - 100 150 10 3
(1ST PHASE)
Total 6 20 100 150 100 350 16 -
List of Program Specific Elective V (PE V) List of Open Elective
MTVLSI611C Communication network MTOE651C Business Analytics

MTVLSI613C Selected Topics in Mathematics MTOE653C Industrial Safety
MTVLSI615C Nano materials and Nanotechnology MTOE655C Operations Research
MTVLSI617C CMOS RF IC Design MTOE657C Cost Management of
Engineering Projects
MTVLSI619C Mixed Signal IC Design MTOE659C Composite Materials
MTOE661C Waste to Energy
Note:
1. Student can opt any one subject for electives (V) and one subject for open elective from given list.
2. The choice of students for any elective shall not be binding on the department to offer, if the department
does not have expertise. The minimum strength of the students opting for the particular subject shall not
be less than 8.
3. The students will be allowed to use non-Programmable Scientific Calculator. However,
4. Dissertation coordinator will be assigned the load of 1 hour per week excluding his/her own guiding
load. However, the dissertation guiding teacher will be assigned a load of one hour per candidate per
week.

(SONEPAT)
SEMESTER IV
S. No. Course No. Course Title Teaching Marks of Examination Total Credit Duration
Schedule Class Marks Marks of Exam.
Work
1 MTVLSI652C DISSERTATION - 32 100 - 200 300 16 -
(II PHASE)
Total - 32 100 - 200 300 16 -
Note:
Dissertation coordinator will be assigned the load of 1 hour per week excluding his/her own guiding load.
However, the dissertation guiding teacher will be assigned a load of one hour per candidate per week.

MTVLSI501C RTL SIMULATION AND SYNTHESIS WITH PLDS
M.Tech. Electronics and Comm. Engg. (VLSI Design)
Semester – I
L T P Credits Class Work : 25 Marks

3 - - 3 Theory : 75 Marks
Total : 100 Marks
Duration of Exam. : 3 Hrs.
Course Objective: The objectives of this course are as under:
1. Familiarity of Finite State Machines, RTL design using reconfigurable logic.
2. Design and develop IP cores and Prototypes with performance guarantees
3. Use EDA tools like Cadence, Mentor Graphics and Xilinx.
UNIT I
Top down approach to design, Design of FSMs (Synchronous and asynchronous), Static Timing analysis, Meta-
stability, Clock issues, Need and design strategies for multi-clock domain designs. Design entry by Verilog/
VHDL/ FSM, Verilog AMS.
UNIT II
Programmable Logic Devices, Introduction to ASIC Design Flow, FPGA, SoC, Floor planning, Placement,
Clock tree synthesis, Routing, Physical verification, Power analysis, ESD protection.
UNIT III
Design for performance, Low power VLSI design techniques. Design for testability.
UNIT IV
IP and Prototyping: IP in various forms: RTL Source code, Encrypted Source code, Soft IP, Netlist, Physical IP,
Use of external hard IP during prototyping, Case studies and Speed issues.
Course Outcomes: At the end of the course, students will be able to:
1. Familiarity of Finite State Machines, RTL design using reconfigurable logic.
2. Design and develop IP cores and Prototypes with performance guarantees.
References Book:
1. Richard S. Sandige, “Modern Digital Design”, MGH, International Editions.
2. Donald D Givone, “Digital principles and Design”, TMH
3. Charles Roth, Jr. and Lizy K John, “Digital System Design using VHDL”, Cengage Model Curriculum of Engineering &
Technology PG Courses [Volume -II]
4. Samir Palnitkar, “Verilog HDL, a guide to digital design and synthesis”, Prentice Hall.
5. Doug Amos, Austin Lesea, Rene Richter, “FPGA based prototyping methodology manual”, Xilinx
6. Bob Zeidman, “Designing with FPGAs & CPLDs”, CMP Books.
Note:
1. In the Semester examination, the examiner will set 08 questions in all selecting two from each unit. The candidates will be required
to attempt five questions in all, atleast one from each unit. All questions carry equal marks.
2. The use of programmable devices such as programmable claculators, phones, etc. and sharing of materials during the examination
is not allowed.
3. A specific note shall be inserted in relevant question paper where ever the use of graph-papers, semi-log papers, steam-tables, etc.
shall be allowed during the examination.

MTVLSI503C ANALOG AND DIGITAL CMOS VLSI DESIGN
M.Tech Electronics and Comm. Engg. (VLSI Design)
Semester – I

Total : 100 Marks
1. To analyze, design, optimize and simulate analog and digital circuits using CMOS constrained by the design metrics.
2. To connect the individual gates to form the building blocks of a system.
3. To use EDA tools like Cadence, Mentor Graphics and other open source software tools like Ngspice.
Unit 1
Review: Technology Scaling and Road map, Scaling issues, Basic MOS structure and its static behavior,
Quality metrics of a digital design: Cost, Functionality, Robustness, Power, and Delay, Stick diagram and
Layout, Wire delay models.
Inverter: Static CMOS inverter, Switching threshold and noise margin concepts and their evaluation, Dynamic
behavior, Power consumption
.
Unit II
Combinational logic: Static CMOS design, Logic effort, Ratioed logic, Pass transistor logic, Dynamic logic,
Speed and power dissipation in dynamic logic, Cascading dynamic gates, CMOS transmission gate logic.
Sequential logic: Static latches and registers, Bi-stability principle, MUX based latches, Static SR flip-flops,
Master-slave edge-triggered register, Dynamic latches and registers.
Unit III
Single Stage Amplifier: CS stage with resistance load, Divide connected load, Current source load, Triode load,
CS stage with source degeneration, Source follower, Common gate stage, Cascade stage, Choice of device
models. Differential Amplifiers: Basic difference pair, Common mode response, Differential pair with MOS
loads, Gilbert cell.
Unit IV
Passive and active current mirrors: Basic current mirrors, Cascade mirrors, Active current mirrors. Frequency
response of CS stage: Source follower, Common gate stage, Cascade stage and difference pair, Noise
Operational amplifiers: One stage OPAMP, Two stages OPAMP, Gain boosting, Common mode feedback,
Slew rate, PSRR, Compensation of 2 stage OPAMP, Other compensation techniques.
Course Outcomes: At the end of this course, students will be able to

1. Analyze, design, optimize and simulate analog and digital circuits using CMOS constrained by the design metrics.
2. Connect the individual gates to form the building blocks of a system.
3. Use EDA tools like Cadence, Mentor Graphics and other open source software tools like Ngspice.
References:
1. Sedra, Adel S., and Kenneth Carless Smith. Microelectronic circuits. Vol. 1. New York: Oxford University Press, 1998.
2. J P Rabaey, A P Chandrakasan, B Nikolic, “Digital Integrated circuits: A design perspective”, Prentice Hall electronics and VLSI
series, 2nd Edition.
3. BehzadRazavi , “Design of Analog CMOS Integrated Circuits”, TMH, 2007.
4. R J Baker, “CMOS circuit Design, Layout and Simulation”, IEEE Inc., 2008.
5. Kang, S. and Leblebici, Y., “CMOS Digital Integrated Circuits, Analysis and Design”, TMH, 3rdEdition.
NOTE:
1. In the Semester examination, the examiner will set 08 questions in all selecting two from each unit. The candidates will be
required to attempt five questions in all, atleast one from each unit. All questions carry equal marks.
2. The use of programmable devices such as programmable claculators, phones, etc. and sharing of materials during the
examination is not allowed.
3. A specific note shall be inserted in relevant question paper where ever the use of graph-papers, semi-log papers, steam-tables,
etc. shall be allowed during the examination.

MTVLSI551C RTL SIMULATION AND SYNTHESIS WITH PLDS LAB
Semester – I

- - 4 2 Theory : 75 Marks
Total : 100 Marks
Duration of Exam. : 3 Hrs

1. Educate students with knowledge to Identify, formulate, solve and implement problems in signal processing, communication
systems etc using RTL design tools.
2. To learn about different EDA Tools.
LIST OF EXPERIMENTS:
1. Verilog implementation of 8:1 Mux/Demux, Full Adder, 8-bit Magnitude comparator,

Encoder/decoder, Priority encoder, D-FF, 4-bit Shift registers (SISO, SIPO, PISO, bidirectional), 3-bit
Synchronous Counters, Binary to Gray converter, Parity generator.
2. Sequence generator/detectors, Synchronous FSM – Mealy and Moore machines.
3. Vending machines - Traffic Light controller, ATM, elevator control.
4. PCI Bus & arbiter and downloading on FPGA.
5. UART/ USART implementation in Verilog.
6. Realization of single port SRAM in Verilog.
7. Verilog implementation of Arithmetic circuits like serial adder/ subtractor, parallel adder/subtractor,
serial/parallel multiplier.
8. Discrete Fourier transform/Fast Fourier Transform algorithm in Verilog.
Course Outcome: At the end of this course, students should be able to:
1. Identify, formulate, solve and implement problems in signal processing, communication systems etc using RTL design tools.
NOTE:
1. Each Laboratory Class/Section shall not be of more than about 20 students.
2. To allow fair opportunity of practical hands-on experience to each student, each experiment may either be done by each
student individually or in a group of not more than 3-4 students. Larger groups be strictly discouraged / disallowed.
3. Pre-experimental & post experimental quiz / questions may be offered for each Lab experiment to reinforce & aid
comprehension of the experiment.

MTVLSI553C ANALOG AND DIGITAL CMOS VLSI DESIGN LAB
Semester – I

Total : 100 Marks
Course Objective: The objectives of this course laboratory as are under:

1. To Design digital and analog Circuit using CMOS technology
2. To use EDA tools like Cadence, Mentor Graphics and other open source software tools like microwind, ngspice.
List of Experiments:
1) Use VDD=1.8V for 0.18um CMOS process, VDD=1.3V for 0.13um CMOS Process and VDD=1V for
0.09um CMOS Process.
a) Plot ID vs. VGS at different drain voltages for NMOS, PMOS.
b) Plot ID vs. VGS at particular drain voltage (low) for NMOS, PMOS and determine Vt.
c) Plot log ID vs. VGS at particular gate voltage (high) for NMOS, PMOS and determine
IOFF and sub-threshold slope.
d) Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine Channel
length modulation factor.
e) Extract Vth of NMOS/PMOS transistors (short channel and long channel). Use VDS
=30mV
To extract Vth use the following procedure.
a) Plot gm vs VGS using NGSPICE and obtain peak gm point.
b) Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load line and
calculate gm, gds, gm/gds, and unity gain frequency.
Tabulate your result according to technologies and comment on it.
2) Use VDD=1.8V for 0.18um CMOS process, VDD=1.2V for 0.13um CMOS Process and VDD=1V for
0.09um CMOS Process.
a) Perform the following.
i. Plot VTC curve for CMOS inverter and thereon plot dVout vs. dVin and determine
transition voltage and gain gm. Calculate VIL, VIH, NMH, NML for the inverter.
ii. Plot VTC for CMOS inverter with varying VDD.
iii. Plot VTC for CMOS inverter with varying device ratio.
b) Perform transient analysis of CMOS inverter with no load and with load and determine tpHL,
tpLH, 20%-to-80% tr and 80%-to-20% tf. (use VPULSE = 2V, Cload = 50fF).
c) Perform AC analysis of CMOS inverter with fanout 0 and fanout 1. (Use Cin= 0.012pF,Cload
= 4pF, Rload = k)
3) Build a three stage and five stage ring oscillator circuit in 0.18um and 0.13um technology and compare
its frequencies and time period.
4) Perform the following:
a) Draw small signal voltage gain of the minimum-size inverter in 0.18um and 0.13um
technology as a function of input DC voltage. Determine the small signal voltage gain at the
switching point and compare the values for 0.18um and 0.13um process.
b) Consider a simple CS amplifier with active load, as explained in the lecture, with NMOS
transistor MN as driver and PMOS transistor MP as load, in 0.18um technology. (W/L)MN=5,
(W/L)MP=10 and L=0.5um for both transistors.
i. Establish a test bench, as explained in the lecture, to achieve VDSQ=VDD/2.
ii. Calculate input bias voltage if bias current=50uA.
iii. Obtain the bias current. Compare its value with 50uA.
iv. Determine small signal voltage gain, -3dB BW and GBW of the
amplifier using small signal analysis (consider 30fF load capacitance).
v. Plot step response of the amplifier for input pulse amplitude of 0.1V.
Derive time constant of the output and compare it with the time
constant resulted from -3dB BW.
vi. To determine input voltage range of the amplifier

5) Two stage OPAMP Vdd=1.8V Vss=0V Note: Adjust accuracy options of the
simulator (setup->options in GUI). Use proper values of resistors to get a Two stage
OPAMP with differential-mode voltage gain=10.
Consider voltage gain=2 for the first stage and voltage gain=5 for the second stage.
i. Draw the schematic of op-amp macro model.
ii. Determine parameters of the op-amp macro model such that
a) Low-frequency voltage gain ,
b) Unity gain BW ,
c) CMRR
iii. Draw schematic diagram of CMRR simulation setup.
6) Technology: UMC 0.18um, VDD=1.8V. Use MAGIC or Microwind.
a) Draw layout of a minimum size inverter in UMC 0.18um technology
using MAGIC Station layout editor. Use that inverter as a cell and lay
out three cascaded minimum-sized inverters. Use M1 as interconnect
line between inverters.
b) Run DRC, LVS and RC extraction. Make sure there is no DRC error.
Extract the netlist.
c) Use extracted netlist and obtain tPHL & tPLH for the middle inverter.
d) Values of delay times with corresponding values obtained in part ‘c’.
Course Outcomes: At the end of the laboratory work, students will be able to:
1. Design digital and analog Circuit using CMOS.
2. Use EDA tools like Cadence, Mentor Graphics and other open source software tools like microwind, ngspice.
NOTE:

MTEC557C RESEARCH METHODOLOGY AND IPR
M.Tech. Electronics and Comm. Engg. (VLSI Design)
Semester – I

Total : 100 Marks
1. To understand research problem formulation.
2. To analyze research related information
3. To follow research ethics
4. To understand that today’s world is controlled by Computer, Information Technology, but tomorrow world will be ruled by ideas,
concept, and creativity.
5. To understanding that when IPR would take such important place in growth of individuals & nation, it is needless to emphasis the need
of information about Intellectual Property Right to be promoted among students in general & engineering in particular.
6. To understand that IPR protection provides an incentive to inventors for further research work and investment in R & D, which leads
to creation of new and better products, and in turn brings about, economic growth and social benefits.
UNIT I
Meaning of research problem, Sources of research problem, Criteria Characteristics of a good research problem,
Errors in selecting a research problem, Scope and objectives of research problem. Approaches of investigation
of solutions for research problem, data collection, analysis, interpretation, Necessary instrumentations.
.
UNIT II
Effective literature studies approaches, analysis, Plagiarism, Research ethics, Effective technical writing, how to
write report, Paper Developing a Research Proposal, Format of research proposal, a presentation and assessment
by a review committee
UNIT III
Nature of Intellectual Property: Patents, Designs, Trade and Copyright. Process of Patenting and Development:
technological research, innovation, patenting, development.
International Scenario: International cooperation on Intellectual Property. Procedure for grants f patents,
Patenting under PCT.
UNIT IV
Patent Rights: Scope of Patent Rights. Licensing and transfer of technology. Patent information and databases.
Geographical Indications.
New Developments in IPR: Administration of Patent System. New developments in IPR; IPR of Biological
Systems, Computer Software etc. Traditional knowledge Case Studies, IPR and IITs.

1. Understand research problem formulation.
2. Analyze research related information
3. Follow research ethics
4. Understand that today’s world is controlled by Computer, Information Technology, but tomorrow world will be ruled by ideas,
concept, and creativity.
5. Understanding that when IPR would take such important place in growth of individuals & nation, it is needless to emphasis the need of
information about Intellectual Property Right to be promoted among students in general & engineering in particular.
6. Understand that IPR protection provides an incentive to inventors for further research work and investment in R & D, which leads to
creation of new and better products, and in turn brings about, economic growth and social benefits.
References:
1. Stuart Melville and Wayne Goddard, “Research methodology: an introduction for science & engineering students’”
2. Wayne Goddard and Stuart Melville, “Research Methodology: An Introduction”
3. Ranjit Kumar, 2nd Edition , “Research Methodology: A Step by Step Guide for beginners”
4. Halbert, “Resisting Intellectual Property”, Taylor & Francis Ltd ,2007.
5. Mayall , “Industrial Design”, McGraw Hill, 1992.
6. Niebel , “Product Design”, McGraw Hill, 1974.
7. Asimov , “Introduction to Design”, Prentice Hall, 1962.
8. Robert P. Merges, Peter S. Menell, Mark A. Lemley, “ Intellectual Property in New Technological Age”, 2016.
9. T. Ramappa, “Intellectual Property Rights Under WTO”, S. Chand, 2008.
NOTE:

MTVLSI511C DIGITAL SIGNAL AND IMAGE PROCESSING
Semester – I
Total : 100 Marks

1. To analyze and characterize discrete-time signals and systems in various domains.
2. To design and implement FIR & IIR filters.
3. To compare algorithmic and computational complexities in processing and coding digital images.
UNIT I
Review of Discrete Time signals and systems, Characterization in time and Z and Fourier domain, Fast Fourier
Transform algorithms – In-place computations, Butterfly computations, bit reversal’s.
UNIT II
Digital Filter design: FIR - Windowing and Frequency Sampling, IIR – Impulse invariance, bilinear
Transformation. Fixed point implementation of filters – challenges and techniques.
UNIT III
Digital Image Acquisition, Enhancement, Restoration. Digital Image Coding and Compression – JPEG and
JPEG 2000.
UNIT IV
Color Image processing – Handling multiple planes, computational challenges. VLSI architectures for
implementation of Image Processing algorithms, Pipelining.
Course Outcomes: At the end of this course, students will be able to:
1. Analyze discrete-time signals and systems in various domains.
2. Design and implement filters using fixed point arithmetic targeted for embedded platforms.
3. Compare algorithmic and computational complexities in processing and coding digital images.
References:
1. J.G. Proakis, Manolakis “Digital Signal Processing”, Pearson, 4th Edition
2. Gonzalez and Woods, “Digital Image Processing”, PHI, 3rd Edition
3. S. K. Mitra. “Digital Signal Processing – A Computer based Approach”, TMH, 3rd Edition, 2006
4. A. K. Jain, “Fundamentals of Digital Image Processing”, Prentice Hall
5. KeshabParhi, “VLSI Digital Signal Processing Systems – Design and Implementation”, Wiley India
Note:

MTVSI 513C PROGRAMMING LANGUAGES FOR EMBEDDED SOFTWARE
Semester – I
Total : 100 Marks
Course Objective : The objectives of this course are as under:

1. To write an embedded C application of moderate complexity.
2. To develop and analyze algorithms in C++.
3. To differentiate interpreted languages from compiled languages.
UNIT I
Embedded ‘C’ Programming: Bitwise operations, Dynamic memory allocation, OS services, linked stack and
queue, Sparse matrices, Binary tree, Interrupt handling in C, Code optimization issues, Writing LCD drives,
LED drivers, Drivers for serial port communication, Embedded Software Development Cycle and Methods
(Waterfall, Agile).
UNIT II
Object Oriented Programming: Introduction to procedural, modular, object-oriented and generic programming
techniques, Limitations of procedural programming, objects, classes, data members, methods, data
encapsulation, data abstraction and information hiding, inheritance, polymorphism.
UNIT III
CPP Programming: ‘cin’, ‘cout’, formatting and I/O manipulators, new and delete operators, Defining a class,
data members and methods, ‘this’ pointer, constructors, destructors, friend function, dynamic memory allocation
Overloading and Inheritance: Need of operator overloading, overloading the assignment, overloading using
friends, type conversions, single inheritance, base and derived classes, friend classes, types of inheritance,
hybrid inheritance, multiple inheritance, virtual base class, polymorphism, virtual functions.
UNIT III
Templates: Function template and class template, member function templates and template arguments,
Exception Handling: syntax for exception handling code: try-catch- throw, Multiple Exceptions.
Scripting Languages Overview of Scripting Languages – PERL, CGI, VB Script, Java Script. PERL: Operators,
Statements Pattern Matching etc. Data Structures, Modules, Objects, Tied Variables, Inter process
Communication Threads, Compilation & Line Interfacing.

1. Write an embedded C application of moderate complexity.
2. Develop and analyze algorithms in C++.
3. Differentiate interpreted languages from compiled languages.
References:
1. Michael J. Pont , “Embedded C”, Pearson Education, 2nd Edition, 2008
2. Randal L. Schwartz, “Learning Perl”, O’Reilly Publications, 6th Edition 2011
3. A. Michael Berman, “Data structures via C++”, Oxford University Press, 2002
4. Robert Sedgewick, “Algorithms in C++”, Addison Wesley Publishing Company, 1999
5. Abraham Silberschatz, Peter B, Greg Gagne, “Operating System Concepts”, John Willey & Sons, 2005
Note:
is not allowed.

MTVLSI515C VLSI SIGNAL PROCESSING
Semester – I
Total : 100 Marks

1. To acquire knowledge about DSP algorithms, pipelining and parallel processing approaches.
2. To acquire knowledge about retiming techniques, folding and register minimization path problems.
3. To familiarize with algorithmic strength reduction techniques and parallel processing of digital filters.
4. To acquire knowledge about finite word-length effects and round off noise computation in DSP
systems.
UNIT I
Introduction to DSP systems, Pipelined and parallel processing, Iteration Bound, Retiming, unfolding,
algorithmic strength reduction in filters and Transforms. Systolic architecture design, fast convolution, pipelined
and parallel recursive and adaptive filters, Scaling and round off noise.
UNIT II
Digital lattice filter structures, bit level arithmetic, architecture, redundant arithmetic. Numerical strength
reduction, synchronous, wave and asynchronous pipe lines, low power design.
UNIT III
Programmable DSP (P-DSP) Processors: Harvard architecture, Multi port memory, architectural structure of P-
DSP- MAC unit, Barrel shifters, Introduction to TI DSP processor family.
VLIW architecture and TMS320C6000 series, architecture study, data paths, cross paths, Introduction to
Instruction level architecture of C6000 family, Assembly Instructions memory addressing, for arithmetic, logical
operations
UNIT IV
Code Composer Studio for application development for digital signal processing, On chip peripheral , Processor
benchmarking.
1. Acquire knowledge about DSP algorithms, its DFG representation, pipelining and parallel processing approaches.
2. Acquire knowledge about retiming techniques, folding and register minimization path problems.
3. Have knowledge about algorithmic strength reduction techniques and parallel processing of FIR and IIR digital filters.
4. Acquire knowledge about finite word-length effects and round off noise computation in DSP systems.
References:
1. Keshab K. Parthi, VLSI Digital signal processing systems, design and implementation , Wiley, Inter Science, 1999.
2. Mohammad Isamail and Terri Fiez, Analog VLSI signal and information processing, McGraw Hill, 1994
3. S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal Processing, Prentice Hall, 1985.
Note:
is not allowed.

MTVLSI517C IC FABRICATION TECHNOLOGY
Semester – I

Total : 100 Marks

1. To understand the manufacturing methods and their underlying scientific principles in the context of technologies used in VLSI
chip fabrication.
2. To introduce the fundamentals of IC fabrication technology, IC chip size and circuit complexity etc.
3. To provide a strong foundation on Linear Circuits.
4. To familiarize students with applications of various IC’s.
UNIT I
Cleanroom technology: Clean room concept – Growth of single crystal Si. Processing considerations for single
crystal growth: Chemical cleaning, getting the thermal Stress factors etc
Epitaxy: Molecular beam epitaxy, Vapour phase epitaxy, Liqid phase epitaxy, Basic Transport processes &
reaction kinetics, doping & auto doping, equipments, & safety considerations, buried layers, epitaxial defects,
Evaluation of epitaxial layers.
UNIT II
Oxidation: Growth mechanism & kinetics, Silicon oxidation model, interface considerations, orientation
dependence of oxidation rates thin oxides. Dry & Wet oxidation. Masking properties of SiO 2
Diffusion: Diffusion Mechanisms, The diffusion equation, Diffusion in a concentration gradient, Associated
issues, Macroscopic and Microscopic view of diffusion, Fick’s Law, Extrinsic and Intrinsic diffusion, Diffusion
Systems
UNIT III
Lithography: Types of photo resists, Electron beam lithography system, Optical Lithography system. Electron
optics: roster scans & vector scans, variable beam shape. X-ray lithography: resists & printing, X ray sources &
masks.
Etching: Wet chemical etching, Dry physical etching, Dry chemical etching, Reactive ion etching, Reactive
plasma etching, Wet etching vs. Plasma etching, Physical vs. Chemical etching, AC & DC plasma excitation,
plasma properties.
Ion Implantation: Penetration range, Implantation damage, Annealing, Implantation systems, High energy
implants, Process Considerations.
UNIT IV
Metallization: Different types of metallization, uses & desired properties
Differential Metal gate transistor: Transport in Nano MOSFET, velocity saturation, ballistic transport, injection
velocity, velocity overshoot, Single electron transistors, coulomb blockade effects in ultra-small metallic tunnel
junctions.
Course Outcome: At the end of this course, students will be able to:
1. Understand the manufacturing methods and their underlying scientific principles in the context of technologies used in VLSI chip
fabrication.
2. Introduce the fundamentals of IC fabrication technology, IC chip size and circuit complexity etc.
3. Provide a strong foundation on Linear Circuits.
4. Familiarize students with applications of various IC’s.
References:
1. S.M. Sze, “VLSI Technology”, John Wiley & Sons, 2000.
2. S.M.Sze, “High Speed Semiconductor Devices”, Wiley, New York.
3. Sorab K.Ghandhi, “VLSI Fabrication Principles”, John Wiley & Sons
4. S.M. Sze, “Modern Semiconductor Device Physics”, Wiley, New York
5. C.Y. Chang and S.M. Sze, “ULSI Devices”, Wiley New York
Note:
is not allowed.

MTVLSI519C SEMICONDUCTOR DEVICE MODELING
Semester – I
Total : 100 Marks
Duration of Exam : 3 Hrs.
1. To study about solid state electronic device modelling.
2. To study of basic and advanced MOSFET models and passive device modelling.
3. To study of advanced MOSFET structures.
4. To study of process variation modelling and device mismatch.
UNIT I
MOSFET Device Physics: MOS capacitor, Basic operation, Basic modelling, Comparison of basic MOSFET
models, Advanced MOSFET modeling, RF modeling of MOS transistors, Equivalent circuit representation of
MOS transistor, High frequency behavior of MOS transistor and A.C small signal modelling.
UNIT II
Noise Modeling: Noise sources in MOSFET, Flicker noise modeling, Thermal noise modeling, model for
accurate distortion analysis, nonlinearities in CMOS devices and modeling, calculation of distortion in analog
CMOS circuits.
UNIT III
Advanced MOSFET Structures and Models: SOI MOSFET, FDSOI and PDSOI, Multigate transistors: double
gate MOSFET and FINFET, Charge based models and surface potential models : ACM, EKV, BSIM5, HiSIM,
MOS Model 11 and SP Model.
UNIT IV
BJT and Passive Device Modelling: Modelling passive BJT, Modelling resistors, capacitors and inductors.
Modeling of Process Variation and Device Mismatch: Influence of process variation, modeling of device
mismatch for Analog/RF Applications, Benchmark circuits for quality assurance.
Course Outcome: At the end of this course, student will be able to

1. Utilize the various MOSFET device models available in various CAD tools.
2. Model basic and advanced MOSFET structures and passive devices.
3. Contribute to development and study of newer models for existing and emerging newer versions of MOSFET devices.
4. Build the process variation and device mismatch models.
Reference Books:
1. Trond Ytterdal, Yuhua Cheng and Tor A. Fjeldly, “Device Modeling for Analog and RF”.
2. Ben G. Streetman, “Solid State Electronic Devices”, Prentice Hall.
3. Trond Ytterdal, Tor A. Fjeldly and Michael S. Shur, “Introduction To Device Modelling and Circuit Simulation”.
4. Narain Arora, “MOSFET modelling for VLSI Simulation”.
5. Richard S. Muller, Theodore I. Kamins, “Device Electronics for integrated circuits”, Wiley, 3rd Edition 2002.
Note:
is not allowed.

MTVLSI521C PARALLEL PROCESSING
Semester – I

Total : 100 Marks
1. To identify limitations of architectures of computers and understand the principle of Parallel Processing and Pipelining.
2. To analyze the performance of different computer architectures.
3. To understand principles of multithreading and investigate issues related to computer architectures..
Unit I
Overview of Parallel Processing and Pipelining, Performance analysis, Scalability. Principles and
implementation of Pipelining, Classification of pipelining processors, Advanced pipelining techniques, Software
pipelining.
Unit II
VLIW processors Case study: Superscalar Architecture- Pentium, Intel Itanium Processor, Ultra SPARC, MIPS
on FPGA, Vector and Array Processor, FFT Multiprocessor Architecture.
Unit III
Multithreaded Architecture, Multithreaded processors, Latency hiding techniques. Principles of multithreading,
Issues and solutions.
Unit IV
Parallel Programming Techniques: Message passing program development, Synchronous and asynchronous
message passing, Shared Memory Programming, Data Parallel Programming, Parallel Software Issues,
Operating systems for multiprocessors systems, Customizing applications on parallel processing platforms.

1. Identify limitations of different architectures of computer
2. Analysis quantitatively the performance parameters for different architectures
3. Investigate issues related to compilers and instruction set based on type of architectures.
References:
1. Kai Hwang, Faye A. Briggs, “Computer Architecture and Parallel Processing”, MGH, International Edition
2. Kai Hwang, “Advanced Computer Architecture”, TMH
3. V. Rajaraman, L. Sivaram Murthy, “Parallel Computers”, PHI.
4. William Stallings, “Computer Organization and Architecture, Designing for performance” Prentice Hall, Sixth edition
5. Kai Hwang, Zhiwei Xu, “Scalable Parallel Computing”, MGH
6. David Harris and Sarah Harris, “Digital Design and Computer Architecture”, Morgan Kaufmann.
Note:
is not allowed.

MTVLSI523 C SYSTEM DESIGN WITH EMBEDDED LINUX
Semester – I

Total : 100 Marks

1. To understand embedded Linux development model
2. To understand Embedded Linux drivers and Real time Linux.
3. To understand Linux BSP for a hardware platform.
UNIT I
Embedded Linux Vs Desktop Linux, Embedded Linux Distributions, Embedded Linux Architecture, Kernel
Architecture – HAL, Memory manager, Scheduler, File System, I/O and Networking subsystem, IPC, User
space, Start-up sequence.
UNIT II
Board Support Package, Embedded Storage: MTD, Architecture, Drivers, Embedded File System, Embedded
Drivers: Serial, Ethernet, I2C, USB, Timer, Kernel Modules.
UNIT III
Porting Applications, Real-Time Linux: Linux and Real time, Programming, Hard Real-time Linux.
UNIT IV
Building and Debugging: Kernel, Root file system, Embedded Graphics, Case study of uClinux.

1. Familiarity of the embedded Linux development model.
2. Write, debug, and profile applications and drivers in embedded Linux.
3. Understand and create Linux BSP for a hardware platform
References:
1. Karim Yaghmour, “Building Embededd Linux Systems”, O'Reilly & Associates
2. P Raghvan, Amol Lad, SriramNeelakandan, “Embedded Linux System Design and Development”, Auerbach Publications
3. Christopher Hallinan, “Embedded Linux Primer: A Practical Real World Approach”, Prentice Hall, 2nd Edition, 2010.
4. Derek Molloy, “Exploring BeagleBone: Tools and Techniques for Building with Embedded Linux”, Wiley, 1st Edition, 2014.
Note:
is not allowed.

MTVLSI525C CAD OF DIGITAL SYSTEM
Semester – I

Total : 100 Marks

1. Fundamentals of CAD tools for modelling, design, test and verification of VLSI systems.
2. To Study of various phases of CAD, including simulation, physical design, test and verification.
3. To demonstrate knowledge of computational algorithms and tools for CAD.
UNIT I
VLSI Design Methodologies: Introduction to VLSI Methodologies – Design and Fabrication of VLSI Devices,
Fabrication Process and its impact on Design. Review of VLSI Design automation tools - Algorithmic Graph
Theory and Computational Complexity - Tractable and Intractable problems - general purpose methods for
combinatorial optimization.
UNIT II
Modeling: Modeling techniques, Types of CAD tools and Introduction to logic simulation Verilog: Syntax,
Hierarchical modeling and Delay modeling, Verilog constructs, Memory modeling.
Synthesis: synthesis - Synthesizable and Non Synthesizable constructs, Logic Optimization, Resource Sharing,
Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis.
UNIT III
Logic and layout synthesis: Technology mapping, ASIC design methodology, FPGA based system design and
prototyping, layout synthesis: the physical design, timing analysis, graph algorithms and their application in IC
design.
High level SYNTHESIS: High level Synthesis - Hardware models - Internal representation - Allocation -
assignment and scheduling - Simple scheduling algorithm - Assignment problem - High level transformations.
UNIT IV
Simulation: Gate-level modeling and simulation, Switch-level modeling and simulation, MCMS-VHDL
Verilog implementation of simple circuits using VHDL
Course Outcomes:
At the end of this course, students will be able to:
1. Fundamentals of CAD tools for modelling, design, test and verification of VLSI systems.
2. Study of various phases of CAD, including simulation, physical design, test and verification.
3. Demonstrate knowledge of computational algorithms and tools for CAD.
References:
1. N.A. Sherwani, “Algorithms for VLSI Physical Design Automation”.
2. S.H. Gerez, “Algorithms for VLSI Design Automation.
3. M. Sarrafzadeh and C.K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1996
4. D.D Gajski et al., High Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992
5. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, Tata McGraw Hill, 1994
NOTE:
is not allowed.

MTVLSI527C INTRODUCTION TO MEMS
Semester – I
Total : 100 Marks

1. To introduce MEMS and micro fabrication.
2. To study various etching techniques.
3. To know various fabrication and machining process of MEMS.
4. To know about the polymer and optical MEMS.
UNIT I
Historical Background: MicroElectroMechanicalSystems.: Introduction,evolution, applications, MEMS
system-level design methodology.
Scaling laws in Miniaturized Designs: Scaling in electrostatic forces, electromagnetic forces, Scaling in
electricity, fluid mechanics and heat transfer
UNIT II
Physical Microsensors: Classification of physical sensors, Integrated, Intelligent, or Smart sensors, Sensor
Principles and Examples: Thermal sensors, Electrical Sensors, Mechanical Sensors, Chemical and
Biosensors,Pressure Sensor,Accelerometer.
Microactuators: Electromagnetic and Thermal microactuation, Microactuator examples,microgrippers,
microvalves, micropumps, micromotors-Microactuator systems : Ink-Jet printer heads, Micro-mirror TV
Projector.
UNIT III
Microfabrication and Micromachining: Integrated Circuit Processes ,Micromachining Introduction , Bulk
Micromachining: Isotropic Etching and Anisotropic Etching, Wafer Bonding, High Aspect-Ratio Processes
(LIGA).
Surface Micromachining: One or two sacrificial layer processes, Surface micromachining requirements,
Polysilicon surface micromachining, Other compatible materials, Silicon Dioxide, Silicon Nitride, Piezoelectric
materials.
UNIT IV
Application Areas: All-mechanical miniature devices, RF/Electronics devices, Optical/Photonic devices,
Medical devices e.g. DNA-chip, micro-arrays.
Micropackaging: Microsystem Packaging, Interfaces in Microsystem Packaging, Packaging Technologies,
Three dimensional packaging, Microsystems assembly, Selection of Packaging Materials.
Course Outcome: After completion of the course, students will be able to

1. Design, analysis and testing of MEMS.
2. Report on various wet etching techniques and describe their principles and possible usage.
3. Qualitatively describe surface micromachining and stress properties associated with various deposition techniques.
4. Describe fundamental principles and processes for packaging of microsystems.
Text Books:
1. Stephen D. Senturia, "Microsystem Design" by, Kluwer Academic Publishers, 2001.
2. Tai-Ran Hsu, “MEMS & MICROSYSTEMS Design and Manufacture”, Mc Graw Hill Pub.,2016.
Reference Books:
1. Fundamentals of Microfabrication by, CRC Press, 1997.Gregory Kovacs, Micromachined Transducers Sourcebook WCB McGraw-
Hill, Boston, 1998.
2. M.-H. Bao, Micromechanical Transducers: Pressure sensors, accelrometers, and gyroscopes by Elsevier, New York, 2000.
Note:
is not allowed.
th
Approved in the 13 meeting of academic council held on 18/6/2018.
MTVLSI529C ADVANCED COMPUTER ARCHITECTURE
Semester – I
Total : 100 Marks

1. To describe modern architectures such as RISC, Super Scalar, VLIW, multi-core and multi-CPU systems.
2. To understand the various techniques to enhance a processors ability to exploit Instruction-level parallelism (ILP), and its
challenges.
3. To improve performance of different CPU architectures and develop applications for high performance computing systems.
UNIT I
Parallel computer models: The state of computing, Classification of parallel computers, Multiprocessors and
multicomputer, Multivector and SIMD computers.
Program and network properties: Conditions of parallelism, Data and resource Dependences, Hardware and
software Parallelism, Program partitioning and scheduling, Grain Size and latency, Program flow mechanisms,
Control flow versus data flow, Data flow Architecture, Demand driven mechanisms, Comparisons of flow
mechanisms.
UNIT II
System Interconnect Architectures:
Network properties and routing, Static interconnection Networks, Dynamic interconnection Networks,
Multiprocessor system Interconnects, Hierarchical bus systems, Crossbar switch and multiport memory,
Multistage and combining network.
Advanced processors: Advanced processor technology, Instruction-set Architectures, CISC Scalar Processors,
RISC Scalar Processors, Superscalar Processors, VLIW Architectures, Vector and Symbolic processors.
UNIT III
Pipelining: Linear pipeline processor, nonlinear pipeline processor, Instruction pipeline Design, Mechanisms for
instruction pipelining, Dynamic instruction scheduling, Branch Handling techniques, branch prediction,
Arithmetic Pipeline Design, Computer arithmetic principles, Static Arithmetic pipeline, Multifunctional
arithmetic pipelines.
Memory Hierarchy Design: Cache basics & cache performance, reducing miss rate and miss penalty, multilevel
cache hierarchies, main memory organizations, design of memory hierarchies.
UNIT IV
Multiprocessor architectures: Symmetric shared memory architectures, distributed shared memory
architectures, models of memory consistency, cache coherence protocols (MSI, MESI, MOESI), scalable cache
coherence, overview of directory based approaches, design challenges of directory protocols, memory based
directory protocols, cache based directory protocols, protocol design trade-offs, synchronization.
Scalable point – point interfaces: Alpha364 and HT protocols, high performance signaling layer.
Enterprise Memory subsystem Architecture: Enterprise RAS Feature set: Machine checks, hot add/remove,
domain partitioning, memory mirroring/migration, patrol scrubbing, fault tolerant system.
Course Outcome: On successful completion of this course student will be able to:
1. Describe modern architectures such as RISC, Super Scalar, VLIW, multi-core and multi-CPU systems.
2. Understand the various techniques to enhance a processors ability to exploit Instruction-level parallelism (ILP), and its
challenges.
3. Improve application performance for different CPU architectures and develop applications for high performance computing
systems.
Reference Books:
1. Kai Hwang, “Advanced computer architecture”, TMH. 2000
2. D. A. Patterson and J. L. Hennessey, “Computer organization and design”, Morgan Kaufmann, 2nd Ed. 2002.
3. J. P. Hayes, “computer Architecture and organization”; MGH. 1998.
4. Harvey G. Cragon, “Memory System and Pipelined processors” Narosa Publication. 1998.
5. V. Rajaranam& C. S. R. Murthy, “Parallel computer”; PHI. 2002
6. R.K.Ghose, Rajan Moona&Phalguni Gupta, “Foundation of Parallel Processing”, Narosa Publications, 2003.
NOTE:
is not allowed.

M.Tech. Programme (Audit Course)
AUD531C: ENGLISH FOR RESEARCH PAPER WRITING

M. Tech. Semester – I/II (Common to all Branches)
L P Credits Class Work : 25Marks
2 -- -- Examination : 75 Marks
Total : 100 Marks
Duration of Examination : 3 Hours
Course Objectives: Students will be able to:

1. Understand that how to improve your writing skills and level of readability,
2. Learn about what to write in each section,
3. Understand the skills needed when writing a Title, and
4. Ensure the good quality of paper at very first-time submission
Course Outcomes:
The Students will become conscious citizens of India aware of their duties, rights and functions of various
bodies of governance and welfare; thereby well equipped to contribute to India.
UNIT I: Basics of Writing Skills:

Subject Verb Agreements; Parallelism; Structuring Paragraphs and Sentences; Being Concise
and Removing Redundancy; Avoiding Ambiguity and Vagueness; Dangling Modifiers
UNIT II: Reviewing and Citation:

Clarifying Who Did What; Highlighting Your Findings from Literature; Hedging and
Critiquing; Paraphrasing; Avoiding Plagiarism; Formatting and Citation (Publication Manual
of the American Psychological Association)
UNIT III: Sections of a Research Paper:

Writing Effective and Impressive Abstract; Writing Introduction; Review of Literature;
Defining Objectives of the Study; Methodology Adopted; Results Obtained; Discussion and
Conclusion; Editing and Proof Reading to Ensure Quality of paper
UNIT IV: Oral Presentation for Academic Purposes:

Oral Presentation for Seminars, Conferences and Symposiums; Poster Presentation; Choosing
AppropriateMedium; Interaction and Persuasion
TEXT / REFERENCE BOOKS:

1. Goldbort R (2006) Writing for Science, Yale University Press (available on Google Books).
2. Day R (2006) How to Write and Publish a Scientific Paper, Cambridge University Press.
3. Highman N (1998), Handbook of Writing for the Mathematical Sciences, SIAM. Highman’sbook.
4. Adrian Wallwork, English for Writing Research Papers, Springer, New York Dordrecht Heidelberg
London, 2011
5. Mc Murrey,David A. and Joanne Buckley. Handbook for Technical Writing. New Delhi: Cengage
Learning, 2008.
NOTE:
1. In the semester examination, the examiner will set 08 questions in all selecting two from each unit. The
candidates will be required to attempt five questions in all selecting at least one from each unit. All
questions will carry equal marks.
2. The students will be allowed to use non-programmable scientific calculator. However,
3. Electronics gadgets including Cellular phones are not allowed in the examination.

AUD533C: DISASTER MANAGEMENT
M. Tech. Semester – I/II (Common for all Branches)
Total : 100 Marks
Course Objectives:
1. Learn to demonstrate a critical understanding of key concepts in disaster risk reduction and
humanitarian response
2. Critically evaluate disaster risk reduction and humanitarian response policy and practice from multiple
perspectives
3. Develop an understanding of standards of humanitarian response and practical relevance in specific
types of disasters and conflict situations
4. Critically understand different aspects of disaster management
Course Outcomes: A student will be able to:

1. Know the significance of disaster management,
2. Study the occurrences, reasons and mechanism of various types of disaster
3. Learn the preventive measures as Civil Engineer with latest codal provisions
4. Apply the latest technology in mitigation of disasters
UNIT I: Introduction to Disaster Management: Definitions: Disaster, Emergency, Hazard,

Mitigation, Disaster Prevention, Preparedness and Rehabilitation, Risk and Vulnerability,
Classification of Disaster, Natural and Man made Disasters, Disaster Management Act 2005,
Role of NDMA, NDRF, NIDM
Risk and Vulnerability to disaster mitigation and management options: Concept and
Elements, Risk Assessment, Vulnerability, Warning and Forecasting.
UNIT II: Hydro-meteorological based disasters I: Tropical Cyclones, Floods, droughts, mechanism,
Causes, role of Indian Metrological Department, Central Water Commission, structure and
their impacts, classifications, vulnerability, Early Warning System, Forecasting, Flood
Warning System, Drought Indicators, recurrence and declaration, Structural and Non-
structural Measures.
Hydro-meteorological based disasters II: Desertification Zones, causes and impacts of
desertification, Characteristics, Vulnerability to India and Steps taken to combat
desertification, Prevention.
UNIT III: Geological based disasters: Earthquake, Reasons, Direct and Indirect Impact of Earthquake;
Seismic Zones in India, Factors, Prevention and Preparedness for Earthquake, Tsunamis,
Landslides and avalanches: Definition, causes and structure; past lesson learnt and measures
taken; their Characteristic features, Impact and prevention, structural and non-structural
measures.
UNIT IV: Manmade Disasters I: Chemical Industrial hazards; causes and factors, pre- and post disaster
measures; control ; Indian Standard Guidelines and Compliance; Oil Slicks and Spills,
Outbreak of Disease and Epidemics, Traffic accidents; classification and impact, War and
Conflicts; Fire risk assessment; Escape routes; fire fighting equipment;
Use of remote sensing and GIS in disaster mitigation and management.

1. Thomas D. Schneid., Disaster Management and Preparedness, CRC Publication, USA, 2001
2. Patrick Leon Abbott, Natural Disasters, Amazon Publications, 2002
3. Ben Wisner., At Risk: Natural Hazards, People vulnerability and Disaster, Amazon Publications, 2001
4. Oosterom, Petervan, Zlatanova, Siyka, Fendel, Elfriede M., “Geo-information for Disaster
Management”, Springer Publications, 2005
5. Savindra Singh and Jeetendra Singh, Disaster Management, Pravalika Publications, Allahabad

6. Nidhi GaubaDhawan and AmbrinaSardar Khan, Disaster Management and Preparedness, CBS
Publishers & Distribution
7. Selected Resources Published by the National Disaster Management Institute of Home Affairs, Govt.
of India, New Delhi.
NOTE:

AUD535C: SANSKRIT FOR TECHNICAL KNOWLEDGE
M. Tech. Semester – I/II (Common for all Branches Engineering)
Total : 100 Marks
Course Objectives:
1. To get a working knowledge in illustrious Sanskrit, the scientific language in the world
2. Learning of Sanskrit to improve brain functioning
3. Learning of Sanskrit to develop the logic in Mathematics, Science & other subjects
4. Enhancing the memory power
Course Outcomes: Students will be able to

1. Understand basic Sanskrit language
2. Understand Ancient Sanskrit literature about science and technology
3. Get equipped with Sanskrit and explore the huge knowledge from ancient literature

1. “Abhyaspustakam” – Dr.Vishwas, Samskrita-Bharti Publication, New Delhi
2. “Teach Yourself Sanskrit” Prathama Deeksha-VempatiKutumbshastri, Rashtriya Sanskrit Sansthanam,
New Delhi Publication
3. “India’s Glorious Scientific Tradition” Suresh Soni, Ocean books (P) Ltd., New Delhi.
NOTE:

AUD537C: VALUE EDUCATION
Total : 100 Marks
Course Objectives: The students will be able to

1. Understand value of education and self- development
2. Imbibe good values in students
3. Let the should know about the importance of character
Course Outcomes: The students will be able to

1. Knowledge of self-development
2. Learn the importance of Human values
3. Developing the overall personality
4. Strengthen the “EQ”
Unit I: Hierarchy and Classification of values,

Values and Belief Systems, Competence in professional ethics,
Value judgment based on cultural, tradition and interdependence.
Unit II: Need for value education

Sense of duty.Devotion, Self-reliance.
Honesty, Humanity, trust.Patriotism and national Unity.
Harmony in the nature and realization of coexistence
Vision of better India
Unit III: Understanding the meaning and realizing the effect of the following:
Aware of self- destructive habits, Knowledge, Acceptance, Love, Situations, happiness, Bliss,
Peace,Power, Purity , Realization, Assertiveness, Regard, Respect, Sensitive, Divinity,
emotions, Repentance, hurt, Ego, Attachment, worry, Resentment, Fear, Anxiety, Greed,
Criticism, Tension, Frustration, Expectation, Irritation, Anger, Guilt, Jealous, Pear Pressure,
True Friendship, Cooperation -Coordination- competition.
Enhancing self esteem and personality.
Unit IV: Hinduism, Jainism, Buddhism, Christianity, Islam, Sikhism.

Self-management and Good health ( Role, Responsibility, Relation, Routine, Requirements,
Resources)
My True self and Original qualities.Supreme-soul- source of values.
What Scientists say about super power?
1. Chakroborty, S.K. Values and Ethics for organizations Theory and practice. Oxford University Press,
New Delhi.
2. R R Gaur, R Sangal, G P Singh.Human Values and Professional Ethics. Excell Books, New Delhi.
3. Value Education in Spirituality- Course-I, course -II by Brahma Kumaris Education Wing,
RajyogaEducation & Research Foundation, Mount Abu, Rajasthan.
4. True Management: I K International Publication 2018.
NOTE:
1. In the semester examination, the examiner will set 08 questions in all selecting two from each unit.
The candidates will be required to attempt five questions in all selecting at least one from each
unit. All questions will carry equal marks.
AUD539C: CONSTITUTION OF INDIA
Total : 100 Marks

1. Understand the premises informing the twin themes of liberty and freedom from a civil rights
perspective.
2. To address the growth of Indian opinion regarding modern Indian intellectuals’ constitutional role and
entitlement to civil and economic rights as well as the emergence of nationhood in the early years of
Indian nationalism.
3. To address the role of socialism in India after the commencement of the Bolshevik Revolution in 1917
and its impact on the initial drafting of the Indian Constitution.
Course Outcomes:
The Students will become conscious citizens of India aware of their duties, rights and functions of various
bodies of governance and welfare; thereby well equipped to contribute to India.
Unit I: Making of the Indian Constitution and its Philosophy

Sources of Indian Constitution, its Preamble and Salient Features.
Unit II: Constitutional Rights & Duties

Fundamental Rights: Right to Equality, Right to Freedom, Right against Exploitation, Right to
Freedom of Religion, Cultural and Educational Rights, Right to Constitutional Remedies
Fundamental Duties
Unit III: Organs of Governance

Legislature: Parliament and its Composition; Qualifications and Disqualifications of Its
members
Executive: President, Governor and Council of Ministers
Judiciary: Appointments, Qualifications, Powers and Functions of judges
Unit IV: Local Administration and institutes for welfare

District Administration Head: Role and Importance; Municipalities: Introduction, Mayor and
role of Elected Representative
Panchayati Raj Institutions: Introduction, Gram Panchayat, Panchayat Samiti and Zila
Panchayat
Institutes and Bodies for the welfare of SC/ST/OBC and women

1. The Constitution of India, 1950 (Bare Act), Government Publication.
2. Dr. S. N. Busi, Dr. B. R. Ambedkar. Framing of Indian Constitution, 1st Edition, 2015.
3. M. P. Jain, Indian Constitution Law, 7th Ed., Lexis Nexis, 2014
NOTE:

AUD541C: PEDAGOGICAL STUDIES
Total : 100 Marks
Course Objectives: The course will enable the student teachers:

1. To understand the concept of pedagogy and conceptual framework.
2. To gain insight on the meaning and nature of different pedagogies.
3. To determine aims and strategies of teaching- learning.
4. To understand the principals, maxims of successful teaching and the different methods of teaching.
5. Comprehend the need and importance of various devices of teaching and learning and their relationship
between the two.
6. Point out and illustrate the difference between teaching and learning and their relationship between the
two.
7. To appreciate that science/ engineering is a dynamic and expanding body of knowledge.
Course Outcomes: Students will be able to understand:

1. It will improve teaching effectiveness of prospective teachers.
2. A prospective teacher will be able to design curriculum and assess the curriculum of their discipline in
an effective way by understating the needs of the learners.
3. How can teacher education, school curriculum and guidance support effective pedagogy?
4. It will be functional for professional development among teachers.
Unit I: Introduction and Methodology

 Aims and Rationale, Conceptual Framework, Terminology related to Pedagogy
 Contexts, Research Questions
 Theories of Learning, Curriculum, Scope of Pedagogy
Unit II: Teaching

 Meaning and importance of Behavioral Objectives
 Writing of Objectives in Behavioral Terms
 Phases and Variables of Teaching
 Principles, levels and maxims off teaching
 Relationship between Teaching and Learning
Unit III: Methods of Teaching

 Methods: Inductive, Deductive, Project, Analytic, Synthetic, Brain Storming, Case
Discussion
 Concept and Significance of Individualized and Cooperative Teaching-Language
Laboratory, Tutorials, Keller’s Plan (PSI), Computer Supporting Collaborative Learning
 Mastery Learning: Concept, Basic Elements, Components and Types of Mastery Learning
Strategies
Unit IV: Evaluation Strategies

 Evaluation in Teaching: Concept of Evaluation, Relationship between Teaching and
Evaluation, Types of Evaluation (Formative and Summative)
 Methods of Evaluation through Essay Type. Objective Type and Oral Method,
Comparative merits and demerits of evaluation methods
 Latest Trends in Evaluation

1. Ackers J, Hardman F (2001) Classroom interaction in Kenyan primary schools, Compare, 31 (2): 245-
261.
2. Agrawal M (2004) Curricular reform in schools: The importance of evaluation, Journal of

Curriculum Studies, 36 (3): 361-379.
3. Akyeampong K (2003) Teacher training in Ghana - does it count? Multi-site teacher education research
project (MUSTER) country report 1. London: DFID.
4. Akyeampong K, Lussier K, Pryor J, Westbrook J (2013) Improving teaching and learning of basic
maths and reading in Africa: Does teacher preparation count? International Journal Educational
Development, 33 (3): 272–282.
5. Alexander RJ (2001) Culture and pedagogy: International comparisons in primary education. Oxford
and Boston: Blackwell.
6. Chavan M (2003) Read India: A mass scale, rapid, ‘learning to read’ campaign.
7. www.pratham.org/images/resource%20working%20paper%202.pdf.
8. Dyer C (2008) Early years literacy in Indian urban schools: Structural, social and pedagogical issues,
Language and Education, 22 (5): 237-253.
9. Sharma N (2013) An exploration of teachers’ beliefs and understanding of their pedagogy, MPhil
thesis, Mumbai: TATA Institute of Social Sciences.
10. Zeichner K, Liston D (1987) Teaching student teachers to reflect, Harvard Educational Review, 56 (1):
23-48.
11. Watkins C, Mortimore P (1999) Pedagogy: What do we know? In Mortimore P (ed.) Understanding
pedagogy and its impact on learning. London: Paul Chapman Publishing.
12. Tyler R (1949) Basic principles of curriculum and instruction. Chicago: Chicago University Press.
13. Arends, R.1. ( 1 994) Learning to Teach, New York: McGraw-Hill.
14. Lunenberg M, Korthagen F, Swennen A (2007) The teacher educator as a role model, Teaching and
Teacher Education, 23: 586-601.
15. Meena . Wilberforce E. Curriculum Innovation in Teacher Education: Exploring Conceptions among
Tanzanian Teacher Educators. ÅBO AKADEMI UNIVERSITY PRESS, 2009.
16. Cooley, W. W., and Lohnes, P. R. (1976). Evaluation research in education. New York: Irvington.
17. Hassard, Jack, 2004, The Art of Teaching Science, Oxford Univesity Press.
18. Joyce, B., Weil, M., Calhoun, E. : (2000). Models of teaching, 6th edition, Allyn & Bacon.
19. Kyriacou, C. (2007) Effective teaching in schools – theory and practice. Cheltenham: Nelson Thornes.
20. Nye, B., Konstantopoulos, S. & Hedges, L.V. (2004) ‘How large are teacher effects?’ Educational
evaluation and policy analysis, 26(3), 237-257.
21. National Staff Development Council. (2001). NSDC’s standards for staff development. Oxford, OH:
Author.
22. Serpell, Z. & Bozeman, L. (1999). Beginning teacher induction: A report on beginning teacher
effectiveness and retention. Washington, DC: National Partnership for Excellence and Accountability
in Teaching.
NOTE:

AUD543C: STRESS MANAGEMENT BY YOGA
Total : 100 Marks
Course Objectives:
1. To achieve overall health of body and mind
2. To overcome stress
Course Outcomes: Students will be able to:

1. Develop healthy mind and healthy body thus improving social health also
2. Improve efficiency
3. Improving “SQ”
Unit I: 1. Causes of stress, consequences of stress, diagnosis of stress, solution of reducing

Stress.
2. Difference and relation b/w Yog and Yoga,
3. benefits of meditation and Yoga,
4. Rules and Regulation of Yog and Yoga.
5. Empowerment of Soul and fitness of body.
Unit II: 1. Do`s and Don’t’s in life.

2. How to be and not to be?
3. Understanding spirituality and materials.
4. Impact of: Truth at mouth/ Truth in thoughts
Non Violence outside / Compassion in thoughts, Celibacy (kamnayn- desire), purity
of mind , non-covetousness, Cleanliness, satisfaction, self study and surrender to
almighty, Austerity, Penance
Unit III: Role of Meditation in reducing Stress.

Role of Yoga in reducing Stress.
Pranyama: AnulomVilom ,Ujjai, Costal Breathing, Abdominal Breathing, Sunyak, Kumbhak
Unit IV: Asan:Sukhasana, Vajrasana, Padmasana, Swastik Asana, Ling Mudra, Gorakshasana,
Talasana, Konasana, Trikonasana, Chakrasana, Utkatasana, Dhurva Asana, Garuda Asana,
Bhadrasana, Parvatasana, Yoga Mudra, Paschimottasana, Vakrasana, Gomukhasana,
Bakasana, Tulasana, Matsyasana, Mayuri Asana, Bhujagasana, DhanurVakrasana,
PavanMuktasana, Viprtkarani, Makarasana, Shavasana, Dridasana, Yonimudra, Nauli, Dhenu
Mudra.

1. ‘Yogic Asanas for Group Tarining-Part-I”: Janardan Swami Yogabhyasi Mandal, Nagpur
2. “Rajayoga or conquering the Internal Nature” by Swami Vivekananda, AdvaitaAshrama, (Publication
Department), Kolkata
3. “Value Education in Spirituality- Course-IV” by Brahma Kumaries Education Wing, Rajyoga
Education Research Foundation, Mount Abu, Rajasthan.
4. “Stress Management for Dummies” by Allen Elkin, IDG Books India (P) Ltd.
5. “Yoga Courses for All” by Dr Hansraj Yadav, BhartyaVidyaBhawan, Mumbai
NOTE:

AUD545C: PERSONALITY DEVELOPMENT THROUGH LIFE
ENLIGHTENMENT SKILLS
Total : 100 Marks

1. To learn and achieve the highest goal happily
2. To become a person with stable mind, pleasing personality and determination
3. To awaken wisdom in students
Course Outcomes:
1. The study of Shrimad-Bhagwad-Geeta will help the student in developing his personality and achieve
the highest goal in life.
2. The person who has studied Geeta will lead the nation and mankind to peace and prosperity.
3. Study of Neetishatakam will help in developing versatile personality of students.
Unit I: Holistic Development of Personality

Neetisatakam-Verses-19,20,21,22 (Wisdom), Verses-29, 31 32 (Pride and Heroism) ,Verses-
26,28,63,65 (Virtue)
Unit II: Approach to Day to Day Work and Duties
Shrimad BhagwadGeeta: Chapter 2 (Verses- 41, 47, 48), Chapter 3 (Verses- 13, 21, 27, 35),
Chapter 6 (Verses- 05, 13, 17, 23, 35), Chapter 18 (Verses- 45, 46, 48)
Unit III: Statements of Basic Knowledge
Shrimad BhagwadGeeta: Chapter 2 (Verses- 56, 62,68), Chapter 12 (Verses- 13, 14, 15, 16,
17, 18)
Unit IV: Personality of a Role Model
Shrimad BhagwadGeeta: Chapter 2 (Verses- 17), Chapter 3 (Verses 36, 37, 42), Chapter 4
(Verses 18, 38, 39), Chapter 18 ( Verses 37, 38 63)

1. Srimad Bhagavad Gita by Swami SwarupanandaAdvaita Ashram (Publication Department), Kolkata
2. Bhartrihari’s Three Satakam (Niti-sringar-vairagya) by P.Gopinath, Rashtriya Sanskrit Sansthanam,
New Delhi.
3. BhagvadGeeta- Prof. Satyavrata Siddhantalankar, Orient Publishing.
NOTE:
2. The students will be allowed to use non-programmable scientific calculator. However, sharing/exchange
of calculator is prohibited in the examination.

MTVLSI502C MICROCONTROLLERS AND PROGRAMMABLE DIGITAL
SIGNAL PROCESSORS
Semester – II
Total : 100 Marks

1. To Compare and select ARM processor with several features/peripherals based on requirements of embedded applications.
2. To study of AVR microcontroller features, application based on AVR microcontroller.
3. To develop small applications by utilizing the ARM processor core based platform.
UNIT I
AVR MICROCONTROLLER: Introduction to AVR microcontroller, features of AVR family
microcontrollers, different types of AVR microcontroller, architecture, memory access and instruction
execution, pipelining, program memory considerations, addressing modes, CPU registers, Instruction set, and
simple operations.
FEATURES OF AVR MICROCONTROLLER: Timer: Control Word, mode of timers, simple programming,
generation of square wave, Interrupts: Introduction, Control word Simple Programming, generation of
waveforms using interrupt, Serial interface using interrupt, Watch-dog timer, Power-down modes of AVR
microcontroller, UART, SRAM.
UNIT II
APPLICATION BASED AVR MICROCONTROLLER: Interfacing of AVR microcontroller with other
devices using serial / parallel communication, I2C Protocol, SPI Protocol, ADC/DAC, DC motor controller
using PWM.
UNIT III
ARM Cortex-M3 processor: Applications, Programming model – Registers, Operation modes, Exceptions and
Interrupts, Reset Sequence Instruction Set, Unified Assembler Language, Memory Maps, Memory Access
Attributes, Permissions, Bit-Band Operations, Unaligned and Exclusive Transfers. Pipeline, Bus Interfaces.
UNIT IV
Exceptions, Types, Priority, Vector Tables, Interrupt Inputs and Pending behavior, Fault Exceptions, Supervisor
and Pendable Service Call, Nested Vectored Interrupt Controller, Basic Configuration, SYSTICK Timer,
Interrupt Sequences, Exits, Tail Chaining, Interrupt Latency.
1. Compare and select ARM processor with several features/peripherals based on requirements of embedded applications.
2. Study of AVR microcontroller features, application based on AVR microcontroller
3. Develop small applications by utilizing the ARM processor core based platform.
References:
1. Joseph Yiu, “The definitive guide to ARM Cortex-M3”, Elsevier, 2nd Edition
2. Venkatramani B. and Bhaskar M. “Digital Signal Processors: Architecture, Programming and Applications” , TMH , 2nd Edition
3. Sloss Andrew N, Symes Dominic, Wright Chris, “ARM System Developer's Guide: Designing and Optimizing”, Morgan Kaufman
Publication
4. Steve furber, “ARM System-on-Chip Architecture”, Pearson Education
5. Frank Vahid and Tony Givargis, “Embedded System Design”, Wiley
6. Technical references and user manuals on www.arm.com, NXP Semiconductor: www.nxp.com and Texas Instruments www.ti.com
NOTE:
are not allowed.

MTVLSI504C VLSI DESIGN VERIFICATION AND TESTING
Semester – II

Total : 100 Marks
Course Objective:
At the end of this course, students will be able to:
1. Familiarity of Front end design and verification techniques and create reusable test environments.
2. Verify increasingly complex designs more efficiently and effectively.
3. Use EDA tools like Cadence, Mentor Graphics.
UNIT I
Verification guidelines: Verification Process, Basic Test bench functionality, directed testing, Methodology
basics, Constrained-Random stimulus, Functional coverage, Test bench components, Layered test bench,
Building layered test bench, Simulation environment phases, Maximum code reuse, Test bench performance.
Data types: Built-in data types, Fixed-size arrays, Dynamic arrays, Queues, Associative arrays, Linked lists,
Array methods, Choosing a storage type, Creating new types with type def ,Creating user-defined structures,
Type conversion, Enumerated types, Constants strings , Expression width.
UNIT II
Procedural statements and routines: Procedural statements, tasks, functions and void functions, Routine
arguments, Returning from a routine, Local data storage, Time values Connecting the test bench and design:
Separating the test bench and design, Interface constructs , Stimulus timing, Interface driving and sampling,
Connecting it all together, Top-level scope Program – Module interactions.
UNIT III
System Verilog Assertions: Basic OOP: Introduction, think of nouns, Not verbs, your first class, where to
define a class, OOP terminology, Creating new objects, Object de-allocation, Using objects, Static variables vs.
Global variables, Class methods, Defining methods outside of the class, Scoping rules, Using one class inside
another, Understanding dynamic objects, Copying objects, Public vs. Local, Straying off course building a test
bench.
UNIT IV
Randomization: Introduction, What to randomize, Randomization in System Verilog, Constraint details
solution probabilities, Controlling multiple constraint blocks, Valid constraints , In-line constraints, The pre
randomize and post randomize functions.
Random number functions, Constraints tips and techniques, Common randomization Problems, Iterative and
array constraints, Atomic stimulus generation vs. Scenario generation,
Random control , Random number generators, Random device configuration.
References Books:
1. Chris Spears, “ System Verilog for Verification”, Springer, 2nd Edition
2. M. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits",
Kluwer Academic Publishers
3. IEEE 1800-2009 standard (IEEE Standard for SystemVerilog— Unified Hardware Design,Specification, and Verification
Language).
4. System Verilog website – www.systemverilog.org
5. http://www.sunburstdesign.com/papers/CummingsSNUG2006Boston_SystemVerilog Events.pdf
6. General reuse information and resources www.design-reuse.com OVM, UVM(on top of SV) www.verificationacademy.com
7. Verification IP resources
http://www.cadence.com/products/fv/verification_ip/pages/default.aspx
http://www.synopsys.com/Tools/Verification/FunctionalVerification/VerificationIP/Pages/default.aspx
NOTE:
are not allowed.

MTVLSI552C Microcontrollers and Programmable Digital Signal Processors Lab
Semester – II

Total : 100 Marks

1. To study the architecture of AVR Microcontroller & AVR development board.
2. To study of assembly language programme and use to interface external blocks
3. To demonstrate a working knowledge of the necessary steps and methods used to interface a microcontroller system to devices
such as motors, sensors, etc
4. To enable the students to program , simulate and test the interface AVR microcontroller with other using serial / parallel
communication
5. To Install, configure and utilize tool sets for developing applications based on ARM processor
List of Experiments:
Part A
Experiments to be carried out on AVR microcontroller
1. To study the architecture of AVR Microcontroller & AVR development board.
2. Write an ALP to enter a word from keyboard and to display.
3. Write an ALP to generate 10 KHz & 100 KHz frequency using AVR Microcontroller.
4. Write an ALP to interface intelligent LCD display.
5. Write an ALP to interface intelligent LED display.
6. Write an ALP to Switch ON alarm when AVR Microcontroller receives interrupt.
7. Write an ALP to interface AVR microcontroller with other using serial / parallel communication.
8. Write an ALP to I2C Protocol interface.
9. Write an ALP to interface ADC/DAC.
10. Write an ALP to interface DC motor controller using PWM.
Part B
Experiments to be carried out on Cortex-M3 development boards and using GNU tool chain
1. Blink an LED with software delay, delay generated using the System timer.
2. System clock real time alteration using the PLL modules.
3. Control intensity of an LED using PWM implemented in software and hardware. 4. Control an LED
using switch by polling method, by interrupt method and flash the LED once every five switch presses.
4. UART Echo Test.
5. Take analog readings on rotation of rotary potentiometer connected to an ADC channel.
6. Temperature indication on an RGB LED.
7. Mimic light intensity sensed by the light sensor by varying the blinking rate of an LED.
8. Evaluate the various sleep modes by putting core in sleep and deep sleep modes.
9. System reset using watchdog timer in case something goes wrong.
10. Sample sound using a microphone and display sound levels on LEDs.
1. Study the architecture of AVR Microcontroller & AVR development board.
2. Study of assembly language programme and use to interface external blocks
3. Demonstrate a working knowledge of the necessary steps and methods used to interface a microcontroller system to devices
such as motors, sensors, etc
4. Enable the students to program , simulate and test the interface AVR microcontroller with other using serial /parallel
communication
5. Install, configure and utilize tool sets for developing applications based on ARM processor.
NOTE:

MTVLSI554C VLSI DESIGN VERIFICATION AND TESTING LAB
Semester – II
Total : 100 Marks
Course Objective: At the end of the laboratory work, students will be able to:
1. To verify increasingly complex designs more efficiently and effectively.
2. To use EDA tools like Cadence, Mentor Graphics.
LIST OF EXPERIMENTS:
1. Sparse memory
2. Semaphore
3. Mail box
4. Classes
5. Polymorphism
6. Coverage
7. Assertions
1. Verify increasingly complex designs more efficiently and effectively.
2. Use EDA tools like Cadence, Mentor Graphics.
NOTE:

MTVLSI556C MINI PROJECT
Semester – II

- - 4 2 Exams : 75 Marks
Total : 100 Marks
The objective of mini project is to develop in students the professional quality of synthesis employing technical
knowledge obtained in the field of Engineering & Technology through a project work involving design /
analysis augmented with creativity, innovation and ingenuity.
The student shall take up investigative study on a topic in the broad relevant field of engineering, involving
hardware or software or both hardware & software, to be assigned by the department on an individual basis,
under the guidance of a supervisor from the department. This is expected to provide a good initiation for the
student(s) in R&D work.
The activities under mini project may normally include:

1. Literature survey on an assigned topic.
2. Working out a preliminary approach to the problem relating to the assigned topic.
3. Conducting preliminary analysis/modelling/simulation/experiment/design.
4. Compilation of the work and presenting it in two seminar talks in the semester, before a committee having
M.Tech. coordinator and supervisor(s).
5. Submit a written spiral-bound report on the work undertaken to the M.Tech. Coordinator.
Internal evaluation of Mini Project will be done at the end of the semester through a seminar by the committee
consisting of the following:
1. Chairperson/Head of Department/ Nominee : Chairperson

2. M.Tech. Coordinator : Member-Secretary
3. Respective Project Supervisor(s) : Member(s)
Final exam. will be conducted by the internal examiner (M.Tech. Coordinator / faculty nominated by
Chairperson) and external examiner to be appointed by Controller of Examinations from a Panel of Examiners
submitted by the Dept.
M.Tech. coordinator will be assigned a load of 1 hour per week excluding his/ her own guiding load. Project
supervisor (guiding teacher) will be assigned a load of 1 hour per week per student subject to a maximum load
of 2 hours.

MTVLSI510C MEMORY TECHNOLOGIES
Semester – II

Total : 100 Marks
Course Objective: The objectives of this course are as under :
1. To select architecture and design semiconductor memory circuits and subsystems.
2. To identify various fault models, modes and mechanisms in semiconductor memories and their testing procedures.
3. To know how of the state-of-the-art memory chip design.
UNIT I
Random Access Memory Technologies: Static Random Access Memories (SRAMs), SRAM Cell Structures,
MOS SRAM Architecture, MOS SRAM Cell and Peripheral Circuit, Bipolar SRAM, Advanced SRAM
Architectures, Application Specific SRAMs.
UNIT II
DRAMs, MOS DRAM Cell, BiCMOS DRAM, Error Failures in DRAM, Advanced DRAM Design and
Architecture, Application Specific DRAMs.SRAM and DRAM Memory controllers. Non-Volatile Memories:
Masked ROMs, PROMs, Bipolar & CMOS PROM, EEPROMs, Floating Gate EPROM Cell, OTP EPROM,
EEPROMs, Non-volatile SRAM, Flash Memories.
UNIT III
Semiconductor Memory Reliability and Radiation Effects: General Reliability Issues, RAM Failure Modes and
Mechanism, Nonvolatile Memory, Radiation Effects, SEP, Radiation Hardening Techniques. Process and
Design Issues, Radiation Hardened Memory Characteristics, Radiation Hardness Assurance and Testing.
UNIT IV
Advanced Memory Technologies and High-density Memory Packing Technologies: Ferroelectric Random
Access Memories (FRAMs), Gallium Arsenide (GaAs) FRAMs, Analog Memories, Magneto Resistive Random
Access Memories (MRAMs), Experimental Memory Devices. Memory Hybrids (2D & 3D), Memory Stacks,
Memory Testing and Reliability Issues, Memory Cards, High Density Memory Packaging
Course Outcome: At the end of the course, students will be able to:
1. Select architecture and design semiconductor memory circuits and subsystems.
2. Identify various fault models, modes and mechanisms in semiconductor memories and their testing procedures.
3. Know how of the state-of-the-art memory chip design.
Reference Books:
1. Ashok K Sharma, “Advanced Semiconductor Memories”, IEEE Press, Wiley & Sons, 2009.
2. Jan M .Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits – A Design Perspective”, 2nd edition
Prentice Hall Publication, 2011
3. S. Kang & Y. Leblebici “CMOS Digital IC Circuit Analysis & Design”- McGraw Hill, 2003
4. Betty Prince, “Semiconductor Memories: A Handbook of Design, Manufacture and Application”, John Wiley & Sons Publication.
5. Kiyoo Itoh, “VLSI memory chip design”, Springer International Edition
6. Ashok K Sharma,” Semiconductor Memories: Technology, Testing and Reliability , PHI
NOTE:
are not allowed.

MTVLSI512 C SOC DESIGN
Semester – II

Total : 100 Marks
Course Objectives: The objectives of this course are as under:

1. To identify and formulate a given problem the framework of SoC based design approaches
2. To design SoC based system for engineering applications
3. To realize impact of SoC on electronic design philosophy and Macro-electronics thereby incline towards entrepreneurship & skill
development
UNIT I
ASIC-Overview of ASIC types, design strategies, CISC, RISC and NISC approaches for SOC architectural
issues and its impact on SoC design methodologies, Application Specific Instruction Processor (ASIP) concepts.
NISC-NISC Control Words methodology, NISC Applications and Advantages, Architecture Description
Languages (ADL) for design and verification of Application Specific Instruction set Processors (ASIP), No-
Instruction-Set-computer (NISC)- design flow, modeling NISC architectures and systems, use of Generic Netlist
Representation - A formal language for specification, compilation and synthesis of embedded processors.
UNIT II
Simulation-Different simulation modes, behavioral, functional, static timing, gate level, switch level, transistor/
circuit simulation, design of verification vectors, Low power FPGA, Reconfigurable systems, SoC related
modeling of data path design and control logic, Minimization of interconnects impact, clock tree design issues.
UNIT III
Low power SoC design / Digital system, Design synergy, Low power system perspective- power gating, clock
gating, adaptive voltage scaling (AVS), Static voltage scaling, Dynamic clock frequency and voltage scaling
(DCFS),building block optimization, building block memory, power down techniques, power consumption
verification.
UNIT IV
Synthesis-Role and Concept of graph theory and its relevance to synthesizable constructs, Walks, trails paths,
connectivity, components, mapping/visualization, nodal and admittance graph. Technology independent and
technology dependent approaches for synthesis, optimization constraints, Synthesis report analysis Single core
and Multi core systems, dark silicon issues, HDL coding techniques for minimization of power consumption,
Fault tolerant designs. Case study for overview of cellular phone design with emphasis on area optimization,
speed improvement and power minimization.
Course Outcomes: At the end of the course, students will be able

1. Identify and formulate a given problem in the framework of SoC based design approaches
2. Design SoC based system for engineering applications
3. Realize impact of SoC on electronic design philosophy and Macro-electronics thereby incline towards entrepreneurship & skill
development
References:
1. Hubert Kaeslin, “Digital Integrated Circuit Design: From VLSI Architectures to CMOS
Fabrication”, Cambridge University Press, 2008.
2. B. Al Hashimi, “System on chip-Next generation electronics”, The IET, 2006
3. RochitRajsuman, “System-on- a-chip: Design and test”, Advantest America R & D Center,
2000
4. P Mishra and N Dutt, “Processor Description Languages”, Morgan Kaufmann, 2008
5. Michael J. Flynn and Wayne Luk, “Computer System Design: System-on-Chip”. Wiley 2011
NOTE:
are not allowed.

MTVLSI514C LOW POWER VLSI DESIGN
Semester – II
Total : 100 Marks
1. To select a particular serial bus suitable for a particular application.
2. To develop APIs for configuration, reading and writing data onto serial bus.
3. To design and develop peripherals that can be interfaced to desired serial bus.
UNIT I
Technology & Circuit Design Levels: Sources of power dissipation in digital ICs, degree of freedom, recurring
themes in low-power, emerging low power approaches, dynamic dissipation in CMOS, effects of Vdd & Vt on
speed, constraints on Vt reduction, transistor sizing & optimal gate oxide thickness, impact of technology
scaling, technology innovations.
UNIT II
Low Power Circuit Techniques: Power consumption in circuits, flip-flops & latches, high capacitance nodes,
energy recovery, reversible pipelines, high performance approaches.
Low Power Clock Distribution: Power dissipation in clock distribution, single driver versus distributed
buffers, buffers & device sizing under process variations, zero skew Vs. tolerable skew, chip & package co-
design of clock network.
UNIT III
Logic Synthesis for Low Power estimation techniques: Power minimization techniques, low power arithmetic
components- circuit design styles, adders, multipliers.
UNIT IV
Low Power Memory Design: Sources & reduction of power dissipation in memory subsystem, sources of
power dissipation in DRAM & SRAM, low power DRAM circuits, low power SRAM circuits.
Low Power Microprocessor Design System: power management support, architectural trade offs for power,
choosing the supply voltage, low-power clocking, implementation problem for low power, comparison of
microprocessors for power & performance.
1. Select a particular serial bus suitable for a particular application.
2. Develop APIs for configuration, reading and writing data onto serial bus.
3. Design and develop peripherals that can be interfaced to desired serial bus.
Reference Books:
1. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002
2. Rabaey, Pedram, “Low power design methodologies” Kluwer Academic, 1997
3. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley, 2000
4. A.P.Chandrasekaran and R.W.Broadersen, “Low power digital CMOS design”,Kluwer,1995
5. J.B.Kulo and J.H Lou, “Low voltage CMOS VLSI Circuits”, Wiley, 1999.
6. P. Rashinkar, Paterson and L. Singh, “Low Power Design Methodologies”, Kluwer Academic, 2002
NOTE:
are not allowed.

MTVLSI516C COMPUTATIONAL INTELLIGENT TECHNIQUES FOR VLSI
DESIGN
Semester – II
L T P Credit Class Work : 25 Marks

3- - 3 Theory : 75 Marks
Total :100 Marks
1. To study computational intelligent techniques for VLSI design.
2. To study interpolation and numerical integration technique.
3. To solve linear and non-linear equations.
UNIT I
Functions of a complex variable:
Limit continuity and differentiability. Analytical functions, Cauchy-Riemann equations, Cauchy integral
theorem, singularities Taylor’s and Laurent Series, Conformal mapping.
Roots Finding for Non Linear equation:
Functions and Polynomials, Zeros of a function, Roots of a nonlinear equation, Bracketing, Bisection and
Newton-Raphson Methods, Polynomial fits.
UNIT II
Interpolation:
Newton’s (Newton-Gregory) Forwarded Difference (FD) Formula and Backward Difference (BD) Formula,
Lagrange’s divided differences and Newton’s Divided Formula.
Numerical Integration:
Evaluation of Integrals, Elementary Analytical Methods, Trapezoidal and Simpson’s Rules, Gaussian
Quadrature, and orthogonal polynomials, Multidimensional Integrals, Numerical differentiation and Estimation
of errors.
UNIT III
Numerical Solution of Linear equation:
Vectors and Matrices, Solutions of linear algebraic equations by direct and iterative methods, Gaussian
elimination, LU, Cholesky and singular value decompositions, Matrix diagonalization methods.
UNIT IV
Numerical Methods for ordinary differential equation:
Solution of initial-value problems of systems of ODEs, Single step and multistep methods, convergence. Finite
difference methods for the solution of two-point boundary-value problem.
1. Study computational intelligent techniques for VLSI design.
2. Study interpolation and numerical integration technique.
3. Solve linear and non-linear equations.
References Books:
1. Murray R Spiegel, “Theory and Problems of Complex Variables”, Schaum’s Outline Series, New York, 1964.
2. Conte, S. D. de Boore, C. “Elementary Numerical Analysis” McGraw Hill, 1980.
3. PradipNiyogi, “Numerical Analysis & Algorithms”, TMH, 2003
4. Kreyszig, E, “Advanced Engineering Mathematics”, John Wiley & Sons, 8 th Edition, 2002
5. Radhey S Gupta, “Elements of Numerical Analysis”, Macmillan, 2009.
6. Brian Bradie, “A Friendly Introduction to Numerical Analysis” Pearson, 2008
7. Chapra, S. C, Canale R P, “Numerical Methods for Engineers”, 3rd Ed., McGraw-Hill 1998
NOTE:
are not allowed.

MTVLSI518C VLSI FOR OPTICAL INTERCONNECTS
Semester – II

Total : 100 Marks
Course Objective:
1. To develop understanding of basic concepts of optical communication and devices
2. To study design of transimpedance amplifiers and limiting amplifiers.
3. To study design of oscillators and various device drivers
4. To furnish clear understanding and distinction of electrical and optical interconnects
UNIT I
Basic Concepts: Introduction to Optical Communication, Properties of Random Binary data and its generation,
Data formats, Effect of Bandwidth limitation on Random data.
Optical Devices: Laser diodes: Operation of lasers, types of lasers, optical fibers loss and dispersion,
photodiodes: Responsivity and efficiency, PIN diodes, Avalanche diode.
UNIT II
Trans-impedance Amplifiers: General considerations: TIA performance parameters, SNR calculation and
noise bandwidth, open loop TIA, feedback TIA.
Limiting amplifier/ output buffer: General considerations: Performance parameters, cascaded gain stages,
AM/PM conversion, broadband technique: inductive peaking, output buffers.
UNIT III
Oscillator: General considerations, ring oscillator, LC oscillators, voltage controlled oscillator.
Multiplexer and Laser driver: Multiplexers (2:1 mux, mux architecture, Laser and Modulator drivers:
performance parameters.
UNIT IV
Optical vs Electrical Interconnects: Electrical Interconnects, Optical interconnects, comparison, optical
interconnects in system.
Course Outcome:
After going through this course the student will be able to
1. Develop knowledge of VLSI design impact on optical interconnects.

2. Design transimpedance and limiting amplifiers
3. Design oscillators and various device drivers
4. Distinguish optical and electrical interconnects features and design.
Text Books:
1. Behzad Razavi, “Design of Integrated circuits for optical communication”, McGraw-Hill, 1st Edition, 2002.
2. Hartmut Grabinski, “Interconnects in VLSI Design”, Springer, 2012.
Reference Books:
1. Ibrahim Gokce Yayla, “Speed and energy comparison between electrical and electro-optical interconnects and application to
optoelectronic computing”, University of California, San Diego, 1996.
2. Pascal Berthome, “Optical Interconnections and Parallel Processing: Trends at the Interface”, Springer, 2010.
3. Sadik Esener and Philippe Marchand, “Present and Future Needs of Free-Space Optical Interconnects”, Springer.
NOTE:
are not allowed.

MTVLSI520C COMMUNICATION BUSES AND INTERFACES
Semester – II
Total : 100 Marks
Course Objectives: The objectives of this course are as under

1. To introduce the communication busses and interfacing
2. To study various types of protocol
3. To learn about serial, parallel and USB port
4. To design and develop peripheral that can interface
UNIT I
Serial Busses Physical interface, Data and Control signals, features, limitations and applications of RS232,
RS485, I2C, SPI.
UNIT II
CAN - Architecture, Data transmission, Layers, Frame formats, applications, PCIe - Revisions, Configuration
space, Hardware protocols, applications
UNIT III
USB - Transfer types, enumeration, Descriptor types and contents, Device driver
UNIT IV
Data Streaming Serial Communication Protocol- Serial Front Panel Data Port (SFPDP) using fibre optic and
copper cable.
1. Introduce the communication busses and interfacing
2. Study various types of protocol
3. Learn about serial, parallel and USB port
4. Design and develop peripheral that can interface
Reference Books:
1. Jan Axelson, “Serial Port Complete - COM Ports, USB Virtual Com Ports, and Ports for Embedded Systems ”, Lakeview
Research, 2nd Edition
2. Jan Axelson, “USB Complete”, Penram Publications
3. Mike Jackson, Ravi Budruk, “PCI Express Technology”, Mindshare Press
4. Wilfried Voss, “A Comprehensible Guide to Controller Area Network”, Copperhill Media Corporation, 2nd Edition, 2005.
5. Serial Front Panel Draft Standard VITA 17.1 – 200x
6. Technical references on www.can-cia.org, www.pcisig.com, www.usb.org
NOTE:
are not allowed.

MTVLSI522C NETWORK SECURITY AND CRYPTOGRAPHY
Semester – II
Total : 100 Marks

1. To identify and utilize different forms of cryptography techniques.
2. To incorporate authentication and security in the network applications.
3. To distinguish among different types of threats to the system and handle the same.
Unit 1
Security- Need, security services, Attacks, OSI Security Architecture, one time passwords, Model for Network
security, Classical Encryption Techniques like substitution ciphers, Transposition ciphers, Cryptanalysis of
Classical Encryption Techniques.
Number Theory- Introduction, Fermat’s and Euler’s Theorem, The Chinese Remainder Theorem, Euclidean
Algorithm, Extended Euclidean Algorithm, and Modular Arithmetic.
Unit 2
Private-Key (Symmetric) Cryptography- Block Ciphers, Stream Ciphers, RC4 Stream cipher, Data
Encryption Standard (DES), Advanced Encryption Standard (AES), Triple DES, RC5, IDEA, Linear and
Differential Cryptanalysis.
Unit 3
Public-Key (Asymmetric) Cryptography- RSA, Key Distribution and Management,Diffie-Hellman Key
Exchange, Elliptic Curve Cryptography, Message Authentication Code, hash functions, message digest
algorithms: MD4 MD5, Secure Hash algorithm, RIPEMD-160, HMAC.
Unit 4
Authentication- IP and Web Security Digital Signatures, Digital Signature Standards, Authentication Protocols,
Kerberos, IP security Architecture, Encapsulating Security Payload, Key Management, Web Security
Considerations, Secure Socket Layer and Transport Layer Security, Secure Electronic Transaction.
System Security- Intruders, Intrusion Detection, Password Management, Worms, viruses, Trojans, Virus
Countermeasures, Firewalls, Firewall Design Principles, Trusted Systems.

1. Identify and utilize different forms of cryptography techniques.
2. Incorporate authentication and security in the network applications.
3. Distinguish among different types of threats to the system and handle the same.
References:
1. William Stallings, “Cryptography and Network Security, Principles and Practices”, Pearson Education, 3rd Edition.
2. Charlie Kaufman, Radia Perlman and Mike Speciner, “Network Security, Private Communication in a Public World”, Prentice Hall, 2nd
Edition
3. Christopher M. King, ErtemOsmanoglu, Curtis Dalton, “Security Architecture, Design Deployment and Operations”, RSA Pres,
4. Stephen Northcutt, LenyZeltser, Scott Winters, Karen Kent, and Ronald W. Ritchey, “Inside Network Perimeter Security”, Pearson
Education, 2nd Edition
5.Richard Bejtlich, “The Practice of Network Security Monitoring: Understanding Incident
NOTE:
are not allowed.

MTVLSI524C PHYSICAL DESIGN AUTOMATION
Semester – II
Total : 100 Marks
Course Objective: The objectives of the course are as under:

1. To study automation process for VLSI System design.
2. To demonstrate knowledge of computational and optimization algorithms of various routing.
3. To study various type of compaction and via minimization.
4. To develop and enhance the existing algorithms and computational techniques for physical design process of VLSI systems.
UNIT I
Logic synthesis & verification:
Introduction to combinational logic synthesis, Binary Decision Diagram, Hardware models for High-level
synthesis.
Partitioning: problem formulation, cost function and constraints, classification of partitioning algorithms,
Group migration algorithms, simulated annealing & evolution, other partitioning algorithms.
UNIT II
Floor planning & pin assignment: Floor planning model and cost function, Classification of Floor planning,
constraint based floor planning, Integer Programming Based Floor planning, floor planning algorithms for
mixed block & cell design. General & channel pin assignment.
Placement: problem formulation, cost function and constraints, simulation base placement algorithms,
Partitioning Based Placement Algorithms, other placement algorithms,
UNIT III
Global Routing: Grid Routing and Global routing, Problem formulation, cost function and constraints,
classification of global routing algorithms, routing regions, sequential global routing, Maze routing algorithm,
line probe algorithm, Steiner Tree based algorithms, Integer Programming Based Approach, Hierarchical Global
Routing, Global Routing by Simulated Annealing
Detailed routing: problem formulation, cost function and constraints, classification of routing algorithms,
single layer routing algorithms, two layer channel routing algorithms, three layer channel routing algorithms,
and switchbox routing algorithms.
UNIT IV
Over the cell routing & via minimization: Over-the-cell Routing: Cell Models, two layers over the cell
routers, Three-Layer Over-the-cell Routing, constrained & unconstrained via minimization.
Compaction: problem formulation, Classification of Compaction Algorithms one-dimensional compaction, two
dimension based compaction, hierarchical compaction.
Course Outcomes: At the end of this course, student will be able to
1. Study automation process for VLSI System design.
2. Demonstrate knowledge of computational and optimization algorithms of various routing.
3. Study various types of compaction and via minimization.
4. Develop and enhance the existing algorithms and computational techniques for physical design process of VLSI systems
Reference Books:
1. Naveed Shervani, “Algorithms for VLSI physical design Automation”, Kluwer Academic Publisher, Second edition.
2. Christophn Meinel & Thorsten Theobold, “Algorithm and Data Structures for VLSI Design”, KAP, 2002.
3. Rolf Drechsheler : “Evolutionary Algorithm for VLSI”, Second edition.
4. Trimburger,” Introduction to CAD for VLSI”, Kluwer Academic publisher, 2002
NOTE:
are not allowed.

MTVLSI526C HARDWARE SOFTWARE CO-DESIGN
Semester – II
Total : 100 Marks
Course Objective: The objectives of the course are as under:
1. To understand system design consideration, Hardware software background.
2. To study Hardware Software partitions, alterations, and trade-offs.
3. To learn methodology for hardware software co-design.
4. To performance evaluation of hardware software co-design.
UNIT I
Introduction: Motivation hardware & software co-design, system design consideration, research scope &
overviews. Hardware Software back ground: Embedded systems, models of design representation, the virtual
machine hierarchy, the performance modeling, Hardware Software development.
UNIT II
Hardware Software co-design research: An informal view of co-design, Hardware Software tradeoffs, crosses
fertilization, typical co-design process, co-design environments, limitation of existing approaches, ADEPT
modeling environment. Co-design concepts: Functions, functional decomposition, virtual machines, Hardware
Software partitioning, Hardware Software partitions, Hardware Software alterations, Hardware Software trade-
offs, co-design.
UNIT III
Methodology for co-design: Amount of unification, general consideration & basic philosophies, a framework
for co-design. Unified representation for Hardware & Software: Benefits of unified representation, modeling
concepts. An abstract Hardware & Software model : Requirement & applications of the models, models of
Hardware Software system, an abstract Hardware Software models, generality of the model.
UNIT IV
Performance evaluation: Application of the abstract Hardware & Software model, examples of performance
evaluation. Object oriented techniques in hardware design: Motivation for object oriented technique, data types,
modelling hardware components as classes, designing specialized components, data decomposition, Processor
example.
Course Outcomes: At the end of the course the student will be able to:
1. Understand system design consideration, Hardware software background.
2. Study Hardware Software partitions, alterations, and trade-offs.
3. Learn methodology for hardware software co-design.
4. Performance evaluation of hardware software co-design.
Reference Books:
1. R. Gupta, Co-synthesis of Hardware and Software for Embedded Systems, Kluwer 1995.
2. S. Allworth, Introduction to Real-time Software Design, Springer-Verlag, 1984.
3. Peter Marwedel, G. Goosens, Code Generation for Embedded Processors, Kluwer Academic Publishers, 1995.
4. Sanjaya Kumar, James H. Ayler “The Co-design of Embedded Systems: A Unified Hardware Software Representation”, Kluwer
Academic Publisher, 2002.
5. H. Kopetz, Real-time Systems, Kluwer, 1997.
NOTE:
are not allowed.

MTVLSI528C OPTIMIZATION FOR VLSI DESIGN
Semester – II
Total : 100 Marks

1. To understand the tradeoffs among various design parameters of any system.
2. To learn how to frame the objective of a problem?
3. To learn the implementation issues for any design using optimization techniques.
4. To understand concept of design optimization algorithms and their application to physical design.
5. To understand the latest soft computing techniques as practiced in the Industry for design layout optimization.
UNIT I
Introduction: Operation Research Models, OR Model, Queuing & Simulation Models, Two Variable LP
Model, Graphical LP solution, Computer Solution with solver & AMPL, Linear Programming Applications.
Sensitivity & Post Optimal Analysis: LP Model in Equation Form, Algebraic Solution, Simplex Method,
Artificial Starting Solution, Sensitivity Analysis, Dual Problem, Primal-Dual Relationships, Economic
Interpretation of Duality, Additional Simplex Algorithms, Post Optimal Analysis.
UNIT II
Models: Transportation Models and its variants, Transportation Algorithms, Assignment Models, Shortest
Route Problem and its Algorithms, Maximal Flow Model, CPM & PERT.
Simulation Modeling: Monte Carlo Simulation, Type of Simulations, Unconstrained Problems, Constrained
Problems, Direct Search Method, Gradient Method, Separable, Quadratic.
UNIT III
Intelligent Optimization Techniques: Introduction to Intelligent Optimization, Soft Computing,Genetic
Algorithm: Types of reproduction operators, crossover & mutation, Simulated Annealing Algorithm, Particle
Swarm Optimization (PSO) - Graph Grammar Approach – Example Problems.
UNIT IV
Genetic Programming (GP): Principles of genetic programming, terminal sets, functional sets, differences
between GA & GP, random population generation, solving differential equations using GP.
1. Understand the tradeoffs among various design parameters of any system.
2. Learn how to frame the objective of a problem?
3. Learn the implementation issues for any design using optimization techniques.
4. Understand concept of design optimization algorithms and their application to physical design.
5. Understand the latest soft computing techniques as practiced in the Industry for design layout optimization.
Reference Books:
1. Operation Research By Taha – Pearson
2. Probability & Statistics with Reliability, Queuing & Computer Serine Application- Kishor S. Trivedi – Willey
3. Operation Research By Taha – Pearson
4. Probability & Statistics with Reliability, Queuing & Computer Serine Application- Kishor S. Trivedi – Willey
5. D. E. Goldberg, “Genetic algorithms in Search, Optimization, and Machine learning”,Addison-Wesley Longman Publishing, 1989.
NOTE:
are not allowed.

MTVLSI611C COMMUNICATION NETWORKS
Semester – III

Total : 100 Marks
1. To analyze protocols and algorithms, acknowledge tradeoffs and rationale
2. To study how to use routing, transport protocols for the given networking scenario and application
3. To evaluate and develop small network applications
.
UNIT I
Introduction: Network Architecture, Performance.

Connecting nodes: Connecting links, Encoding, framing, Reliable transmission, Ethernet and Multiple access
networks, Wireless networks.
UNIT II
Queuing models: For a) one or more servers b) with infinite and finite queue size c) Infinite population
Internetworking: Switching and bridging, IPv4, Addressing, Routing Protocols, Scale issues, Routers
Architecture, IPv6
End-to-End Protocols: Services, Multiplexing, De-multiplexing, UDP, TCP, RPC, RTP.
UNIT III
Congestion control and Resource Allocation: Issues, Queuing disciplines, TCP congestion control,Congestion
avoidance, QoS Applications: - Domain Name Resolution, File Transfer, Electronic Mail, WWW, Multimedia
Applications.
UNIT IV
Network monitoring: Packet sniffing tools such as Wireshark Simulations using NS2/OPNET.
1. Analyze protocols and algorithms, acknowledge tradeoffs and rationale
2. Use routing, transport protocols for the given networking scenario and application
3. Evaluate and develop small network applications
Reference Books:
1. Larry L. Peterson, Bruce S, Devie, “Computer Networks” , MK, 5th Edition
2. Aaron Kershenbaum, “Telecommunication Network Design Algorithms”, MGH, International Edition 1993.
3. Vijay Ahuja, “Communications Network Design and Analysis of Computer Communication Networks”, MGH, International
Editions.
4. Douglas E. Comer, “Internetworking with TCP/IP”, Pearson Education, 6th Edition
NOTE:
are not allowed.

MTVLSI613 C SELECTED TOPICS IN MATHEMATICS
Semester – III

Total : 100 Marks

1. To characterize and represent data collected from experiments using statistical methods.
2. To model physical process/systems with multiple variables.
3. To represent systems/architectures using graphs and trees towards optimizing desired objective.
UNIT I
Probability and Statistics: Definitions, conditional probability, Bayes Theorem and independence.
Random Variables: Discrete, continuous and mixed random variables, probability mass, Probability density and
cumulative distribution functions, mathematical expectation, moments, moment generating function, Chebyshev
inequality.
UNIT II
Special Distributions: Discrete uniform, Binomial, Geometric, Poisson, Exponential, Gamma, Normal
distributions Pseudo random sequence generation with given distribution, Functions of a Random
Variable.
Joint Distributions: Joint, marginal and conditional distributions, product moments, correlation, independence
of random variables, bi-variate normal distribution.
Stochastic Processes: Definition and classification of stochastic processes, Poisson process Norms, Statistical
methods for ranking data
UNIT III
Multivariate Data Analysis: Linear and non-linear models, Regression, Prediction and Estimation, Design of
Experiments : factorial method , Response surface method.
UNIT IV
Graphs and Trees:
Graphs: Basic terminology, multi graphs and weighted graphs, paths and circuits, shortest path
Problems, Euler and Hamiltonian paths and circuits, factors of a graph, planar graph and Kuratowski’s graph
and theorem, independent sets, graph colouring
Trees: Rooted trees, path length in rooted trees, binary search trees, spanning trees and cut Set theorems on
spanning trees, cut sets , circuits, minimal spanning trees, Kruskal’s and Prim’s algorithms for minimal spanning
tree
1. Characterize and represent data collected from experiments using statistical methods.
2. Model physical process/systems with multiple variables towards parameter estimation and prediction
3. Represent systems/architectures using graphs and trees towards optimizing desired objective.
Reference Books:
1. Henry Stark, John W. Woods, “Probability and Random Process with Applications to Signal Processing”, Pearson Education, 3rd
Edition
2. C. L. Liu, “Elements of Discrete Mathematics”, Tata McGraw-Hill, 2nd Edition
3. Douglas C. Montgomery, E.A. Peck and G. G. Vining, “Introduction to Linear Regression Analysis”, John Wiley and Sons, 2001
4. Douglas C. Montgomery, “Design and Analysis of Experiments”, John Wiley and Sons, 2001.
5. B. A. Ogunnaike, “Random Phenomena: Fundamentals of Probability and Statistics for Engineers”, CRC Press, 2010.
NOTE:
are not allowed.

MTVLSI615C NANOMATERIALS AND NANOTECHNOLOGY
Semester – III
Total : 100 Marks

1. To understand the basic science behind the design and fabrication of nano scale systems.
2. To understand and formulate new engineering solutions..
3. To be able make inter disciplinary projects applicable to wide areas by clearing and fixing the boundaries in system development.
4. To gather detailed knowledge of the operation of fabrication and characterisation devices to achieve precisely designed systems.
UNIT I
Nano-materials in one and higher dimensions, Applications of one and higher dimension nano-materials.
UNIT II
Nano-lithography, micro electro-mechanical system (MEMS) and nano-phonics.
UNIT III
Carbon Nanotubes : Synthesis and applications.
UNIT IV
Inter-disciplinary arena of nanotechnology.
1. Understand the basic science behind the design and fabrication of nano scale systems.
2. Understand and formulate new engineering solutions for current problems and competing technologies for future applications.
3. Make inter disciplinary projects applicable to wide areas by clearing and fixing the boundaries in system development.
4. Gather detailed knowledge of the operation of fabrication and characterisation devices to achieve precisely designed systems.
Reference Books:
1. Nanoscale Materials in Chemistry edited by Kenneth J. Klabunde and Ryan M. Richards, 2ndedn, John Wiley and Sons, 2009.
2. Nanocrystalline Materials by A I Gusev and A ARempel, Cambridge International
3. Science Publishing, 1st Indian edition by Viva Books Pvt. Ltd. 2008. Springer Handbook of Nanotechnology by Bharat Bhushan,
Springer, 3rdedn, 2010.
4. Carbon Nanotubes: Synthesis, Characterization and Applications by Kamal K. Kar, Research Publishing Services; 1stedn, 2011,
ISBN-13: 978-9810863975.
NOTE:
are not allowed.

MTVLSI617C CMOS RF IC DESIGN
Semester – III
Total : 100 Marks
1. Designing CMOS RF circuits to achieve performance specifications.
2. Exposure to RF circuit design techniques in integrated context.
3. Learn to design VCO, LNA, Power Amplifier building blocks.
4. Learn to design RF synthesizers, transceivers.
UNIT I
Introduction: Basic concepts in RF design: Nonlinearly and Time Variance, Intersymbol interference, random
processes and noise. Sensitivity and dynamic range, conversion of gains and distortion.
Modulation and Detection: Analog and digital modulation of RF circuits, Comparison of various techniques
for power efficiency, Coherent and non-coherent detection.
UNIT II
RF transceivers: Receiver Architectures: Heterodyne Receiver, homodyne Receiver, Image-reject Receiver,
Digital-IF Receiver, Sub sampling Receiver, RF Transmitters: Transmitter Architecture: direct-conversion
Transmitters, Two-step Transmitters.
RF Transistors: BJT and MOSFET Behavior at RF Frequencies Modeling of the transistors and SPICE model,
Noise performance and limitations of devices, integrated parasitic elements at high frequencies.
UNIT III
RF circuits Design: Low noise Amplifier design in various technologies, Design of Mixers at GHz frequency
range, various mixers- working and implementation.
RF Oscillators: Basic LC Oscillators topologies, VCO, phase noise: effect, Mechanisms, Noise power and
trade off, Bipolar and CMOS LC Oscillator designs, Quadrature signal and single sideband generators.
UNIT IV
RF Synthesizers: General Considerations, Phase-locked Loops: basic concept, Types of PLLs, Noise in PLLs ,
Various RF Synthesizer Architectures and Frequency Dividers.
RF Power Amplifier: General Considerations, Classification of Power Amplifiers, high frequency Power
Amplifiers, Liberalization techniques.
1. Design CMOS RF circuits to achieve performance specifications.
2. Design RF circuit techniques in integrated context.
3. Design VCO, LNA, Power Amplifier building blocks.
4. Design RF synthesizers, transceivers.
.
Text Books:
1. Behzad Razavi, “RF Microelectronics”, Pearson Education.
2. Reinhold Ludwig, Paul Bretchko,“RF Circuit Design: Theory & Applications ”.
Reference Books
1. Thomas.H. Lee, “The design of CMOS Radio-Frequency Integrated Circuits”, Cambridge University Press, 2nd Edition, 2004.
NOTE:
1. In the semester examination, the examiner will set 08 questions in all selecting two from each unit. The candidates will be
required to attempt five questions in all selecting at least one from each unit. All questions will carry equal marks.
2. The students will be allowed to use non-programmable scientific calculator. However, sharing/exchange of calculator is
prohibited in the examination.

MTVLSI619C MIXED SIGNAL IC DESIGN
Semester – III
Total : 100 Marks

1. Designing CMOS mixed signal circuits to achieve performance specifications.
2. Exposure to analog and digital circuit design techniques in integrated context.
3. Learn to design mixed-signal building blocks including comparators and data converters.
4. Analyzing CMOS based switched capacitor circuits.
UNIT I
PLL: Characterization of a comparator, basic CMOS comparator design, analog multiplier design, PLL - simple
PLL, charge-pump PLL, applications of PLL.
Switched Capacitor Circuits: Switched Capacitor circuits - basic principles, some practical circuits such as
switched capacitor integrator, biquad circuit, switched capacitor filter, switched capacitor amplifier, non-
filtering applications of switched capacitor circuit such as programmable gate arrays, DAC and ADC, MOS
comparators, modulators, rectifiers, detectors, oscillators.
UNIT II
Sampling Circuits: Sampling circuits: Basic sampling circuits for analog signal sampling, performance metrics
of sampling circuits, different types of sampling switches. Sample-and-Hold Architectures: Open-loop &
closed-loop architectures, open-loop architecture with miller capacitance, multiplexed-input architectures,
recycling architecture, switched capacitor architecture, current-mode architecture.
DAC: Input/output characteristics of an ideal D/A converter, performance metrics of D/A converter, D/A
converter in terms of voltage, current, and charge division or multiplication, switching functions to generate an
analog output corresponding to a digital input. D/A converter architectures: Resistor-Ladder architectures,
current-steering architectures.
UNIT III
ADC: Input/output characteristics and quantization error of an A/D converter, performance metrics of A/D
converter. A/D converter architectures: Flash architectures, two-step architectures, interpolate and folding
architectures, pipelined architectures, Successive approximation architectures, interleaved architectures.
Filters: Low Pass filters, active RC integrators, MOSFET-C integrators, transconductance-C integrator,
discrete time integrators. Filtering topologies - bilinear transfer function and biquadratic transfer function.
UNIT IV
Data Converter SNR: Quantization Noise, Signal to Noise Ratio, improving SNR by using Averaging and
Feedback.
Mixed-Signal Layout Issues: Floor planning, Power Supply and Ground Issues, Fully Differential Design,
Guard Rings, Shielding, Other Interconnect Considerations.
1. Designing CMOS mixed signal circuits to achieve performance specifications.
2. Exposure to analog and digital circuit design techniques in integrated context.
3. Learn to design mixed-signal building blocks including comparators and data converters.
4. Analyzing CMOS based switched capacitor circuits.
Text Books:
1. Razavi, "Design of analog CMOS integrated circuits", McGraw Hill, 2001
2. Razavi, "Principles of data conversion system design", S.Chand and company ltd, 2000
Reference Books
1. Jacob Baker, "CMOS Mixed-Signal circuit design", IEEE Press, 2002
2. Gregorian, Temes, "Analog MOS Integrated Circuit for signal processing", John Wiley & Sons
3. Baker, Li, Boyce, "CMOS : Circuit Design, layout and Simulation", PHI, 2000
NOTE:
are not allowed.
th
Approved in the 13 meeting of academic council held on 18/6/2018.
MTVLSI651C DISSERTATION (PHASE-I)
Semester – III
- - 20 10 Exams : 100
Total : 150 Marks
Course Objectives:
1. The objective of Dissertation Phase 1 is to teach students literature survey.

2. Literature review in a particular subject area will be taught.
3. The purpose of literature review is to summarize and synthesize the ideas of others.
4. The students are able to identify their problem and find a suitable software tool to work on.
The objective of this course is to develop in students the capacity for analysis & judgment and the ability to
carry out independent investigation in design/development through a dissertation work involving creativity,
innovation and ingenuity. The work should start with comprehensive literature search and critical appreciation
thereof so as to select a research problem and finalize the topic of dissertation.
Each student will carry out an independent dissertation under the supervision of a supervisor; in no case, more
than two supervisors may be associated with one dissertation work. The first supervisor must be from the
department, however, for interdisciplinary research work,the second supervisor may be from other department
of the university/ outside university/industry. In the latter case, consent of the second supervisor with
justification thereof needs to be submitted to the dissertation coordinator.
The Dissertation (Phase-I) involving literature survey and problem formulation along with data collection (if
required) commences in 3rd semester &will be completed as Dissertation (Phase-II) in 4th semester. Each
student will be required to present two seminar talks, first towards the beginning of the Dissertation (Phase-I) to
present the scope of the work and to finalize the topic, and the second towards the end of the semester,
presenting the progress report containing literature survey, partial results (if any) of the work carried out by
him/her in the semester.The student will be required to submit one copy of spiral-bound progress report to the
M.Tech. Coordinator.
Internal evaluation of Dissertation (Phase-I) will be done by following committee:
1. Chairperson / Head of Department / Nominee : Chairperson

2. M.Tech. Coordinator/Senior Faculty : Member-Secretary
3. Respective Dissertation Supervisor(s) : Member(s)
Final exam will be conducted by the internal examiner (M.Tech. Coordinator/ faculty nominated by
Chairperson) &an external examiner to be appointed by Controller of Examinations from a panel of examiners
submitted by the Dept.
For this course, M. Tech. coordinator will be assigned a load of 1 hour per week excluding his/ her own guiding
load. Dissertation supervisor (guiding teacher) will be assigned a load of 1 hour per week for the first student
and additional 1 hour per week (for their own department only) for the subsequent student(s) subject to a
maximum load of 2 hours. Work load allocated for the joint supervision within the department will be treated as
half for each supervisor.
Course Outcome:
1. Students can now write the introduction section that describes the topic of the review, Body section which contains the
discussion of sources, Conclusions from the discussion of sources and recommendations (if any).
2. They can confidently highlight the main point in the conclusion of the literature review which would be the clarification and
emphasis of the gaps (unexplored/unsolved problem in the field).
3. They develop ability to write a review paper.
4. They are also apprised of various reputed journals in the field.

.
OPEN ELECTIVES
MTOE651C: BUSINESS ANALYTICS
M. Tech. Semester – III (Common for all Branches)
3 -- 3 Examination : 75 Marks
Total : 100 Marks
Course Objectives:
The main objective of this course is to give the student a comprehensive understanding of business analytics
methods
1.
Understand the role of business analytics within an organization.
2.
Business Analytics industry sequence is to familiarize the students with the concept of Data Analytics
(Big Data) and its applicability in a business environment
3. Analyze data using statistical and data mining techniques and understand relationships between the
underlying business processes of an organization.
4. To gain an understanding of how managers use business analytics to formulate and solve business
problems and to support managerial decision making.
5. To become familiar with processes needed to develop, report, and analyze business data.
6. Use decision-making tools/Operations research techniques.
7. Mange business process using analytical and management tools.
Analyze and solve problems from different industries such as manufacturing, service, retail, software, banking
and finance, sports, pharmaceutical, aerospace etc
Course Outcomes:
1. At the end of the Fall semester, students should have acquired an understanding of Analytics – the
terminology, concepts and familiarity of potential tools and solutions that exist today Students will
demonstrate knowledge of data analytics.
2. Students will demonstrate the ability of think critically in making decisions based on dataand deep
analytics
3. Students will demonstrate the ability to use technical skills in predicative and prescriptivemodeling to
support business decision-making
4. Students will demonstrate the ability to translate data into clear, actionable insights. student should
be better familiar with overall analytics tools/techniques and their use in corporate
Syllabus contents:
UNIT I: Business analytics: Overview of Business analytics, Scope of Business, analytics, Business
Analytics Process, Relationship of Business Analytics, Process and organisation, competitive
advantages of Business Analytics. Statistical Tools: Statistical Notation, Descriptive Statistical
methods, Review of probability distribution and data modelling, sampling and estimation
methods overview.
UNIT II: Trendiness and Regression Analysis: Modelling Relationships and Trends in Data, simple
Linear Regression, Important Resources, Business Analytics Personnel, Data and models for
Business analytics, problem solving, Visualizing and Exploring Data, Business Analytics
Technology.
UNIT III: Organization Structures of Business analytics, Team management, Management Issues,
Designing Information Policy, Outsourcing, Ensuring Data Quality, Measuring contribution
of Business analytics, Managing Changes. Descriptive Analytics, predictive analytics,
predicative Modelling, Predictive analytics analysis, Data Mining, Data Mining
Methodologies, Prescriptive analytics and its step in the business analytics Process,
Prescriptive Modelling, nonlinear Optimization.
UNIT IV: Decision Analysis: Formulating Decision Problems, Decision Strategies, with the without
Outcome Probabilities, Decision Trees, the Value of Information, Utility and Decision
Making. Forecasting Techniques: Qualitative and Judgmental Forecasting, Statistical
Forecasting Models, Forecasting Models for Stationary Time.
1. Project Management: The Managerial Process by Erik Larson and, Clifford Gray
2. Business Analysis by James Cadle et al.
3. Bajpai Naval, Business Statistics, Pearson, New Delhi.
4. Whigham David, Business Data Analysis, Oxford University, Press, Delhi.
5. Predictive Analytics: The Power to Predict Who Will Click, Buy, Lie or Die. Eric Siegel.
6. Big Data, Analytics and the Future of Marketing and Sales. McKinsey.
NOTE:

MTOE653C: INDUSTRIAL SAFETY
Total : 100 Marks
Course Objectives:
Course Outcomes:
Syllabus contents:
UNIT I: Industrial safety: Accident, causes, types, results and control, mechanical and electrical
hazards, types, causes and preventive steps/procedure, describe the salient points of factories
act 1948 for health and safety, washrooms, drinking water layouts, light, cleanliness, fire,
guarding, pressure vessels, etc., Safety color codes. Fire prevention and firefighting,
equipment and methods.
Fundamentals of maintenance engineering: Definition and aim of maintenance engineering,

Primary and secondary functions and responsibility of the maintenance department, Types of
maintenance, Types and applications of tools used for maintenance, Maintenance cost & its
relation to replacement economy, Service life of the equipment.
UNIT II: Wear and Corrosion and their prevention: Wear- types, causes, effects, wear reduction
methods, lubricants-types and applications, Lubrication methods, general sketch, working and
applications, (i). Screw down grease cup, (ii). Pressure grease gun, (iii). Splash lubrication,
(iv). Gravity lubrication, (v). Wick feed lubrication (vi). Side feed lubrication, (vii). Ring
lubrication, Definition, principle and factors affecting the corrosion. Types of corrosion,
corrosion prevention methods.
UNIT III: Fault Tracing: Fault tracing-concept and importance, decision tree concept, need and
applications, sequence of fault finding activities, show as decision tree, draw decision trees for
problems in machine tools, hydraulic, pneumatic, automotive, thermal and electrical
equipment’s like, (i). Any one machine tool, (ii). Pump (iii). Air compressor, (iv). Internal
combustion engine, (v). Boiler, (vi). Electrical motors, Types of faults in machine tools and
their general causes.
UNIT IV: Periodic and Preventive Maintenance: Periodic inspection-concept and need, degreasing,
cleaning and repairing schemes, overhauling of mechanical components, overhauling of
electrical motor, common troubles and remedies of electric motor, repair complexities and its
use, definition, need, steps and advantages of preventive maintenance. Steps/procedure for
periodic and preventive maintenance of: (i). Machine tools, (ii). Pumps, (iii). Air compressors,
(iv). Diesel generating (DG) sets, Program and schedule of preventive maintenance of
mechanical and electrical equipment, advantages of preventive maintenance. Repair cycle
concept and importance.
1 Maintenance Engineering Handbook Higgins & Morrow Da Information Services
2 Maintenance Engineering H. P. Garg S. Chand and Company
3 Pump-hydraulic Compressors, Audels Mcgraw Hill Publication

4 Foundation Engineering Handbook Winterkorn, Hans Chapman & Hall London.
NOTE:

MTOE655C: OPERATIONS RESEARCH
Total : 100 Marks
Course Objectives:
1. To develop modeling skills in students.

2. To develop skill in students for efficient designing analysis and control of complete system.
3. To make students capable of formulating the practical problems into mathematical problems.
4. To acquaint student with linear as well as non-linear programming problem and their application.
Course Outcomes:
1. Students will be able to apply the dynamic programming to solve problems of discrete and continuous
variables.
2. Students will be able to carry out sensitivity analysis.
3. Student will be able to model the real world problem and simulate it.
4. The students will be able to carry forward the operation research techniques in practical problems.
Syllabus contents:
UNIT I: Linear optimization methods: General mathematical model formation of L.P.P, its solution by
Graphical method, Simplex method, big –M method, two phase method sensitivity analysis
(change in cj, bj&aij’s)
Revised Simplex method.Concept of duality, formation of Dual L.P.P, advantage of Duality,

dual simplex method, parametric programming.
UNIT II: Non liner programming: NLPP Mathematical formulation and solution with equally
constraints, Lagrange’s method, Graphical method, Kuhn—Tucker necessary &sufficient
conditions for the optimality of objective function in GNLP problem.
Dynamic programming: Kuhn –Tucker condition’s, Wolfe’s and Bcale’s method.
UNIT III: Deterministic inventory control models: Meaning & function role of inventory control,
reason for carrying inventory, single item inventory control model with & without shortages.
Probabilistic inventory control models: Inventory control models without set up cost and
with set up cost.
UNIT IV: Project management; PERT and CPM, Basic difference between PERT & CPM, Phases up
project management PERT /CPM network component & precedence relationships, critical
path analyses, projects scheduling with uncertain activity times, project time –cost trade-off.
Sequencing problem: Processing an jobs through two machines, three machines and
through m-machines. Theory of games: Two- person zero –sum games,pure strategies (with
saddle points) mixed strategies (without saddle point), algebraic method only.
1. H.A Taha, Operations Research, An introduction, PHI, 2008

2. H.M.Wanger, Principles of Operation Research PHI, Delhi, 1982
3. J.K.Sharma, Operations Research, Mcmillan India. Ltd,1990
4. S.D.Sharma, Operations Research, KedarnathRamnath publication,1985

5. P.K.Gupta and D.S Hira, Operations Research, S.Chand& Co.,1987
6. Pannerselvam, Operations Research; PHI, 2010
7. Harvey M Wanger , Principles of Operations Research; PHI, 2010
NOTE:
1. In the semester examination, the examiner will set 08 questions in all selecting two from each unit.
The candidates will be required to attempt five questions in all selecting at least one from each
unit. All questions will carry equal marks.

MTOE657C: COST MANAGEMENT OF ENGINEERING PROJECTS
Total : 100 Marks
Course Objectives:
Course Outcomes:
Syllabus contents:
UNIT I: INTRODUCTION AND OVERVIEW
Chapter 1 Introduction, basic economic concepts, interest formulae, present worth, rate of
return. Elements of financial accounting: depreciation, taxes and their impact in economic
studies
Chapter 2 Cost concepts in decision making; elements of cost, relevant cost, overheads,
differential cost, incremental cost and opportunity cost, objectives of a costing system,
inventory valuation, creation of a data base for operational control, provision of data for
decision making.
UNIT II: PROJECT
Chapter 3 Meaning, different types, why to manage, cost overrun centres, various stages of
project execution, concept to commissioning. Project execution as conglomeration of technical
and non technical activities. Detailed engineering activities, Pre project execution main
clearances and documents project team: Role of each member.
Chapter 4 Importance Project site: Data required with significance. Project contracts.Types
and contents. Project cost control. Bar charts and network diagram. Project commissioning:
Mechanical and process. Project appraisal and selection, recent trends in project management
UNIT III: ECONOMIC ANALYSIS FOR ENGINEERING PROJECTS
Chapter 5 Cost behavior and profit planning, Marginal costing, distinction between marginal
costing and absorption costing, Break even analysis, cost volume profit relationship, various
decision making problems.
Standard costing and variance analysis, pricing strategies Pareto analysis, Target analysis, life
cycle costing, Costing of service sector.
Chapter 6 just in time approach, material requirement planning, enterprise resource planning,
Total Quality management and theory of constraints, Activity based cost management, Bench
marking, Balanced score card, value chain analysis,
Budgetory control, Flexible budget, Performane budget, Zero based budget, Measurement of
divisional profitability pricing decisions including transfer pricing.
UNIT IV: QUANTITATIVE TECHNIQUES FOR COST MANAGEMENT
Chapter 7 PERT CPM; Activity networks, basic PERT/CPM calculations, Planning and
scheduling of activity networks, Assumptions in PERT modeling, time cost tradeoffs, PERT/

cost accounting, Scheduling with limited resources, Generalized activity networks GERT,
Prospects of PERT/CPM
Chapter 8 Linear programming, Transportation problems, Assignment problems, Simulation,

Learning curve theory.
1 Cost Accounting: A Managerial Emphasis Charles T. Horngren, Srikant Pearson Edu.

M. Datar, Madhav V. Rajan
2 Fundamentals of Financial Management Prasanna Chandra Tata McGraw Hill
3 Quantitative Techniques in Management N D Vohra Tata McGraw Hill
4 Foundation Engineering Handbook Winterkorn, Hans Chapman & Hall London.
5 Principles and Practice of cost accounting Ashish K Bhattacharya A H Wheeler
6 Principles of engineering economy E L Grant et al. John Wiley and Sons,

New York.
NOTE:

MTOE659C: COMPOSITE MATERIALS
Total : 100 Marks
Course Objectives:
Course Outcomes:
Syllabus contents:
UNIT I: INTRODUCTION: Definition – Classification and characteristics of Composite materials.

Advantages and application of composites.Functional requirements of reinforcement and
matrix.Effect of reinforcement (size, shape, distribution, volume fraction) on overall
composite performance.REINFORCEMENTS: Preparation-layup, curing, properties and
applications of glass fibers, carbon fibers, Kevlar fibers and Boron fibers. Properties and
applications of whiskers, particle reinforcements. Mechanical Behavior of composites: Rule of
mixtures, Inverse rule of mixtures. Isostrain and Isostress conditions.
UNIT II: Manufacturing of Metal Matrix Composites: Casting – Solid Stat e diffusion technique,
Cladding – Hot isostatic pressing.Properties and applications. Manufacturing of Ceramic
Matrix Composites: Liquid Metal Infiltration – Liquid phase sintering. Manufacturing of
Carbon – Carbon composites: Knitting, Braiding, Weaving. Properties and applications.
UNIT III: Manufacturing of Polymer Matrix Composites: Preparation of Moulding compounds and
prepregs – hand layup method – Autoclave method – Filament winding method –
Compression moulding – Reaction injection moulding. Properties and applications.
UNIT IV: Strength: Laminar Failure Criteria-strength ratio, maximum stress criteria, maximum strain
criteria, interacting failure criteria, hygrothermal failure. Laminate first play failure-insight
strength; Laminate strength-ply discount truncated maximum strain criterion; strength design
using caplet plots;stress concentrations.
1. Material Science and Technology – Vol 13 – Composites by R.W.Ca hn – VCH, West Germany.
2. Materials Science and Engineering, An introduction. WD Callister, Jr., Adapted by R.
Balasubramaniam, John Wiley & Sons, NY, Indian edition, 2007.
3. Hand Book of Composite Materials-ed-Lubin.
4. Composite Materials – K.K.Chawla.
5. Composite Materials Science and Applications – Deborah D.L. Chung.
6. Composite Materials Design and Applications – Danial Gay, Suong V. Hoa, and Stephen W. Tasi.
NOTE:

MTOE661C: WASTE TO ENERGY
Total : 100 Marks
Course Objectives:
To give an idea about different biomass and other solid waste materials as energy source and their processing
and utilization for recovery of energy and other valuable products. A comprehensive knowledge of how wastes
are utilized for recovery of value would be immensely useful for the students from all fields.
Course Outcomes:
In these days of energy crisis and environmental deterioration, students will understand the concept of energy by
waste products. It is being used globally to generate electricity and provide industrial and domestic applications.
Students will also enable to understand the environmental issues related to harnessing and utilization of various
sources of energy and related environmental degradation.
Syllabus contents:
UNIT I: Sun as Source of Energy, Availability of Solar Energy, Nature of Solar Energy, Solar Energy
& Environment. Various Methods of using solar energy –Photothermal, Photovoltaic,
Photosynthesis, Present & Future Scope of Solar energy.
UNIT II: Introduction to Energy from Waste: Classification of waste as fuel – Agro based, Forest
residue, Industrial waste, MSW
UNIT III: Biogas: Properties of biogas (Calorific value and composition) - Biogas plant technology and
status - Bio energy system - Design and constructional features - Biomass resources and their
classification, Biomass conversion processes, Thermo chemical conversion, Direct
combustion, Types of biogas Plants, Applications.
UNIT IV: Thermo-chemical Conversion: Pyrolysis, Combustion, Gasification, Liquification. Bio-

Chemical Conversion: Aerobic and Anaerobic conversion, Fermentation etc. Bio-fuels:
Importance, Production and applications. Bio-fuels: Types of Bio-fuels, Production processes
and technologies, Bio fuel applications, Ethanol as a fuel for I.C. engines, Relevance with
Indian Economy.
1. Non Conventional Energy, Desai, Ashok V., Wiley Eastern Ltd., 1990.
2. Biogas Technology - A Practical Hand Book - Khandelwal, K. C. and Mahdi, S. S., Vol. I & II, Tata
McGraw Hill Publishing Co. Ltd., 1983.
3. Food, Feed and Fuel from Biomass, Challal, D. S., IBH Publishing Co. Pvt. Ltd., 1991.
4. Biomass Conversion and Technology, C. Y. WereKo-Brobby and E. B. Hagan, John Wiley & Sons,
1996.
NOTE:

MTVLSI652C DISSERTATION (PHASE II)
Semester – IV

- - 32 16 Exams : 100 Marks
Total : 150 Marks
Course Objectives:
1. As part of DCRUST curriculum, a student is required to undertake dissertation in their final year of study.
2. Aim of this research is to develop student’s knowledge for solving technical problems through structured research study in order to
produce competent and sound engineers.
3. The thesis is very important component for students by the following ways.
4. It provides the students with the opportunity to design undertake or conduct an independent research or study related to their degree
course.
The Dissertation (Phase-II) shall be the extension of Dissertation (Phase-I) carried out in 3rd semester. Each
student will be required to present three seminar talks, first at the beginning of the semester to present the
progress made during the winter break; second in the middle of the semester involving partial results obtained
and comparative analysis; and third towards the end of the semester, presenting the dissertation report of the
work carried out. Each student will be required to submit two copies of dissertation report to M.Tech.
coordinator. The committee constituted by the Chairperson of the department will screen all the presentations so
as to award the sessional marks.
INTERNAL ASSESSMENT:
The internal assessment (Class-work evaluation) will be effected through presentation and discussion thereon by
the following committee:
1. Chairperson/Head of Department / Nominee : Chairperson
2. M.Tech. Coordinator/Senior Faculty : Member-Secretary
EXTERNAL ASSESSMENT:
Dissertation will be evaluated by the following committee:
1. Chairperson/Head of the Department / Nominee : Chairperson
3. External Expert : To be appointed by the University.
For this course, supervisor(s) will be assigned a load of 2hours per week for the first student and additional 1
hour per week for the subsequent student(s) subject to a maximum load of 3 hours. Work load allocated for the
joint supervision within the department will be treated as half for each supervisor.
NOTE: There is a desirable requirement of one publication in a UGC-listed journal / unpaid journal. The
external expert must be from the respective area of the specialization. Chairperson &M.Tech. Coordinator in
mutual consultation will divide the submitted dissertations into groups depending upon area of specialization
and recommend the list of experts for each group separately to the Vice-Chancellor for selecting the examiners
(one examiner for not more than four students of a group).
Course Outcome:
1. Upon completion of Final year dissertation, students are able to identify and describe the problem and scope of research clearly.
2. Students develop cognitive, technical and creative skills to analyze and present data into meaningful information using relevant
tools, select, plan and execute a proper methodology in problem solving, work independently and ethically.
3. They have acquired technical & communication skill to design, evaluate, implement, analyze, theorise and disseminate research
that makes a contribution to knowledge.
4. Communication & technical skills to present a coherent and sustained argument and to disseminate research results to specialist
and non specialist audience.


Mtec Ece-Vlsi-Design 2018

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Mtec Ece-Vlsi-Design 2018

Hochgeladen von

Copyright:

Verfügbare Formate

SCHEME

Department of Electronics & Communication Engineering

Approved in the 13th meeting of academic council held on 18/6/2018.

3. Application and Synthesis:

 To inculcate in students professional and ethical attitude, effective communication skills

Approved in the 13th meeting of academic council held on 18/6/2018.

a. an ability to apply knowledge of mathematics, science, and engineering,

Approved in the 13th meeting of academic council held on 18/6/2018.

6 MTVLSI553C Analog and Digital - 4 25 - 75 100 2 3

Approved in the 13th meeting of academic council held on 18/6/2018.

Total 14 8 200 375 225 800 18 -

Approved in the 13th meeting of academic council held on 18/6/2018.

List of Program Specific Elective V (PE V) List of Open Elective

MTVLSI611C Communication network MTOE651C Business Analytics

Approved in the 13th meeting of academic council held on 18/6/2018.

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Outcomes: At the end of this course, students will be able to

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Objective: The objectives of this course are as under:

1. Verilog implementation of 8:1 Mux/Demux, Full Adder, 8-bit Magnitude comparator,

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Objective: The objectives of this course laboratory as are under:

Approved in the 13th meeting of academic council held on 18/6/2018.

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Outcomes: At the end of this course, students will be able to

Approved in the 13th meeting of academic council held on 18/6/2018.

Course Objective: The objectives of this course are as under:

Approved in the 13th meeting of academic council held on 18/6/2018.

Course Objective : The objectives of this course are as under:

Course Outcomes: At the end of this course, students will be able to

Approved in the 13th meeting of academic council held on 18/6/2018.

Course Objective: The objectives of this course are as under:

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Objective: The objectives of this course are as under:

Approved in the 13th meeting of academic council held on 18/6/2018.

Course Outcome: At the end of this course, student will be able to

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Outcomes: At the end of this course, students will be able to

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Objective: The objectives of this course are as under:

Course Outcomes: At the end of this course, students will be able to

Approved in the 13th meeting of academic council held on 18/6/2018.

L T P Credits Class Work : 25 Marks

Course Objective: The objectives of this course are as under:

Approved in the 13th meeting of academic council held on 18/6/2018.

Course Objective: The objectives of this course are as under:

Course Outcome: After completion of the course, students will be able to

Course Objective: The objectives of this course are as under:

Approved in the 13th meeting of academic council held on 18/6/2018.

AUD531C: ENGLISH FOR RESEARCH PAPER WRITING

Course Objectives: Students will be able to:

UNIT I: Basics of Writing Skills:

UNIT II: Reviewing and Citation:

UNIT III: Sections of a Research Paper: