NATIONAL INSTITUTE OF TECHNOLOHY SIKKIM

Ravangla Campus
Barfung Block, Ravangla Sub Division, South Sikkim 737139

Subject: Semiconductor Devices (EC13103)

Module 4: JFET and MOSFET

 Field Effect Transistor:

The field effect transistor (FET) is a device in which the flow of current through the conducting
region is controlled by an electric field:
• Classification of FET:

FET
Based on construction

Junction Metal Oxide

Field Effect Transistor Field Effect Transistor
(JFET) (MOSFET)
Based on majority carrier Based on manner of construction

n-JFET p-JFET D-MOSFET E-MOSFET

1
 Construction of n- and p-channel JFET:

D ()
D ()

Depletion
region Depletion
n region
p

G
p p G
n n

n
p

S (- )
S ( )
n - JFET Constructi on
p - JFET Constructi on

• A JFET consists of a p-type or n-type silicon bar containing two pn junctions at the sides.
1. bar is n-type: n-channel FET
2. bar is p-type: p-channel FET
• The bar forms the conducting channel for the charge carriers.
• Ohmic contacts (terminals) made at two ends of the bar are called ‘source’ and ‘drain’.
• The two pn junctions forming the diodes are connected internally and a common terminal
called ‘gate’ is taken out.
• Thus, a JFET has essentially three terminals: source (S), drain (D), and gate (G).
Source:
• Connected to the negative pole of the battery for n-JFET and positive pole of the battery
for p-JFET.
• Majority carriers enter the bar through this terminal.
Drain:
• Connected to the positive pole of the battery for n-JFET and negative pole of the battery
for p-JFET.
• Majority carriers leaves the bar through this terminal.

2
 Gate:
• Acceptors are doped heavily on both sides of n-type silicon bar for n-JFET and donors
are doped heavily on both sides of p-type silicon bar for p-JFET to form pn junction in
respective JFETs.
• The pn junctions in respective JFETs are internally joined together and called gate G.
Channel:
• The region between depletion regions of two pn junctions is called channel.
• The majority carriers move from source to drain when a potential difference VDS is
applied between source and drain.
Schematic symbol:

D
D

G
G

S
S

n - Chennel JFET
p - Chennel JFET

• Operation of n-Channel JFET:

1. For VGS=0, VDS=0:
D • When no voltage is applied between drain and source,
and gate and source, the thickness of the depletion
Depletion
region regions round the PN junction is uniform as shown in
n
figure.
G
p p

3
2. For VDS=0, VGS decreased from zero:
• The PN junctions are reverse biased and hence the D
thickness of the depletion region increases.
• As VGS is decreased from zero, the reverse bias Depletion
region
n
voltage across the PN junction is increased and
hence, the thickness of the depletion region in the
G
channel increased until the two depletion regions p p
make contact with each other.
• Thus, the channel is said to be cut-off and the value - n
of VGS for which the channel is cut-off is called VGG
‘cut-off voltage’. 

3. For VDS=0, VGS decreased from zero:

D
• The drain is positive with respect to the source with
VGS = 0.
Depletion
• Thus, the majority carriers (electrons) flow through n
region
the n-channel from source to drain. B
• Therefore, the conventional current ID flows from G 
p p
drain to source. VDD
-
• The magnitude of the current will depends upon the n
following factors:

i.The number of majority carriers (electrons) available in the channel, i.e. the conductivity
of the channel.
ii.The length L of the channel.
iii.The cross-sectional area A of the channel at B.
iv.The magnitude of the applied voltage is VDS.
• Thus the channel acts as a resistor of resistance R given by:
L
R …………(1) Where, ρ resistance of channel
A

• Because of the resistance of the channel and the applied voltage V DS, there is a gradual
increase of positive potential along the channel from source to drain.

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 • Thus the reverse voltage across the PN junction increases and hence the thickness of the
depletion regions also increases.
• Therefore, the channel is wedge shaped as shown in the figure.
• As VDS is increased, the cross-sectional area of the channel will be reduced.
• For certain value VP of VDS, the cross-sectional area at B becomes minimum.
• At this voltage, the channel is said to be “pinched off“ and the drain voltage V P is called
the ”pinch-off voltage”.
• As a result of the decreasing cross section of the channel with increase of V DS, the
following results are obtained.

I D (mA)
Break down
Ohmic Pinch - off voltage i. - As VDS is increased from zero, ID
region region increases along OP, and the rate of
increase of ID with VDS decreases as
shown in Fig.
I DSS - The region from VDS = 0 to VDS = VP
P VGS  0V
is called the ‘Ohmic region’.
- In the channel ohmic region the drain
to source resistance VDS/ID is related
to the gate voltage VGS in an almost
linear manner.
VDS (V)
0 VP BVDGO

ii. - When VDS = VP, ID becomes maximum.

- When VDS is increased beyond VP, the length of the pinch-off or saturation region
increases, and hence there is no further increase of I D.
iii. - At a certain voltage BVDGO, the drain current ID increases suddenly.
- The sudden increase of drain current is due to the avalanche multiplication of electrons
caused by the breaking of covalent bonds of silicon atoms in the depletion region
between the gate and the drain.

5
4. For VGS=-ve, VDS is increased:
I D (mA)
• When the gate is maintained at a negative Ohmic Pinch - off
Break down
voltage
region region
voltage less than the negative cut-off
voltage, the reverse voltage across the
junction is increased further.
• Hence for a negative value of VGS, the
I DSS VGS  0V
curve of ID versus VDS is similar to that for
VGS = 0, but the values of VP and BVDGO VGS  1V
are lower.
VGS  2V
• From the figure it is seen that, the pinch-
off voltage at a constant value of VDS, ID VGS  3V
increases with an increase of VGS.
• It is also seen from the figure that, for
voltage VDS = VP the drain current is not VDS (V)
reduced to zero. 0 VP BVDGO

• If the drain current is to be reduced to zero, the ohmic voltage drop along the channel
should also be reduced to zero.
• Further, the reverse biasing to the gate-source PN junction essential for pinching off the
channel would also be absent.
• The drain current ID is controlled by the electric field that extends into the channel due to
reverse biased voltage applied to the gate, and hence this device has been given the name
‘Field Effect Transistor’.
• Operation of p-Channel JFET:
D • The p-channel JFET is one in which the channel is a p-
type bar and gate is formed by n-type doping on both side
Depletion of the bar.
p
region
• The working of the p-channel JFET will be similar to that
G
of n-channel JFET with proper alterations in biasing
n n circuit.
• The current carriers in p-channel JFET are holes instead
p
of electrons.

6
• Circuit Symbol of n- & p-channel JFET:
D D
 
 ID  ID

G G
 
 VDS   
IG VDD IG VDS
 
VDD
VGG VGS  VGS 
 IS VGG
   IS
 S  
 S

n - Chennel JFET p - Chennel JFET

• The circuit symbol of n-channel and p-channel JFETs are shown.

• The direction of the arrow points in the direction of conventional current which flow into
the gate if the PN junction was forward biased.
 Expression for Drain current:

I D (mA)
VGS  0
I DSS

- VGS VDS
(volts) VGS (off) 0 VP (volts)

• The shape of the transfer characteristics of JFET is very nearly a parabola.

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 • The mathematical expression representing the transfer characteristics curve is given by:
2
 VGS 
I D  I DSS 1   …………(2)
 VGS (off ) 

Where, ID drain current at given VGS

IDSS shorted gate drain current
VGS gate-source voltage
VGS (off) gate-source cut off voltage
• The gate-source cut off voltage on transfer characteristics is equal to pinch of voltage on
drain characteristics.

i.e. VGS (off )  VP ………..(3)

Ex 1: A FET has a driven current of 4 mA. If I DSS = 8 mA and VGS(off) = -6V. Find the values of
VGS and VP.
Answer: Given: Drain current: I D  4mA  4  10 3 A
Shorted gate drain current: I DSS  8mA  8  10 3 A
Gate-Source cut off voltage: VGS (off )  6V
Expression for drain current:
2
 VGS  3  V 
3
2
I D  I DSS 1    4  10  8  10 1  GS 
 VGS (off )   6
2
 V  1 VGS 1
 1  GS    1   0.707
 6  2 6 2
VGS
  0.707  1  0.293V
6
 VGS  1.76V

Pinch off voltage: VP  VGS ( off )  6V

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 Characteristics Parameter of JFET:

1. Mutual Conductance or transconductance (gm):

• The ratio of small change in drain current to the corresponding change in gate voltage at a
constant drain voltage is called mutual condutance or transconductance.
i.e. The slope of transfer characteristics curve.

 I  I D
Thus, g m   D   ………. (4)
 VGS VDS const VGS VDS  const

• The change in ID and VGS should be taken on straight part of the transfer characteristics.
• The unit of ‘gm’ is mho.

Ex 2: When the gate reverse voltage of JFET changes from 4.0 to 3.9 V, the drain current
changes from 1.3 to 1.6 mA. Find the value of transconductance.
Answer: Given: Change in gate reverse voltage: VGS  4.0  3.9  0.1V
Change in drain current: I D  1.6  1.3  0.3mA  0.3  10 3 A

I D
Transconductance: gm 
VGS
3
0.3  10

0.1
3
 3  10 A

2. Drain resistance (rd):

• The ratio of small change in drain voltage to the corresponding small change in drain
current at a constant gate voltage is called drain resistance.
i.e. The reciprocal of the slope of drain characteristics.

 V  VDS
Thus; rd   DS   …………..(5)
 I D VGS const I D VGS  const

• The unit of ‘r d’ is ohms.

• The drain resistance at VGS=0V (i.e. when the depletion regions of the channel are
absent) is called as “drain-source ON resistance”, and represented as RDS or RDS(ON).
• The reciprocal of rd is called the drain conductance (gd or gGS)
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3. Amplification factor ():
• The ratio of small change in drain voltage to the corresponding small change in gate voltage
at a constant drain current is called amplification factor.

 V  V DS
Thus;    DS   …………(6)
 VGS  I D  cons tan t
VGS I D  cons tan t

• The negative sign represents that when VGS is increased, VDS must be decreased for ID to
remain constant.
 Relation among FET parameters:
• ID depends on VDS and VGS.

Thus; I D  f VDS , VGS  ………..(7)

• For small change in drain voltage from VDS to (VDS+VDS) and gate voltage from VGS to
VGS +VGS, the corresponding change in ID obtained by Taylor’s theorem depends is
given by:

 I   I 
I D   D  VDS   D  VGS ………..(8)
 VDS VGS  VGS VDS

I D  I  VDS  I D 
   D     ………….(9)
VGS  VDS VGS VGS  VGS VDS

I D
• For ID = constant: 0 ………….(10)
VGS

Using Equation (10) in Equation (9):

 I  VDS  I D 
0   D    
 VDS VGS VGS  VGS VDS

1 
 0       g m
 rd 
   rd g m …………..(11)
Amplification factor () is the product of drain resistance (rd) and transconductance (gm).

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 Power dissipation of FET:
• The FETs continuous power dissipation (PD) is the product of ID and VDS.

PD  I DVDS …………..(12)
 Variation of gm in JFET:

I D (mA)
15
I DSS
10

5
I D
VGS (off) VGS
- VGS
(volts) VP 0
-6 -4 -2
2
• The shape of the transfer characteristics of JFET is very nearly a parabola.
• The mathematical expression representing the transfer characteristics curve is given by:
2
 V 
I D  I DSS 1  GS  ………..(13)
 VP 

Where, ID drain current at given VGS

IDSS shorted gate drain current
VGS gate-source voltage
VP pinch off voltage
• Differentiating equation (13) with respect to VGS:
I D  V  1 
 I DSS  21  GS   
VGS  VP  VP 
 2 I DSS  VGS  ……….(14)
 gm  1  
VP  VP 
11
 • From equation (13):

 VGS  ID
1   …………(15)
 VP  I DSS

• Substituting equation (15) in (14):

 2 I DS I DSS ………….(16)
gm 
VP
 gm decreases linearly with increase of VGS.

• Suppose for VGS=0, gm=gm0.

 2 I DSS
Then, g m0  …………..(17)
VP

Using equation (17) in (14):

 V 
g m  g m0 1  GS  …………(18)
 VP 

 gm decreases linearly with increase of VGS.

 Slope of Transfer characteristics at IDSS:

 2 I DS I DSS
• From equation (16): g m 
VP

or, I DS  2 I DS I DSS …………(19)


VGS VP

Substituting IDS = IDSS,

I DS 2I I
  DSS  DSS
VGS VP  VP / 2 ………….(20)

The tangent to the curve at IDS = IDSS, and VGS = 0 will have an intercept at Vp/2 on the
axis of VGS.
The value of Vp can be found by drawing the tangent at IDS = IDSS, VGS = 0.
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 Applications of JFET:
1. FET is used as a buffer in measuring instruments, receivers since it has high input
impedance and low out put impedance.
2. FETs are used in RF amplifiers in FM tuners and communication equipment for the low
noise levels.
3. Since the input capacitance is low, FETs are used in cascade amplifiers in measuring and
testing instruments.
4. Since the device is voltage controlled, it is used as a voltage variable resistor in
operational amplifiers and tone controls.
5. FETs are used in mixer circuits in FM and TV receivers, and communication equipment
because inter modulation distortion is low.
6. It is used in oscillator circuits because frequency drift is low.
7. As coupling capacitor is small, FETs are used in low frequency amplifiers in hearing aids
and inductive transducers.
8. FETs are used in digital circuits in computers, LSD and memory circuits because of its
small size.

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 Metal Oxide Field Effect Transistor (MOSFET):
• The metal-oxide-semiconductor field-effect transistor (MOSFET) is composed of an
MOS diode and two p-n junctions placed immediately adjacent to the MOS diode.
• The MOSFET is called the insulated gate FET (IGFET) because of the insulating layer of
SiO2.
• Since the first demonstration in 1960, MOSFET has developed quickly and has become
the most important devices for advanced integrated circuits such as microprocessors and
semiconductor memories.
• The MOSFET, in conjunction with other circuit elements, is capable of voltage gain and
signal power gain.
• A MOSFET can also be used in any of the circuit covered for JFET.
• Moreover, a MOSFET has several advantages over JFET including high input
impedance, and low cost production.
• The MOSFET can also be readily scale down and will take up less space than a bipolar
transistor using same design rule.
 MOS Diode:
• The MOS diode is the heart of the MOSFET - the most important device for advanced
integrated circuits.
• The MOS diode can be used as a storage capacitor in integrated circuits and it forms the
basic building block for charge coupled devices (CCD).
• The MOS diode is of paramount important in semiconductor device physics because the
device is extremely useful in the study of semiconductor surfaces.
 Ideal MOS Diode:

Insulator d Al
SiO 2
Metal
0

Si
x

Ohmic contact

14
 • The perspective view of an MOS diode and the cross section of the device is shown in the
figure, where d is the thickness of the oxide and V is the applied voltage on the metal
field plate.
• The voltage V is positive when the metal plate is positively biased with respect to the
ohmic contact and V is negative when the metal plate is negatively biased with respect to
the ohmic contact.
 Energy band diagram:

Evaccum

q
q M q S
EC
1
2 Eg
q B
Ei
EF EF
EV
d
Metal p - type
semiconduc tor

Oxide

q m : Work function of metal i.e. the energy difference between the Fermi level of metal and
vacuum level
q s : Work function of semiconductor i.e. the energy difference between the Fermi level of
semiconductor and vacuum level
q B :the energy difference between the Fermi level E F and intrinsic Fermi level
q : the electron affinity of the semiconductor i.e. energy difference between the conduction
band edge and vacuum level
• An ideal MOS is defined as follows:
(a) At zero applied bias, the energy difference between the metal work function qM and the
semiconductor work function qS is zero. (i.e. the work function difference qMS is zero).
 Eg  ………….(21)
q ms  q m  q s  q m   q   q B   0
 2 
 The energy band is flat (flat-band condition) when there is no applied voltage.
15
 (b) The only charges that exist in the diode under any biasing conditions are those in the
semiconductor and those with equal but opposite sign on the metal surface adjacent to the
oxide.
(c) There is no carrier transport through the oxide under direct current (dc)-biasing conditions
i.e. the resistivity of the oxide is infinite.
• The ideal MOS diode theory serves as a foundation for the understanding the practical MOS
devices.
• When an ideal MOS diode is biased with positive or negative voltages, three cases may exist
at the semiconductor surface.
Case I: -Ve voltage applied to metal plate

EF
V 0
EC QS
Metal
Ei
EF x
EV 0
QM

• For p-type semiconductor with negative voltage (V<0) is applied to the metal plate,
excess positive carriers (holes) will be induced at the SiO2-Si interface.
• Thus the bands near the semiconductor surface are bent upward.
• For an ideal MOS diode, no current flows in the device regardless of the value of applied
voltage and thus the Fermi level in the semiconductor will remain constant.
• We know;
 Ei  EF  / kT
pn  ni e ……….(22)
The upward bending of the energy band at the semiconductor surface causes an increase in
the energy Ei-EF, which in turn gives rise to an accumulation of holes near the oxide
semiconductor interface.

16
• This is called the case of “accumulation” and the corresponding charge distribution is
shown on the right side of the figure, where Q s is the positive charge per unit area in the
semiconductor and Qm is the negative charge per unit area (Qm= Qs) in the metal.

Case II: small +Ve voltage applied to metal plate

EC
QM
Ei
0 W
V 0
EF x
EF EV
qN AW
Metal

• When a small positive voltage (V>0) is applied to an ideal MOS diode, the energy band
near the semiconductor surface are bent downward, and the majority carriers (holes) are
depleted as shown in the Figure.
• This is called the case of “depletion”.
• The space charge per unit area (Qsc) in the semiconductor is equal to –qNAW, where W is
the width of surface depletion region.

17
Case III: Large +Ve voltage applied to metal plate

EC QM
Ei 0 Wm
EF x
V  0 EV qN AW
xi
EF Qn
Metal

• When a large positive voltage is applied, the energy bands bend downward even more so
that the intrinsic Fermi level Ei at the surface crosses over the Fermi level as shown in the
figure.
• This means the positive gate voltage starts to induce excess negative carriers (electrons)
at the SiO2-Si interface.
 E F  Ei  / kT
• We know; n p  ni e ………(23)
 Since (EF-Ei) > 0, the electron concentration np at the interface is larger than ni, and the
hole concentration given by equation 2 is less than ni.
• The number of electrons (minority carriers) at the surface is greater than holes (majority
carriers), and the surface is thus inverted.
• This is called the case of “inversion”.
• Since the electron concentration is small initially, the surface is in a weak inversion
condition.
• As the bands are bent further, eventually the conduction band edge comes close to the
Fermi level.
• The onset of strong inversion occurs when the electron concentration near the SiO 2-Si
interface is equal to the substrate doping level.
• After this point most of the additional negative charges in the semiconductor consist of
the charge Qn in a very narrow n-type inversion layer 0  x  xi, where xi is the width of
the inversion region.

18
 • Typically, the value of xi ranges from 1 to 10 nm and is always much smaller than the
surface depletion-layer width.
• Once strong inversion occurs, the surface depletion layer width reaches a maximum.
• This is because when the bands are bent downward far enough for strong inversion to
occur, even a very small increase in the band bending corresponding to a very small
increase in depletion-layer width results in a large increase in the charge Qn in the
inversion layer.
• Thus, under a strong inversion condition the charge per unit area Q s in the semiconductor
is the sum of the charge Qn in the inversion layer and the charge Qsc in the depletion
region:
Qs  Qn  Qsc  Qn  qN AW ………..(24)

Where Wm Maximum width of the surface depletion region

 Surface Depletion Region:

Semiconduc tor
surface

EC
Eg

q S q q B Ei
S  0 EF
xi
EV
Oxide Semiconduc tor

q B : the energy difference between the Fermi level E F and intrinsic Fermi level Ei
q : the electrostatic potential which is zero at the bulk of the semiconductor and equal to
surface potential s at the surface of semiconductor.
ni , n p , p p : Intrinsic, electron and hole concentration of the semiconductor.

19
• From equation (22) and (23):

  B  / kT
n p  ni e …………(25a)

 B   / kT
p n  ni e
…………(26a)

Where  +ve when band bent downward

-ve when band bent upward

At the surface densities are:

 s  B  / kT ……….(26a)
ns  ni e
 B  s  / kT
p s  ni e ………..(26b)
• The surface potential can be distinguished as:
s  0 Accumulation of holes (bands bend upward)
s  0 Flat band condition
 s  s  0 Depletion of holes (bands bend downward)
 s  B Midgap with ns=np=ni (intrinsic concentration)
 s  B Inversion (bands bend downward)
• According to onedimensional Poisson’s Equation:
d  s x 
2
………(27)

dx
2
s
Where;  x  charge density per unit volume at position x
 s  dielectric permittivity
• Let W  Width of depleted semiconductor
 s  qN A Charge within the semiconductor
From Equation (7):
d  d   x 
  s
dx  dx  s
 d    s x 
 d     dx
 dx   s 

20
  d    x 
  d     s  dx (integrating both sides)
 dx   s 
d  x  …………(28)
  s xC Where 
C constant
dx s
  x  
  d    s x  C  dx (integrating both sides)
 s 
 x  x
2

   s  Cx  D …………(29) Where 
D constant
s 2
d
From the figure: 0
dx x W

 s W 
 W C  0
s
 s W 
C  W ………….(30)
s

From the figure:  x W

0

 W  W  W  2
2

  W D0 [From equation (9)]

s 2 s
 W  2  W  2
 W D0 D W ………….(31)
2 s 2 s

Using equation (30) and (31) in (29):

 x   W
2 2

   s  s Wx   s
s 2 s s 2

 sW  x  x 
2 2

   1  2    
2 s  W  W  
2 2
qN AW  x
  1  …………(32)   s  qN A 
2 s  W 

21
 Also from the figure:
 x 0
 s

 D  s
 W  2
 s   W
2 s
2
qN AW
 s  ………….(33)
2 s

Using equation (13) in (12):

2
 x ………….(34)
   s 1  
 W

The potential distribution is identical to that for one-sided n+-p junction.

• The surface is inverted whenever s is larger than B.
• A simple criterion for inverted surface is that the concentration of electron at the surface
is equal to the substrate impurity concentration.

i.e. ns  N A …………..(35)

q B / kT
We know: N A  ni e …………(36)

Using equation (6a) and (16):

 B / kT  s  B  / kT
ni e  ni e
 B / kT  s  B  / kT
e e
B  s  B
 
kT kT
  B   s  B
  s  2 B
2kT N A
 s  ln …………(37) [Using equation (36)]
q ni

22
• Equation 37 states that a potential s is required to bend the energy bands down to the
intrinsic condition at the surface (Ei = Ef) and bands must then be bent downward by
another qB at the surface to obtain the condition of strong inversion.
• As discussed previously, the surface depletion layer reaches a maximum when the
surface is strongly inverted.
• Accordingly, the maximum width of the surface depletion region W m is given by :

2 s s inv  2 s 2 B 
Wm   …………(38)
qN A qN A

 NA 
 s kT ln  
 Wm  2  i 
n
2 …………..(39)
q NA

and Qsc  qN AWm   2q s N A 2 B  ……………(40)

• The plot of depletion width Wm and the impurity concentration for Si and GaAs is shown
in Figure, where NB is equal to NA for p-type and ND for n-type semiconductors.

10
Maximum depletion-layer width Wm (m)

Si GaAs

0.1

0.01
1014 1015 1016 1017 1018
Impurity concentration N B(cm-3)

23
Ex 3: For an ideal metal-SiO2-Si diode having NA = 1017 cm-3, calculate the maximum width of
the surface depletion region.
3
Answer: Given; Acceptor concentration: N A  10 cm
17

Intrinsic concentration: ni  9.65  10 9 cm 3

14
Dielectric permittivity:  s  11.9  8.5  10 F / cm

Depletion width: Wm  2
11.9  8.85  10
14
 0.026 ln 10
17
9
9.6510

19
1.6  10  10
17

12
 2 1.7114  10  16.154
6 6
 2  5.25  10  10.5  10 cm
6
 0.105  10 m  0.1m

 Ideal MOS Curves:

• The energy band diagram of an ideal MOS
diode with band bending is shown in
qV0
EC figure (a).
q s q B Ei
EF • In absence of any work function
Neutral region EV
V 0 Depletion region
difference, the applied voltage will partly
EF xi Inversion region across the oxide and partly across the
semiconductor.
Metal
• Thus, V  V0   s ……….(41)
 s x 
QM Where V0 Potential across the oxide
Q d Qs
0 W and V0  E0 d  s  ..…..(42)
d
x  0x C0
 Qn  qN A
Where E0 Field in the oxide
Qs Qs Charge per unit area in the
E x  semiconductor
QS /  0  E0  0x
C0  
Oxide capacitance per
d
d W
x unit area
0
• The charge distribution, electric field and
s the corresponding electrostatic potential
distribution is shown in Fig (b), (c) and
V V0 (d).
s
d 0 W
x •

24
• The total capacitance C of the MOS diode is a series combination of the oxide
capacitance C0 and the semiconductor depletion-layer capacitance Cj.

1 1 1 s
i.e.   Where Cj 
C C0 C j W
1 C0  C j
 
C C0C j
C0C j
C  …………(43)
C0  C j

• From Equation 13, 21, 22, and 23, we can eliminate W and obtain the formula for the
capacitance as:
C 1

Cj 2 0 xV
2 …………..(44)
1
qN A s d
2

• Equation 44 predicts that the capacitance will decrease with increasing metal-plate
voltage while the surface is being depleted.
• When applied voltage is negative, there is no depletion region, and we have an
accumulation of holes at the semiconductor surface.
• As a result, the total capacitance is close to the oxide capacitance 0x/d.
• In other extreme when strong inversion occurs, the width of the depletion region will not
increase with a further increase in applied voltage.
• This condition takes place at a metal-plate voltage that causes the surface potential  s to
reach s(inv), as given by equation (37).
• Substituting s(inv) into equation (41), and noting that the corresponding charge per unit
area is qNAWm yields the metal plate voltage at the onset of strong inversion.
• This voltage is called the threshold voltage given by:

qN AWm 2 s qN A 2 B 
VT    s inv   ………….(45)
C0 C0

• Once the strong inversion takes place, the total capacitance will remain at minimum value
given by equation (42) with Cj = s/Wm.
 0x ………..(46)
C min 
d   0 x /  s Wm

25
 • A typical capacitance-voltage characteristics of an ideal MOS diode is shown in the fig.
(a) based on both the depletion approximation Eq 44-66. The solid curve gives the exact
calculations.
• The C-V curves at different frequencies shown in Fig (b). The onset of the low-frequency
curves occurs at f  100Hz.

(a) I D (mA) (b) C/C 0

10Hz
C0 1.0
2
V 10 Hz

0.8 3
10 Hz
C0 d Si - SiO 2
Cj C min
N  1.45 10 cm
16 -3
VT 0.6 Ad  200nm 4 5
10 Hz 10 Hz
- 0  - 20 - 10 10
VV 
0 20
VV 

Ex 4: For an ideal metal-SiO2-Si diode having NA=1017 cm-3, and d=5 nm. Calculate maximum
depletion width, oxcide capacitance, (inv), and minimum capacitance of MOS diode. The
relative dielectric constant of SiO2 is 3.9.
3
Answer: Given; Acceptor concentration: N A  10 cm
17

Intrinsic concentration: ni  9.65  10 9 cm 3

14
Dielectric permittivity:  s  11.9  8.5  10 F / cm
14
Dielectric constant of SiO2:  SiO2  3.9  8.5  10 F / cm
7
Thickness of SiO2: d  5nm  5  10 cm
Depletion width:

Wm  2
11.9  8.85  10
14
 0.026 ln 
10
17

9.6510
9 
19
1.6  10  10
17

12 6 6
 2 1.7114  10  16.154  2  5.25  10  10.5  10 cm
6
 0.105  10 m  0.1m

26
Oxide capacitance per unit area
14
 0x 3.9  8.85  10 7
C0   7  6.9  10 F / cm
2

d 5  10
Space charge: Qsc  qN AWm  1.6  10 19  1017  1 10 5  
7
 1.6  10 C / cm
2

2kT  N A 
We know;  s inv   2 B  ln  
q  ni 
 1017 
 2  0.026 ln  
 9.65  10 9 
 
 0.84V

Minimum capacitance:
 0x
C min 
d   0 x /  s Wm
14
3.9  8.85  10

 3.9 / 11.9  1  10
7 5
5  10
5
 9.1  10 F / cm
2

27
 Work Function Difference:
• The work function difference (ms) between metal and semiconductor is given by:
…………..(47)
q ms  q m  q s

Where m 
Work function of metal
 S Work
 function of semiconductor

• For a given metal the work function (qm) is fixed.

• On the other hand, the position of Fermi level of
1.2
semiconductor varies with doping concentration
and hence the work function of a semiconductor 1.0
(qs), which is the energy difference between p+ poly(n-Si)
0.8
the vacuum level and the Fermi level, varies
with doping concentration. 0.6

• Thus the work function difference (ms) will 0.4

vary with doping concentration of 0.2 p+ poly(p-Si)

semiconductor. ms(V) 0.0
• One of the most common metal electrodes is the Al(n-Si)
-0.2
aluminum with qm=4.1 eV. n+ poly(n-Si)
-0.4
• The other material used extensively is the
heavily doped polycrystalline silicon with work -0.6
function 4.05 eV for n+-polysilicon and 5.05 eV Al(p-Si)
-0.8
for p+-polysilicon.
• The work function differences for aluminum, -1.0 n+ poly(p-Si)
n+-, and p+-polysilicon on silicon with doping -1.2
1013 1014 1015 1016 1017 1018
concentration is shown in the figure.
NB (cm-3)

28
 Classification of MOSFET:

MOSFET
Based on construction

Depletion MOSFET Enhancement MOSFET)

(D-MOSFET) (E-MOSFET)
x
Based on majority carrier Based on manner of construction

n-DMOSFET p-DMOSFET n-EMOSFET p-EMOSFET

• Thus there are two basic forms of MOSFETs.

Drain (D) Drain (D)

SiO 2 SiO 2
layer layer
n n

Gate (G) Gate (G)

p p
Substrate Substrate

n n

n Chanel

Source (S) Source (S)

n - Channel D - MOSFET n - Channel E - MOSFET

 The EMOSFET has no channel between source and drain unlike the D-MOSFET.

29
Principle:
• By applying a transverse electric field across an insulator deposited on the semiconductor
material, the thickness and hence the resistance of a conducting channel of a
semiconducting material can be controlled.
D-MOSFET: The controlling electric field reduces the number of majority carriers
available for conduction.
E-MOSFET: The application of electric field causes an increase in the majority carrier
density in the conducting regions of the transistor.

 Enhancement MOSFET:

Construction:
VGG
- 

S D
SiO 2 G Al



   ID
n n
Induced n - channel
p - Substrate

- 

D
D

Substrate
Substrate
G B
G B

S
S
p - Channel E - MOSFET
n - Channel E - MOSFET

30
• The n-channel enhancement MOSFET and the circuit symbols of an n-channel and p-
channel enhancement MOSFET are shown in the figure.
• Two highly doped N+ regions with a separation of 1 mil (10-3 inch) are diffused in a
lightly doped substrate of p-type silicon.
• One n+-region is called the source “S” and the other one is called the drain “D”.
• A thin insulating layer of SiO2 is grown over the surface of the structure and holes are cut
into the oxide layer, allowing the contact with source and drain.
• A thin layer of metal aluminum is formed over the layer of SiO 2 which covers the entire
channel region and forms the gate G.
• The metal area of the gate in conjunction with the insulating oxide layer of SiO2 and the
semiconductor channel forms a parallel plate capacitor.

Operation:
• If the substrate is grounded and a positive voltage is applied at the gate, the positive
charge on G induces an equal negative charge on the substrates side between the source
and the drain regions.
• Thus, an electric field is produced between the source and drains regions.
• The direction of the electric field is
perpendicular to the plates of the 
capacitor through the oxide. I D (mA)

• The negative charge of the electrons 8

which are minority carriers in the p-type VGS  3V
substrate forms an inversion layer.

Enhancement
6
• As the positive voltage on the gate  2V
increases, the induced negative charge
in the semiconductor increases. 4
• Hence, the conductivity increases and  1V
the current flows from source to drain
through the induced channel. 2 0V Depletion
 1V
• Thus the drain current is enhanced by  2V
 3V
the positive gate voltage and is shown in
the figure below. 0 5 10 10 20
VDS (V) 

31
 Depletion MOSFET:
Construction:
VGG
 -

S D
SiO 2 G Al



n
   ID
n
n - channel
p - Substrate

- 
VDD

D D

Substrate Substrate

G B G B

S S
n - Channel D - MOSFET p - Channel D - MOSFET

• The n-channel depletion MOSFET and the circuit symbols of an n-channel and p-channel
depletion MOSFET are shown in the figure.
• An n-channel is diffused between the source and drain to the basic structure of MOSFET.

Operation:
• With VGS=0 and the drain D at a positive potential with respect to the source, the
electrons (majority carriers) flow through the n-channel from S to D.
• Therefore, the conventional current ID flows through the channel D to S.

32
• If the gate voltage is made negative, positive charge consisting of holes is induced in the
channel through SiO2 of the gate-channel capacitor.
• The introduction of positive charge causes depletion of mobile electrons in the channel.
• Thus a depletion region is produced in the channel.
• The shape of the depletion region depends on VGS and VDS.
• Hence the channel will be wedge shaped as shown in the figure.
• When VDS is increased, ID increases and it becomes practically constant at a certain value
of VDS called “pinch-off voltage”.
• The drain current ID almost gets saturated beyond the pinch-off voltage.
• Since the current in an FET is due to majority carriers (electrons for N-type materials),
the induced positive charges makes the channel less conductive, I D drops as VGS is made
negative.
• The depletion MOSFET may also be operated in an enhancement mode.
• It is only necessary to apply a positive gate voltage so that negative charges are induced
into the channel.
• Hence, the conductivity of the channel increases and I D increases.
• As the depletion MOSFET can be operated with bipolar inputs signal irrespective of
doping of the channel, it is also called as dual mode MOSFET.
• The transfer characteristics curve of ID versus VGS for constant VDS is shown in the figure
below.

I D (mA)
Depletion Enhancemen t
6

2
I DSS

-4 -3 -2 -1 0 1 2 3 4 5
VGS (off) VGS (V) 
33
 Effect of Channel width Modulation:


I D (mA)

1
Slope 
r0

1 0 VDS (V) 
- VA 


• A nonzero slope exists beyond saturation point of the actual MOSFET characteristics, as
shown in the figure above.
• For the saturation [i.e. VDS > VDS(sat)], the effective channel length decreases and this
phenomenon is called channel length modulation.
• For an n-channel device, the slope of the curve in the saturation region can be expressed
by using the drain current ID given by:
I D  K N VGS  VTN  1  VDS  ………….(48)
2

Where; 
Channel length modulation parameter

K NConduction parameter

VTNThreshold voltage

• The output resistance due to channel length modulation is expressed as:

1
 I 
r0   D  ………..(49)
 VDS  VGS const

34
 • The output resistance can be determined at the Q-point by:


r0  K N VGSQ  VTN 
2 1
 ………….(50)
1
  VGSQ  
2

 I DSS 1   

  VP  

i.e. 
r0  I DQ 1

1 V
 BE …………(51)
I DQ I DQ

 Temperature Effects:
• The threshold voltage VTN or VTP and conduction parameter KN or KP are functions of
temperatures.
• The magnitude of threshold voltage decreases with temperature, and hence drain current
ID increases with temperature at a given VGS.
• The conduction parameter is directly proportional to mobility n or p of the carrier,
which increases as the temperature decreases.
• The temperature dependent of mobility is larger than that of threshold voltage.
• Hence the net effect of decreasing drain current at a given V GS due to increase in
temperature provides a negative feedback condition and hence the stability of power of
MOSFET.

 Comparison of MOSFET with JFET:

1. In enhancement and depletion type MOSFET, the transverse electric field induced across
an insulating layer deposited on semiconductor materials controls the conductivity of the
channel. Where as in JFET the transverse electric field across the reverse bias pn junction
control the conductivity of the channel.
2. The gate leakage current in a MOSFET is of the order of 10 -12 A. Hence the input
resistance of a MOSFET is very high in the order of 1010 to 1015 . The gate leakage
current of a JFET is of the order of 10-9 A and its input resistance is of the order of 108.
3. The output characteristics of the JFET are flatter than those of the MOSFET and hence,
the drain resistance of a JFET (0.1 to 1M) is much higher than that of a MOSFET ( 1 to
50k).
4. JFET are operated only in the depletion mode. The depletion type MOSFET may be
operated in both depletion and enhancement mode.
5. Comparing to JFET, MOSFETs are easier to fabricate.

35
6. MOSFET is very susceptible to overload voltage and needs special handling during
installation. It gets damage easily if it is not properly handled.
7. MOSFET has zero offset voltage. As it is a symmetrical device, the source and drain can
be interchanged. These two properties are very useful in analog signal switching.
8. Special digital CMOS circuits are available which involves near zero power dissipation
and very low voltage and current requirements. This makes them most suitable for
portable systems.

36