EE213, Fall 2019 HW #2 2019, in class

1.
i.1) When the input is high, M1 doesn’t saturate, then
VDD − VOL
= k I  2 (VOH − VTN )VOL − VOL2 
RL
VDD
VOL 
1 + 2k I RL (VOH − VTN )

i.2) When the input is low, M1 cuts off, then

VDD − VOH
=0  VOH = VDD
RL

ii. 1) When the input is high, M1 doesn’t saturate and ML

saturate,
k L (VDD − VOL − VTN ) = k I  2 (VOH − VTN )VOL − VOL 
2 2

(VDD − VTN ) ,  = kI = (W / L ) I ,
2

VOL 
2 R (VOH − VTN ) k L (W / L ) L
R

ii. 2) When the input is low, M1 cuts off and ML saturates

kL (VDD − VOH − VTN ) = 0 VOH = VDD − VTN
2

iii. 1) When the input is high, M1 doesn’t saturate and ML doesn’t saturate,
k L  2 (VGG − VOL − VTN )(VDD − VOL ) − (VDD − VOL )  = k I  2 (VOH − VTN )VOL − VOL2 
2
 
(VDD − VTN ) ,  = kI = (W / L ) I , m =
2
VDD
VOL  ,0  m 1
2m R (VOH − VTN ) k L (W / L ) L 2 (VGG − VTN ) − VDD
R

iii. 2) When the input is low, M1 cuts off and ML doesn’t saturate

kL  2 (VGG − VOH − VTN )(VDD − VOH ) − (VDD − VOH )  = 0

2
 
 VOH = VDD

iv. 1) When the input is high, MN doesn’t saturate and MP cuts off,
 2 (VOH − VTN )VOL − VOL 
kN  =0 VOL = 0
2

iv. 2) When the input is high, MP doesn’t saturate and MN cuts off,

−kP  2 (VOL − VDD − VTP )(VOH − VDD ) − (VOH − VDD )  = 0

2
 
 VOH = VDD

According to the derivations, we can get the results in

(a) When the input is high, (i), (ii), (iii) consume static power;
(b) When the input is low, none of these circuits consume static power;
(c) (i), (iii), (iv);
(d) (iv);

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2.

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3.

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4.

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5.
1. Energy dissipation.[12 pts]
a) In the following circuit, calculate the energy dissipated as heat in M1 during the low to high transition in the
output. Ignore the parasitic capacitances.[3 pts]
Solution:
In the low to high transition, M1 is on.
The energy drawn from supply:
𝑉𝑂𝐻
𝐸𝑠𝑢𝑝𝑝𝑙𝑦 = 𝑉𝑑𝑑 𝐶𝐿 ∫ 𝑑𝑉𝑜𝑢𝑡 = 𝐶𝐿 𝑉𝑑𝑑 2
𝑉𝑂𝐿
𝑉𝑂𝐻
1
𝐸𝐶𝐿 = 𝐶𝐿 ∫ 𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡 = 𝐶𝐿 𝑉𝑑𝑑 2
𝑉𝑂𝐿 2
1 2
The energy dissipated as heat in M1 is 𝐶 𝑉
2 𝐿 𝑑𝑑
.

b) What happens to the energy dissipation in a) if the transistor length of M1 is doubled? [3 pts]
Solution:
The energy dissipation will not change.
c) In the following circuit, calculate the energy dissipated as heat in M1 if the supply voltage is increased from
0V to 𝑉𝑑𝑑 with the step of 𝑉𝑑𝑑 /2. The output is initially at 0V. Ignore the parasitic capacitance and assume
that |𝑉𝑡𝑝 | < 𝑉𝑑𝑑 /2. [6 pts]
Solution:
The energy drawn from supply:
𝑉𝑂𝐻1
1 1
𝐸𝑠𝑢𝑝𝑝𝑙𝑦1 = 𝑉𝑑𝑑 𝐶𝐿 ∫ 𝑑𝑉𝑜𝑢𝑡 = 𝐶𝐿 𝑉𝑑𝑑 2
2 𝑉𝑂𝐿 1 4
𝑉𝑂𝐻2
1
𝐸𝑠𝑢𝑝𝑝𝑙𝑦2 = 𝑉𝑑𝑑 𝐶𝐿 ∫ 𝑑𝑉𝑜𝑢𝑡 = 𝐶𝐿 𝑉𝑑𝑑 2
𝑉𝑂𝐿2 2
The energy stored in the capacitor:
1
𝐸𝐶𝐿 = 𝐶𝐿 𝑉𝑑𝑑 2
2

The The energy dissipated as heat in M1:

3 1 1
𝐸𝑀1 = 𝐶𝐿 𝑉𝑑𝑑 2 − 𝐶𝐿 𝑉𝑑𝑑 2 = 𝐶𝐿 𝑉𝑑𝑑 2
4 2 4

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6. Consider two types of inverters shown in Fig. 8. The left inverter has a balanced pull-up and pull-down while the
right one has a skewed pull-up and pull-down. Which N-stage ring oscillator will run slower, one using (left) balanced
inverters or one using (right) skewed inverters? What is the percentage difference between the balanced and skewed
ring oscillator periods? [12 pts]

WP = 2 WP = 1
R0 2 R0

Wn = 1 Wn = 2
R0 ½ R0

Fig. 8

Solution:
For the left balanced inverter, the equivalent resistance is R0 for both PMOS and NMOS.
For the right skewed inverter, the equivalent resistance are respectively 2R0 and 0.5R0.

CL

The period of the balanced ring oscillator including N-stage inverters:

𝑡𝑏𝑎𝑙 = 2N𝑅0 𝐶𝐿

The period of the skewed ring oscillator including N-stage inverters:

1 5
𝑡𝑠𝑘𝑒 = 2N𝑅0 𝐶𝐿 + N𝑅0 𝐶𝐿 = N𝑅0 𝐶𝐿
2 2
The percentage difference:
5
N𝑅0 𝐶𝐿 − 2N𝑅0 𝐶𝐿
∆t = 2 = 0.25 = 25%
2N𝑅0 𝐶𝐿

8.

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7.

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8.

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9. For the circuit below in Fig. 9, prove that its Elmore delay at the right-most node can be computed as
[10 pts]
τ𝑁 ≈ ∑ 𝑅𝑖 𝑡𝑜 𝑠𝑜𝑢𝑟𝑐𝑒 𝐶𝑖 = 𝑅1 𝐶1 + (𝑅1 + 𝑅2 )𝐶2 + ⋯ + (𝑅1 + ⋯ + 𝑅𝑁 )𝐶𝑁
𝑛𝑜𝑑𝑒𝑠 𝑖

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10. (Bonus Problem) Both resistance and capacitance increase with wire length L, so the RC delay of a wire
increases with L2, as shown in Fig. 10. By splitting the wire into N segments and inserting an inverter or buffer
called a repeater to actively drive the wire, the delay can be reduced, as shown in Fig. 11.
Suppose a unit inverter has resistance Rref, diffusion capacitance Ciref and gate capacitance Ciref/γ. A wire has
resistance rw and capacitance cw per unit length. Considering inserting repeaters of S times unit size. Fig. 12
shows a model of one segment. [20 pts]

Fig. 10

Fig. 11

Fig. 12

a) Given the size of the driver and receiver SD and SR, derive the Elmore delay expression of the repeated
wire in Fig. 11.
Solution:
The Elmore delay of the segment of Fig. 12:
𝑅𝑟𝑒𝑓 𝐿 𝑅𝑟𝑒𝑓 𝐿 𝑅𝑟𝑒𝑓 𝐿 𝐶𝑖𝑟𝑒𝑓 𝑅𝑟𝑒𝑓 𝐿
τ𝑠𝑒𝑔𝑚𝑒𝑛𝑡 = 𝑆𝐶𝑖𝑟𝑒𝑓 + 𝑐𝑤 + 𝑐𝑤 ( + 𝑟𝑤 ) + 𝑆( + 𝑟𝑤 )
𝑆 2𝑁 𝑆 2𝑁 𝑆 𝑁 𝛾 𝑆 𝑁
𝑅𝑟𝑒𝑓 𝐿 𝐶𝑖𝑟𝑒𝑓 𝐿 𝐿 𝐶𝑖𝑟𝑒𝑓
= (𝑆𝐶𝑖𝑟𝑒𝑓 + 𝑐𝑤 + 𝑆) + 𝑟𝑤 (𝑐𝑤 + 𝑆)
𝑆 𝑁 𝛾 𝑁 2𝑁 𝛾
The Elmore delay of the repeated wire in Fig. 11:
τ = N τ𝑠𝑒𝑔𝑚𝑒𝑛𝑡
b) According to a), derive the optimal S and N respectively to minimize the Elmore delay.
Solution:
By differentiating τ with respect to S and N, you can get the optimal S and N.
𝛾𝑐𝑤 𝑅𝑟𝑒𝑓
S=√
𝑐𝑖𝑟𝑒𝑓 𝑟𝑤

L 2(1+𝛾)𝐶𝑖𝑟𝑒𝑓 𝑅𝑟𝑒𝑓
=√
𝑁 𝛾𝑐𝑤 𝑟𝑤

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