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Dr Ambedkar Institute of Technology

prepared by Yajnesh Padiyar

Electronics & Communication

VLSI Lab
06ECL77
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Dr. Ambedkar Institute of Technology

LABORATORY CERTIFICATE

This is to certify that Smt/Sri ………………………… has


satisfactorily completed the course of Experiments in Practical VLSI LAB
prescribed by the Visvesvaraya Technological University Bachelor of
Engineering course in the Laboratory of this college in the year.

Date …………..
Signature of the Teacher In charge of the batch

Head of the Department

Name of the Candidate .………………………….

Reg. No. ………………………………………….

Examination Centre .………………….…………

Date of Practical Examination ….……..…………

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INDEX

I. Getting started with cadence ASIC Flow

II. ASIC Digital Design Flow


 Inverter
 Basic Gates
 Buffer
 JK Flip Flop
 SR Flip Flop
 D Flip Flop
 T Flip Flop
 MS Flip Flop
 Synchronous 4-bit up/down counter
 Asynchronous 4-bit up/down counter
 Serial Adder
 Parallel Adder

III. Analog Design


 Inverter Design
 Common Drain Amplifier
 Common Source Amplifier

IV. VLSI Viva Questions

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I. Getting started with cadence digital lab


1. Right click on the desktop and select open terminal
2. Now check the connection with server
ping 192.168.3.81
if server connection is successful then u see a series of lines showing data transfer information’s
3. A. Now type
cd /mnt/cadence press enter
B. then type
ls press enter (ls is used to see the contents of present directory as DIR in DOS)
C. now you must be able to see a series of files if not type
mount -t nfs 192.168.3.81:/root/cadence /mnt/cadence
repeat the instruction twice
D. check set A and B again
4. After the 3 step its necessary to go back to root directory type cd /
now type
#cd /
# source ~/cshrc (if u get error then type next step else skip it)
#csh (now type the above step again and then continue)
#ls (ls can be skipped if you know which is the next directory to go)
#cd root
#ls
#cd Cadence_digital_labs
#ls
#cd Workarea
#ls
here u will be placing all your code files
the 4th step can be done in single step
#cd root/ Cadence_digital_labs/ Workarea
5. Now to compile and simulate the code
type
#ncvlog inverter_test.v –mess (test bench compilation)
#ncvlog inverter.v –mess (RTL code compilation)
#ncelab inv_test –mess (elaboration)
#ncsim inv_test (simulation)

for GUI the first two commands remain the same but from third
#ncelab inv_test –access +rwc
#ncsim inv_test -gui
6. The 5th step can also be done using the single step with GUI
#irun inverter.v inverter_test.v –access +rwc -gui

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Synthesize procedure

1. Go to rclabs directory in workarea


#cd rclabs
2. Go to work directory in rclabs
#cd work
3. Type
#rc –gui (this would start a GUI window)
After the 3rd step again come back to the terminal
type the following
rc:/>set_attr lib_search_path ../library
rc:/>set_attribute hdl_search_path ../rtl
rc:/>set_attr library slow_highvt.lib
(if this step gives an error then close the rc window and then type the following
#cd /
#cd root/Cadence_digital_labs
#tar -xzvf Cadence_digital_labs.tar.gz
this should work and then continue with RC labs again)
rc:/>read_hdl {file_name.v}
(in the above step it is necessary to copy the RTL code(file_name.v) to the folder rtl in the
rclabs folder)
rc:/>read_sdc ../constraints_filename.g
(if any constraints file they must be read here)
rc:/>elaborate
rc:/>synthesize -to_mapped -effort medium
(now you must be able to see the schematic . else go to file and click on update)
rc:/>write > any_name.v
rc:>report timing
rc:/>report power
rc:/>report area

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II. ASIC Digital Design Flow


1. INVERTER
RTL Code
module inverter(a, b);
input a;
output b;
assign b = ~a;
endmodule

Test Bench Code


module test_inv;
// Inputs
reg a;
// Outputs
wire b;
inverter my_inv (a,b);
initial begin
// Initialize Inputs
a = 0; #100;
// Wait 100 ns for global reset to finish
$display(“a=%d |”,a,”b=%d”,b);
a = 1; #100;
$display(“a=%d |”,a,”b=%d”,b);
end
endmodule

Block Diagram

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Output Waveform

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2. BASIC GATES
RTL Code
AND Gate
module and_gate(a,b,c);
input a,b;
output c;
assign c = a & b;
endmodule

Test Bench Code


module test_and;
// Inputs
reg a,b;
// Outputs
wire c;
and_gate my_gate (a,b,c);
initial begin
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 1; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
end
endmodule

Block Diagram

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Output Waveform

RTL Code
OR Gate
module or_gate(a,b,c);
input a,b;
output c;
assign c = a | b;
endmodule

Test Bench Code


module test_or;
// Inputs
reg a,b;
// Outputs
wire c;
or_gate my_gate (a,b,c);
initial begin
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 1; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
end
endmodule

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Block Diagram

Output Waveform

RTL Code
XOR Gate
module xor_gate(a,b,c);
input a,b;
output c;
assign c = a ^ b;
endmodule

Test Bench Code


module test_xor;
// Inputs
reg a,b;
// Outputs
wire c;
xor_gate my_gate (a,b,c);
initial begin
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);

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a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 1; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
end
endmodule

Block Diagram

Output Waveform

RTL Code
XNOR Gate
module xnor_gate(a,b,c);
input a,b;
output c;
assign c = ~ (a ^ b;)
endmodule

Test Bench Code


module test_xnor;
// Inputs
reg a,b;
// Outputs
wire c;

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xnor_gate my_gate (a,b,c);


initial begin
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 1; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
end
endmodule

Block Diagram

Output Waveform

RTL Code
NOR Gate
module nor_gate(a,b,c);
input a,b;
output c;
assign c = ~ (a | b;)

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endmodule

Test Bench Code


module test_nor;
// Inputs
reg a,b;
// Outputs
wire c;
nor_gate my_gate (a,b,c);
initial begin
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 1; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
end
endmodule

Block Diagram

Output Waveform

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RTL Code
NAND Gate
module nand_gate(a,b,c);
input a,b;
output c;
assign c = ~ (a & b;)
endmodule

Test Bench Code


module test_ nand;
// Inputs
reg a,b;
// Outputs
wire c;
nand _gate my_gate (a,b,c);
initial begin
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 1; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
end
endmodule

Block Diagram

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Output Waveform

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3. BUFFER
RTL Code
module buffer_1(a, b);
input a;
output b;
not(ta,a);
not(b,ta);
endmodule

Test Bench Code


module buff_test;
reg a;
wire b;
buffer_1 my_buff(a,b);
initial begin
a = 0;
#100;
a = 1;
#100;
end
endmodule

Block Diagram

Output Waveform

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4. JK Flip Flop
RTL Code
module jk_ff(j, k, clk, q, qb);
input j,k,clk;
output reg q,qb;
reg kk = 1’b0;
reg [1:0] t;
always@(posedge(clk))
begin
t={j,k};
case(t)
2'b00 : kk = kk;
2'b01 :kk = 1’b0;
2'b10 : kk = 1’b1;
2'b11 :kk = ~kk;
default: ;
endcase
q = kk; qb = ~q;
end
endmodule

Test Bench Code


module jk_test;
reg j,k,clk;
wire q,qb;
jk_ff my_ff (j,k,clk,q,qb);
initial clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
j = 0; k = 0; #10;
j = 1; k = 1; #20;
j = 0; k = 1; #10;
j = 1; k = 1; #20;
j = 1; k = 0; #10;
end
endmodule

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Block Diagram

Output Waveform

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5. SR Flip flop
RTL Code
module sr_ff(s,r, q,qb);
input s,r;
output reg q,qb;
reg st = 1'b0;
reg [1:0] k;
always@(s,r)
begin
k = {s,r};
case(k)
2'b00 : st = st;
2'b01 : st = 1'b0;
2'b10 : st = 1'b1;
2'b11 : st = 1'bz;
default: ;
endcase
q = st;
qb = ~q;
end
endmodule

Test Bench Code


module sr_test;
reg r,s;
wire q,qb;
sr_ff my_ff(s,r,q,qb);
initial
begin
r = 0; s = 0; #10;
r = 0; s = 1; #10;
r = 1; s = 0; #10;
r = 1; s = 1; #10;
r = 0; s = 0; #10;
r = 0; s = 1; #10;
r = 1; s = 0; #10;
r = 1; s = 1; #10;
end
endmodule

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Block Diagram

Output Waveform

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6. D Flip flop
RTL Code
module d_ff(d,clk, q,qb);
input d,clk;
output reg q,qb;
always@(posedge(clk))
begin
q = d;
qb = ~d;
end

Test Bench Code


module d_test;
reg d,clk;
wire q,qb;
d_ff my_ff(d,clk,q,qb);
initial
clk = 1'b1;
always
#5 clk = ~clk;
initial
begin
d = 0; #10;
d = 1; #10;
d = 0; #10;
d = 1; #10;
end
endmodule

Block Diagram

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Output Waveform

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7. T Flip flop
RTL Code
module t_ff(t,clk, q,qb);
input t,clk;
output q,qb;
jk_ff u1(t,t,clk,q,qb);
endmodule

(note: write the jk_ff code JK Flip flop in a separate file and save it )
JK Flip flop Code
module jk_ff(j, k, clk, q, qb);
input j,k,clk;
output reg q,qb;
reg kk = 1’b0;
reg [1:0] t;
always@(posedge(clk))
begin
t={j,k};
case(t)
2'b00 : kk = kk;
2'b01 :kk = 1’b0;
2'b10 : kk = 1’b1;
2'b11 :kk = ~kk;
default: ;
endcase
q = kk;
qb = ~q;
end
endmodule

Test Bench Code


module t_test;
reg t,clk;
wire q,qb;
t_ff my_ff(t,clk,q,qb);
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial

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begin
t = 0; #10;
t = 1; #10;
t = 0; #10;
t = 1; #10;
end
endmodule

Block Diagram

Output Waveform

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8. MS Flip flop
RTL Code
module ms_ff(j,k,clk, q,qb);
input j,k,clk;
output q,qb;
jk_ff u1(j,k,clk,qm,qmb);
jk_ff u2(qm,qmb,~clk,q,qb);
endmodule

(note: write the jk_ff code in a separate file and save it )


JK Flip flop Code
module jk_ff(j, k, clk, q, qb);
input j,k,clk;
output reg q,qb;
reg kk = 1’b0;
reg [1:0] t;
always@(posedge(clk))
begin
t={j,k};
case(t)
2'b00 : kk = kk;
2'b01 :kk = 1’b0;
2'b10 : kk = 1’b1;
2'b11 :kk = ~kk;
default: ;
endcase
q = kk;
qb = ~q;
end
endmodule

Test Bench Code


module ms_test;
reg j,k,clk;
wire q,qb;
ms_ff my_ff (j,k,clk,q,qb);
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial

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begin
j = 1; k = 0; #10;
j = 0; k = 1; #10;
j = 1; k = 0; #10;
j = 0; k = 1; #10;
j = 1; k = 1; #10;
end
endmodule

Block Diagram

Output Waveform

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9. Synchronous 4-bit up/down counter


RTL Code
module count(clk,UpDown, reset, q);
input clk,UpDown;
input reset;
output reg [3:0] q;
reg [3:0] t=4'd0;
always@(posedge(clk))
begin
if(reset==0)
t=4'd0;
else if(UpDown == 1)
t = t + 1;
else
t = t - 1;
q=t;
end
endmodule

Test Bench Code


module Test_updown;
reg clk,reset,updown;
wire [3:0] q;
count my_count (clk,updown,reset,q);
initial
clk=1'd0;
always
#5 clk = ~clk;
initial
begin
reset = 0;
updown = 1;
#5;
reset = 1;
#30;
updown = 0;
#30;
updown = 1;

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end
endmodule

Block Diagram

Output Waveform

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10. Asynchronous 4-bit up/down counter


RTL Code
module count_ashyn(clk,rst,updown, count);
input clk,rst,updown;
output reg [3:0] count;
always@(posedge(clk),posedge(rst))
begin
if(rst == 1)
count = 4'd0;
else if(clk == 1)
if( updown == 1)
count = count + 1;
else
count = count - 1;
end
endmodule

Test Bench Code


module test_asyn;
reg clk,rst,updown;
wire [3:0] count;
count_ashyn uut (clk,rst,updown,count);
initial
clk = 1'd0;
always
#5 clk = ~clk;
initial
begin
updown = 1;
rst = 0;
#10;
rst = 1;
#20;
rst=0;
#43;
rst = 1;
#10;
rst = 0;
updown = 0;

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#33;
rst = 1;
end
endmodule

Block Diagram

Output Waveform

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11. SERIAL ADDER


RTL Code
module serial_adder(a,b,clk,load, sum);
input [7:0] a,b;
input clk,load;
output [8:0] sum;
reg [7:0] ina,inb;
reg [8:0] oreg;
wire c0,s0;
always@(posedge(clk))
begin
if(load == 1)
ina = a;
inb = b;
else
ina[7:0] = {1’b0,ina[7:1]};
inb[7:0] = {1’b0,inb[7:1]};
end
always@(posedge(clk))
begin
if(load == 1)
begin
oreg = 8'd0;
end
else
begin
oreg[8] = c0;
oreg[7:0] = {s0,oreg[7:1]};
end
end
assign s0 = ina[0] ^ inb[0] ^ oreg[8];
assign c0 = (ina[0] & inb[0]) | (ina[0] & oreg[8]) | (oreg[8] & inb[0]);
assign sum = oreg ;
endmodule

Test Bench Code


module serial_test_v;
reg [7:0] a;
reg [7:0] b;
reg clk;

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reg load;
wire [8:0] sum;
serial_adder my_adder(a,b,clk,load,sum);
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
load = 0;
a = 8’d100;
b = 8’d25;
#10;
load = 1;
#10;
load = 0;
#80 ;
$display("a=%d",a," b=%d", b, " sum = %d",sum);
end
endmodule

Block Diagram

Output Waveform

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12. Parallel Adder


RTL Code
module parallelAdder(a,b, sum);
input [7:0] a,b;
output reg [8:0] sum;
reg tc = 1'b0 ;
integer i;
always@(a,b)
begin
for(i = 0 ; i < 8 ; i = i + 1 )
begin
sum[i] = a[i] ^ b[i] ^ tc;
tc = ( a[i] & b[i] ) | ( a[i] & tc ) | ( tc & b[i] ) ;
end
sum[8] = tc;
end
endmodule

Test Bench Code


module parAdrTest_v;
reg [7:0] a;
reg [7:0] b;
wire [8:0] sum;
parallelAdder myAdder (a,b,sum);
initial
begin
$monitor("a=%d",a," b=%d", b, " sum = %d",sum);
//$monitor("a=%b",a," b=%b", b, " sum = %b",sum);
//this to display binary bit vector
a = $random();
b = $random();
#100;
a = $random();
b = $random();
#100;
end
endmodule

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Block Diagram

Output Waveform

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III. Analog Design


1. INVERTER
An inverter is a logic gate in digital design, which implements logical negation.
The truth table of the inverter gate in as below
Vin Vout

0 1

1 0

Schematic of The Inverter

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Test Circuit

Layout

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Graphs of Various Analyses

Transient analysis

DC Analysis

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2. COMMON SOURCE AMPLIFIER


The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a
voltage amplifier. As a transconductance amplifier, the input voltage is seen as modulating the
current going to the load. As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance according to Ohm's
law. The easiest way to tell if a FET is common source is to examine where the signal enters, and
leaves. The remaining terminal is what is known as "common". In this example, the signal enters
the gate, and exits the drain. The only terminal remaining is the source. This is a common-source
FET circuit.

Schematic

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Test Circuit

Layout

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Graphs of Various Analyses

Transient analysis

DC Analysis

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AC Analysis- Frequency

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3. COMMON DRAIN AMPLIFIER


A common-drain amplifier, also known as a source follower, is one of three basic single-
stage field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this
circuit the gate terminal of the transistor serves as the input, the source is the output, and the
drain is common to both (input and output), hence its name. The analogous bipolar junction
transistor circuit is the common-collector amplifier. In addition, this circuit is used to
transform impedances. For example, the Thévenin resistance of a combination of a voltage
follower driven by a voltage source with high Thévenin resistance is reduced to only the output
resistance of the voltage follower, a small resistance. That resistance reduction makes the
combination a more ideal voltage source. Conversely, a voltage follower inserted between a
small load resistance and a driving stage presents an infinite load to the driving stage, an
advantage in coupling a voltage signal to a small load.

Schematic

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Test Circuit

Layout

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Graphs of Various Analyses

Transient analysis

DC Analysis

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AC Analysis

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VLSI Questions
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Because we can't get full voltage swing with only NMOS or PMOS .We have to use both of them
together for that purpose.

Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for pass transistor,
both voltage levels need to be passed and hence both nmos and pmos need to be used.

What are set up time & hold time constraints? What do they signify?
Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the
signal changes state during this interval, the output of that flip-flop cannot be predictable (called
metastable).

Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If the
signal changes during this interval, the output of that flip-flop cannot be predictable (called
metastable).

Explain Clock Skew?

clock skew is the time difference between the arrival of active clock edge to different flip-flops’
of the same chip.

Why is not NAND gate preferred over NOR gate for fabrication?
NAND is a better gate for design than NOR because at the transistor level the mobility of
electrons is normally three times that of holes compared to NOR and thus the NAND is a
faster gate. Additionally, the gate-leakage in NAND structures is much lower.

What is Body Effect?


In general multiple MOS devices are made on a common substrate. As a result, the substrate
voltage of all devices is normally equal. However while connecting the devices serially this
may result in an increase in source-to-substrate voltage as we proceed vertically along the
series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

Why is the substrate in NMOS connected to Ground and in PMOS to VDD?


we try to reverse bias not the channel and the substrate but we try to maintain the drain,
source junctions reverse biased with respect to the substrate so that we don’t loose our
current into the substrate.

What is the fundamental difference between a MOSFET and BJT ?


In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-
channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a
current controlled device and MOSFET is a voltage controlled device

In CMOS technology, in digital design, why do we design the size of pmos to be higher than
the nmos. What determines the size of pmos wrt nmos. Though this is a simple question try
to list all the reasons possible?

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In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the
carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos
helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd. If
the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the

output node. If we have a larger PMOS than there will be more carriers to charge the node
quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise
and fall times for the output node.

Why PMOS and NMOS are sized equally in a Transmission Gates?


In Transmission Gate, PMOS and NMOS aid each other rather competing with each other.
That's the reason why we need not size them like in CMOS. In CMOS design we have
NMOS and PMOS competing which is the reason we try to size them proportional to their
mobility.

What happens when the PMOS and NMOS are interchanged with one
another in an inverter?

If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1
O/P will be degraded 1 Similarly degraded 0

Why are pMOS transistor networks generally used to produce high signals, while nMOS
networks are used to product low signals?
This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS
can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in
pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing.

What’s the difference between Testing & Verification?

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid
Latch Up?
A latch up is the inadvertent creation of a low-impedance path between the power supply rails of
an electronic component, triggering a parasitic structure(The parasitic structure is usually
equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning
of the part. Depending on the circuits involved, the amount of current flow produced by this
mechanism can be large enough to result in permanent destruction of the device due to electrical
over stress - EOS

What is slack?

The slack is the time delay difference from the expected delay(1/clock) to the actual
delay in a particular path. Slack may be +ve or -ve.

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Difference between Synchronous and Asynchronous reset.

What is DRC ?What is LVS ?

what are the differences between SIMULATION and SYNTHESIS ?

Simulation <= verify your design.

synthesis <= Check for your timing

Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study of ckt's
operation independent of timing parameters and gate delays. b) Timing Simulation :study including
estimated delays, verify setup, hold and other timing requirements of devices like flip flops are met.

Synthesis: One of the foremost in back end steps where by synthesizing is nothing but converting VHDL
or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit
into the target technology. Basically the synthesis tools convert the design description into equations or
components.

FPGA vs ASIC
Definitions

FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductor device containing


programmable logic components called "logic blocks", and programmable interconnects. Logic
blocks can be programmed to perform the function of basic logic gates such as AND, and XOR,
or more complex combinational functions such as decoders or mathematical functions.

ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed for a


particular use, rather than intended for general-purpose use. Processors, RAM, ROM, etc are
examples of ASICs.

Speed
ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific application they can
be optimized to maximum, hence we can have high speed in ASIC designs. ASIC can have high
speed clocks.

Cost
FPGAs are cost effective for small applications. But when it comes to complex and large volume
designs (like 32-bit processors) ASIC products are cheaper.

Size/Area
FPGA are contains lots of LUTs, and routing channels which are connected via bit
streams(program). As they are made for general purpose and because of re-usability. They are in-
general larger designs than corresponding ASIC design. For example, LUT gives you both
registered and non-register output, but if we require only non-registered output, then it’s a waste

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of having an extra circuitry. In this way ASIC will be smaller in size.

Power
FPGA designs consume more power than ASIC designs. As explained above the unwanted
circuitry results wastage of power. FPGA won’t allow us to have better power optimization.
When it comes to ASIC designs we can optimize them to the fullest.

Time to Market

FPGA designs will still take less time, as the design cycle is small when compared to that of
ASIC designs. No need of layouts, masks or other back-end processes. It’s very simple:
Specifications -- HDL + simulations -- Synthesis -- Place and Route (along with static-analysis) --
Dump code onto FPGA and Verify. When it comes to ASIC we have to do floor planning and
also advanced verification. The FPGA design flow eliminates the complex and time-consuming
floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the
design logic is already synthesized to be placed onto an already verified, characterized FPGA
device.

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Type of Design

ASIC can have mixed-signal designs, or only analog designs. But it is not possible to design
those using FPGA chips.

Customization
ASIC has the upper hand when comes to the customization. The device can be fully customized
as ASICs will be designed according to a given specification. Just imagine implementing a 32-bit
processor on a FPGA!

Prototyping
Because of re-usability of FPGAs, they are used as ASIC prototypes. ASIC design HDL code is
first dumped onto a FPGA and tested for accurate results. Once the design is error free then it is
taken for further steps. It’s clear that FPGA may be needed for designing an ASIC.

Non Recurring Engineering/Expenses

NRE refers to the one-time cost of researching, designing, and testing a new product, which is
generally associated with ASICs. No such thing is associated with FPGA. Hence FPGA designs
are cost effective.

Simpler Design Cycle

Due to software that handles much of the routing, placement, and timing, FPGA designs have
smaller designed cycle than ASICs.

More Predictable Project Cycle

Due to elimination of potential re-spins, wafer capacities, etc. FPGA designs have better project
cycle.

Tools
Tools which are used for FPGA designs are relatively cheaper than ASIC designs.

Re-Usability
A single FPGA can be used for various applications, by simply reprogramming it (dumping new
HDL code). By definition ASIC are application specific cannot be reused.

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