Lecture 7

Overview of FPGAs
 Programmable Logic
• ROM
– read only memory
– non-volatile (info not lost when powered down)
• Fixed array of 1s and 0s
• Address represents truth table entry
– index into array
– contents at that location are truth table entry
• Large look up table
– rows input
– columns output
• Originally programmed in factory
– PROM programmable ROM
– EPROM erasable PROM
• Slow, consume much power and area
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 ROM Technologies

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Source: Peter Cheung, Imperial College
 Reading
• https://www.embedded.com/electronics-
blogs/beginner-s-
corner/4023326/Introduction-to-Memory-
Types

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 PLAs and PALs
• PLA – Programmable Logic Array
– programmable AND matrix, programmable OR matrix
– SOP structures
• PAL – Programmable Array Logic
– programmable AND matrix, fixed OR matrix
– faster
• Less expensive and higher performance that ROM
• Array of fixed logic gates (AND/OR)
• Set connections – add/remove wires
– originally only possible to do once
• EPROM technology
– can program multiple times
• EEPROM Electrically erasable PROM
– even faster, chip does not have to be removed from circuit
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 PLD
• PLD Programmable Logic
Devices AND OR
– generic term for ROM PAL
matrix matrix
PLA
• CPLD Complex
Programmable Logic ROM Fixed Prog
Devices
– multiple simple PLD type
blocks on single chip
PAL Prog Fixed
• Interested in the history?
– http://www.eecg.toronto.e
du/~jayar/pubs/brown/sur
vey.pdf PLA Prog Prog

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 FPGA
• Field programmable gate array
• Xilinx went for ROM or LUT (lookup table)
approach
• 1985 XC2064 FPGA family from Xilinx
• Programmable logic units
– can be programmed to realise different digital
functions
• Programmable interconnect
– allow different blocks to be connected together
• Programmable I/O pins
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 Concept of FPGA (Chu)

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 Concept of FPGA (Brown & Rose)

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 FPGA in practice
• Logic cells configured (programmed) to
perform simple functions
• Programmable switch provides
interconnections between logic cells
• Do synthesis, use adaptor cable to
download desired configuration to FPGA
• Have your custom circuit
• All “in field”

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 LUT Logic Cell
• Logic cell comprises
small configurable
combinational circuit
with DFF
• Implement with LUT
• n-input LUT gives 2nx1
memory
• Gives n-input
combinational function
• Example a xor b xor c

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 Interconnect
• An FPGA device has a flexible
programmable routing matrix
– long lines to connect distant logic blocks
– short lines connect neighbouring blocks
– dedicated clock trees distribute
synchronization signals
– dedicated set/reset lines to reset all flip-flops
in the FPGA.

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 Macro Cells
• Extra functionality to complement logic
cells, e.g.
– Block RAMs are dedicated memory blocks that
can be used to implement in-chip data storage
– Clock management blocks
– Dedicated DSP modules containing hardware
MACs
– Dedicated high-speed serial transceivers allows
high-speed input/output. Support multiple
serial communication standards.
– Dedicated hardware CPU

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 Basys3 Board

http://www.farnell.com/datasheets/1884379.pdf?_ga=2.219266909.551518954.1549873003-
13648540.1546965210&_gac=1.213057824.1549873003.EAIaIQobChMI7Ir4rJ6z4AIVic13Ch0_5AbfEAQYASABEgLOnPD_B
wE
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 Features

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 Design Flow
• 1&2 write and test RTL – we
have been doing this
• 3 Synthesis and
implementation
– logic synthesis: translate
HDL to gates
– implement: translate, map,
place&route
– translate = turn design files
into single netlist
– map or technology
mapping, map netlist to the
FPGAs logic cells and IOBs
– P&R – physically place and
layout on FPGA, routing
• 4 Configuration file
generated for final netlist
and downloaded to FPGA
device serially to configure
logic cells and switches.
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 Watch these!
• Video from Intel:
https://www.youtube.com/watch?v=jbOj
Wp4C3V4

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 FPGA Design Flow
• Discussed in Lecture 3 that both ASIC and
FPGA design follow a standard design flow
• Exact details will be company specific
• For FPGA, extra steps specific to platform
• Until now, course has focused on design
entry and behavioural simulation
• Time to review complete design flow

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 Same Flow

Just slightly different representation!

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 Design Entry
• Designer specification of required system
• Various levels:
– Structural: instantiate gates and connect
– RTL (Register transfer level): describe circuit
by flow of signals between registers and logic
operations on signals between
– Behavioural: describe in terms of operation at
higher level
• You have used all these for your modules

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 Behavioural (RTL) Simulation
• Does the circuit do what it is meant to do?
• Testing is THE most important stage in hardware
design
• FPGAs are reprogrammable so errors not as
serious as ASIC but can still be expensive
• An error should never make it to a customer
• Automate testbenches to give automatic Pass/Fail
– iterative process
• 10% design, 90% verification

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 Simulation Strategy
• Exhaustive testing
– all combinations of input, check outputs correct
– not feasible with complex systems
• Get smart about simulation strategy
• Test at lowest level first
– LabB, test 2-bit comparator before testing 8-bit less-that
circuit
– important to partition design into modules that are
suitable test units
• Exhaustively test lower level modules
– higher level modules then eventually just testing
connectivity issues = System level testing
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 Module level verification
• After testing a module you should know:
– does the module perform as per spec
requirements?
– Are all features in spec implemented?
– Is every part of module tested?
– Are all inputs tested?
• are you assuming too much about those inputs if
coming from another block?
• unexpected inputs?
– Push module into corner conditions
• overflow in adder
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 Testbench Design
• Instantiates design/unit under test and
puts it through its paces
• Should have/be:
– Human readable inputs and outputs
– Compare outputs to expected outputs WITHIN
testbench
– Automatic pass/fail results
– Comparison to software model (C/Matlab)
useful
– Golden vectors
– Code coverage
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 Synthesis and Implementation
• Working design now ready to be mapped to FPGA
• Logic synthesis translates HDL to gates
• Need to translate design files into single netlist
• Then map netlist to the FPGAs logic cells and
IOBs
• In place and routing, you physically place and
layout design on FPGA
• Examples of steps in synthesis:
– implement implied registers, apply logic minimisation,
minimise FSMs and implement state encoding
• Examples of steps in mapping:
– decide to map logic to dedicatd resource, e.g. multipliers
and Block RAMS versus LUTs

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 Can I bypass all this?
• DSP System Generator
– Matlab to Xilinx FPGA
• System C
• More direct route from high level language
to hardware
• Trade-off faster design time for less
efficient hardware

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 Place and Route
• Arrange spatially on target device
• Related logic close together to achieve
high speeds
• Simulated annealing (a mathematical
optimisation strategy) can be used to
optimally solve routing issues
• Huge impact on performance of design

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 Compare!

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 Tools
• Vivado – Xilinx specific toolkit
• Complete design flow
• Practical– intro to Vivado and how to
target design onto FPGA

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