Soft Commutation Isolated DC-DC Converters PDF

Power Systems
Ivo Barbi · Fabiana Pöttker
Soft
Commutation
Isolated DC-DC
Converters
Power Systems
More information about this series at http://www.springer.com/series/4622
Ivo Barbi Fabiana Pöttker
•
Soft Commutation Isolated

DC-DC Converters
123
Ivo Barbi Fabiana Pöttker
Federal University of Santa Catarina Department of Electronics
Florianópolis, Santa Catarina, Brazil Federal University of Technology—Paraná
Curitiba, Paraná, Brazil
ISSN 1612-1287 ISSN 1860-4676 (electronic)

Power Systems
ISBN 978-3-319-96177-4 ISBN 978-3-319-96178-1 (eBook)
https://doi.org/10.1007/978-3-319-96178-1
Library of Congress Control Number: 2018948691
© Springer International Publishing AG, part of Springer Nature 2019

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar
methodology now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt from
the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
authors or the editors give a warranty, express or implied, with respect to the material contained herein or
for any errors or omissions that may have been made. The publisher remains neutral with regard to
jurisdictional claims in published maps and institutional affiliations.
This Springer imprint is published by the registered company Springer Nature Switzerland AG
The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
To Antônio Barbi and Adriana Barbi.
—Ivo Barbi
To my beloved husband, Douglas,
for his encouragement and support.
—Fabiana Pöttker
Preface
Power electronics can be defined as the applied science dedicated to the electrical
energy processing by the use of power semiconductors as switches. The use of
static converters in the processing and control of electrical energy matured in the
twentieth century to the point of becoming a vital technology of great economical
relevance to society. There is a number of benefits of power electronics when
compared to previous techniques including lower cost, high efficiency, high power
density, and simplicity of control.
The static power converters, according to whether the input and output are
alternating current (AC) or direct current (DC), are classified into four basic types:
DC-DC converters, AC-DC converters, DC-AC converters, and AC-AC converters.
The DC-DC converters are designed to control the power flow from a DC power
source to another. They may be unidirectional or bidirectional, isolated or not. Their
power ranges from a few watts to hundreds of kilowatts, while their voltage ranges
from a few volts to tens of kilovolts.
DC-DC converters are used in personal computers, mobiles, electrical vehicles,

lighting, railway systems, microgrids, medical equipment, avionics, and many other
applications.
To optimize the power efficiency of isolated DC-DC converters, soft commu-

tation is mandatory, particularly in high power density applications.
The aim of the authors is to present a detailed description and a quantitative

analysis of the most common unidirectional soft-commutated isolated DC-DC
converters, focusing on the soft commutation process, its quantitative and mathe-
matical analysis, and the quantification of the switching parameters.
This book evolved from the author’s long-term experience at two Brazilian
Universities: the Federal University of Santa Catarina (UFSC) and the Federal
University of Technology—Paraná (UTFPR) for graduate and undergraduate
electrical engineering students. Hence, this book provides valuable information for
vii
viii Preface
power electronics engineers, graduate and undergraduate students, as well as

researchers at universities and research institutes.
During the planning and writing of this book, we have incurred indebtedness to
many people, particularly our graduate students who for years, through successive
generations, have helped us to improve our texts, our methods of work, and
especially our way of teaching.
Florianópolis, Santa Catarina, Brazil Ivo Barbi

Curitiba, Paraná, Brazil Fabiana Pöttker
June 2018
Acknowledgements
Ivo Barbi would like to thank and acknowledge valuable support provided by José
Airton Beckhäuser Filho, Leonardo Freire Pacheco, Guilherme Martins Leandro,
and Ygor Pereira Marca.
Fabiana Pöttker acknowledges the support of the Federal University of
Technology—Paraná, for providing sufficient time and a three-month sabbatical to
work on this book.
ix
Contents
1 Basic Electric Circuits with Switches . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 RC and RL DC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 RC DC Circuit with a Series Thyristor . . . . . . . . . . . . 2
1.2.2 RL DC Circuit with a Series Thyristor . . . . . . . . . . . . 3
1.2.3 RL DC Circuit with a Series Switch and Free
Wheel Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
1.3 Inductor DC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6
1.3.1 Inductor DC Circuit with a Series Switch, Free-Wheel
Diode and Energy Recovery . . . . . . . . . . . . . . . . . . .. 6
Diode and Energy Recovery Transformer . . . . . . . . . . 7
1.4 Constant Current Capacitor Charging Circuit . . . . . . . . . . . . . . 10
1.5 LC and RLC DC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.1 LC DC Circuit with a Series Switch . . . . . . . . . . . . . . 11
1.5.2 LC DC Circuit with a Series Thyristor . . . . . . . . . . . . 15
1.5.3 Capacitor Voltage Polarity Inversion Circuit . . . . . . . . 16
1.5.4 Capacitor Charging Circuits . . . . . . . . . . . . . . . . . . . . 17
1.5.5 RLC Circuit with a Low Dumping Factor . . . . . . . . . . 21
1.5.6 LC Circuit with Voltage and Current Source . . . . . . . . 22
1.6 Solved Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2 Series Resonant Converter . . . . . . . . . . . . . . . . . . . . . . ......... 33
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......... 35
2.2 Circuit Operation in Continuous Conduction Mode . ......... 36
2.3 Mathematical Analysis for Operation in Continuous
Conduction Mode . . . . . . . . . . . . . . . . . . . . . . . . . ......... 39
2.3.1 Time Interval Dt1 . . . . . . . . . . . . . . . . . . . ......... 40
2.3.2 Time Interval Dt2 . . . . . . . . . . . . . . . . . . . ......... 41
xi
xii Contents
2.3.3 Normalized State Plane for One Half of the

Switching Period . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
2.3.4 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . .. 43
2.4 Analysis of the Series Resonant Converter Based in the First
Harmonic Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . .. 47
2.5 Simplified Numerical Example for Calculation of Lr and Cr . .. 53
2.6 Operation in Discontinuous Conduction Mode . . . . . . . . . . . .. 57
2.7 Mathematical Analysis for Operation in Discontinuous
Conduction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
2.8 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 68
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 69
3 Half Bridge Capacitor Voltage-Clamped Series
Resonant Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.2 Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3 Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3.1 Time Interval Dt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.2 Time Interval Dt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.3.3 State Plane Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.3.4 DCM Constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.3.5 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.3.6 Normalized Output Power . . . . . . . . . . . . . . . . . . . . . . 82
3.3.7 Switches RMS Current . . . . . . . . . . . . . . . . . . . . . . . . 82
3.3.8 Clamping Diodes Average Current . . . . . . . . . . . . . . . 83
3.4 CVC-SRC Topological Variations . . . . . . . . . . . . . . . . . . . . . . 84
3.5 Design Example and Methodology . . . . . . . . . . . . . . . . . . . . . 85
3.6 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4 Half Bridge CVC-PWM Series Resonant Converter . . . . . . . . . . . . 93
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3.1 Time Interval Dt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.2 Time Interval Dt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.3.3 Time Interval Dt3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.3.4 Time Interval Dt4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3.5 Normalized State-Plane Trajectory . . . . . . . . . . . . . . . . 104
4.3.6 DCM Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Contents xiii
4.4 Numerical Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5 Series Resonant Converter Operating Above the
Resonant Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.4 Commutation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.5 Numerical Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6 LLC Resonant Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.2 First Harmonic Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . 142
6.3 Voltage Gain Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.1 Numerical Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.4 Static Gain Without Load (Open Circuit) . . . . . . . . . . . . . . . . . 151
6.5 Static Gain as a Function of Load Resistance . . . . . . . . . . . . . . 152
6.6 Minimum Normalized Frequency . . . . . . . . . . . . . . . . . . . . . . . 155
6.7 Commutation’s Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.7.1 Current in the Switches During Commutation . . . . . . . 159
6.7.2 Commutation Analysis . . . . . . . . . . . . . . . . . . . . . . . . 162
6.8 Input Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.9 Resonant Capacitor Current and Voltage . . . . . . . . . . . . . . . . . 170
6.10 Design Methodology and Example . . . . . . . . . . . . . . . . . . . . . 174
6.11 Detailed Description of the LLC’s Operation Modes . . . . . . . . . 178
6.11.1 Operation at the Resonance Frequency (fs = fr1) . . . . . . 178
6.11.2 Operation Below Resonant Frequency (fs < fr1) . . . . . . 180
6.11.3 Operation Above Resonant Frequency (fs > fr1) . . . . . . 182
6.12 Summary of Properties of the LLC Converter . . . . . . . . . . . . . . 184
6.13 Proposed Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
7 Full-Bridge ZVS-PWM Converter with Capacitive
Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.2.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . 191
7.2.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . 195
xiv Contents

7.3.1 Commutation Currents . . . . . . . . . . . . . . . . . . . . . . . . 198
7.3.3 RMS Inductor Current . . . . . . . . . . . . . . . . . . . . . . . . 206
7.4.1 Continuous Conduction Mode (CCM) . . . . . . . . . . . . . 208
7.4.2 Discontinuous Conduction Mode (DCM) . . . . . . . . . . . 210
7.5 Simplified Design Methodology and an Example of the
Commutation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8 Full-Bridge ZVS-PWM Converter with Inductive Output Filter . . . 219
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.2 Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.3.1 Leading Leg Commutation . . . . . . . . . . . . . . . . . . . . . 227
8.3.2 Lagging Leg Commutation . . . . . . . . . . . . . . . . . . . . . 228
8.4.2 RMS Switches Current . . . . . . . . . . . . . . . . . . . . . . . . 234
8.4.3 Average Diodes Current . . . . . . . . . . . . . . . . . . . . . . . 235
8.5 Simplified Design Example and Methodology . . . . . . . . . . . . . 235
8.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9 Three-Level Neutral Point Clamped ZVS-PWM Converter . . . . . . 245
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
10 Asymmetric Half-Bridge ZVS-PWM Converter . . . . . . . . . . . . . . . 271
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Contents xv

10.4.1 Switch S1 Commutation . . . . . . . . . . . . . . . . . . . . . . . 282
10.4.2 Switch S2 Commutation . . . . . . . . . . . . . . . . . . . . . . . 285
10.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
11 Active Clamp ZVS-PWM Forward Converter . . . . . . . . . . . . . . . . 297
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
11.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Abbreviations
CCM Continuous conduction mode

CVC Capacitor voltage clamped
DC Direct current
DCM Discontinuous conduction mode
FB Full bridge
HB Half bridge
LC Inductor capacitor
LCT Inductor capacitor thyristor
PFM Pulse frequency modulation
PWM Pulse width modulation
RC Resistor capacitor
RCT Resistor capacitor thyristor
RL Resistor inductor
RLC Resistor inductor capacitor
SRC Series resonant converter
ZCS Zero current switching
ZVS Zero voltage switching
xvii
Chapter 1
Basic Electric Circuits with Switches
Nomenclature
Vi Input DC voltage
E1 DC voltage
vC Capacitor voltage
iC Capacitor current
vL Inductor voltage
vR Resistor voltage
vS Switch voltage
k Time constant
S Switch
D Diode
T, T1 and T2 Thyristors
Io and iL(∞) Steady state inductor current
vL(∞) and vR(∞) Steady state inductor and resistor voltages, respectively
W Energy
tf Energy recovery time interval
N1 and N2 Transformer primary and secondary windings, respectively
Lm Transformer magnetizing inductance
L0m Transformer magnetizing inductance referred to the secondary
winding
v1 and v2 Transformer primary and secondary voltages, respectively
Δt1 and Δt2 Time interval 1 and 2, respectively
i1 and i2 Currents at time interval 1 and 2, respectively
I1 and I2 Initial currents at time interval 1 and 2, respectively
V1 Input DC voltage referred to the transformer secondary
winding
VC0 and IL0 Capacitor and inductor initial conditions, respectively
© Springer International Publishing AG, part of Springer Nature 2019 1

I. Barbi and F. Pöttker, Soft Commutation Isolated DC-DC Converters,
Power Systems, https://doi.org/10.1007/978-3-319-96178-1_1
2 1 Basic Electric Circuits with Switches
1.1 Introduction
In this chapter, basic electric circuits with switches are presented and analyzed as a
basic knowledge for the next chapters, in which the static converters topological
states, for every time interval, are represented by first and second order equivalent
electric circuits. Furthermore, in the mathematical analysis, all semiconductors are
considered ideal.
1.2 RC and RL DC Circuits
In this section, RC and RL DC circuits with switches, diodes and thyristors are
analyzed.
1.2.1 RC DC Circuit with a Series Thyristor
The electric circuit studied in this section is in Fig. 1.1.

At the time t = 0 s the thyristor is fired, so the voltage source Vi is connected in
series with the RC circuit. As there is only one energy storage device, this is a first
order circuit. Considering that the capacitor voltage initial condition is zero
(vC(0) = 0), (1.1) and (1.2) may be written.
Vi ¼ vC ðt) þ RiC ðt) ð1:1Þ
dvC ðt)
iC ðt) ¼ C ð1:2Þ
dt
Substituting (1.2) in (1.1) gives
dvC ðt)
Vi ¼ vC ðt) þ RC ð1:3Þ
dt
Fig. 1.1 Series RCT circuit T iC

+
R vR
+
Vi -
-
+
C vC
-
1.2 RC and RL DC Circuits 3
(a) (b)
Vi Vi
R
vC
iC
0 0
0 t 0 t
Fig. 1.2 Capacitor voltage and current waveforms
Solving (1.3), it is found

vC ðt) ¼ Vi 1 ek
t
ð1:4Þ
The capacitor current is given by
dvc ðtÞ Vi t
iC ðt) = C ¼ e k ð1:5Þ
dt R
where k = RC is the circuit time constant.

The capacitor voltage and current waveforms are shown in Fig. 1.2. First the
capacitor is initially discharged, so the voltage Vi is applied to the resistor and the
current is equal to Vi/R. As the capacitor is charged, the current decreases. When
the current reaches zero in steady state (approximately at t = 5k), the thyristor
spontaneously turns off.
1.2.2 RL DC Circuit with a Series Thyristor
The electric circuit studied in this section is shown in Fig. 1.3.

At the instant t = 0 s the thyristor is triggered, then the voltage source Vi is
connected to the series RL circuit. As the inductor is the only energy storage device,
this is also a first order circuit. Considering that the inductor current initial condition
is zero (iL (0) = 0), (1.6) and (1.7) are obtained.
Vi = vL ðt) + R iL ðt) ð1:6Þ

Fig. 1.3 Series RLT circuit iL

T
+
L vL
+
Vi -
-
+
R vR
-
diL ðt)
vL ðt) = L ð1:7Þ
dt
Substituting (1.7) into (1.6) gives
diL ðt)
Vi = L + R iL ðt) ð1:8Þ
dt
Solving (1.8) the inductor current and voltage are found and given by (1.9) and
(1.10) respectively.
Vi
1 ek
t
iL ðt) ¼ ð1:9Þ
R
diL ðt) t
vL ðt) ¼ L ¼ Vi e k ð1:10Þ
dt
where k = L/R is the circuit time constant.

The inductor voltage and current waveforms are shown in Fig. 1.4.
(a) (b)
Vi
Vi
R
iL
vL
0 0
0 t 0 t
Fig. 1.4 Inductor voltage and current waveforms

1.2 RC and RL DC Circuits 5
1.2.3 RL DC Circuit with a Series Switch and Free

Wheel Diode
The electric circuit studied in this section is illustrated in Fig. 1.5.

In the time interval 1 the switch S is closed and the diode D is reverse biased by
the input voltage Vi. Current flows through switch S, the resistor and inductor, as
presented in Fig. 1.6a. Therefore, Eqs. (1.11), (1.12) and (1.13) define the steady
state condition (t 5k, where k = L/R) for this time interval.
Vi
i L ð 1Þ ¼ I 0 ¼ ð1:11Þ
R
vL ð1Þ ¼ 0 ð1:12Þ
vR ð1Þ ¼ Vi ð1:13Þ
At the instant t = 0 s switch S is turned off. The diode D is forward biased by the
inductor, initiating the time interval 2, known as the free-wheeling time interval, as
shown in Fig. 1.6b. Equation (1.14) may be written for this time interval.
diL ðt)
L þ RiL ðt) ¼ 0 ð1:14Þ
dt
S iL
+
+ L vL
Vi D -
- +
R vR
-
Fig. 1.5 RL DC circuit with a series switch and free wheel diode
S iL S iL
(a) (b)
+ +
+ L vL + L vL
Vi D - Vi D -
- + - +
R vR R vR
- -
Fig. 1.6 RL DC circuit with a series switch and free wheel diode: a topological state for time
interval 1, b topological state for time interval 2
Solving (1.14) gives
iL ðt) ¼ Io ek
t
ð1:15Þ
During the free-wheeling time interval, the energy accumulated in the inductor L
is dissipated in the resistor R. The inductor demagnetization time depends on the
value of resistance R. The higher the resistance, the faster the inductor
demagnetization.
The total amount of energy dissipated in the resistor is given by
1
W ¼ LI2o ð1:16Þ
2
If there was no free wheel diode, an unpredictable overvoltage across the switch
S could be produced at the instant it is turned off.
1.3 Inductor DC Circuits
In this section, inductor DC circuits with switches, diodes and transformers are
analyzed.

Diode and Energy Recovery
In many applications, due to efficiency constrains, it is important to recover the

energy accumulated in the inductor. A basic circuit that enables this recovery is
shown in Fig. 1.7.
During the time interval 1 switch S is closed and energy is stored in the inductor,
as presented in Fig. 1.8a.
At the instant t = 0 s the switch S is turned off and the inductor current is
iL(0) = I0. Diode D is forward biased by the inductor, initiating the free-wheeling
time interval, as shown in Fig. 1.8b. Equation (1.17) represents the time interval in
which the energy accumulated in the inductor is transferred to the voltage source E1.
Fig. 1.7 Inductor DC circuit S iL

with a series switch, a
free-wheel diode and energy D
+ +
recovery
Vi L vL
- -
E1 -
+
1.3 Inductor DC Circuits 7
S iL S iL
(a) (b)
D + D +
+ +
Vi L vL Vi L vL
- - - -
E1 - E1 -
+ +
Fig. 1.8 Inductor DC circuit with a series switch, a free-wheel diode and energy recovery:
a topological state for time interval 1, b topological state for time interval 2
diL ðt)
L ¼ E1 ð1:17Þ
dt
Solving (1.17) gives
E1
iL ðt) ¼ Io t ð1:18Þ
L
At the instant t = tf, given by (1.19), the inductor current reaches zero.
According to this expression, the larger voltage E1, the lower the energy recovery
time interval (tf).
LIo
tf ¼ ð1:19Þ
E1

Diode and Energy Recovery Transformer
Another circuit to recover the energy accumulated in an inductor is presented in

Fig. 1.9. The transformer recovers the inductor energy to the input voltage source
Vi. This technique is usually utilized in some isolated DC-DC circuits, such as the
forward converter, to demagnetize the transformer.
Fig. 1.9 DC circuit with a D

series switch, a free-wheel
diode and energy recovery
transformer
S
+
Vi N1 N2
-
Considering an ideal transformer (no leakage inductance or parasitic resistance)

the equivalent circuit is shown in Fig. 1.10, with the magnetizing inductance
referred to the primary side of the transformer.
In the time interval 1, shown in Fig. 1.11, switch S is turned on and energy is
transferred from the input source Vi to the transformer magnetizing inductance.
Also, the diode D is reverse biased by the transformer secondary voltage.
When switch S is turned off, time interval 2 begins. At this time interval, the
transformer magnetizing inductance is referred to the secondary side, as illustrated
in Fig. 1.12. Then, diode D is forward biased by the transformer secondary voltage
and the energy accumulated in the transformer magnetic field is delivered to the
input voltage Vi.
The currents i1 and i2 for the time interval 1 (Dt1) and 2 (Dt2), respectively, are
presented in Fig. 1.13, as well as the voltage across the switch S (vS).
The initial currents I1 and I2 are given by
Vi
I1 ¼ DT1 ð1:20Þ
Lm
N1
I2 ¼ I1 ð1:21Þ
N2
The expression for the current in the time interval 2 is given by
Vi
i2 ðt) ¼ I2 t ð1:22Þ
L0m
Fig. 1.10 Equivalent circuit S D

+ +
Vi Lm N1 N2 Vi
- -
Fig. 1.11 Topological state S i1 D

for time interval 1 + -
+ + vS - +
Vi Lm v1 v2 Vi
- -
- +
N1 N2
Fig. 1.12 Topological state S i2 D

for time interval 2 -
+ + vS - + +
Vi v1 v2 Lm’ Vi
- -
- +
N1 N2
1.3 Inductor DC Circuits 9
Fig. 1.13 Currents i1 and i2

and voltage vS I1
I2 i2
i1
Δt1 Δt2 t
vS
Vi
⎛ N1 ⎞
Vi ⎜⎜1 + ⎟
⎝ N2 ⎟⎠
At the end of time interval 2 the current reaches zero. Thus
Vi
0 ¼ I2 DT2 ð1:23Þ
L0m
Substituting (1.21) into (1.23), (1.24) it is obtained
N1 Vi
I1 0 DT2 ¼ 0 ð1:24Þ
N2 Lm
Referring the magnetizing inductance to the primary side of the transformer

gives
N1 Vi DT2 N21
I1 ¼ ð1:25Þ
N2 Lm N22
Substituting (1.20) into (1.25), (1.26) is found
Vi N1
Lm DT1 ¼ Vi DT2 ð1:26Þ
Lm N2
Hence,
N2
DT2 ¼ DT1 ð1:27Þ
N1
The energy recovery time DT2 may be adjusted according to the transformer
turns ratio, according to expression (1.27).
During the time interval 2 the voltage across switch S is given by
vS ¼ ð Vi + V1 Þ ð1:28Þ
where
N1
V1 ¼ Vi ð1:29Þ
N2

N1
vS ¼ 1 þ Vi ð1:30Þ
N2
After the end of the interval 2 the current is zero and the voltage across switch S
is vS ¼ Vi .
1.4 Constant Current Capacitor Charging Circuit
A constant current capacitor charging circuit is provided in Fig. 1.14. In the time
interval 1 shown in Fig. 1.15a switch S is opened. The capacitor voltage is vc = 0
and the current I flows through diode D. At the instant t = 0 s switch S is turned on
then the diode D turns off and the current I starts to flow through capacitor C, as
shown in Fig. 1.15b, charging it with a constant current.
During the time interval 2 the capacitor voltage is stated as
I
vC ðt) ¼ t ð1:31Þ
C
S C
+ -
+ vC
Vi D I
-
Fig. 1.14 Constant current capacitor charging circuit
(a) S C (b) S C
+ - I + -
+ vC +
vC
Vi D I Vi D I
- -
Fig. 1.15 Constant current capacitor charging circuit: a topological state for time interval 1,
b topological state for time interval 2
1.4 Constant Current Capacitor Charging Circuit 11
Fig. 1.16 Voltage across vC

capacitor C
Vi
Δt2 t
When vC (t) = Vi the diode D is forward biased and turned on. The capacitor
remains charged with the voltage Vi. The time interval 2 is calculated as follows.
Vi C
Dt2 ¼ ð1:32Þ
I
The capacitor voltage waveform is shown in Fig. 1.16.
1.5 LC and RLC DC Circuits
In this section, LC and RLC DC circuits with switches and thyristors are analyzed.
1.5.1 LC DC Circuit with a Series Switch
The LC DC circuit with a series switch is demonstrated in Fig. 1.17. The initial
conditions are vC ð0Þ ¼ VCo and iL ð0Þ ¼ ILo .
At the instant t = 0 s switch S is turned on and the following equations may be
written:
diL ðt)
Vi ¼ vC ðt) þ L ð1:33Þ
dt
dVC ðt)
iL ðt) ¼ C ð1:34Þ
dt
Fig. 1.17 LC DC circuit with

S C iL L
a series switch
+ + - + -
vC vL
Vi
-
d2 vC ðt)
Vi ¼ vC ðt) þ LC ð1:35Þ
dt2
Solving (1.35), it can be obtained (1.36) and (1.37).

rffiffiffiffi
L
vC ðt) ¼ ðVi VCo Þ cosðxo tÞ þ ILo senðxo tÞ þ Vi ð1:36Þ
C
rffiffiffiffi rffiffiffiffi
L L
iL ðt) ¼ ðVi VCo Þ senðxo tÞ þ ILo cosðxo tÞ ð1:37Þ
C C
Multiplying (1.37) by “j” and adding to (1.36) we obtain

rffiffiffiffi
L
vC ðt) þ j iL ðt) ¼ ðVi VCo Þ½cosðxo tÞ jsenðxo tÞ
C
rffiffiffiffi
L
þ jILo ½cosðxo tÞ j senðxo tÞ þ Vi ð1:38Þ
C
where xo ¼ p1ffiffiffiffi
LC
ffi.
Let us define zðtÞ and z1 as follows:
rffiffiffiffi
L
z(t) ¼ vC ðt) þ j iL ðt) ð1:39Þ
C
rffiffiffiffi
L
z1 ¼ ðVi VCo Þ þ jILo ð1:40Þ
C
Since
ejxo t ¼ cosðxo tÞ j sen ðxo tÞ ð1:41Þ
z(t) can be rewrite as
z(t) ¼ z1 ej xo t þ Vi ð1:42Þ
(A) Particular Cases

(A:1) VCo = 0, ILo = 0, Vi 6¼ 0
According to initial conditions of this particular case, using the previous
equations we find
1.5 LC and RLC DC Circuits 13
z1 ¼ Vi ð1:43Þ
At the instant t = 0 s we have z ð0Þ ¼ 0.

Thus,
z(t) ¼ Vi ej xo t þ Vi ð1:44Þ
The state plane representation of this particular case is shown in Fig. 1.18.
(A:2) ILo = 0, Vi = 0, VCo > 0
With these initial conditions and the previous equations, we have
z1 ¼ VCo ð1:45Þ
z(t) ¼ VCo ð1:46Þ
z(t) ¼ VCo ej xo t ð1:47Þ
The normalized state plane of this particular case is shown in Fig. 1.19.
(A:3) VCo = Vi = 0, ILo > 0
With these initial conditions, Eqs. (1.48), (1.49) and (1.50) can be found.
rffiffiffiffi
L
z1 ¼ jILo ð1:48Þ
C
rffiffiffiffi
L
z(0) ¼ jILo ð1:49Þ
C
Fig. 1.18 State plane

L
representation for
VCo = ILo = 0 and Vi 6¼ 0
iL
C
z1
ωo t
0
z (0)
0 Vi 2Vi
vC
Fig. 1.19 Normalized state

plane for ILo = 0, Vi = 0 and L
VCo > 0 iL
C
z (0)
0
ωo t
z1
0 VCo
vC

representation for L z (0)
VCo = Vi = 0 and ILo > 0 iL
C
ωo t
0
z1
0 vC
rffiffiffiffi
L j xo t
z(t) ¼ jILo e ð1:50Þ
C
The corresponding state plane representation of this particular case is shown in

Fig. 1.20.
Regardless of the particular cases presented above we have
vC ðt) ¼ Refz(t)g ð1:51Þ

rffiffiffiffi
L
iL ðt) ¼ Imfz(t)g ð1:52Þ
C
Substituting z(t) into (1.51) and (1.52) yields

vC ðt) ¼ Re z1 ej xo t þ Vi ð1:53Þ
rffiffiffiffi
L
iL ðt) ¼ Im z1 ejxo t ð1:54Þ
C
1.5.2 LC DC Circuit with a Series Thyristor
The LC DC circuit with a series thyristor is illustrated in Fig. 1.21. The initial
conditions are vC ð0Þ ¼ 0 and iL ð0Þ ¼ 0. At the instant t = 0 s the thyristor T is
gated on. The corresponding normalized state plane trajectory of the capacitor
voltage and the inductor current is shown in Fig. 1.22. The capacitor voltage and
inductor current waveforms are presented in Fig. 1.23.
At the instant t ¼ xpo , the inductor current reaches zero and the thyristor naturally
turns off. At this instant the capacitor is charged and its voltage is equal to 2Vi.
The following equations represent the capacitor voltage and the inductor current
as function of time, respectively:
vC ðt) ¼ Vi cos ðxo tÞ þ Vi ð1:55Þ
Fig. 1.21 LC DC circuit with

T C iL L
a series thyristor
+ + -
vC
Vi
-
Fig. 1.22 Normalized state

L
plane for the LCT circuit iL
C π/2
Vi
ωo t
0
0 Vi 2Vi
vC
(a) (b)
2Vi Vi
vC L
iL
C
Vi
0
0
0 π/2 π 0 π/2 π
t [rad] t [rad]
Fig. 1.23 Capacitor voltage (a) and inductor current (b) waveforms
rffiffiffiffi
L
iL ðt) ¼ Vi sen ðxo tÞ ð1:56Þ
C
1.5.3 Capacitor Voltage Polarity Inversion Circuit
A capacitor voltage polarity inversion circuit is shown in Fig. 1.24.

At t = 0 s the thyristor is triggered. The capacitor initial voltage is vC ð0Þ ¼ Vo .
The state plane trajectory is provided in Fig. 1.25, also the capacitor voltage and
inductor current waveforms are shown in Fig. 1.26. At the instant the inductor
p
current reaches zero the capacitor voltage is vC xo = +Vo , with inverted polarity
in relation to the initial voltage.
Fig. 1.24 Capacitor voltage

T iL
polarity inversion circuit
L +
C vC
-
L
iL π /2
C
ωot
0
-Vo 0 Vo
vC
Fig. 1.25 State plane trajectory for the circuit shown in Fig. 1.24
(a) (b)
Vo Vo
vC
L
iL
C
0
-Vo 0
0 π/2 π 0 π/2 π t [rad]
t [rad]
Fig. 1.26 Capacitor voltage (a) and inductor current (b) waveforms
1.5.4 Capacitor Charging Circuits
(A) First Circuit

The circuit analyzed in this section is shown in Fig. 1.27.
Thyristor T1 and T2 are gated on at a switching frequency lower than the
resonant frequency. The capacitor voltage and the inductor current waveforms
are shown in Fig. 1.28 and the state plane trajectory is presented in Fig. 1.29.
To simplify, all components are considered ideal. Consequently, the circuit
damping factor is zero and the energy transferred to the capacitor rises over
time indefinitely (at least theoretically).
Fig. 1.27 Capacitor charging T1 T2

circuit
vC + C
+ -
Vi
- iL L
(a) (b)
4Vi
vC 3Vi
2Vi L
iL
C Vi
0 0
-2Vi -2Vi
-4Vi -4Vi
0 π 2π 3π 4π 0 π 2π 3π 4π
t [rad] t [rad]
Fig. 1.28 Capacitor voltage (a) and parameterized inductor current (b) waveforms over time
Fig. 1.29 State plane 4Vi

trajectory for the circuit L
shown in Fig. 1.27
iL
C
2Vi
-2Vi
-4Vi
-4Vi -2Vi 0 2Vi 4Vi
vC
(B) Second Circuit

Now, analyzing the operation of the circuit shown in Fig. 1.30, with initial
conditions VCo < 0 and ILo = 0. At t = 0 s, T1 is gated on. The capacitor
voltage and current evolves over time and before the current reaches zero T2
turned on, switching off T1. Therefore, energy is transferred from the input
Fig. 1.30 Capacitor charger +

vC C
circuit -
iL L T1
+
Vi
-
T2
voltage source Vi to the capacitor C, rising its voltage above Vi. The capacitor
voltage and inductor current waveforms are shown in Fig. 1.31.
During the time interval T1 is closed, the capacitor voltage is given by
vC ðt) ¼ VCo cos ðxo tÞ ð1:57Þ
At the end of this interval the capacitor voltage and current are given by
Eqs. (1.58) and (1.59) respectively.
V1 ¼ VCo cos ðxo sÞ ð1:58Þ

rffiffiffiffi
L
I1 ¼ VCo sen ðxo sÞ ð1:59Þ
C
When T2 is turned on we have

rffiffiffiffi
L
z1 ¼ ðV1 Vi Þ þ jI1 ð1:60Þ
C
(a) (b)
vC L
iL
Vf C
VC1
L
I1
C
0 0
-VCo
0 π/2 ωoτ π ωota 0 π/2 ωoτ π ωota
t [rad] t [rad]
Fig. 1.31 Capacitor voltage (a) and inductor current (b) waveforms for the circuit shown in
Fig. 1.30
rffiffiffiffi
L
z(0) ¼ V1 þ jI1 ð1:61Þ
C
At the end of this time interval the capacitor voltage is given by
V f ¼ V i þ j z1 j ð1:62Þ
Substituting (1.58) and (1.59) into (1.60) yields
jz1 j2 ¼ ðVCo cos ðxo sÞ Vi Þ2 þ V2Co sen2 ðxo sÞ ð1:63Þ

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Vf ¼ Vi þ ðVCo cos ðxo sÞ Vi Þ2 þ V2Co sen2 ðxo sÞ ð1:64Þ
According to Eq. (1.64) the capacitor voltage is controlled by the angle xos. In
the particular case which xos = p, the capacitor final voltage value (Vf) is given by
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Vf ¼ Vi þ ðVCo Vi Þ2 ¼ Vi Vi VCo ð1:65Þ
or,
Vf ¼ VCo ð1:66Þ
This circuit is used in auxiliary commutation circuits as well as in resonant

converters. The state plane trajectory is shown in Fig. 1.32.

trajectory for the circuit L
shown in Fig. 1.31 iL
C
L
i1
C
ωoτ z(0)
0
-VCo 0 VC1 Vf
vC
1.5.5 RLC Circuit with a Low Dumping Factor
Let us consider the circuit shown in Fig. 1.33. The capacitor current and voltage are
given by (1.67) and (1.68) respectively.
Vi Vo a t xo
iC ðt) ¼ e senðxt) Io ea t senðxt cÞ ð1:67Þ
xL x
x a t Io a t
vC ðt) ¼ Vi ðVi Vo Þ e senðxt + cÞ þ e senðxt) ð1:68Þ
xo xC
where
1
xo ¼ pffiffiffiffiffiffiffi ð1:69Þ
LC
R
a¼ ð1:70Þ
2L
x
c ¼ arc tg ð1:71Þ
a
x2 ¼ x2o a2 ð1:72Þ
Assuming that the circuit quality factor is high, what is true for very small losses,
we have
xo ffi x ð1:73Þ
Let
rffiffiffiffi
L 1
X¼ ¼ xL ffi ð1:74Þ
C xC
X
w¼ ð1:75Þ
R
a R 1
¼ ¼ ð1:76Þ
x 2xL 2w
Fig. 1.33 RLC circuit with a C L R

low dumping factor
+ -
+ vC
Vi iC
-
p
c¼ ð1:77Þ
2
sen(xt cÞ ¼ cos(xt) ð1:78Þ
Manipulating Eqs. (1.74), (1.75), (1.76), (1.77) and (1.78) gives

Vi Vo xt
iL ðt) ¼ sen ðxt) þ Io cos ðxt) e2 w ð1:79Þ
X
and
xt
vC ðt) ¼ Vi þ ½X Io sen ðxt) ðVi Vo Þ cos ðxt) e2 w ð1:80Þ
xt
where e2w ¼ eat can be represented by the series
a2 t2 a3 t3
ea t ¼ 1 at þ ð1:81Þ
2 6
For small values of a the following statement is true
eat ¼ 1 at ð1:82Þ
We know that
rffiffiffiffi
L
C
Consequently, with appropriate algebraic manipulation it is found
z(t) ¼ Vi þ z1 ejxt eat ð1:84Þ
In an ideal circuit a ¼ 0, so the Eq. (1.84) becomes equal to Eq. (1.42).
1.5.6 LC Circuit with Voltage and Current Source
A LC circuit with voltage and current sources is shown in Fig. 1.34.
Fig. 1.34 LC circuit with iL L

voltage and current sources
+ + vL - iC
Vi vC
+ I
-
- C
Applying Kirchhoff’s voltage and current law in the circuit, we obtain
Vi ¼ vL ðt) þ vC ðt) ð1:85Þ
and
iL ðt) ¼ iC ðt) þ I ð1:86Þ
The instantaneous inductor voltage and capacitor current are given by

diL ðt) dðI + iC ðt)Þ diC ðt)

vL ðt) ¼ L ¼L ¼L ð1:87Þ
dt dt dt
dvC ðt)
iC ðt) ¼ C ð1:88Þ
dt
Substituting (1.88) into (1.87) yields
d2 vC ðt)
vL ðt) ¼ LC ð1:89Þ
dt2
Replacing (1.89) into (1.85) leads to
d2 vC ðt)
Vi ¼ LC þ vC ðt) ð1:90Þ
dt2
Rearranging Eq. (1.90) gives
d2 vC ðt) vC ðt) Vi
2
þ ¼ ð1:91Þ
dt L C L C
The solution of the differential Eq. (1.91) yields

rffiffiffiffi
L
vC ðt) ¼ ðVCo Vi Þ cosðxo tÞ þ ðILo IÞ sen ðxo tÞ þ Vi ð1:92Þ
C
Substitution of Eq. (1.92) into (1.88) and (1.87), with appropriate algebraic
manipulations gives
rffiffiffiffi rffiffiffiffi rffiffiffiffi

L L L
iL ðt) ¼ ðVCo Vi Þ sen ðxo tÞ þ ðILo IÞ cos ðxo tÞ þ I ð1:93Þ
C C C
The value of zðtÞ is given by

rffiffiffiffi
L
C
qffiffiffiffi
L
Replacing C iL ðtÞ and vC ðtÞ, that were obtained in Eqs. (1.92) and (1.93), into
Eq. (1.94), gives
rffiffiffiffi ! " rffiffiffiffi #
L L
z(t) ¼ Vi þ j I þ ðVCo Vi Þ + j ðILo IÞ ej xo t ð1:95Þ
C C
The quantities of zo and z1 are given by Eqs. (1.96) and (1.97):

rffiffiffiffi
L
zo ¼ Vi þ j I ð1:96Þ
C
rffiffiffiffi
L
z1 ¼ ðVCo Vi Þ þ j ðILo IÞ ð1:97Þ
C
Substitution of (1.96) and (1.97) into (1.95) gives
z(t) ¼ zo þ z1 ej wo t ð1:98Þ
The state plane trajectory is illustrated in Fig. 1.35.

L
trajectory for the circuit iL
shown in Fig. 1.34 C
z1
L
I
C z(0)
0
0 Vi vC
Fig. 1.36 Parallel LC circuit iC iL

connected to a DC current +
source -
I vC L vL
+ C
-
(A) First Particular Case: I = 0

Assuming that I = 0, it can be obtained Eq. (1.99) from Eq. (1.97).
" rffiffiffiffi #
L
z(t) ¼ Vi þ ðVCo Vi Þ þ j ILo ej xo t ð1:99Þ
C
This particular case was analyzed in Sect. 1.2.1 of this Chapter.

Second Particular Case: Vi = 0
Making Vi = 0 and substituting in Eq. (1.97) yields
rffiffiffiffi " rffiffiffiffi #
L L
z(t) ¼ j I þ ðVCo Vi Þ + j ðILo IÞ ej wt ð1:100Þ
C C
Equation (1.100) represents the behavior of a circuit constituted by the parallel

association of a capacitor C, an inductor L and a current source I, illustrated in
Fig. 1.36.
1.6 Solved Problem
The circuit is presented in Fig. 1.37. Assume that the thyristor T is gated on at the
instant t = 0 s. The parameters of the circuit are L = 30 lH, C = 120 lF and
VCo(0) = −75 V. Find the equations for i(t), vL(t), vC(t) and iD(t) and plot them as a
function of time.
Fig. 1.37 Exercise 3 T iD

i + D
vL L
Vi + - E1
100V - +
75V
-
+
vC C
-
Fig. 1.38 First time interval T iD

equivalent circuit
i + D
vL L
Vi + - E1
100V - + 75V
-
+
vC C
-
First Time Interval (0 t t1): The equivalent circuit for this interval is
shown in Fig. 1.38. It is a second order LC circuit. Substituting the values of C, L
and VCo(0) in Eqs. (1.36) and (1.37) we find
vC ðt) ¼ Vi þ ðVCo Vi Þcosðxo tÞ ¼ 100 175 cos ðxo tÞ

rffiffiffiffiffi
L
iðtÞ ¼ ðVCo Vi Þ sinðxo tÞ ¼ 175 sinðxo tÞ
C
vL ðt) ¼ VC ðtÞ + Vi = 175 cos ðxo tÞ
According to the inductor voltage expression, this time interval ends at the
instant t = 120.8 ls, when vL(t) = −75 V and diode D is turned on. At this instant
vC(t) = 175 V.
Second Time Interval (t1 t t0): The second time interval begins at the
instant diode D is forward biased. The inductor current decays linearly and delivers
energy to E1 until the instant it reaches zero. The second time interval equivalent
circuit is shown in Fig. 1.39.
The results obtained by simulation are shown in Fig. 1.40 as a function of time,
while the corresponding state plane trajectory is represented in Fig. 1.41.
Fig. 1.39 Second time T iD

interval equivalent circuit
i + D
vL L
Vi + - E1
100V - +
75V
-
+
vC C
-
1.7 Problems 27
400
i
200
vc
400
iD
200
vL
0 50 100 150 200 250 300

Time (μs)
Fig. 1.40 Simulation results
200
L iL(t)
C
100
-100 0 100 200

vC (t)
Fig. 1.41 State plane trajectory
1.7 Problems
1. Describe the operation of the circuits shown in Fig. 1.42, considering L = 100
lH and C = 25 lF, and plot the waveforms of i(t), vL(t) and vC(t). The initial
voltages of the capacitor are: (a) vC(0) = 0 V, (b) vC = −50 V, and
(c) vC = −50 V. The initial current in the inductor is zero. Verify the results by
simulation.
Answers: (a) z(t) ¼ 100ejxo t þ 100; (b) z(t) ¼ 150ejxo t þ 100;
(c) z(t) ¼ 150ejxo t þ 100
(a) (b) D (c) D

T + vL -
T + vL - T + vL -
+ L +
vC + L + + L +
100V C C vC C vC
- - - 100V - - 100V -
Fig. 1.42 Exercise 1
2. Describe the operation of the circuits shown in Fig. 1.43, considering L = 100
lH, C = 25 lF and vC(0) = −100 V.
Answers: (a) z(t) ¼ 100ejxo t ; (b) z(t) ¼ 100ejxo t ; (c) z(t) ¼ 100ejxo t ;
(d) z(t) ¼ 100ejxo t .
3. The capacitor initial voltage of the circuit shown in Fig. 1.44 is zero. Thyristor
T1 and T2 are gated on periodically at a switching frequency lower than the
resonant frequency of the pair LC, so they turn off spontaneously every half
D
(a) (b)
T + vL - T + vL -
L L +
+ vC
C vC C D
- -
(c) D
(d)
+ vL - T + vL -
T
L L +
+ C vC
C vC -
-
Fig. 1.44 Exercise 3 T1 T2
R
+
Vi C
-
L
1.7 Problems 29
period of the switching period. The parameters of the circuit are L = 200 lH,
C = 20 lF and the quality factor is Q = 5. Determine: (a) the capacitor final
voltage after the circuit reaches steady-state (theoretically after an infinite
number of operation cycles); (b) find vC(t) and iL(t), and plot them against the
time and show the state plane trajectory.
Answers: vCmin = −270 V and vCmax = 370 V.
4. The thyristor T of the circuit shown in Fig. 1.45 is turned on at the instant t = 0
s. The parameters of the circuit are C = 300 lF with VCo = 0 and ILo = 0. Find
the inductance of the inductor L that results in a derivative of current diL/
dt = 100 A/µs.
Answer: L = 6 µH.
5. The number of turns in the primary and secondary windings of the transformer
shown in Fig. 1.46 are N1 = 100 and N2 = 200 respectively. The switch S,
initially closed for a long time interval, is opened at the instant t = 0 s. The
transformer magnetizing inductance is 200 lH. Obtain the equation for the
current in the secondary winding and the voltage across the switch S. Plot the
relevant waveforms as a function of time and use simulation to verify the
calculations.
6. Consider the circuit shown in Fig. 1.47. Thyristors T1 and T2 are gated on
complementarily to T3 and T4 respectively. The switching frequency is lower
+ vL
T -
+ L +
600V - C vC
-
Fig. 1.46 Exercise 5 D
S 1Ω
+ +v -
S
Vi N1 N2
-

T1 T3
+ Vco=100V
- + R
100V
- L
C
T4 T2
(a) (b) (c)
I I I C
S S S
D C L C L D1 L
D2

T L
+
Vi C D I
-
than the resonant frequency and the thyristors turn off spontaneously. The
parameters of the circuit are VCo = −100 V, Vi = 100 V, ILo = 0 A and
a = 10°. Determine the voltage across the capacitor C after the circuit reaches
steady-state operation. The operation of the circuit initiates at the instant that T1
and T2 are gated on.
Answer: Vc = 4 kV.
7. Consider the circuits shown in Fig. 1.48. The switch S is initially closed for a
long time and then is opened at the instant t = 0 s. Describe the operation of the
circuits and plot the respective state planes.
8. Let the circuit shown in Fig. 1.49. At the instant t = 0 s the thyristor is turned
on. Analyze the circuit and obtain the capacitor voltage (vC) and the inductor
current (iL) waveforms as well as the state plane trajectory. Consider that the
pffiffiffiffiffiffiffiffiffi
initial conditions are zero and I L/C\Vi .
9. The circuits shown in Fig. 1.50a, b are initially with the switch S closed and
conducting the current I. At the instant t = 0 s the switch S is opened. Describe
(a) L D2 (b) L D2
S
+ S D1 +
I C Vi I C Vi
- -
D1

1.7 Problems 31

+
100V T1
-
L C R
- +
+ iL vC
100V - T2
Fig. 1.52 Exercise 11 D
S
+
Vi N 2N
-
the circuits operation and obtain equations for vC(t) and iL(t). Plot the relevant
waveforms against the time, along with the corresponding state planes. The
initial conditions are Vco = 0 and ILo = 0.
10. In the circuit shown in Fig. 1.51, T1 and T2 are gated on complementarily with
a switching frequency of 6 kHz. The parameters of the circuit are L = 100 lH,
C = 5 lF and R = 0.447 X. Consider the circuit operating in steady-state.
(a) Describe the operation of the circuit, representing the different topological
states;
(b) Find the equations for the inductor current iL(t) and the capacitor voltage vC(t)
and plot their waveforms against the time;
(c) Determine the inductor peak current and capacitor peak voltage.
(d) Calculate the power dissipated in resistor R.
Answers:
2eap=x þ e2ap=x Þ
(b) VCmax ¼ Vi ð1 þð1 e2ap=x Þ ; iLmax ¼ ðVi þxV
L
Cmin Þ ap=2xo
e
(c) VCmax ¼ 1:27 kV; iLmax ¼ 283 A; (d) PR ¼ 15:15 kW.
11. The parameters of the circuit shown in Fig. 1.52 are Vi = 100 V and L = 1 H,
where L is the transformer magnetizing inductance reflected to the primary
winding. Switch S is closed for a time interval t1 = 1 s and then opened. Find
the time necessary time (t2) to completely demagnetize the transformer.
Answer: t2 = 0.25 s.
Chapter 2
Series Resonant Converter
Nomenclature
Vi Input DC voltage
V1 Half of the DC input voltage
Vo Output DC voltage
Po Nominal output power
Po min Minimum output power
Co Output filter capacitor
Ro Output load resistor
Ro min Minimum output load resistor
q, qco, qc1 Static gain
D Duty cycle
fs Switching frequency (Hz)
xs Switching frequency (rad/s)
fs min Minimum switching frequency (Hz)
fs max Maximum switching frequency (Hz)
Ts Switching period
fo Resonant frequency (Hz)
xo Resonant frequency (rad/s)
lo Frequency ratio (fs/fo)
q Frequency ratio
td Dead time
T Transformer
n Transformer turns ratio
N1 and N2 Transformer windings
V0o Output DC voltage referred to the transformer primary
side
io Output current
I0o Output current referred to the transformer primary side

I0o I0o Average output current referred to the transformer
primary side and its normalized value in CCM

34 2 Series Resonant Converter

I0o max Maximum normalized average output current referred
to the transformer primary in CCM
I0o min Minimum normalized average output current referred
to the transformer primary in CCM
I0o D I0o D Average output current in DCM referred to the
transformer primary side and its normalized value
I0o SC Short circuit average output current
S1, S2, S3 and S4 Switches
D1, D2, D3 and D4 Diodes
vg1 and vg2 Switches gate signals
Lr Resonant inductor (may include the transformer leak-
age inductance)
Cr Resonant capacitor
vCr ðvCr Þ Resonant capacitor voltage
VCo Resonant capacitor peak voltage
VC1 Resonant capacitor voltage at the end of time interval 1
and three

iLr iLr Resonant inductor current and its normalized value

ILr ILr Inductor peak current and its normalized value,
commutation
IL Fundamental inductor peak current
I1 I1 Inductor current at the end of the first and third step of
operation and its normalized value in CCM
Ip1 and Ip2 Ip1 and Ip2 Inductor peak current and its normalized value in
DCM
vab Full bridge ac voltage, between points “a” and “b”
vcb Inductor voltage, between points “c” and “b”
vab1 Fundamental ac voltage, between points “a” and “b”
vcb1 Fundamental inductor voltage, between points “c” and
“b”
vac Voltage at the ac side of the rectifier, between points
“a” and “c”
vS1, vS2 Voltage across switches
iS1, iS2 Current in the switches
Δt1 Time interval one (t1-t0)
Δt2 Time interval two (t2-t1)
Δt3 Time interval three (t3-t2)
Δt4 Time interval four (t4-t3)
Δt5 Time interval five (t5-t4)
Δt6 Time interval six (t6-t5)
A1 and A2 Area
xLr, xCR and x Reactance
2 Series Resonant Converter 35
Q Capacitor charge
z Characteristic impedance
R1, R2 State plane radius
/r, /o, b, h State plane angles
2.1 Introduction
The series resonant converter was proposed by Francisc C. Schwarz in 1975 [1] for
thyristor based DC–DC converters. Due to the sinusoidal current waveforms, the
thyristor naturally turns off at the instant that current reaches zero, without the need
of auxiliary commutation circuits, which usually includes auxiliary thyristors,
inductors and capacitors.
With the improvement of power semiconductor switches, first the Bipolar [2]
and then MOSFET’s and IGBT’s, the series resonant converter became a very
attractive option for switched mode power supply not only because it became
possible to operate at high switching frequency increasing the power density, but
also due to reduced commutation losses.
The series resonant converters are employed in many practical applications,
which include:
• High voltage and low current power supplies for radar, X-ray and laser
applications;
• Electric vehicles on-board battery chargers;
• Converters for wireless power transfer;
• DC–DC converters for traction applications;
• Solid-State Transformers (SST).
Besides its historical and technical relevance, the series resonant converter gave
rise to a large family of high density resonant mode DC–DC converters, commonly
used in many practical applications.
In this chapter, the series resonant converter is studied. The chapter is organized
to present at first the converter topology, followed by operation description and
detailed analysis in continuous and discontinuous conduction modes.
The schematics of the half-bridge and full-bridge series resonant converters are
shown in Figs. 2.1 and 2.2, respectively. It consists of a full-bridge or half-bridge
inverter, a resonant inductor (Lr), a resonant capacitor (Cr), a transformer, a full
bridge diode rectifier and a capacitive output filter.
The series-resonant converter (SRC) is a PFM (pulse-frequency modulated) con-
verter, since it uses a variable frequency to control the power transfer from the input to
the output. In DCM (discontinuous conduction mode), ZCS (zero current switching)
is achieved for both commutations of each switch, whereas in CCM (continuous
conduction mode) zero current switching is achieved only when the switches turn off.
S1 D1 io
Cr /2 +
Lr
Vi
+ a b c
.T.
- S2 D2 iLr Co Ro Vo
Cr /2
Fig. 2.1 Half-bridge series resonant converter
S1 D1 D2 S2 io
Cr
+
iLr Lr
Vi
+ a b c
.T.
- S3 D3 D4 S4 + - Co Ro Vo
vCr
Fig. 2.2 Full-bridge series resonant converter
2.2 Circuit Operation in Continuous Conduction Mode
In this section, the half-bridge series resonant converter shown in Fig. 2.3, that is
equivalent to the topology represented in Fig. 2.1, is analyzed. For the sake of
simplification, we assume that [3]:
• all components are ideal and the transformer magnetizing inductance is ignored;
• the converter is in steady-state operation;
• the output filter is represented by a DC voltage source V0o , whose value is the
output voltage referred to the primary side of the transformer;
+ S1 D1
Vi / 2
- io'
Cr Lr iLr Vo'
a c b
- +
vCr S2 D2
+
Vi / 2
-
Fig. 2.3 Half-bridge series resonant converter

2.2 Circuit Operation in Continuous Conduction Mode 37
• current flows through the switches is unidirectional, i.e. the switches allow the
current to flow only in the direction of the arrow when indicated;
• the converter is controlled by frequency modulation and the switches S1 and S2
are triggered with 50% duty cycle without dead-time.
In continuous conduction mode (CCM), the switches turn on is dissipative and
turn off is non-dissipative (ZCS). As it will be demonstrated in the next sections, the
converter operates in CCM when 0:5 f o f s f o , where fo and f s are the resonant
and the switching frequencies, respectively.
The resonant capacitor peak voltage depends on the switching frequency, and it
may be larger than the DC bus voltage.
(A) Time Interval Δt1 (t0 < t < t1)
Before this time interval, switch S2 is conducting the resonant inductor current. At
t = t0 the inductor current reaches zero and the diode D2 starts conducting, as illustrated
in Fig. 2.4. During this time interval energy is delivered to both the DC bus and the
load. Switch S2 must be turned off during this time interval to achieve soft commu-
tation. This time interval finishes at the instant t = t1, when switch S1 is gated on.
(B) Time Interval Δt2 (t1 < t < t2)
This time interval, shown in Fig. 2.5, stars at t = t1 when S1 is gated on. Forced
commutation of the current takes place, from the diode D2 to the switch S1.
The resonant capacitor Cr is discharged and charged again with opposite polarity.
+ S1 D1
Vi / 2
- io'
Cr Lr iLr Vo'
a c b
- +
vCr S2 D2
+
Vi / 2
-
Fig. 2.4 Topological state during time interval Δt1
+ S1 D1
Vi / 2
- io'
Cr Lr iLr Vo'
a c b
- +
vCr S2 D2
+
Vi / 2
-

The inductor current evolves with a sinusoidal waveform until it reaches zero at the
instant t = t2, when this time interval finishes. At this instant the resonant capacitor
voltage is VC0. During this interval the DC bus delivers energy to the load.
(C) Time Interval Δt3 (t2 < t < t3)
This time interval begins at t = t2, when the inductor current reaches zero and the
diode D1 starts to conduct, as provided in Fig. 2.6. During this time interval energy
is delivered to both the DC bus and the load. Switch S1 must be turned off during
this time interval to achieve soft commutation.
(D) Time Interval Δt4 (t3 < t < t4)
Figure 2.7 shows the interval Δt4. It begins at t = t3 when switch S2 is gated on.
Once again, forced commutation of the current takes place, from diode D1 to switch
S2. Hence, this commutation is dissipative. The resonant capacitor Cr is discharged
and charged again with opposite polarity. The inductor current evolves with a
sinusoidal waveform until it reaches zero at the end of this time interval. At this
instant the resonant capacitor voltage is −VC0. During this time interval, the DC bus
delivers energy to the load. The main waveforms along with time diagram are
shown in Fig. 2.8.
+ S1 D1
Vi / 2
- io'
Cr Lr iLr Vo'
a c b
- +
vCr S2 D2
+
Vi / 2
-
+ S1 D1
Vi / 2
- io'
Cr Lr iLr Vo'
a c b
- +
vCr S2 D2
+
Vi / 2
-
Fig. 2.7 Topological state for time interval Δt4

2.3 Mathematical Analysis for Operation in Continuous … 39
TS
vg1
vg2 t
iLr
I1
-I1
vCr
VCo
VC1
-VC1
-VCo
vS1
iS1
vS2
iS2
t0 t1 t2 t3 t4
Fig. 2.8 Main waveforms and time diagram in continuous conduction mode
2.3 Mathematical Analysis for Operation in Continuous

Conduction Mode
In this section, the resonant capacitor voltage and resonant inductor current
expressions are obtained. Since the converter is symmetrical, only half switching
period is analyzed.
2.3.1 Time Interval Δt1
In this time interval, the initial current in

the resonant inductor and the initial
iLr ðt0 Þ ¼ 0
voltage across the resonant capacitor are:
vCr ðt0 Þ ¼ VC0
From the equivalent circuit shown in Fig. 2.4, we find Eqs. (2.1) and (2.2).
Vi diLr ðtÞ
¼ Lr vCr ðtÞ V0o ð2:1Þ
2 dt
dvCr ðtÞ
iLr ðtÞ ¼ Cr ð2:2Þ
dt
Applying the Laplace Transform yields
ðVi =2Þ þ V0o

¼ s Lr iLr ðsÞ vCr ðsÞ ð2:3Þ
s
iLr ðsÞ ¼ s Cr vCr ðsÞ þ Cr VC0 ð2:4Þ
Substituting (2.4) in (2.3) and applying the inverse Laplace Transform we

obtain,

vCr ðtÞ ¼ V1 V0o þ VC0 cosðxo tÞ V1 V0o ð2:5Þ
and

iLr ðtÞz ¼ V1 V0o þ VC0 senðxo tÞ ð2:6Þ
where:
qffiffiffiffiffi
V1 ¼ V2 i , xo ¼ pffiffiffiffiffiffiffiffiffi
1 Lr .
and z ¼ C
Lr Cr r
Defining the variable z1 ðtÞ as follows:

rffiffiffiffiffi
Lr
z1 ðtÞ ¼ vCr ðtÞ þ j iLr ðtÞ ð2:7Þ
Cr
Substitution of Eqs. (2.5) and (2.6) into Eq. (2.7), with appropriate algebraic
manipulation, results in

z1 ðtÞ ¼ V1 V0o þ V1 þ V0o VC0 ej xo t ð2:8Þ
Fig. 2.9 State-plane for the

time interval Δt1
z iLr
z I1
ωo Δt1 R1
0
vCr
-VC0 -V1-Vo’ -2V 1-2V o’-VC0
-VC1
Equation (2.8) allows us to plot the state-plane for time interval Δt1, shown in
Fig. 2.9, which the coordinates of the center of the circle are (0, −V1−Vo′) and the
radius is given by (2.9).
R1 ¼ VC0 V1 V0o ð2:9Þ

iLr ðt0 Þ ¼ I1
vCr ðt0 Þ ¼ VC1
The equivalent circuit presented in Fig. 2.5 yields the following equations:
diLr ðtÞ
V1 ¼ Lr þ vCr ðtÞ þ V0o ð2:10Þ
dt
dvCr ðtÞ
dt
Applying the Laplace Transforming in Eqs. (2.10) and (2.11) we obtain the
following equations:
V1 V0o
¼ s Lr iLr ðsÞ Lr I1 þ vCr ðsÞ ð2:12Þ
s
iLr ðsÞ ¼ s Cr vCr ðsÞ þ Cr VC1 ð2:13Þ
Substituting (2.13) in (2.12) and applying the inverse Laplace Transform yields
Eqs. (2.14) and (2.15).

vCr ðtÞ ¼ V1 V0o þ VC1 cos ðxo tÞ þ I1 z sen ðxo tÞ þ V1 V0o ð2:14Þ

iLr ðtÞ z ¼ V1 V0o þ VC1 sen ðxo tÞ þ I1 z cos ðxo tÞ ð2:15Þ
Defining z2 ðt) by Eq. (2.16):
z2 ðtÞ ¼ vCr ðtÞ þ j z iLr ðtÞ ð2:16Þ
Substituting Eqs. (2.14) and (2.15) in Eq. (2.16) and rearranging terms, we have

z2 ðtÞ ¼ V1 V0o V1 V0o þ VC1 þ j I1 z ej xo t ð2:17Þ
Fig. 2.10, which the coordinates of the center of the circle are (0, V1 − Vo′) and the
radius is given by (2.18).
2
R22 ¼ V0o VC1 V1 þ ðI1 zÞ2 ð2:18Þ
Fig. 2.10 State-plane for the

time interval Δt2
z iLr
z I1
ωo Δt2 R2
0
-z I1
-VC1 0 -V1 -Vo’ VCo

vCr
2.3.3 Normalized State Plane for One Half of the Switching

Period
The state-plane trajectory for time intervals Δt1 and Δt2 of one half of a switching
period, normalized with the voltage V1, is shown in Fig. 2.11, where
V0
iLr ¼ iV
Lr z
, vCr ¼ vVCr , I1 ¼ IV1 z, q ¼ Vo , qCo ¼ V VC1
V1 , qC1 ¼ V1
Co
1 1 1 1
2.3.4 Output Characteristics
The normalized state plane for half of a switching period, shown in Fig. 2.11, yields
the following equations:
wr þ h ¼ p ¼ xo ðDt1 þ Dt2 Þ ð2:19Þ
1 xo f s 1
¼ ¼ ð2:20Þ
Ts 2p f o 2ðDt1 þ Dt2 Þ
1 l 1 1
¼ o¼ ¼ ð2:21Þ
Ts p xo ðDt1 þ Dt2 Þ wr þ h
Fig. 2.11 Normalized

state-plane trajectory for one iLr
half of a switching period of
the series resonant converter,
operating in continuous
conduction mode
I1 R2
R1
ψr β ψ0 θ
0
-qC0 -1-q -qC1 0 1-q qC0

vCr
p
wr þ h ¼ ð2:22Þ
lo
and
b þ ð p w r Þ þ ð p hÞ ¼ p ð2:23Þ

p
b ¼ wr þ h p ¼ p ð2:24Þ
lo
The radios R1 and R2 are given by Eqs. (2.25) and (2.26).
R1 ¼ qCo 1 q ð2:25Þ
R2 ¼ qCo 1 þ q ð2:26Þ
In one half of the switching period the capacitor charge (Q) is:
ZTs =2
Q ¼ Cr 2 VCo ¼ iLr ðtÞ dt ð2:27Þ
0
The average load current is
ZTs =2
1
I0o ¼ iLr ðtÞdt ð2:28Þ
Ts =2
0
Substituting (2.28) in (2.27), we find:
Ts 0
Q ¼ 2Cr VCo ¼ I ð2:29Þ
2 o
and
I0o
VCo ¼ ð2:30Þ
4f s Cr
Normalizing VCo in Eq. (2.30) in relation to V1 gives:
VCo I0o
qCo ¼ ¼ ð2:31Þ
V1 4f s Cr V1
The normalized average output current is:
zI0o
I0o ¼ ð2:32Þ
V1
Substitution of (2.32) into (2.31) yields
VCo I0 V1 1 I0 p I0 p
qCo ¼ ¼ o ¼ o ¼ o ð2:33Þ
V1 z 4f s Cr V1 2 2pf s Cr z 2 lo
Substituting (2.22) in (2.25) and (2.26) we obtain
I0o p
R1 ¼ 1q ð2:34Þ
2 lo
I0o p
R2 ¼ 1þq ð2:35Þ
2 lo
Figure 2.12 shows a detail of the state plane for time intervals Δt1 and Δt2, which
will be used to find the steady state operation of the series resonant converter. Using
the law of cosines, we have
22 ¼ R21 þ R22 2 R1 R2 cos b ð2:36Þ
Substituting (2.24), (2.34) and (2.35) in (2.36) gives

!2 !2
I0o p I0o p
4¼ 1q
þ 1þq
2 lo 2 lo
! ! ð2:37Þ
I0o p I0o p p
2 1q 1 þ q cos p
2 lo 2 lo lo
Fig. 2.12 A detail of the

state plane for time intervals
Δt1 and Δt2 β
R1 R2
ψr θ
2
By doing q ¼ p=lo and knowing that cosðq pÞ ¼ cosðqÞ yields

!2 !2
I0o I0o
4¼ q1q
þ q1 þ q
2 2
! ! ð2:38Þ
I0o I0o
2 q1q q1 þ q cosðq pÞ
2 2
After appropriate algebraic manipulation of Eq. (2.38) we find

!2 2 !2 3
I0 q I0 q
2 o 1 þ 2 q2 þ 2 4 o 1 q2 5 cosðqÞ 4 ¼ 0 ð2:39Þ
2 2
Rearranging terms gives

!2
I0 q
2q ½1 cosðqÞ ¼ 4 2 o 1
2
½1 þ cosðqÞ ð2:40Þ
2
Dividing Eq. (2.40) by 4 yields
!2
1 cosðqÞ I0o q 1 þ cosðqÞ
q2
¼1 1 ð2:41Þ
2 2 2
1cosðqÞ q 1 þ cos ðqÞ q

Doing 2 ¼ sin2 2 and 2 ¼ cos2 2 in Eq. (2.41) gives
!2
q I0o q q
2
q sin ¼1
2
1 cos2 ð2:42Þ
2 2 2
Solving the algebraic Eq. (2.42) for the static gain q yields
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u 0 2
u
u1 Io q 1 cos2 q
u 2 2
q¼t
2 q
ð2:43Þ
sin 2
Fig. 2.13 Output 1.0

characteristics of the series q
resonant converter operating
in continuous current mode 0.8
0.6
0.4
0.2
μο=0.5 0.70 0.75 0.80 0.85
0.65
0
0.5 1.0 1.5 2.0 2.5 3.0
Io’
Substituting q ¼ lp in Eq. (2.43) gives

o
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u 0 2
u
u1 Io p 1 cos2 p
u 2 lo 2 lo
q¼ u
t ð2:44Þ
sin2 2 pl
o
Equation (2.44) represents the static gain of the series resonant converter,
operating in continuous current mode, as a function of the normalized output
current, having lo as a parameter. The generated output characteristics are plotted in
Fig. 2.13. As it can be noticed, the series resonant converter has a current source
characteristic that can be beneficial for protection against overload or short circuit.
2.4 Analysis of the Series Resonant Converter Based

in the First Harmonic Approximation
The equivalent circuit of the series resonant converter, operating in continuous

conduction mode, with parameters of the secondary side reflected to the primary
side of the transformer, is shown in Fig. 2.14.
The transformer is considered ideal and its magnetizing current is null. The
amplitude of the fundamental components of the rectangular voltage vab and vcb are
given by the expressions (2.45) and (2.46), respectively.
Lr Cr
a c io’
iLr
+ +
Vi Inverter Vi' Vo' Vo’
- -
b b
Fig. 2.14 Equivalent circuit of the series resonant converter
Fig. 2.15 Equivalent circuit Lr Cr

for the voltage and current iLr
fundamental components
vab1 vcb1
4
vab1 ¼ V1 ð2:45Þ
p
4
vcb1 ¼ V0o ð2:46Þ
p
The equivalent circuit of the first harmonic is shown in Fig. 2.15.

Defining the absolute values of xLr and xCr by the expressions (2.47) and (2.48),
respectively,
jxLr j ¼ Lr xs ¼ 2pf s Lr ð2:47Þ
1 1
jxCr j ¼ ¼ ð2:48Þ
Cr xs 2pf s Cr
Hence, the absolute value of the equivalent reactance is given by expression

(2.49).
jxj ¼ jxCr j jxLr j ð2:49Þ
Therefore,
1
j xj ¼ Lr xs ð2:50Þ
Cr xs
2.4 Analysis of the Series Resonant Converter … 49
Fig. 2.16 Phasor diagram of IL vcb1

the equivalent circuit shown
in Fig. 2.15
x IL
vab1
The diode rectifying bridge forces the current iL to be in phase with the voltage
vcb1.
We also know that when the converter operates with fs < fo, the current iL leads
the voltage vab1 by 90°.
Therefore, in steady state operation, we can represent the voltage and current by
the phasor diagram found in Fig. 2.16.
where IL is the amplitude of the current IL, considered sinusoidal.
From the phasor diagram, we can write:
v2ab1 ¼ v2ac1 þ ðjxjIL Þ2 ð2:51Þ
Hence,
v2ac1 ¼ v2ab1 ðjxjIL Þ2 ð2:52Þ
Substituting Eqs. (2.45) and (2.46) into (2.52), we obtain:

2 2
4 0 4
V ¼ V1 þ ðjxjIL Þ2 ð2:53Þ
p o p
Thus,
!2 !2
4 0
p Vo jxjIL
4
¼1 4
ð2:54Þ
p V1 p V1
The static gain was already defined by
V0o
q¼ ð2:55Þ
V1
Thus,
!2
jxjIL
q ¼1
2
4
ð2:56Þ
p V1
or yet,
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!2
u
u jxjIL
t
q¼ 1 4 ð2:57Þ
p V1
Figure 2.17 shows the currents at the diode rectifier input and output.
The average value of the rectified current is:
2
I0o ¼ ILr ð2:58Þ
p
Thus,
p 0
ILr ¼ I ð2:59Þ
2 o
Replacing the expression (2.59) in (2.57), we get:

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!2ffi
u
u jxj p Io 0
q ¼ t1 ð2:60Þ
2 p4 V1
After the appropriate simplifications, we find:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
0 2 2ffi
x Io p
q¼ 1 ð2:61Þ
V1 8
iL(θ)
IL
π 2π
θ
i o’(θ)
IL
Io’
Fig. 2.17 Current at the diode rectifier input and output

2.4 Analysis of the Series Resonant Converter … 51
The expression (2.62) of the normalized current was already defined by

z 0
I0o ¼ I ð2:62Þ
V1 o
Thus,
V1 0
I0o ¼ I ð2:63Þ
z o
Or,
2 !2
jxj I0o jxj I0o
¼ ð2:64Þ
V1 z
But,

j xj 1 1
¼ qffiffiffiffiffi xs Lr ð2:65Þ
z Lr xs Cr
Cr
With:
1
xo ¼ pffiffiffiffiffiffiffiffiffi ð2:66Þ
Lr Cr
With the appropriate algebraic manipulation of expressions (2.65) and (2.66), we

find:
2 2 2
jxj I0o p2 p xo xs 2 0 2
¼ Io ð2:67Þ
V1 8 8 xs xo
Substituting Eq. (2.55) into (2.61), we find:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

2
p xo xs 0 2
q¼ 1 I ð2:68Þ
8 xs xo o
We know that
xo f o
¼ ð2:69Þ
xs f s
Therefore, we can write:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

p4 f o f s 2 0 2
q¼ 1 Io ð2:70Þ
64 f s f o
The normalized switching frequency is defined by the expression (2.71):
fo
lo ¼ ð2:71Þ
fs
Substitution of Eq. (2.71) in Eq. (2.70) yields

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 ffi
p4 1 2
q¼ 1 lo I0o ð2:72Þ
64 lo
Equation (2.72) represents the output characteristics of the series resonant

converter, obtained for voltage and current fundamental components, considering
fo/2 fs fo.
The output characteristics given by Eq. (2.72) are plotted in Fig. 2.18.
The percentage error introduced by the analysis based on the first harmonic
approximation is plotted in Fig. 2.19.

characteristics of the series q
resonant converter obtained
for the first harmonic 0.8
approximation
0.6
0.4
μο=0.5 0.65 0.70 0.75 0.80 0.85

0.2
0
0 0.5 1.0 1.5 2.0 2.5 3.0
Io s
2.5 Simplified Numerical Example for Calculation of Lr and Cr 53
Fig. 2.19 Percentage error as 100

a function of the static gain, ε%
taking lo as a parameter
80
60
40
μ0=0.5 0.65 0.85
0.75
20
0
0 0.2 0.4 0.6 0.8 1.0
q
2.5 Simplified Numerical Example for Calculation

of Lr and Cr
In this section is presented a numerical example, using the equations deduced in

previous sections, to calculate the parameters Lr and Cr of the resonant tank. The
specifications are given in Table 2.1.
A normalized switching frequency µo = 0.87 is chosen to provide a wide load
range operation in continuous conduction mode. The maximum normalized output
current is I0o max ¼ 2:5 for a static gain q = 0.6.
The output voltage referred to the transformer primary side is:
Vi 400
V0o ¼ q¼ 0:6 ¼ 120 V
2 2
The transformer turns ratio (n) and the average output current referred to the
primary side of the transformer (Io′) are:
N1 V0o 120
¼ ¼ ¼ 2:4
N2 Vo 50
Table 2.1 Design Input DC voltage (Vi) 400 V

specifications
Output DC voltage (Vo) 50 V
Output DC current (Io) 10 A
Output nominal power (Po) 500 W
Minimum output power (Po min) 50 W
Maximum switching frequency (fs max) 40 kHz
and
N1 1
I0o ¼ Vo ¼ 10 ¼ 4:17 A
N2 2:4
The average output current referred to the primary side of the transformer gives a
relation between the inductance of the resonant inductor and the capacitance of the
resonant capacitor. Hence,
qffiffiffiffiffi
I0o Lr
Cr
I0o ¼
V1
and
2
Lr Io V 1 2:5 200 2
¼ ¼ ¼ 14; 400
Cr Io 4:16667
The resonant frequency is
f s max 40 103
fo ¼ ¼ ¼ 45; 977:01 Hz
lo 0:87
Since f o ¼ p1ffiffiffiffiffiffiffiffiffi, then Lr Cr ¼ 11:98276 1012 .

Lr Cr
2p
From these two equations we find Cr = 29 nF and Lr = 413.23 µH.
For the minimum power Po min = 50 W, q = 0.6 and I0o min ¼ 1, from the output
characteristics we have lo = 0.7. Hence, the minimum switching frequency is:
f s min ¼ f o lo ¼ 45; 977 0:7 ¼ 32; 183:91 Hz
The operating region of the output characteristics for the calculated parameters is
presented in Fig. 2.20.
The ideal half-bridge series resonant converter, whose equivalent circuit is
shown in Fig. 2.21, with the parameters given in Table 2.1 and the resonant tank
parameters calculated above, is simulated at nominal and minimum load power.
Figure 2.22 shows the resonant capacitor voltage, the resonant inductor current
and the voltage vab at the nominal power and Fig. 2.23 shows the voltage and
current in the switches. As it may be noticed, the switches turn on is dissipative and
soft commutation (ZCS) is achieved only at the switches turn off.
2.5 Simplified Numerical Example for Calculation of Lr and Cr 55
1.0
q
0.8
0.6
Load Range
0.4
0.65 0.70 0.75 0.80 0.85 0.87
μo= 0.50
0.2
0
0.5 1 1.5 2.0 2.5 3.0
Io’
Fig. 2.20 Output characteristics showing the operation region of the numerical example
+ S1 D1
Vi / 2
- io'
Cr Lr iLr Vo'
a c b
- +
vCr S2 D2
+
Vi / 2
-
Fig. 2.21 Ideal half-bridge series resonant converter
1000
v
500 Cr
0
- 500
-1000
10
5
iLr
0
-5
-10
200
vab
0
-200
0.50 0.52 0.54 0.56 0.58 0.60

Time (ms)
Fig. 2.22 Resonant capacitor voltage, resonant inductor current and voltage vab at nominal power
1
vg1 vg2
400
vS1 iS1 x 50
200
0
400
iS2 x 50 vS2
200
0
0.50 0.51 0.52 0.53 0.54
Time (ms)
Fig. 2.23 Switches commutation at nominal power: S1 and S2 drive signals, voltage and current
on the switches
400 vCr
0
-400
4
2
0 iLr
-2
-4
200 vab
0
-200
0.50 0.52 0.54 0.56 0.58 0.60

Time (ms)
Fig. 2.24 Resonant capacitor voltage, resonant inductor current and voltage vab at minimum
power
Figure 2.24 shows the resonant capacitor voltage, the resonant inductor current
and the voltage vab at minimum power. Figure 2.25 shows the voltage and current
in the switches. Again, the switches turn on are dissipative and soft commutation
(ZCS) is achieved only when the switch turns off.
2.6 Operation in Discontinuous Conduction Mode 57
1
vg1 vg2
400
vS1
200
iS1 x 50
0
400
vS2
200
iS2 x 50
0
0.50 0.51 0.52 0.53 0.54 0.55 0.56
Time (ms)
Fig. 2.25 Switches commutation at minimum power: S1 and S2 drive signals, voltage and current
on the switches
2.6 Operation in Discontinuous Conduction Mode
In DCM the switching frequency range is 0 f s 0:5 f o and in one operation cycle
there are six time intervals.
(A) Time Interval Δt1 (t0 < t < t1)
At t = t0, because iLr = 0, the switch S1 turn on is non-dissipative (ZCS). The
inductor current evolves sinusoidally, and the capacitor that in the beginning of this
time interval was charged with a negative voltage is discharged. During this time
interval the DC bus delivers energy to the load. Figure 2.26 shows the topological
state for this interval.
(B) Time Interval Δt2 (t1 < t < t2)
The topological state for this time interval is illustrated in Fig. 2.27. In t = t1 the
inductor current reaches zero. The diode D1 turns on conducting the inductor
current that evolves negatively. During this time interval switch S1 must be turned
+ S1 D1
Vi / 2
-
Cr Lr iLr VO'
a c b
- +
vCr S2 D2
+
Vi / 2
-

+ S1 D1
Vi / 2
-
Cr Lr iLr VO'
a c b
- +
vCr S2 D2
+
Vi / 2
-
off to ensure soft commutation. This time interval ends when the inductor current
reaches zero again, at the instant t = t2.
(C) Time Interval Δt3 (t2 < t < t3)
During this time interval, shown in Fig. 2.28, both switches are open and the
inductor current is null. No power is transferred to the load. This time interval
finishes at t = t3, when switch S2 is turned on.
(D) Time Interval Δt4 (t3 < t < t4)
At t = t3 the inductor current is zero and switch S2 turns on with zero current.
The inductor current evolves sinusoidally, and the capacitor is discharged. During
this time interval the DC bus delivers energy to the load. Figure 2.29 shows the
topological state for this time interval.
(E) Time Interval Δt5 (t4 < t < t5)
The topological state for this time interval is presented in Fig. 2.30. At t = t4 the
inductor current reaches zero. The diode D2 starts conducting the inductor current
that evolves positively. During this time interval switch S2 must be turned off to
ensure soft commutation. This interval ends when the inductor current reaches zero
again.
+ S1 D1
Vi / 2
-
Cr Lr VO'
a c b
- + iLr=0
vCr S2 D2
+
Vi / 2
-

2.6 Operation in Discontinuous Conduction Mode 59
+ S1 D1
Vi / 2
-
Cr Lr iLr VO'
a c b
- +
vCr S2 D2
+
Vi / 2
-
+ S1 D1
Vi / 2
-
Cr Lr iLr VO'
a c b
- +
vCr S2 D2
+
Vi / 2
-
(F) Time Interval Δt6 (t5 < t < t6)

During this time interval, presented in Fig. 2.31, both switches are open and the
inductor current is null. No power is transferred to the load. This interval finishes at
t = t6, when switch S1 is turned on. The main waveforms with the time diagram are
shown in Fig. 2.32.
+ S1 D1
Vi / 2
-
Cr Lr VO'
a c b
+ - iLr=0
vCr S2 D2
+
Vi / 2
-

TS
vg1
t
TS / 2
vg2
iLr
Ip1
Ip2
-Ip2
-Ip1
vCr
VCo
VC1
-VC1
-VCo
vS1
iS1
vS2
iS2
t0 t1 t2 t3 t4 t5 t6
Fig. 2.32 Main waveforms and time diagram in discontinuous current mode
2.7 Mathematical Analysis for Operation in Discontinuous

Conduction Mode
In this section the resonant inductor current and the resonant capacitor voltage are
obtained. Since the converter is symmetrical, only one half switching period is
analyzed.
2.7 Mathematical Analysis for Operation in Discontinuous … 61
(A) A Time Interval Δt1

In this time interval, the initial
current in the resonant inductor and voltage across
i ðt Þ ¼ 0
the resonant capacitor are: Lr 0
vCr ðt0 Þ ¼ VC0
The equivalent circuit shown in Fig. 2.26 yields the following equations:
Vi diLr ðtÞ
¼ Lr þ vCr ðtÞ þ V0o ð2:73Þ
2 dt
dvCr ðtÞ
dt
Applying the Laplace Transform we find
ðVi =2Þ V0o

¼ sLr ILr ðsÞ þ vCr ðsÞ ð2:75Þ
s
ILr ðsÞ ¼ sCr vCr ðsÞ þ Cr VC1 ð2:76Þ
Applying the inverse Laplace Transform in Eqs. (2.75) and (2.76) and rear-
ranging terms, we have

vCr ðtÞ ¼ V1 V0o þ VC1 cos ðxo tÞ þ V1 V0o ð2:77Þ

iLr ðtÞ z ¼ V1 V0o þ VC1 sen ðxo tÞ ð2:78Þ
This time interval ends when the inductor current reaches zero. Considering
iLr ðtÞ ¼ 0 in Eq. (2.78) gives

V1 V0o + VC1 senðxo Dt1 Þ ¼ 0 ð2:79Þ
Hence,
p
Dt1 ¼ ð2:80Þ
xo
Defining
Substituting (2.77) and (2.78) in (2.81) leads to

z1 ðtÞ ¼ V1 V0o V1 V0o þ VC1 cosðxo tÞ þ j V1 V0o þ VC1 senðxo tÞ
ð2:82Þ
Fig. 2.33 State-plane

trajectory for time interval z iLr
Δt1, in discontinuous
conduction mode
Ip1
R1
0
-VC1 V1-Vo’ VC0
0 vCr
Hence,

z1 ðtÞ ¼ V1 V0o V1 V0o þ VC1 ej xo t ð2:83Þ
Equation (2.83) gives the state-plane trajectory for time interval Δt1, shown in
Fig. 2.33. It is a circle whose center coordinates is (0, V1 V0o ) and radius is
R1 ¼ VC1 þ V1 V0o ð2:84Þ
(B) Time Interval Δt2

In this time interval, the initial current
in the resonant inductor and the voltage
iLr ðt1 Þ ¼ 0
across the resonant capacitor are: .
vCr ðt1 Þ ¼ VC0
The equivalent circuit shown in Fig. 2.27 yields the following equations:
diLr ðtÞ
V1 ¼ Lr þ vCr ðtÞ V0o ð2:85Þ
dt
dvCr ðtÞ
dt
Applying the Laplace Transform, we find:
V1 þ V0o
¼ sLr iLr ðsÞ þ vCr ðsÞ ð2:87Þ
s
iLr ðsÞ ¼ sCr vCr ðsÞ þ Cr VC0 ð2:88Þ
Applying the inverse Laplace Transform in Eqs. (2.87) and (2.88) and rear-
ranging, we find

vCr ðtÞ ¼ V1 þ V0o VC0 cosðxo tÞ þ V1 þ V0o ð2:89Þ

iLr ðtÞ z ¼ V1 þ V0o VC0 senðxo tÞ ð2:90Þ
This time interval ends when the inductor current reaches zero. Considering
iLr ðt) = 0 in Eq. (2.90) yields

V1 þ V0o VCo senðxo Dt2 Þ ¼ 0 ð2:91Þ
Thus,
p
Dt2 ¼ ð2:92Þ
xo
Defining the variable z2 ðt) as follows:
Substituting (2.89) and (2.90) in (2.93) yields

z2 ðtÞ ¼ V1 þ V0o V1 þ V0o VC0 cos ðxo tÞ þ j V1 þ V0o VC0 sen ðxo tÞ
ð2:94Þ
Hence,

z2 ðtÞ ¼ V1 þ V0o V1 þ V0o VC0 ej xo t ð2:95Þ
Equation (2.95) allows us to plot the state-plane trajectory for time interval Δt2
as shown in Fig. 2.34. The coordinates of the center of the circle are (0, V1 þ V0o )
and the radius is

R2 ¼ VC0 V1 þ V0o ð2:96Þ
(C) Initial Conditions

The complete state-plane trajectory of a half switching period is shown in Fig. 2.35.
By inspection of the figure, we can write Eqs. (2.97) and (2.98).

trajectory for time interval z iLr
Δt2, in discontinuous
conduction mode
VC1 V1+Vo’ VC0

0
R2
-Ip2
vCr

trajectory for half-period, in z iLr
discontinuous conduction
mode
Ip1
R1
VC1 V1+Vo’ VC0

0
-VC1 V1-Vo’ R2
-Ip2
0 vCr
VC1 ¼ VC0 2R2 ð2:97Þ

VC0 ¼ R1 þ V1 V0o ð2:98Þ
Substitution of Eqs. (2.96) in (2.97) and Eq. (2.84) in (2.98) gives:

VC1 ¼ VC0 þ 2 V1 þ V0o ð2:99Þ

VC0 ¼ VC1 þ 2 V1 V0o ð2:100Þ
Substituting (2.99) in (2.100) we find:
VC1 ¼ 2 V0o ð2:101Þ
VC0 ¼ 2 V1 ð2:102Þ
The radius R1 and R2 are determined by:
R1 ¼ V1 þ V0o ð2:103Þ
R2 ¼ V1 V0o ð2:104Þ
The peak currents Ip1 and Ip2 are given by Eqs. (2.105) and (2.106), respectively.
Ip1 ¼ Ip1 z ¼ R1 ¼ V1 þ V0o ð2:105Þ
Ip2 ¼ Ip2 z ¼ R2 ¼ V1 V0o ð2:106Þ
(D) Output Characteristics

Figure 2.36 shows a detail of the power stage diagram of the series resonant
converter, whose currents at the input and output terminals of the diode rectifier are
shown in Fig. 2.37.
The areas A1 and A2 are determined by Eqs. (2.107) and (2.108), respectively.
Fig. 2.36 Detail of the power Lr Cr

stage diagram of the series io’
resonant converter iLr
+
V’
- o
iLr
Ip1
-Ip2 t
Δt1 Δt2
io’
A2
A1
t1 t2 Ts / 2 Ts
Fig. 2.37 Currents at the input and output terminals of the rectifier
Zp
1 V1 þ V0o V1 þ V0o
A1 ¼ senðxo tÞ dt ¼ ð2:107Þ
xo Z pf o z
0
Zp
1 V1 V0o V1 V0o
A2 ¼ senðxo tÞ dt ¼ ð2:108Þ
xo Z pf o z
0
The average output current, referred to the transformer primary side, is obtained
by adding (2.107) and (2.108). Hence,
2 ðA 1 þ A 2 Þ 4 V 1 f s
I0o D ¼ ¼ ð2:109Þ
Ts p z fo
Thus, the normalized current is
I0o D z 4 f s
I0o D ¼ ¼ ð2:110Þ
V1 p fo
The output characteristics or the static gain as a function of the normalized

output current, having lo as a parameter, are plotted in Fig. 2.38. It should be noted
that the converter, in this operation mode, has current source characteristic, so the
load current does not depend of the load voltage.
(E) DCM Constraints
The discontinuous conduction mode described in Sect. 2.6 is only possible if three
constraints are observed.
The first one is given by Eq. (2.111).

characteristics in q
discontinuous current mode
0.8
μο=0.1 0.2 0.3 0.4 0.5
0.6
0.4
0.3
0 0.2 0.4 0.6 0.8
Io’ D
xo ðDt1 þ Dt2 Þ p ð2:111Þ
Hence, substituting (2.80) and (2.92) in (2.111) we find
fs
0:5 ð2:112Þ
fo
Substitution of Eq. (2.112) to (2.110) gives the second constraint, given by

Eq. (2.113).
2
I0o D ð2:113Þ
p
The third constraint, obtained by inspection of the state-plane trajectory of

Fig. 2.34 is:
VC1 V1 V0o ð2:114Þ
Substituting (2.101) in (2.114), we find:
V1
V0o ð2:115Þ
3
2.8 Problems
(1) The specification of the full-bridge series resonant converter shown in Fig. 2.39
are:
Vi ¼ 400 V Vo ¼ 120 V Ns =Np ¼ 1 Ro ¼ 20 X

f s ¼ 30 103 Hz Cr ¼ 52:08 nF Lr ¼ 48:63 lH
(a) Calculate the resonant frequency.

(b) Calculate the output voltage and the output average current.
(c) Calculate the resonant capacitor peak voltage and the switches peak
current.
Answers: (a) fo = 100 kHz, (b) Vo = 100 V; Io = 5 A and (c) VC0 = 800 V;
Ip1 = 16.36 A
(2) For exercise 1 calculate the switching frequency to ensure that the output
voltage is 160 V.
Answer: fs = 48 kHz
(3) The full-bridge series resonant converter shown in Fig. 2.39 operates in CCM
with a switching frequency of 80 kHz. Calculate the output voltage.
Answer: Vo = 344 V
(4) Find the expression of the output short-circuit current for a series resonant
converterhoperating in CCM. i
Answer: Io SC ¼ Vz1 2lpo 1 þ cosðp=21
lo Þ
(5) For exercise 4 calculate the output short circuit current.
Answer: Io_SC = 24 A
(6) Find the expression for the resonant capacitor peak voltage of the half-bridge
series resonant converteroperating with the output short-circuited.
Answer: VCo SC ¼ V1 1 þ 1 p
cos 2l
o
S1 D1 D2 S2
+
Cr iLr Lr c T
Vi
+ a b
..
- S3 D3 D4 S4 + - Co Ro Vo
vCr

2.8 Problems 69
(7) Calculate the minimum output resistance (Ro min) to ensure that a half-bridge
series resonant converter operates in discontinuous conduction mode. Consider
the following specifications:
Vi ¼ 400 V Cr ¼ 300 nF Lr ¼ 40 lH
f s ¼ 20 103 Hz Ns =Np ¼ 1
Answer: Ro min = 15.625 Ω
References
1. Schwarz, F.C.: An improved method of resonant current pulse modulation for power
converters. IEEE Trans. Ind. Electron. Control Instrum. IECI-23(2), 133–141 (1976)
2. Schwarz, F.C., Klaassens, B.J.: A 95-percent efficient 1-kW DC converter with an internal
frequency of 50 kHz. IEEE Trans. Ind. Electron. Control Instrum. IECI-24(4), 326–333 (1978)
3. Witulski, A.F., Erickson, R.W.: Steady-state analysis of the series resonant converter. IEEE
Trans. Aerosp. Electron. Syst. AES-21(6), 791–799 (1985)
Chapter 3
Half Bridge Capacitor Voltage-Clamped
Series Resonant Converter
Nomenclature
Vi Input DC voltage
V1 Half of the DC input voltage
Po Output power
Po max Maximum output power
µo Normalized switching frequency
q Static gain
D Duty cycle
fs Switching frequency
fs max Maximum switching frequency
fs min Minimum switching frequency
Ts Switching period
td Dead time
T Transformer
N1 and N2 Transformer primary and secondary winding turns
V0o Output DC voltage referred to the transformer primary side
io Output current
i0o Output current referred to the transformer primary side

I0o I0o Average output current referred to the transformer primary side
and its normalized value
S1 and S2 Switches
vg1 and vg2 Switches gate signals
DC1 and DC2 Clamping diodes
Lr Resonant inductor (may include the transformer leakage
inductance)
iLr Resonant inductor current

72 3 Half Bridge Capacitor Voltage-Clamped Series Resonant Converter

ILr ILr Resonant inductor peak current and its normalized value,
commutation current for S1 and S3
xo Resonant frequency
z1 and z2 State plane impedance
I1 I1 Inductor current at the end of the first and fourth step of operation
vS1 and vS2 Voltage across switch S1 and S2
iS1 and iS2 Current in the switch S1 and S2
Δt1 Time interval of the first step of operation in (t1−t0)
Δt2 Time interval of the second step of operation (t2−t1)
Δt3 Time interval of the third step of operation in (t3−t2)
Δt4 Time interval of the fourth step of operation (t4−t3)
Δt5 Time interval of the fifth step of operation in (t5−t4)
Δt6 Time interval of the sixth step of operation (t6−t5)
IS RMS IS RMS Switches S1 and S2 RMS currents and its normalized value

IDC IDC Diodes DC1 and DC2 average currents and its normalized value
3.1 Introduction
The half bridge capacitor voltage-clamped series resonant converter [1], presented
in Fig. 3.1, has two clamping diodes compared to the series resonant converter
presented in Chap. 2. The power is transferred to the load is also controlled by the
switching frequency. The resonant capacitor voltage is clamped with half of the DC
Bus voltage, resulting in two linear time intervals in the switching period. The
converter operates in discontinuous conduction mode (DCM) in a wide switching
+ S1 io
Vi / 2 DC1
- Cr +
Lr
a
-
b .T.
+ vCr
+ S2 iLr Co Ro Vo
Vi / 2 DC2
-
-
Fig. 3.1 Half bridge capacitor voltage-clamped series resonant converter

3.1 Introduction 73
frequency range, up to the resonant frequency. The operation in DCM ensures a

zero-current switching (ZCS) at the semiconductors when it is turned on and off.
The output characteristic is not an ideal current source as it is in the series resonant
converter, so short circuit protection is not inherent to this topology. The output
power depends linearly on the switching frequency and does not depend on the
load. The schematics of the HB CVC-SRC is shown in Fig. 3.1.
In this chapter, principle of operation, detailed analysis in discontinuous con-
duction mode (DCM), as well as a design example are presented.
3.2 Circuit Operation
In this section, the converter shown in Fig. 3.2 is analyzed. The following
assumptions are made:
• all components are considered ideal;
• the converter is in steady-state operation;
• the output filter is represented as an DC voltage V0o , whose value is the output
voltage referred to the primary winding of the transformer;
• current that flows through the switches is unidirectional, i.e. the switches allow
the current to flow only in the direction of the arrow;
• the converter is controlled by frequency modulation, the switches S1 and S2 are
gated with 50% duty cycle, and dead time is not considered.
The converter is analyzed in DCM. In this conduction mode the switches turn on
and off are non-dissipative, with zero current (ZCS).
(A) Time Interval Δt1 (t0 t t1)
This time interval, shown in Fig. 3.3, starts at t = t0, when the switch S1 is gated on.
Prior to t = t0, the capacitor voltage is −Vi/2 and the inductor current is zero, so
switch S1 turns on softly, with zero current (ZCS). During this time interval, both
the capacitor voltage and inductor current evolve in a resonant way.
Fig. 3.2 Half bridge

CVC-SRC converter + S1
Vi / 2 DC1 io’
- Cr Vo’ Lr
a b
- + iLr
+ vCr S2
Vi / 2 DC2
-
Fig. 3.3 Topological state

for time interval Δt1 + S1
Vi / 2 DC1 io’
- Cr Vo’ Lr
a b
+
+v - iLr S2
Cr
Vi / 2 DC2
-

Vi / 2 DC1 io ’
- Cr Vo ’ Lr
a b
- + iLr
+ vCr S2
Vi / 2 DC2
-

Vi / 2 DC1 io’
- Cr Vo’ Lr
a b
- + iLr=0
+ vCr S2
Vi / 2 DC2
-
(B) Time Interval Δt2 (t1 t t2)

Time interval Δt2, presented in Fig. 3.4, begins at the instant t = t1, when the
capacitor voltage reaches Vi/2 and the clamping diode DC1 starts conducting the
inductor current iLr. The capacitor voltage is clamped with Vi/2 and the inductor
current decreases linearly and eventually reaches zero at the instant t = t2.
(C) Time Interval Δt3 (t2 t t3)
During this time interval switch S2 is not gated on yet, the capacitor voltage is Vi/2,
and the inductor current is zero. No power is transferred from the input voltage
source to the load. The converter topological state is illustrated in Fig. 3.5.

Vi / 2 DC1 io’
- Cr Vo’ Lr
a b
- + iLr
+ vCr S2
Vi / 2 DC2
-
3.2 Circuit Operation 75

Vi / 2 DC1 io ’
- Cr Vo ’ Lr
a b
+
+v - iLr S2
Cr
Vi / 2 DC2
-

Vi / 2 DC1 io’
- Cr Vo’ Lr
a b
+ +v - iLr=0 S2
Cr
Vi / 2 DC2
-
(D) Time Interval Δt4 (t3 t t4)

In the instant t = t3, that corresponds to half of the switching period, switch S2 is
gated on with zero current (ZCS). The capacitor voltage and inductor current evolve
in a resonant way until vCr(t) = −Vi/2 and iLr(t) = −I1, at the instant t = t4. The
equivalent circuit for this time interval may be observed at Fig. 3.6.
(E) Time Interval Δt5 (t4 t t5)
Time interval Δt5 begins when the capacitor voltage reaches −Vi/2, turning on the
clamping diode DC2. The capacitor voltage is clamped at −Vi/2 and the inductor
current decreases linearly until it reaches zero. The topological state for this interval
is presented in Fig. 3.7.
(F) Time Interval Δt6 (t5 t t6)
During this time interval switch S1 is not gated on yet, the capacitor voltage is
clamped with −Vi/2 and the inductor current is zero. No power is transferred from
the input voltage source to the load. The topological state is shown in Fig. 3.8.
The main waveforms and the time diagram are shown in Fig. 3.9.
vg1 TS
TS / 2 t
vg2
iLr
I1
-I1
vCr
Vi / 2
-Vi / 2
vS1
Vi
iS1
vS2
Vi
iS2
t0 t1 t2 t3 t4 t5 t6
Fig. 3.9 Main waveforms and time diagram of the half bridge CVC-SRC
3.3 Mathematical Analysis
In this section, the resonant capacitor voltage and resonant inductor current
expressions are obtained likewise the DCM operations constraints, the output
characteristics and output power. The switches RMS current and clamping the
diodes average current. Since the converter is symmetrical, only half of the
switching period is analyzed.
3.3 Mathematical Analysis 77
In time interval Δt1, the DC bus delivers energy to the resonant tank and the load.
The initial current in the resonant inductor and the initial voltage across the
iLr ðt0 Þ ¼ 0
resonant capacitor are:
vCr ðt0 Þ ¼ Vi =2
From the equivalent circuit shown in Fig. 3.3, we have
Vi diLr ðtÞ
2 dt
dvCr ðtÞ
dt
ðVi =2Þ V0o

¼ s Lr iLr ðsÞ þ vCr ðsÞ ð3:3Þ
s
Vi
iLr ðsÞ ¼ s Cr vCr ðsÞ þ Cr ð3:4Þ
2

iLr ðtÞ z ¼ 2 V1 V0o senðxo tÞ ð3:6Þ
qffiffiffiffiffi
V0
where V1 ¼ V2 i , xo ¼ pffiffiffiffiffiffiffiffiffi
1 ffi Lr :
, q ¼ Vo and z ¼ C
Lr Cr 1 r
Normalizing the capacitor voltage and the inductor current with the voltage V1
gives
vCr ðtÞ
vCr ðtÞ ¼ ¼ ð2 qÞ cosðxo tÞ þ 1 q ð3:7Þ
V1
iLr ðtÞ z
iLr ðtÞ ¼ ¼ ð2 qÞ senðxo tÞ ð3:8Þ
V1
Substituting (3.4) in (3.3) and applying the inverse Laplace Transform we find:

vCr ðtÞ ¼ 2 V1 V0o cosðxo tÞ þ V1 V0o ð3:5Þ
This time interval finishes when the capacitor voltage reaches V1 and conse-
quently vCr ðt) = 1. Therefore, from Eq. (3.7) we have
1 ¼ ð2 qÞ cosðxo Dt1 Þ þ 1 q ð3:9Þ

Thus,

1
xo Dt1 ¼ p cos1 ð3:10Þ
2q
Time interval Δt1, shown in (3.10), does not depend on the switching frequency.
In the end of this time interval the inductor current is:

iLr ðt1 Þ z q
I1 ¼ ¼ ð2 qÞ sen p cos1 ð3:11Þ
V1 2q
After appropriate algebraic manipulation we find

pffiffiffiffiffiffiffiffiffiffiffiffi
I1 ¼ 2 1q ð3:12Þ
Defining the variable z1 ðt) as follows:
Substitution of Eqs. (3.7) and (3.8) into Eq. (3.13) yields:
z1 ðtÞ ¼ ð2 qÞ cosðxo tÞ þ 1 q þ j ð2 qÞ senðxo tÞ ð3:14Þ
Hence,
z1 ðtÞ ¼ ð1 qÞ ð2 qÞ ej xo t ð3:15Þ
Fig. 3.10. The state-plane trajectory is a circle with center at the coordinates (0, 1
−q) and radius given by Eq. (3.16).
R1 ¼ 2 q ð3:16Þ

iLr I1
diagram of HB CVC-SRC for
an operation cycle
ωο Δt1 ωο Δt2
-(1-q)
0
1-q
-I1
-1 0 1
vCr
In time interval Δt2, the energy stored in the resonant inductor at the end of the time
interval Δt1 is totally transferred to the load.
The initial current in the resonant inductor and the initial voltage across the
iLr ðt0 Þ ¼ I1
resonant capacitor are:
vCr ðt0 Þ ¼ V1
From the equivalent circuit shown in Fig. 3.4, we have
V0o
iLr ðtÞ ¼ I1 ðt t1 Þ ð3:17Þ
Lr
and
vCr ðtÞ ¼ V1 ð3:18Þ
Normalizing (3.17) and (3.18) with V1 gives
vCr ðtÞ
vCr ðtÞ ¼ ¼1 ð3:19Þ
V1
and
iLr ðtÞ z
iLr ðtÞ ¼ ¼ I1 q xo ðt t1 Þ ð3:20Þ
V1
This time interval finishes when the inductor current reaches zero. Hence, from
Eq. (3.20) we have
0¼2 1 q q xo ðDt2 Þ ð3:21Þ
Thus,
1q
2
xo Dt2 ¼ ð3:22Þ
q
Defining z2(t) according to Eq. (3.23).
z2 ðtÞ ¼ vCr ðtÞ þ j iLr ðtÞ ð3:23Þ
Substitution of Eqs. (3.19) and (3.20) in Eq. (3.23) gives

z2 ðt) = 1 + j I1 q xo ðt t1 Þ ð3:24Þ
The state-plane trajectory for this time interval is a line, parallel to iLr axis, as
shown in Fig. 3.10.
3.3.3 State Plane Diagram
The state plane trajectory of the HB CVC-SRC is shown in Fig. 3.10, with resonant
and linear time intervals, for a complete operation cycle of the converter.
3.3.4 DCM Constrains
In the limit of operation in discontinuous conduction Δt3 = 0 and
Ts
¼ Dt1 þ Dt2 ð3:25Þ
2
Thus,
p
¼ xo ðDt1 þ Dt2 Þ ð3:26Þ
f s =f o
Substitution of Eqs. (3.10) and (3.22) into Eq. (3.26) gives:
f s max p
¼ 2 pffiffiffiffiffiffiffi
1q
ffi ð3:27Þ
fo q
p cos1 2q þ q
Equation (3.27) gives the maximum switching frequency, normalized with the
resonant frequency, as a function of the static gain, which is plotted in Fig. 3.11. As
the static gain increases, the maximum switching frequency increases too. The limit
is with q = 1, when fsmax = fo. If the maximum switching frequency is not
respected, the converter will operate in continuous conduction mode (CCM), and
soft commutation will not be achieved when the semiconductors turn on and off.
Fig. 3.11 Normalized 1.0

maximum switching fs max
frequency, as a function of the fo
static gain q 0.8
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0
q
The average output current is calculated according to (3.28)

0 1
Zt1 Zt2
2 @
I0o ¼ iLr ðtÞ dt þ iLr ðtÞ dtA ð3:28Þ
Ts
to t1
Substituting (3.8) and (3.20) in Eq. (3.28) and integrating, gives

2 2 ð 1 qÞ
I0o ¼ 2þ ð3:29Þ
xo Ts q
Rearranging terms we find Eq. (3.30) that represents the static gain of the
converter.
I0o z 2 1 fs
q= ¼ ð3:30Þ
V1 p I0o f o
Equation (3.30), plotted in Fig. 3.12, gives the output characteristics of the
converter. It represents a hyperbola and for a given value of µo, the product q I0o is
constant.

characteristics q
0.8
μo=0.1 0.3 0.5 0.7
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0
Io
3.3.6 Normalized Output Power
The normalized output power is found multiplying Eq. (3.30) with the normalized
output voltage.
pffiffiffiffiffiffiffiffiffiffiffiffiffi
Po Lr =Cr 2 f s
Po ¼ ¼ ð3:31Þ
V21 p fo
3.3.7 Switches RMS Current
The switches RMS current is calculated by (3.32).

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u Zt1 Zt2
u
I0o RMS
1 u2 2 2
IS RMS ¼ pffiffiffi ¼ pffiffiffi t iLr ðtÞ dt þ iLr ðtÞ dt ð3:32Þ
2 2 T s
t0 t1
Substituting Eqs. (3.8) and (3.20) in Eq. (3.32) yields
1
IS RMS ¼ pffiffiffi
2vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u " #
u 1 f s ð 2 qÞ 2

q

8

8 pffiffiffiffiffiffiffiffiffiffiffiffi
t p cos 1 þ qþ 1q
p fo 2 2q 3q 3
ð3:33Þ
Fig. 3.13 Switches RMS 1.0

current as a function of the
I s RMS
static gain (q), taking lo as a
parameter 0.8
μo=0.1 0.3 0.5 0.7
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0
q
Hence,
IS RMS z
IS RMS ¼
V1
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
" #
u
u 1 f s ð2 qÞ2

q

8

8 pffiffiffiffiffiffiffiffiffiffiffiffi
¼ t p cos 1 þ qþ 1q
2p f o 2 2q 3q 3
ð3:34Þ
The switches RMS current characteristics, as a function of the static gain, taking
lo as a parameter, are plotted in Fig. 3.13.
3.3.8 Clamping Diodes Average Current
The clamping diodes average current is determined by:
Zt2
1
IDC ¼ iLr ðtÞ dt ð3:35Þ
Ts
t1
Substituting (3.20) in (3.35) gives:
IDC z 1 ð1 qÞ f s
IDC ¼ ¼ ð3:36Þ
V1 p q fo
The clamping diodes average current as a function of the static gain (q), taking
lo, as a parameter, is plotted in Fig. 3.14.
Fig. 3.14 Clamping diodes 1.0

average current as a function
IDC
of the static gain (q), taking lo
as a parameter 0.4
μo=0.1 0.3 0.5 0.7

0.3
0.2
0.1
0
0 0.2 0.4 0.6 0.8 1.0
q
3.4 CVC-SRC Topological Variations
Topological variations of the half bridge capacitor voltage-clamped series resonant

converter are shown in Fig. 3.15. The operation is similar to the topology analyzed
in previous subsections. Noted that these topologies do not need an input voltage
with a middle point.
(a)
S1
Cr /2 DC1 io’
+ Vo’ Lr
Vi a b
- iLr S2
Cr /2 DC2
(b)
S1
DC1 io’
+ Vo’ Lr
Vi a b
- iLr S2
DC2 Cr
(c)
S1
DC1 Cr io’
+ Vo’ Lr
Vi a b
- iLr S2
DC2
Fig. 3.15 Half bridge CVC-SRC topological variations

3.5 Design Example and Methodology 85
3.5 Design Example and Methodology
In this section, a design methodology and an example are presented, using the
mathematical analysis results obtained in the Sect. 3.3. The converter is designed to
operate in DCM according to the specifications given in Table 3.1.
A static gain (q) of 0.8 is chosen. The output DC voltage referred to the primary
side of the transformer (V0o ) is calculated as follows:
400
V0o ¼ q V1 ¼ 0:6 ¼ 160 V
2
The transformer turns ratio (n) and the output current referred to the primary side
of the transformer (I0o ) are given by:
N1 V0o 160
n¼ ¼ ¼ ¼ 3:2
N2 Vo 50
Io 10
I0o ¼ ¼ ¼ 3:125 A
n 3:2
A normalized switching frequency (lo max = fs max/fo) of 0.5 is chosen for the
nominal power. Thus, the resonant frequency is:
f s max 100 103

fo ¼ ¼ ¼ 200 kHz
lo max 0:5
Since
1
pffiffiffiffiffiffiffiffiffiffiffi ¼ 2p f o ¼ 2 p 200 103
Lr Cr
We have
Lr Cr ¼ 6:3325 1013 :
second relation between the inductance Lr and the capacitance Cr. From the output
characteristics, if q = 0.8 we have

specifications
Nominal average output current (Io) 10 A
Nominal power (Po) 500 W
Minimum switching frequency (fs min) 20 kHz
pffiffiffiffiffiffiffiffiffiffiffiffiffi
I0o Lr =Cr
I0o ¼ ¼ 0:4
V1
Thus,
Io 10
I0o ¼ ¼ ¼ 3:125 A
N1 =N2 3:2
And
rffiffiffiffiffiffi
Lr
¼ 25:6
Cr
Finishing the calculations, we find
Cr ¼ 31:085 nF
Lr ¼ 20:372 lH
The switches S1 and S2 conduction time (Δt1) as well as the clamping diodes DC1
and DC2 conduction time (Δt2) are calculated as follows:

pffiffiffiffiffiffiffiffiffiffiffi
1 1 q 2 1q
Dt1 ¼ p cos þ ¼ 2:72 ls
xo 2q q
pffiffiffiffiffiffiffiffiffiffiffi
2 1 q=q
Dt2 ¼ ¼ 0:8897 ls
xo
The initial conditions, the inductor peak current, the switches RMS current and
diodes average current, for nominal power are calculated with the equations
obtained in Sect. 3.3 and it results in:
ILr ¼ 9:375 A I1 ¼ 6:98 A IS RMS ¼ 3:351 A IDC ¼ 0:311 A
For the minimum switching frequency of 20 kHz, the normalized switching

frequency ratio lo is:
f s min
lo min ¼ ¼ 0:1
fo
For this normalized frequency, the output power is:
2 f s min V21
Po min ¼ ¼ 100 W
p fo z
3.5 Design Example and Methodology 87
The initial conditions, the switches RMS current and diodes average current, for
minimum power, are calculated with the equations obtained in Sect. 3.3, as follows:
ILr ¼ 9:375 A I1 ¼ 6:98 A IS RMS ¼ 1:499 A IDC ¼ 0:062 A
3.6 Simulation Results
The HB CVC-SRC presented in Fig. 3.16 is simulated to validate the analysis and
design example presented in Sect. 3.5 in the nominal and minimum power.
Figure 3.17 shows the resonant capacitor voltage, the resonant inductor current,
the AC voltage vab and the output current i0o in the nominal power. It may be noticed
that the converter is operating in DCM, as predicted. Figure 3.18 shows the voltage
and current in switches S1 and S2 and clamping diodes DC1 and DC2. ZCS com-
mutation is achieved when it turns on and off.
Table 3.2 presents theoretical and simulated parameters and component stresses
at nominal power to validate the mathematical analysis.
the AC voltage vab and the output current i0o , at minimum power. Figure 3.20 shows
the voltage and current in switches S1 and S2 and clamping diodes DC1 and DC2.
ZCS commutation is also achieved when it turns on and off and the converter is
operating in DCM. The inductor current peak value is the same at minimum and
nominal power.
Table 3.3 presents theoretical and simulated parameters and component stresses
with minimum power to validate the mathematical analysis.
+ S1
Vi / 2 DC1 io’
- Cr Vo’ Lr
a b
- + iLr
+ vCr S2
Vi / 2 DC2
-
Fig. 3.16 Simulated circuit

vCr
200
-200
10
iLr
-10
vab
200
-200
10
io
-10
50 54 58 62 66 70
Time (μs)
Fig. 3.17 Resonant capacitor voltage, resonant inductor current, AC voltage vab and output
current i0o , at nominal power
vS1
400
200
iS1 x 20
0
vS2
400
200
iS2 x 20
0
200
iDc1 x 20
0
-200
vDc1
-400
200
iDc2 x 20
0
vDc2
-200
-400
50 54 58 62 66 70
Time (μs)
Fig. 3.18 Switches and clamping diodes soft commutation at nominal power: switches S1 and S2
voltage and current, clamping diodes DC1 and DC2 voltage and current
3.6 Simulation Results 89
Table 3.2 Theoretical and simulated results at nominal power

Theoretical Simulated
I0o [A] 3.125 3.10
ILr [A] 9.375 9.37
I1 [A] 6.98 6.95
IS RMS [A] 3.351 3.35
ID [A] 0.311 0.30
vCr
200
-200
10
iLr
5
0
-5
-10
vab
200
-200
10 ‘
io
5
0
-5
-10
60 80 100 120 140 160
Time (μs)
current i0o , at minimum power
vS1
400
200
iS1 x 20
0
vS2
400
200
iS2 x 20
0
200
vDc1 iDc1 x 20
0
-200
-400
200
iDc2 x 20
0
-200
-400
60 70 80 90 100 110 120

Time (μs)
Fig. 3.20 Switches and clamping diodes soft commutation at the minimum power: switches S1
and S2 voltage and current, clamping diodes DC1 and DC2 voltage and current
Table 3.3 Theoretical and simulated results with minimum power

I0o [A] 0.625 0.64
ILr [A] 9.375 9.37
I1 [A] 6.98 6.95
IS RMS [A] 1.499 1.36
ID [A] 0.062 0.053
3.7 Problems
(1) The half-bridge capacitor voltage clamped converter has the following
specifications:
Vi ¼ 400 V V0o ¼ 150 V Cr ¼ 40 nF

Lr ¼ 30 lH f s ¼ 100 103 Hz
3.7 Problems 91
Calculate:
(a) The resonant frequency;
(b) The output average current and power;
(c) The resonant inductor peak current.
Answers: (a) fo = 145.3 kHz; (b) Io = 4.27 A; Po = 640 W; (c) ILr = 9.13 A.
(2) For the previous exercise, calculate the maximum switching frequency and the
output power at this point of operation.
Answers: (a) fsmax = 128.7 kHz; (b) Pomax = 823.42 W.
(3) Consider the topological variation of the HB CVC-SRC shown in Fig. 3.21.
Show that this topology is similar to the one presented in this chapter and the
same equations can be applied. Comment the advantages and disadvantages of
this topology.
(4) For the topological variation presented in Fig. 3.22 and with the following
parameters, calculate:
I¼5A V0o ¼ 15 V Cr =2 ¼ 20 nF Ci ¼ 1 lF
Lr = 30 lH and f s ¼ 100 103 Hz, calculate

(a) The input voltage;
(b) The output power.
Answers: (a) Vi = 500 V and (b) Po = 1000 W.
Fig. 3.21 HB CVC-SRC

topological variation S1
Cr /2 DC1 io’
+ Vo’ Lr
Vi a b
- iLr S2
Cr /2 DC2
Fig. 3.22 HB CVC-SRC

topological variation S1
Cr /2 DC1 io’
+ Ci Vo’ Lr
Ii Vi a b
iLr S2
- Cr /2 DC2
(5) A series-resonant converter with isolating transformer and voltage clamping of

the resonant capacitor has the following parameters:
Vi ¼ 60 V, Vo ¼ 400 V, lo ¼ 0:6; q ¼ 0:8; f s ¼ 120 kHz and Po ¼ 300 W:
Calculate: (a) Lr, (b) Cr; and (c) (Np/Ns).

Answers: (a) Lr = 0.512 µH; (b) Cr = 699.5 nF and (c) n = 0.06.
Reference
1. Agrawal, J.P., Lee, C.Q.: Capacitor voltage clamped series resonant power supply with
improved cross regulation. In: IEEE IAS Annual Meeting, pp. 1141–1146 (1989)
Chapter 4
Half Bridge CVC-PWM Series
Resonant Converter
Nomenclature
Vi DC Bus voltage
V1 Half of the DC Bus voltage
Po Output power
q Static gain
D Duty cycle
Dmax Maximum duty cycle
Dmin Minimum duty cycle
Ts Switching period
fo Resonant frequency [Hz]
xo Resonant frequency [rad/s]
lo Frequency ratio
io Output current

i0o I0o Average output current referred to the transformer primary
Io min Minimum average output current
i0o min S2—main switches
S3 and S4 Auxiliary switches
vg1, vg2, vg3 and vg4 Switches gate signals
S1 and S2 main switches
DC1 and DC2 Clamping diodes
Cr Resonant capacitors

94 4 Half Bridge CVC-PWM Series Resonant Converter

inductance)
vCr
Resonant capacitor voltage
I1 I1 Inductor current at the end of the first step of operation and
its normalized value
I2 I2 Resonant inductor peak current and its normalized value

I3 I3 Inductor current at the end of the third step of operation and
vab AC voltage, between points “a” and “b”
vS1, vS2, vS3 and vS4 Voltage across switches
iS1, iS2, iS3 and iS4 Switches currents
Δt1 Time interval of the first step of operation (t1−t0)
Δt2 Time interval of the second step of operation (t2–t1)
Δt3 Time interval of the third step of operation (t3–t2)
Δt4 Time interval of the fourth step of operation (t4–t3)
Δt5 Time interval of the fifth step of operation (t5–t4)
Δt6 Time interval of the sixth step of operation (t6–t5)
Δt7 Time interval of the seventh step of operation (t7–t6)
Δt8 Time interval of the eighth step of operation (t8–t7)
Δt9 Time interval of the ninth step of operation (t9–t8)
Δt10 Time interval of the tenth step of operation (t10–t9)
/, ho, hr, h State plane angle
r1 and r2 State plane radius
4.1 Introduction
The half bridge capacitor voltage-clamped series resonant converter studied in

Chap. 3 had the frequency modulation as the main disadvantage. So, for a wide
load range, the switching frequency has to vary as well. This means that the
magnetic devices, such as resonant inductor and isolation transformer, are designed
for a wide switching frequency range. This implies in a complex design of these
components, in order to optimize losses, volume and size.
The half bridge capacitor voltage-clamped pulse width modulation series reso-
nant converter [1], shown in Fig. 4.1, has two auxiliary switches, S3 and S4, that
allow to control the power transfer to the load at constant switching frequency. To
ensure soft commutation in the semiconductors turn on and off, the converter must
operate in discontinuous conduction mode (DCM). The main switches (S1 and S2)
commutate under zero current (ZCS) while the auxiliary switches (S3 and S4)
commutate with zero voltage (ZVS).
+ S1 io
Vi / 2 DC1
- - vCr + +
Cr iLr Lr
a b .T.
+ S4 S3 S2 Co Ro Vo
Vi / 2 DC2
-
-
Fig. 4.1 Half bridge CVC-PWM series resonant converter
In this section, the topology shown in Fig. 4.2 is analyzed. In order to simplify, we
assume that:
• the converter is on steady-state operation;
• the output filter is represented as a DC voltage V0o , whose value is the output
• the transformer magnetizing current is very small and can be neglected;
• the converter is controlled by pulse width modulation (PWM) and no dead time
is considered at this point;
• the switches S1 and S2 operate with 50% duty cycle and the auxiliary switches
S3 and S4 operate with variable duty-cycle, in order to control the power transfer
to the load;
The converter is analyzed in DCM. In this conduction mode, the semiconduc-
tors’ turn on and off are non-dissipative, switches S1 and S2 have zero current
(ZCS) and switches S3 and S4 have zero voltage (ZVS).
+ DC1 S1
Vi / 2 io’
- - vCr + Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2
Fig. 4.2 Ideal half-bridge CVC-PWM series resonant converter with all parameters referred to the
transformer primary winding
+ DC1 S1
Vi / 2 io’
- + vCr - Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2
+ DC1 S1
Vi / 2 io’
- vCr = 0
Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2

Time interval Δt1, which converter topological state is shown in Fig. 4.3, starts at
t = t0, when switch S1 is gated on. The resonant capacitor initial condition is −Vi/2
and the resonant inductor initial condition is zero. The circuit state variables evolve
in a resonant way and this time interval ends in the instant t = t1, when the capacitor
voltage reaches zero.
In the instant t = t1, the resonant capacitor reaches zero, switch S3 turns on with
zero voltage (ZVS) and the inductor current starts to evolve linearly. This time
interval controls the power transferred to the load. The topological state is shown in
Fig. 4.4.
At the instant t = t2 switch S3 is turned off with zero voltage (ZVS). During this
time interval, shown in Fig. 4.5, the capacitor voltage and inductor current evolve
in a resonant way. This time interval ends at the instant t = t3, when the resonant
capacitor reaches Vi/2.
+ DC1 S1
Vi / 2 io’
- - vCr + Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2
+ DC1 S1
Vi / 2 io’
- - Vi/2 + Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2

In the moment that the capacitor voltage reaches Vi/2, the clamping diode DC1 starts
conducting, as shown in Fig. 4.6. The capacitor voltage remains clamped at Vi/2
and the inductor current decreases linearly. This time interval ends when the
inductor current reaches zero, at the instant t = t4.
The topological state for time interval Δt5 is shown in Fig. 4.7. At t = t4, the
inductor current reaches zero turning off the clamping diode DC1. As the switch S2
+ DC1 S1
Vi / 2 io’
- - Vi/2 + Vo’ Lr
a Cr b
+ S4 S3 iLr = 0
S2
Vi / 2
- DC2

+ DC1 S1
Vi / 2 io’
- - vCr + Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2
is not gated on yet, the current does not flow through the circuit and the capacitor
voltage remains clamped at Vi/2.
Time interval Δt6, shown in Fig. 4.8, starts at t = t5 = Ts/2 when switch S2 is turned
on. The resonant capacitor initial condition is +Vi/2 and the resonant inductor initial
condition is zero. The circuit evolves in a resonant way and this time interval ends
when the capacitor voltage reaches zero.
(G) Time Interval Δt7 (t6 t t7)
At t = t6, the resonant capacitor reaches zero, switch S4 turns on with zero voltage
(ZVS) and the inductor current evolves linearly. This time interval also controls the
power transferred to the load. The topological state for this time interval is pre-
sented in Fig. 4.9.
(H) Time Interval Δt8 (t7 t t8)
At t = t7, switch S3 is turned off with zero voltage (ZVS). During this time interval,
shown in Fig. 4.10, the capacitor voltage and inductor current evolve in a resonant
way. This time interval ends when the resonant capacitor reaches −Vi/2, in the
instant t = t8.
+ DC1 S1
Vi / 2 io’
- vCr = 0
Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2

+ DC1 S1
Vi / 2 io’
- + vCr - Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2
+ DC1 S1
Vi / 2 io’
- + Vi/2 - Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2
(I) Time Interval Δt9 (t8 t t9)

When the capacitor voltage reaches −Vi/2, at the instant t = t8, the clamping diode
DC2 is turned on, as shown in Fig. 4.11. The capacitor voltage is clamped at −Vi/2
and the inductor current decreases linearly. This time interval ends at the instant
t = t9, when the inductor current reaches zero.
(J) Time Interval Δt10 (t9 t t10)
The topological state for time interval Δt10 is shown in Fig. 4.12. It starts at t = t9,
when the inductor current reaches zero, turning off the clamping diode DC2. As
switch S1 is not gated on yet, the current does not flow through the circuit and the
capacitor voltage remains clamped at −Vi/2. The main waveforms along with time
diagram are shown in Fig. 4.13.
+ D C1 S1
Vi / 2 io ’
- + Vi/2 - Vo ’ Lr
a Cr b
+ S4 S3 iLr = 0
S2
Vi / 2
- D C2

vg1 TS
TS / 2 t
vg2
vg3
vg4 D TS / 2
iLr D TS / 2
I2
I3
I1
-I1
-I3
-I2
vCr
Vi / 2
-Vi / 2
Vi
vS1
iS1
iS3
vS3
Vi / 2
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Fig. 4.13 Main waveforms and time diagram

In this section, using mathematical analysis, it will be obtained the resonant

capacitor voltage and the resonant inductor current expressions, as well as the DCM
constraints and the output characteristics. Since symmetry is assumed, only half of
the switching cycle will be analyzed.
In this time
interval, the initial resonant inductor current and resonant capacitor
iL r ðt0 Þ ¼ 0
voltage are:
vCr ðt0 Þ ¼ V1
From the equivalent circuit shown in Fig. 4.3, we have:
diLr ðtÞ
V1 ¼ Lr þ V0o þ vCr ðtÞ ð4:1Þ
dt
dvCr ðtÞ
dt
Application of the Laplace Transform gives:
V1 V0o
¼ s Lr ILr ðsÞ þ VCr ðsÞ ð4:3Þ
s
and
ILr ðsÞ ¼ s Cr VCr ðsÞ þ Cr V1 ð4:4Þ
Applying the inverse Laplace Transform in Eqs. (4.3) and (4.4) and rearranging
terms, we find:
vCr ðtÞ
vCr ðtÞ ¼ ¼ 1 q ð2 qÞ cos ðxo tÞ ð4:5Þ
V1
iLr ðtÞ z
iLr ðt) ¼ ¼ ð2 qÞ sen ðxo tÞ ð4:6Þ
V1
qffiffiffiffiffi
V0
where V1 ¼ V2 i , q ¼ Vo , z ¼ Lr pffiffiffiffiffiffiffiffiffi
1 ffi
Cr and xo ¼ Lr Cr .
1
This time interval ends when the capacitor voltage reaches zero. Thus, from
Eq. (4.5) we have:

1q
xo Dt1 ¼ cos1 ð4:7Þ
2q
Substituting Eq. (4.7) into Eq. (4.6), it can be found the normalized resonant
current in the end of this time interval, given by:
I1 ðtÞ z pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I1 ¼ ¼ 3 2q ð4:8Þ
V1
In this time
iLr ðt1 Þ ¼ I1
voltage are:
vCr ðt1 Þ ¼ 0
From the equivalent circuit presented in Fig. 4.4, we have:
vCr ðtÞ ¼ 0 ð4:9Þ
V1 V0o
iLr ðtÞ ¼ I1 þ ðt t 1 Þ ð4:10Þ
Lr
Normalizing (4.9) and (4.10) with V1, we find:
vCr ðtÞ
V1
i1 ðtÞ z
iLr ðtÞ ¼ ¼ I1 þ ð1 qÞ xo ðt t1 Þ ð4:12Þ
V1
The duty-cycle D, that controls the power transferred to the load during this time
interval, is given by:
D t2
D¼ ð4:13Þ
Ts =2
Substituting Eq. (4.13) in Eq. (4.12) and rearranging terms, we find the inductor
current in the end of this time interval, given by:
pD
I2 ¼ I1 þ ð1 qÞ ð4:14Þ
f s =f o

iLr ðt2 Þ ¼ I2
The initial conditions for time interval are:
vCr ðt2 Þ ¼ 0
From the topological state of Fig. 4.5, we have:
diLr ðtÞ
V1 ¼ Lr þ V0o þ vCr ðtÞ ð4:15Þ
dt
dvCr ðtÞ
dt
Applying the Laplace Transform yields:
V1 V0o
¼ s Lr ILr ðsÞ Lr I2 þ VCr ðsÞ ð4:17Þ
s
ILr ðsÞ ¼ s Cr VCr ðsÞ ð4:18Þ
Applying the inverse Laplace Transform in Eqs. (4.17) and (4.18), normalizing
with V1, and rearranging terms, we find:
vCr ðtÞ
vCr ðtÞ ¼ ¼ 1 q ð1 qÞ cos ðxo tÞ þ I2 sen ðxo tÞ ð4:19Þ
V1
iLr ðtÞ z
iLr ðtÞ ¼ ¼ ð1 qÞ sen ðxo tÞ þ I2 cos ðxo tÞ ð4:20Þ
V1
This time interval ends at t = t3, when the capacitor voltage reaches V1. Hence,
from Eq. (4.19), we have:
0 1 0 1
B 1q C B q C
xo Dt3 ¼ p cos1 @qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiA cos1 @qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiA ð4:21Þ
2 2 2 2
I2 þ ð1 qÞ I2 þ ð1 qÞ
Substitution of Eq. (4.21) in Eq. (4.20) gives the normalized inductor current in
the end of this time interval:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2
I3 ¼ I2 þ ð1 qÞ2 q2 ð4:22Þ
In this time
iLr ðt3 Þ ¼ I3
voltage are:
vCr ðt3 Þ ¼ V1
Based on the topological state shown in Fig. 4.6, we have:
vCr ðtÞ ¼ V1 ð4:23Þ
V0o
iLr ðtÞ ¼ I3 ðt t3 Þ ð4:24Þ
Lr
Normalization with V1, gives:
vCr ðtÞ
V1
iLr ðtÞ z
iLr ðtÞ ¼ ¼ I3 q xo ðt t3 Þ ð4:26Þ
V1
This time interval ends at the instant t = t3, when the inductor current reaches
zero. Thus, considering iLr ðt) ¼ 0 in Eq. (4.26), we find:
I3
xo Dt4 ¼ ð4:27Þ
q
4.3.5 Normalized State-Plane Trajectory
The normalized state-plane trajectory for the Half Bridge CVC-PWM SRC is
illustrated in Fig. 4.14.
Fig. 4.14 State-plane 2

diagram of the half bridge iLr I2
CVC-PWM SRC I3
r2
I1 θ
1
r1
θr
φ
θo
0
1-q
-1
-I1
-I3
-I2
-2
-2 -1 0 1 2
vCr
4.3.6 DCM Constraint
The switching period constraint at the boundary between discontinuous and con-
tinuous conductions mode is:
Ts
¼ Dt1 þ Dt2 þ Dt3 þ Dt4 ð4:28Þ
2
Assuming that the resonant frequency is much higher than the switching fre-
quency, which implies in a very low value of the normalized switching frequency
µo. Thus, the time interval Dt3 ffi 0 can be neglected, to simplify.
Multiplying the terms of Eq. (4.28) by xo gives
xo Ts
¼ xo ðDt1 þ Dt2 þ Dt3 þ Dt4 Þ ð4:29Þ
2
Substitution of Eqs. (4.7), (4.13) and (4.27) into Eq. (4.28), and doing appro-
priate algebraic manipulation gives:

p 1 1 q p pffiffiffiffiffiffiffiffiffiffiffiffiffiffi p
¼ cos þ Dmax þ 3 2q þ ð1 2qÞ Dmax ð4:30Þ
lo 2q lo lo
Solving Eq. (4.30) for Dmax, we obtain

pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1q
lo cos1 2q þ lo 3 2q p
Dmax ¼ ð4:31Þ
pðq 2Þ
Fig. 4.15 Maximum 1.0

duty-cycle as a function of the Dmax
static gain q, taking µo as a 0.8
parameter μo=0.025
0.6
0.1
0.2
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0
q
The maximum duty-cycle, as a function of the static gain, taking µo as a

parameter given by Eq. (4.31), is plotted in Fig. 4.15. If this constraint is not
respected, the converter will not operate in discontinuous conduction mode
(DCM) as we assumed in the beginning of the theoretical analysis.
The normalized output current referred to the transformer primary side is shown in
Fig. 4.16. Note that the period of this current waveform is half of the converter
switching period.
The average value of the normalized output current I0o is determined by
Eq. (4.32).
0 t 1
Z1 Zt2 Zt3 Zt4
2@
I0o ¼ iLr ðtÞ dt þ iLr ðtÞ dt þ iLr ðtÞ dt þ iLr ðtÞ dtA ð4:32Þ
T
t0 t1 t2 t3
Substituting (4.6), (4.12), (4.20) and (4.26) in (4.32) and rearranging terms,
yields:
i o‘
I2
I3
I1
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Fig. 4.16 Normalized output current referred to the transformer primary side
(a) (b)
1.0 1.0
q 0.8 q 0.8
0.6
0.8 0.8
0.6
0.4
0.6 0.6
0.4
μo=0.2
0.2
0.4 0.4
0.2 μo=0.8
D=0
0.2 0.2
D=0
0 0
0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0
Io Io
Fig. 4.17 Output characteristics taking the duty-cycle as parameter for a µo = 0.2 and b µo = 0.8
I0 z 2 lo ð1 qÞ p D2 3 2q
I0o ¼ o ¼ þ þ D ð4:33Þ
V1 p q 2q lo q
Equation (4.33) represents the normalized load current as a function of the static
gain (q), taking the duty-cycle (D) and the normalized switching frequency (µo) as
parameters. This means that this converter can be controlled by frequency modu-
lation or pulse-width modulation. The output characteristics, given by Eq. (4.33)
are plotted in Fig. 4.17.
4.4 Numerical Example
The converter shown in Fig. 4.1 operates with the specifications given by
Table 4.1.
Table 4.1 Design specifications

Input DC voltage (Vi) 400 V
Minimum power (Po min) 100 W
Resonant frequency (fo) 400 kHz
Static gain (q) 0.6
Transformer turns ratio (n) 3.2
Frequency ratio (µo) 0.1
Duty cycle (D) 0.4
Find: (a) the inductance of the resonant inductor Lr, the capacitance of the resonant capacitor Cr,
and (b) the duty-cycle for operation at minimum power
Solution:
The output DC voltage referred to the primary side of the transformer (V0o ) is:
400
V0o ¼ q V1 ¼ 0:6 ¼ 160 V
2
The normalized output current is:

I0 z 2 1 f s ð1 qÞ p D2 3 2q
I0o ¼ o ¼ þ þ D ¼ 1:3
V1 p q f o 2q f s =f o q
Thus, the average output current referred to the primary side of the transformer
is:
Io 10
I0o ¼ ¼ ¼ 3:125 A
N1 =N2 3:2
Hence,
rffiffiffiffiffi
Lr I0o V1
z¼ ¼ 0 ¼ 83:2
Cr Io
Consequently,
Lr ¼ 6922:24Cr
We know that
1
Lr Cr ¼ ¼ 1:58 1013
ð2pf o Þ2
Thus:
Cr ¼ 4:782 nF
Lr ¼ 33:1 lH
(b) The load current at the minimum power is
100
Io min ¼ ¼2A
50
4.4 Numerical Example 109
Hence,
Io min 2
I0o min ¼ ¼ ¼ 0:625 A
N1 =N2 3:2
and
I0o min Lr =Cr 0:625 83:2
I0o min ¼ ¼ ¼ 0:26
V1 200
At minimum power we have:

2 1 fs ð1 qÞ p D2min 3 2q
I0o min ¼ þ þ Dmin
p q fo 2q f s =f o q
Solving for Dmin we find:
Dmin ¼ 0:0236
The Half Bridge CVC-PWM series resonant converter shown in Fig. 4.18 was
simulated with the parameters of Sect. 4.4, to validate the analysis.
the AC voltage vab and the output current I0o , with nominal power. Note that the
converter is in DCM. Figure 4.20 shows the voltage and current in switches S1
and S2.
Figure 4.21 shows the voltage and current in the auxiliary switch S3 during the
commutation under zero voltage.
+ DC1 S1
Vi / 2 io’
- - vCr + Vo’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- DC2

200
vCr
-200
10
iLr
5
0
-5
-10
200
vab
-200
10
io ’
5
0
-5
-10
50 55 60 65 70 75 80
Time (μs)
current i0o , with nominal power
400
vS1
200
iS1 x 20
400
vS2
200
iS2 x 20
0
50 55 60 65 70 75 80
Time (μs)
Fig. 4.20 Voltage and current in switches S1 and S2

4.6 Problems 111
vS3
200
iS3 x 20
100
55.4 55.5 55.6 55.7

Time (μs)
Fig. 4.21 A detail of the switch S3 ZVS commutation turn off
4.6 Problems
(1) A HB CVC-PWM series resonant converter and its switches gate signals are
shown in Fig. 4.22, with the following parameters:
Vi ¼ 400 V V0o ¼ 140 V Cr ¼ 30 nF

Lr ¼ 10 lH f s ¼ 60 kHz DTs =2 ¼ 4:63 ls
Find:
(a) The average output current;
(b) The output power.
Answers: (a) Io = 19.123 A; (b) Po = 2.68 kW
(2) The HB CVC-PWM series resonant converter shown in Fig. 4.23 along with its
gate drive signals has the specifications bellow:
Vi ¼ 400 V Ro ¼ 10 X Co ¼ 30 lF Cr ¼ 30 nF
Lr ¼ 20 lH f s ¼ 40 kHz D ¼ 0:44
Find:
(a) The output voltage referred to the transformer primary side;
(b) The output power;
(c) The duty cycle.
Answers: (a) V0o = 125 V; (b) Po = 1563 W; (c) D = 0.364.
+ D C1 S1
Vi / 2 io ’
- - vCr + Vo ’ Lr
a Cr b
+ S4 S3 iLr
S2
Vi / 2
- D C2
S1 TS
TS / 2 t
S2
S3
S4 4.63μs
4.63μs
Fig. 4.22 HB CVC-PWM SRC and its drive signals
+ S1 io
Vi / 2 DC1
- - vCr + +
Cr iLr Lr
a b .T.
+ S4 S3 S2 Co Ro Vo
Vi / 2 DC2
-
-
S1 TS
TS / 2 t
S2
S3
S4 80o
80o
Fig. 4.23 HB CVC-PWM SRC and its drive signals
(3) Consider the topological variation of the HB CVC-SRC presented in Fig. 4.24.
Describe the time intervals and the main waveforms for one switching period.
Show that this topology has the same static gain expression like the converter
presented in this chapter.
Reference 113
+ Cr /2 DC1 S1
Vi / 2 io’
- Vo’ Lr
a
S4 S3 b
+ iLr
S2
Vi / 2
- Cr /2 DC2
Fig. 4.24 HB CVC-PWM SRC topological variation
Reference
1. Freitas Vieira, J.L., Barbi, I.: Constant frequency PWM capacitor voltage-clamped series
resonant power supply. IEEE Trans. Power Electron. 8(2), 120–126 (1993)
Chapter 5
Series Resonant Converter Operating
Above the Resonant Frequency
Nomenclature
Vi Input DC voltage
Po Output power
q and qCo Static gain
fs Switching frequency [Hz]
xs Switching frequency [rad/s]
Ts Switching period
fo Resonant frequency [Hz]
xo Resonant frequency [rad/s]
lo Frequency ratio
td Dead time
T Transformer
N1 and N2 Transformer windings
io Output current

I0o I0o Average output current referred to the transformer primary
D1, D2, D3 and D4 Diodes
C1, C2, C3 and C4 Capacitors
vCr Resonant capacitor voltage

116 5 Series Resonant Converter Operating …
VCo Resonant capacitor peak voltage

VC1 Resonant capacitor voltage at the end of time interval 1 and
three
Q Resonant capacitor charge
inductance)
ILr Inductor fundamental peak current
I1 I1 Inductor current at the end of the first and fourth step of
operation and its normalized value
vcb AC voltage, between points “c” and “b”
vab1 Fundamental AC voltage, between points “a” and “b”
vcb1 Fundamental AC voltage, between points “c” and “b”
vS1 and vS2 Voltage across switches S1 and S2
vg1 and vg2 Switches drive signals
iS1 and iS2 Current in the switches S1 and S2
iC1 and iC2 Capacitors current
xLr, xCR and x Reactance
R1, R2 State plane radius
c, b, h State plane angles
Δt1 Time interval of the first step of operation in (t1–t0)
5.1 Introduction
In Chap. 2, the series resonant converter was studied operating with a switching
frequency bellow the resonant frequency, leading to zero current switching (ZCS).
In this chapter, it will be analyzed the series resonant converter operating with a
switching frequency above the resonant frequency. As a result, the switches
commutate with zero voltage (ZVS) and the switches’ intrinsic capacitance may be
incorporated into the commutation process.
The power stage diagrams of the Full-Bridge ZVS and Half-Bridge ZVS series
resonant converters operating above the resonant frequency are shown in Figs. 5.1
and 5.2, respectively.
S1 D1 C1 C2 D2 S2 io
Cr +
Lr c T
Vi
+ a b
..
- S3 D3 C3 C4 D4 S4 iLr + - Co Ro Vo
vCr
Fig. 5.1 Full-bridge ZVS series resonant converter
+ C2 D2 S2 io
Vi / 2
- Lr Cr +
c T
a b
..
C4 D4 S4 iLr + - Co Ro Vo
+ vCr
Vi / 2
-
-
Fig. 5.2 Half-bridge ZVS series resonant converter
In this section, the converter shown in Fig. 5.3, without the commutation capacitor,
is analyzed (the soft commutation analysis is presented in Sect. 5.4). The following
assumptions are made:
Fig. 5.3 Half-bridge series

resonant converter + S1
Vi / 2 io ’ D1
- Vo ’ Cr Lr iLr b
a
+
- +
vCr S2
Vi / 2 D2
-
voltage referred to the primary of the transformer;
• the converter is controlled by frequency modulation and the switches operate at
50% duty cycle without dead time between the gate signals of the switches.

The topological state for this time interval is presented in Fig. 5.4. It begins when
the inductor current reaches zero at t = t0. Switch S1, that was already gated on,
conducts the inductor current. The inductor current and capacitor voltage evolve in
a resonant way. The DC bus delivers energy to the load.
At t = t1 switch S1 is turned off and switch S2 is gated on. As the inductor current is
still positive, it starts to flow through diode D2, as shown in Fig. 5.5. The resonant
tank delivers energy to the DC bus and the load.

Vi / 2 io ’ D1
a
+
- +
vCr S2
Vi / 2 D2
-

Vi / 2 io ’ D1
a
+
- +
vCr S2
Vi / 2 D2
-

Time interval Δt3 begins when the inductor current reaches zero at t = t2, as shown
in Fig. 5.6. Switch S2, that was already gated on, conducts the inductor current. The
inductor current and capacitor voltage evolve in a resonant way. The DC bus
delivers energy to the load.
At t = t3 switch S2 is turned off and switch S1 is gated on. As the inductor current is
negative, it starts to flow through diode D1, as shown in Fig. 5.7. The resonant tank
delivers energy to the DC bus and to the load. The main waveforms and the time
diagrams are shown in Fig. 5.8.

Vi / 2 io ’ D1
a
+
- +
vCr S2
Vi / 2 D2
-

Vi / 2 io’ D1
- Vo’ Cr Lr iLr b
a
+ +v - S2
Cr
Vi / 2 D2
-
vg1 TS
vg2 t
iLr
I1
-I1
vCr
VC0
VC1
-VC1
-VC0
vS1
Vo’
iS1
vS2
Vo’
iS2
t0 t1 t2 t3 t4
Fig. 5.8 Main waveforms and time diagram of the series-resonant converter operating with
switching frequency above the resonant frequency
In this section, the resonant capacitor voltage and resonant inductor current equa-
tions are obtained as well as the output characteristics. Since the converter is
symmetrical, only half of the switching cycle is analyzed.
(A) Time Interval Δt1

iLr ðt0 Þ ¼ 0
vCr ðt0 Þ ¼ VC0
From the equivalent circuit shown in Fig. 5.4, we can write the differential
equations:
Vi diLr ðtÞ
2 dt
dvCr ðtÞ
dt
The Laplace Transform of Eqs. (5.1) and (5.2) are:
V1 V0o
¼ s Lr iLr ðsÞ þ vCr ðsÞ ð5:3Þ
s
iLr ðsÞ ¼ s Cr vCr ðsÞ þ Cr V0o ð5:4Þ
where: V1 = Vi/2.
Substituting (5.4) in (5.3) and applying the inverse Laplace Transform we
obtain:

vCr ðtÞ ¼ V1 V0o V1 V0o þ VC0 cos ðxo tÞ ð5:5Þ

iLr ðtÞz ¼ V1 V0o þ VC0 sen ðxo tÞ ð5:6Þ
qffiffiffiffiffi
where z ¼ Lr pffiffiffiffiffiffiffiffiffi
1 ffi
Cr and xo ¼ Lr Cr .
Normalizing (5.5) and (5.6) with V1, we find:
vCr ðtÞ
vCr ðtÞ ¼ ¼ 1 q 1 q þ VC0 cosðxo tÞ ð5:7Þ
V1
iLr ðtÞz
iLr ðtÞ ¼ ¼ 1 q þ VC0 senðxo tÞ ð5:8Þ
V1
V0
where q ¼ Vo .
1
The time interval Δt1 is:
h
Dt1 ¼ t1 t0 ¼ ð5:9Þ
xo
At the end of this interval the inductor current and capacitor voltage are:

I1 ¼ 1 q þ VC0 senðhÞ ð5:10Þ

V1 ¼ ð1 qÞ 1 q þ VC0 cosðhÞ ð5:11Þ
To obtain the state-plane trajectory for this time interval, we define:

vCr ðtÞ þ jiLr ðtÞ ¼ ð1 qÞ 1 q þ VC0 ejwo t ð5:12Þ
represents a circle, with the center at coordinates (1 − q) and

Equation (5.12)
radius equal to 1 q þ VC0 .
(B) Time Interval Δt2
The initial current in the resonant
inductor and voltage across the resonant capac-
iLr ðt2 Þ ¼ I1
itor, in this time interval, are:
vCr ðt2 Þ ¼ VC1
From the equivalent circuit shown in Fig. 5.5, we have:
diLr ðtÞ
V1 ¼ Lr vCr ðtÞ V0o ð5:13Þ
dt
dvCr ðtÞ
dt
Applying the Laplace Transform, we find:

V1 þ V0o
¼ s Lr iLr ðsÞ þ Lr I1 vCr ðsÞ ð5:15Þ
s
iLr ðsÞ ¼ s Cr vCr ðsÞ Cr VC1 ð5:16Þ
Substituting (5.16) into (5.15) and applying the inverse Laplace Transform, we
obtain:

vCr ðtÞ ¼ V1 V0o V1 V0o VC1 cosðxo tÞ þ I1 z sen ðxo tÞ ð5:17Þ

iLr ðtÞz ¼ V1 þ V0o þ VC1 sen ðxo tÞ þ I1 z cos ðxo tÞ ð5:18Þ
Normalizing with V1 gives:

vCr ðtÞ
vCr ðtÞ ¼ ¼ 1 q þ 1 þ q þ VC1 cosðxo tÞ þ I1 sen ðxo tÞ ð5:19Þ
V1
iLr ðtÞz
iLr ðtÞ ¼ ¼ 1 þ q þ VC1 senðxo tÞ þ I1 cosðxo tÞ ð5:20Þ
V1
Time interval Δt2 is:

c
Dt2 ¼ t2 t1 ¼ ð5:21Þ
xo
The capacitor voltage in the end of this time interval is:

VC0 ¼ 1 q þ 1 þ q þ VC1 cosðcÞ þ I1 senðcÞ ð5:22Þ
To obtain the state-plane trajectory for this time interval, we define:

vCr ðtÞ þ j iLr ðtÞ ¼ ð1 þ qÞ þ 1 þ q þ VC1 þ jI1 ejxo t ð5:23Þ
Equation (5.23) represents a circle, with the center at coordinates −(1 − q) and
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 ffi
2
radius equal to 1 þ q þ VC1 þ I1 .
(C) State Plane Trajectory for one Switching Cycle

The state plane trajectory for one switching cycle is shown in Fig. 5.9.
(D) Output Characteristics
For the normalized state plane shown in Fig. 5.9, the radius R1 and R2, and the
angles h and c are given by Eqs. (5.24), (5.25), (5.26) and (5.27), respectively.

iLr
trajectory for the series
I1
resonant converter operating
on steady-state, for lo 1 R2 β
R1
γ θ
0 -1-q 1-q
-I1
-qC0 -qC1 0 qC1 qC0

vCr
R1 ¼ qCO þ 1 q ð5:24Þ
R2 ¼ qCO þ 1 þ q ð5:25Þ
h ¼ xo Dt1 ð5:26Þ
c ¼ xo Dt2 ð5:27Þ
In one switching period the following equation may be written:
1 1
¼ ð5:28Þ
Ts 2ðDt1 þ Dt2 Þ
Hence,
fs 2p 1
lo ¼ ¼ ð5:29Þ
f o 2ðDt1 þ Dt2 Þ xo
Therefore,
lo 1 1
¼ ¼ ð5:30Þ
p xo ðDt1 þ Dt2 Þ h þ c
In half of the switching period the capacitor charge (Q) is:
ZTs =2
2
Q ¼ 2 Cr VCo ¼ iLr ðtÞdt ð5:31Þ
Ts
0
The average load current is determined by:
ZTs =2
2
I0o ¼ iLr ðtÞdt ð5:32Þ
Ts
0
Substituting (5.32) in (5.31) yields:
0 0
Q ¼ 2 Cr VCo ¼ I ð5:33Þ
2 o
Thus,
I0o
VCo ¼ ð5:34Þ
4 f s Cr
Normalizing (5.34) with V1, we have:
VCo I0o
qCo ¼ ¼ ð5:35Þ
V1 4 f s Cr V1
The normalized average output current is:

z I0o
I0o ¼ ð5:36Þ
V1
Substituting (5.35) in (5.34), it can be found:
VCo I0o V1 1 I0 p I0 p
qCo ¼ ¼ ¼ o ¼ o ð5:37Þ
V1 z 4 f s Cr V1 2 2p f s Cr z 2 lo
Substitution of (5.36) in (5.24) and (5.25) yields:
R1 ¼ qco þ 1 q ð5:38Þ
R2 ¼ qco þ 1 þ q ð5:39Þ
From the state-plane trajectory in Fig. 5.9, using the law of cosines, we find:
22 ¼ R21 þ R22 2 R1 R2 cosb ð5:40Þ
Since the sum of the interior angles of a triangle is p, we have: b ¼ p c h or

b ¼ p lp .
o
Let q ¼ lp . Thus, b ¼ p q.
o
With appropriate algebraic manipulation and rearranging terms, we find
I0o
R1 ¼ qþ1 q ð5:41Þ
2
I0o
R2 ¼ qþ1þq ð5:42Þ
2
cosðbÞ ¼ cosðqÞ ð5:43Þ
Substituting (5.41), (5.42) and (5.43) in (5.40) we obtain:

!2 !2
I0o I0o
4¼ qþ1 qþ qþ1þq
2 2
! ! ð5:44Þ
I0o I0o
þ2 qþ1 q q þ 1 þ q cosðqÞ
2 2
Thus,
!2 ! !
I0 q I0 q I0o q
2 o þ1 þ 2 q2 þ 2 o þ 1 q þ 1 þ q cosðqÞ 4 ¼ 0
2 2 2
ð5:45Þ
Rearranging terms, gives:

!2 !2
I0 q I0 q
2 o þ1 þ2q þ2 o þ1
2
cosðqÞ 2q2 cosðqÞ 4 ¼ 0 ð5:46Þ
2 2
1cosðqÞ q 1 þ cosðqÞ q
Letting 2 ¼ sin2 2 and 2 ¼ cos2 2 in Eq. (5.46) gives:
!2
q I0o q q
q2 sin2 ¼1 þ1 cos2 ð5:47Þ
2 2 2
Solving the algebraic Eq. (5.47) in relation to the static gain q, yields:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u
0 2
u
u1 Io q 1 cos2 q
u 2 2
q¼t
2 q
ð5:48Þ
sin 2

characteristics of the ideal q
series resonant converter for
lo 1 0.8
0.6
0.4
0.2
1.5 1.3 1.1 μo=1.05

0
0 2 4 6 8 10
Io’
Substitution of q ¼ p=lo in Eq. (5.48) gives:

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u
0 2
u
u1 Io p þ 1 cos2 p
u 2 lo 2 lo
q¼u
t ð5:49Þ
sin2 2 pl
o
Equation (5.49) represents the static gain of the series resonant converter, with
switching frequency larger than the resonant frequency, as a function of the nor-
malized output current and having the normalized switching frequency µo as
parameter. The output characteristics are plotted in Fig. 5.10. Note that the series
resonant converter operating above the resonant frequency has a current source
characteristic that can be beneficial for protection of the converter against overload
or overcurrent, similar to the series resonant converter operating with switching
frequency lower than the resonant frequency.
(E) Analysis of the Series Resonant Converter for lo 1, Based in the First
Harmonic Approximation
In this section, the analysis of the series resonant operating above the resonant
frequency, using the first harmonic approximation, is studied. The series resonant
converter equivalent circuit is shown in Fig. 5.11.
The transformer is considered ideal and its magnetizing current is neglected. The
amplitude of the fundamental components of the rectangular voltage vab and vcb are
given by expressions (5.50) and (5.51), respectively.
4
vab1 ¼ V1 ð5:50Þ
p
4
vcb1 ¼ V0o ð5:51Þ
p
Lr Cr
a c io’
iLr
+ +
Vi Inverter Vi' Vo' Vo’
- -
b b
Fig. 5.11 Series resonant converter equivalent circuit

Defining the absolute values of xLr and xCr by the expressions (5.52) and (5.53),
respectively.
jxLr j ¼ Lr xs ¼ 2pf s Lr ð5:52Þ
1 1
jxCr j ¼ ¼ ð5:53Þ
Cr xs 2pf s Cr
Hence, the absolute value of the equivalent reactance is given by expression

(5.54).
jxj ¼ jxLr j jxcr j ð5:54Þ
Therefore,
1
jxj ¼ Lr xs ð5:55Þ
Cr xs
The output diode rectifier forces the current iLr to be in phase with the voltage
vcb1. Also, when the converter operates with fs fo, the current iLr lags the voltage
vab1 by 90°.
Therefore, on steady state operation, we can represent the voltage and current by
the phasor diagram shown in Fig. 5.12.
From the phasor diagram, we have:
v2ab1 = v2cb1 þ ðjxjILr Þ2 ð5:56Þ
where ILr is the inductor’s fundamental peak current.

Thus,
v2cb1 = v2ab1 ðjxjILr Þ2 ð5:57Þ
Fig. 5.12 Phasor diagram

for the first harmonic
approximation vab1
x ILr
ILr vcb1
Substituting Eqs. (5.50) and (5.51) into (5.57), we obtain:

2
2
4 0 4
V ¼ V1 þ ðjxjILr Þ2 ð5:58Þ
p o p
Thus,
!2 !2
4 0
p Vo jxjILr
4
¼1 4
ð5:59Þ
p V1 p V1
The static gain is defined by:
V0o
q¼ ð5:60Þ
V1
Hence,
!2
jxjILr
q ¼1
2
4
ð5:61Þ
p V1
or yet,
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!2
u
u j jI
q ¼ t1 4
x Lr
ð5:62Þ
p V1
Figure 5.13 shows the currents on the input and output of the diode rectifier.
θ)
iL(θ
ILr
π 2π
θ
θ)
io’(θ
ILr
I o’
Fig. 5.13 Current on the input and output of the diode rectifier
The average value of the rectified current is:
2
I0o ¼ ILr ð5:63Þ
p
Thus,
p 0
ILr ¼ I ð5:64Þ
2 o
Substituting expression (5.64) in (5.62), we get:

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!2ffi
u
u jxj p Io 0
q ¼ t1 ð5:65Þ
2 p4 V1
After appropriate simplifications, it can be found:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

0 2 2ffi
x Io p
q¼ 1 ð5:66Þ
V1 8
The expression (5.67) of the normalized current was already defined in previous
sections:
z 0
I0o ¼ I ð5:67Þ
V1 o
Thus,
V1 0
I0o ¼ I ð5:68Þ
z o
Or,

2 !2
jxj I0o jxj I0o
¼ ð5:69Þ
V1 z
But,

j xj 1 1
¼ qffiffiffiffiffi xs Lr ð5:70Þ
z Lr xs Cr
Cr
With
1
xo ¼ pffiffiffiffiffiffiffiffiffi ð5:71Þ
Lr Cr
and the appropriate algebraic manipulation of expressions (5.70) and (5.71), we

find:

2
2 2

jxj I0o p2 p xs xo 2 0 2
¼ Io ð5:72Þ
V1 8 8 xo xs
Substituting Eq. (5.72) into (5.66), we find:

2

p xs xo 0 2
q¼ 1 I ð5:73Þ
8 xo xs o
Since
xo f o
¼ ð5:74Þ
xs f s
We have:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

p4 f s f o 2 0 2
q¼ 1 Io ð5:75Þ
64 f o f s
The normalized switching frequency is defined by:
fs
lo ¼ ð5:76Þ
fo
Substitution of Eq. (5.76) in Eq. (5.75) yields

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

ffi
p4 1 2 02
q¼ 1 l Io ð5:77Þ
64 o lo
Equation (5.77) represents the output characteristics of the series resonant

converter, obtained for voltage and current fundamental components, for fs fo.
The output characteristics given by Eq. (5.77) are plotted in Fig. 5.14.

characteristics obtained for q
the first harmonic
approximation 0.8
0.6
0.4
0.2
1.5 1.3 1.1 μo=1.05

0
0 2 4 6 8 10 12
I o’
5.4 Commutation Analysis
Figure 5.15 shows the topological state and the relevant waveforms for the first
commutation time interval that takes place between time interval Δt1 and Δt2 of
Sect. 5.2. When switch S1 is turned off but switch S2 is not yet gated on (dead
time). The inductor current during this time interval is I1 and half of this current
(I1/2) flows through each of the commutation capacitors, charging C1 from zero to
Vi and discharging C2 from Vi to zero. Figure 5.15 also shows the main waveforms
where the soft commutation (ZVS) of the switches may be noted. As soon as
capacitor C2 is discharged, the diode D2 starts to conduct the inductor current. The
accomplishment of soft commutation requires that commutation capacitors’ charge/
discharge must finish before the dead time ends.
The second commutation time interval, whose topological state is shown in
Fig. 5.16, takes place between time interval Δt3 and Δt4 of Sect. 5.2, when switch
S1 dead
time
S2 t
+ C1 D1 S1
vs1
Vi / 2 io’ Vi
- Vo’ Cr Lr
iS1
iLr b
I1
a
+
- + vs2
vCr C2 D2 S2 Vi
Vi / 2 iD2
- I1
iC1
I1/2
Fig. 5.15 Topological state and main waveforms for the first commutation time interval
5.4 Commutation Analysis 133
S2 is turned off but switch S1 is not yet gated on (dead time). The value of the
inductor current during this time interval is also I1 and half of it flows through each
one of the commutation capacitors, charging C2 from zero to Vi and discharging C1
from Vi to zero. Figure 5.16 also shows the relevant waveforms where the soft
commutation (ZVS) of both switches may be noticed. At the instant the capacitor
C1 is fully discharged, diode D1 starts conducting the inductor current. The
capacitors must be fully charge/discharge before the dead time ends to realize soft
commutation.
The commutation current I1 may be found from the analysis of the state-plane
trajectory in Fig. 5.9. According to the sine law we have:
2 R2 R1
¼ ¼ ð5:78Þ
sin b sin h sin c
The commutation current is
I1 ¼ R2 sinc ð5:79Þ
Substituting (5.78) in (5.79) we find:

R1 R2 R1 R2 p
I1 ¼ sin b ¼ sin p ð5:80Þ
2 2 lo
The radius R1 and R2 are:
I1 p
R1 ¼ þ1þq ð5:81Þ
2 lo
I1 p
R2 ¼ þ1 q ð5:82Þ
2 lo
S2 dead
time
S1 t
+ C1 D1 S1
Vi / 2 io’ vs2
- Vo’ Cr Lr Vi iS2
iLr b I1
a
+ +v - C2 D2 S2 vs1
Cr
Vi / 2 Vi
- I1
iD1
iC2
I1/2
Fig. 5.16 Topological state and main waveforms for the second commutation time interval
Fig. 5.17 Commutation 15

current I1 as a function of the I1
frequency ratio lo, taking the
static gain (q) as a parameter
10
5
q=0.25
0.50
0.75
0
1.0 1.2 1.4 1.6 1.8 2.0
μο
Substitution of (5.82) and (5.81) in (5.80) gives:

"
2 #

1 Io p p
I1 ¼ þ1 q 2
sin p ð5:83Þ
2 2 lo lo
Substitution of (5.65) in (5.83) yields:

p
I1 ¼ 1 q2 tg ð5:84Þ
2 lo
The normalized commutation current I1 , as a function of the frequency ratio lo,

taking the static gain (q) as a parameter, is plotted in Fig. 5.17. The smaller the
commutation current, the longer the capacitors take to charge/discharge. It is not
possible to ensure soft commutation in all load range because I1 may reach a critical
value, in which is not possible to fully charge/discharge the capacitors, and a
dissipative commutation will take place. For a giving dead time and load range, the
capacitors are calculated as follows:
I1 td
C1 ¼ C2 ¼ ð5:85Þ
Vi
5.5 Numerical Example
A series resonant converter that operates with the switching frequency above the
resonant frequency, has the parameters given by Table 5.1.
Find: (a) the resonant inductance Lr, (b) the resonant capacitance Cr, (c) the
capacitances of the commutation capacitors.
Solution:
The output DC voltage referred to the primary side of the transformer (V0o ) and
the transformer turns ratio is calculated as follows:
400
V0o ¼ q V1 ¼ 0:6 ¼ 120 V
2
N1 V0o 120
n¼ ¼ ¼ ¼ 2:4
N2 Vo 50
At nominal power, the switching frequency is
f s min ¼ f o lo ¼ 20 103 1:1 ¼ 22 103 Hz
The resonant frequency is given by
1
fo ¼ pffiffiffiffiffiffiffiffiffiffi ¼ 20 103 Hz
2p Lr Cr
Therefore,
Lr Cr ¼ 63:325 1012
In the operation point, from the output characteristic we find the normalized
output current:
Table 5.1 Specifications Input DC voltage (Vi) 400 V

of the converter
Static gain (q) 0.6
Normalized switching frequency (lo) 1.1
Dead time (td) 1 µS
I0o ¼ 3:25
second ratio between the resonant components.
Io 10
I0o ¼ ¼ ¼ 4:1667 A
N1 =N2 2:4
From the equation

I0o Lr =Cr
I0o ¼
V1
we find

0 2
Lr Io V1
¼ ¼ 24; 336
Cr Io0
Thus, combining the previous results, we find:
Cr ¼ 51 nF
Lr ¼ 1:2414 mH
The series resonant converter operating above the switching frequency shown in
Fig. 5.18 is simulate, with commutation capacitances Cc = 2.125 nF and a dead
time of 455 ns. Figure 5.19 shows the voltage and current in the resonant tank, the
AC voltage vab and the output current i0o . The voltage and current in the switches are
presented in Fig. 5.20 and a detail of the commutation showing the zero voltage
switching (ZVS) in switch S1 is presented in Fig. 5.21.
+ C1 D1 S1
Vi / 2 io ’
a
+
- +
vCr C2 D2 S2
Vi / 2
-

1000
vCr
0
1000
-
10
iLr
-10
vab
200
-200
10
i o’
-10
120 140 160 180 200
Time (μs)
current i0o , at nominal power
1
vg1 vg2 td
vS1
400
200
iS1 x 20
0
vS2
400
200
iS2 x 20
0
70 80 100 120
Time (μs)
Fig. 5.20 Switches S1 and S2 commutation at nominal power: gate signals, voltage and current in
the switches
1
vg1 vg2
td
vS1
400
200
iS1 x 20
0
112 113 114 115

Time (μs)
Fig. 5.21 A detail of switch S1 commutation at turn off, for nominal power: S1 and S2 gate
signals, voltage and current at the switch S1
5.6 Problems
(1) The full-bridge series resonant converter shown in Fig. 5.22 has the following
parameters:
Vi ¼ 400 V Np =Ns ¼ 1 Cr ¼ 52 nF
Lr ¼ 48:65 lH lo ¼ 1:5 Ro ¼ 25 X
Calculate:
(a) The resonant frequency;
(b) The output average current;
(c) The output voltage;
(d) The resonant capacitor peak voltage;
(e) The resonant inductor peak current.
Answers: (a) fo = 100 kHz; (b) Io = 9.19 A; (c) Vo = 229.7 V;
(d) VCo = 294 V; (e) 15.2 A.
S1 D1 D2 S2 io
Cr +
Lr c T
Vi
+ a b
..
- S3 D3 D4 S4 iLr + - Co Ro Vo
vCr

5.6 Problems 139
(2) Consider the full-bridge series resonant converter shown in Fig. 5.22 operating
with lo = 1.5 and the output short circuited. Find the equations for:
(a) The resonant capacitor peak voltage;
(b) The average output short circuit current;
(c) The resonant inductor peak current.
Answer: (a) vCrpeak = Vi ; (b) I0o ¼ p3 Vz i ; (c) iLrpeak ¼ 2 zVi

(3) For the converter of previous exercises, find:
(a) The average output short circuit current;
(b) The resonant inductor peak current;
(c) The resonant capacitor peak voltage;
(d) The dc-bus average current.
Describe the converter operation, representing the topological states and the
main waveforms, considering all components ideal and verify the results with
simulation.
Answers: (a) Io ¼ 12:4 A; (b) iLrpeak ¼ 26:18 A; (c) vCrpeak ¼ 400 V; (d) iVi ¼ 0.
(4) The converter of exercise 1 operates with lo = 1.5 and Vo = 200 V. Find the
load resistance Ro.
Answer: Ro = 20 Ω.
Chapter 6
LLC Resonant Converter
6.1 Introduction
Figure 6.1 shows the power stage diagram of two common topological variations of
the LLC converter, with a full bridge rectifier.
The Series Resonant Converter (SRC) is a particular topology of the LLC
converter, where the magnetizing inductance is relatively large and not involved in
the resonance operation [1–4].
The LLC converter has many benefits over the conventional series resonant
converter. For example, it can regulate the output voltage over wide line and load
variations with a relatively small variation of switching frequency, while preserving
very high efficiency. It can also operate at zero voltage switching (ZVS) over the
entire operating range.
A representation of the Full Bridge LLC converter with all parameters reflected
to the primary side of the transformer, including the magnetizing inductance, is
shown in Fig. 6.2.
For the converter’s steady state analysis, the capacitor Co in parallel with Ro is
replaced with the voltage source V0o .
In Fig. 6.2, it can be observed that there are two inductors (Lr and Lm) and a
resonant capacitor (Cr) that provide unique characteristics, in comparison to others
resonant converters, in terms of static and dynamic characteristics and also
switching losses.
The LLC converter can operate with frequency modulation (FM) or pulse width
modulation (PWM), but we will study only its behavior under frequency modu-
lation, which is the most common case.

142 6 LLC Resonant Converter
(a)
S1 D1
Cr /2
Lr
Vi
+ a b c
.T.
- S2 D2 iLr Co Ro
Cr /2 Lm
iLm
(b)
S1 D1 D2 S2
+
Cr iLr Lr c T
Vi +
a b
..
–
S3 D3 D4 S4 + - vs vp Co Ro Vo
vCr
Lm
iLm -
Fig. 6.1 Power stage diagram of the: a Half Bridge and b Full Bridge LLC resonant converter
S1 D1 D2 S2
Cr iLr Lr i'o
+ a b
Vi –
S3 D3 D4 S4 + -
vCr
Lm +
V'o
–
iLm
Fig. 6.2 Power stage of the Full Bridge LLC resonant converter, with ideal components and
parameters reflected to the primary side of the transformer
6.2 First Harmonic Equivalent Circuit
Figure 6.3 represents the LLC converter in a different perspective with all param-
eters reflected to the transformer’s primary side.
The waveform of the rectangular voltage Vx is represented in Fig. 6.4 with its
fundamental harmonic. The converter switching frequency is represented by fs.
6.2 First Harmonic Equivalent Circuit 143
Lr Cr iy
a c i'o
ix
+
V1 +
Inverter Vx Lm Vy – V'o
–
im
b b
Fig. 6.3 Simplified representation of the LLC converter
Fig. 6.4 Waveform of the vx1(t)

voltage Vx and its first
vx(t)
harmonic V1
0 Ts / 2 Ts
-V1
Then,
4V1
vx1 ðt) ¼ sinðxs tÞ ð6:1Þ
p
where
xs ¼ 2pf s ð6:2Þ
and
1
Ts ¼ ð6:3Þ
fs
The voltage Vy can also be considered rectangular, which amplitude is V0o .

Its waveform and first order harmonic are represented in Fig. 6.5.
The first harmonic of Vy is given by (6.4).
4V0o
vy1 ðt) ¼ sinðxs t f) ð6:4Þ
p
The displacement angle between Vx1 and Vy1 is represented by /.

Fig. 6.5 Waveform of the vy1 (t)

voltage Vy and its first
vy (t)
harmonic V'o
(0 + t) (Ts / 2 + t) (Ts + t)
-V'o
The first harmonic equivalent circuit of the LLC converter is shown in Fig. 6.6.
The output diode rectifier keeps current iy1 and voltage Vy1 in phase.
Applying Thevenin’s Theorem, it can be obtained the equivalent circuit shown
in Fig. 6.7.
The voltage VTp is defined by (6.5).
jxs Lm
VTp ¼ Vxp ð6:5Þ
jxs Cr + jxs ðLr + Lm Þ
1
With the proper algebraic manipulation of (6.5) it can be obtained (6.6).
x2s Cr Lm
VTp ¼ Vxp ð6:6Þ
x2s Cr ðLr + Lm Þ 1
The expression (6.6) shows that voltages VTp and Vyp are in phase.
Fig. 6.6 First harmonic Cr i Lr iy1

equivalent circuit of the LLC x1
converter
im1
Vx1 Lm Vy1
Fig. 6.7 Equivalent circuit LT iyp a

obtained from Thevenin’s
Theorem
VTp Vyp
b
6.2 First Harmonic Equivalent Circuit 145
The equivalent Thevenin’s impedance can be defined by (6.7).

jxs Lm jxs Lr þ jx1C
ZT ¼ 1 s r
ð6:7Þ
jx C + jx ðL
s r + Lm Þ
s r
With the proper algebraic manipulation of (6.7), (6.8) is obtained.

jxs Lm x2s Cr Lr 1
ZT ¼ 2 ð6:8Þ
xs Cr ðLr + Lm Þ 1
6.3 Voltage Gain Characteristics
To obtain the steady state curves of a LLC converter for sinusoidal currents and
voltages, the phasorial representation is employed, as shown in Fig. 6.8.
4V1
Vxp ¼ ð6:9Þ
p
4V0o
Vyp ¼ ð6:10Þ
p

Lm x2s Cr Lr 1
LT ¼ 2 ð6:11Þ
xs Cr ðLr + Lm Þ 1
In Fig. 6.8, the phasors represent voltages and currents amplitude. The angle /
represents the phase displacement between the voltages Vxp and Vyp. From the
analysis of the phasorial diagram shown in Fig. 6.8, (6.12) can be written.
2
V2Tp ¼ V2yp þ xs LT Iyp ð6:12Þ
Thus:
0 2
4Vo 2
V2Tp ¼ þ xs LT Iyp ð6:13Þ
p
Fig. 6.8 Phasorial

representation for the first
harmonic circuit
sLT
iyp Vyp
The peak value of Iy, in terms of the average value of the reflected load to the
primary winding Io, is given by (6.14).
p
Iyp ¼ I0o ð6:14Þ
2
Substituting (6.14) into (6.13), the expression (6.15) can be obtained.

0 2 2
4Vo xs LT pI0o
V2Tp ¼ þ ð6:15Þ
p 2
From the substitution of (6.6) and (6.11) into (6.15), (6.16) can be written.
2 0 2 2
4V1 2 x2s Cr Lm 4Vo p 2 xs Lm x2s Cr Lr 1 I0o
¼ þ
p x2s Cr ðLr + Lm Þ 1 p 2 x2s Cr ðLr + Lm Þ 1
ð6:16Þ
The simplification of (6.16) leads to (6.17).

2 2
2 x2s Cr Lm p4 xs Lm x2s Cr Lr 1 I0o
V0o ¼ 2
ðV 1 Þ ð6:17Þ
x2s Cr ðLr + Lm Þ 1 64 x2s Cr ðLr + Lm Þ 1
Considering the following definitions:
V0o
M¼ ð6:18Þ
V1
xs ¼ 2pf s ð6:19Þ
1
xr1 ¼ pffiffiffiffiffiffiffiffiffi ð6:20Þ
Cr Lr
xs
xn ¼ ð6:21Þ
xr1
Therefore:
x2s Cr Lr ¼ x2n ð6:22Þ
Lr
k¼ ð6:23Þ
Lm
xs Lr 0
I0o ¼ I ð6:24Þ
V1 o
6.3 Voltage Gain Characteristics 147
Replacing (6.18) and (6.24) into (6.17), it can obtain the expression (6.25).
2 " 0 #2
x 2
p4 x 2
1 Io
M2 ¼ 2 n
n
ð6:25Þ
x n ð k þ 1Þ k 64 x2n ðk þ 1Þ k
Appropriate algebraic manipulation gives

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
h i2
x4n 64 p4
x2n 1 I0o
M¼ ð6:26Þ
x2n ðk þ 1Þ k
Also:
xr1 ¼ 2pf r1 ð6:27Þ
xs ¼ 2pf s ð6:28Þ
In addition:
fs
xn ¼ ð6:29Þ
f r1
xn ¼ f n ð6:30Þ
Then, the voltage gain M can now be represented by (6.31).

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
h i2
f 4n 64 p4
f 2n 1 I0o
M¼ ð6:31Þ
f 2n ðk þ 1Þ k
When fr = fs, the relative frequency fn = 1 and M = 1, regardless the value of

the current I0o . The resonance frequency fr is defined by the values of Cr and Lr,
according to the expression (6.32).
1
f r1 ¼ pffiffiffiffiffiffiffiffiffi ð6:32Þ
2p Cr Lr
The converter’s voltage gain is infinite, theoretically, when the denominator of

(6.32), represented by (6.33), is equals to zero.
f 2n ðk þ 1Þ k ¼ 0 ð6:33Þ
Therefore, when:
rffiffiffiffiffiffiffiffiffiffiffi
k
fn ¼ ð6:34Þ
kþ1
Substituting (6.23) into (6.34), leads to (6.35).

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Lr
fn ¼ ð6:35Þ
Lr + Lm
Also:
fs
fn ¼ ð6:36Þ
f r1
Therefore:
Lr
fs ¼ fr ð6:37Þ
Lr + Lm
Substituting (6.32) into (6.37) leads to (6.38).

1 Lr
f s ¼ pffiffiffiffiffiffiffiffiffi ð6:38Þ
2p Cr Lr Lr + Lm
Thus:
1
fs ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð6:39Þ
2p Cr ðLr + Lm Þ
The Eq. (6.39) represents the resonance frequency of a series resonant circuit,
composed by Cr, Lr and Lm, as shown in (6.40).
1
f r2 ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð6:40Þ
2p Cr ðLr + Lm Þ
Dividing (6.40) by (6.32), the relation (6.41) is obtained.

f r2 k
¼ ð6:41Þ
f r1 kþ1
Equation (6.41) is also graphically represented for Fig. 6.9.

From the design step of the LLC resonant converter, it can be ensured that fr2 is
sufficiently smaller than fr1. A typical value for k is 0.2, which implies in
fr2 = 0.4fr1.
Fig. 6.9 fs/fr for different 0.8

values of k
0.6
λ
0.4
λ+ 1
0.2
0
0 0.2 0.4 0.6 0.8 1
λ
Fig. 6.10 Voltage gain M for 2

different values of the
parametrized current I0o 0.2
1.5
0.3
M 1 0.5
0.75
1.0
0.5
0
0.25 0.5 0.75 1 1.25 1.5 1.75
fn
The curves relating M and the normalized frequency fn for different values of the
parametrized current I0o are shown in Fig. 6.10. The ratio k between the inductances
is 0.2.
Figure 6.11 represents the static gain M as function of the parametrized current
I0o for different values of relative frequency fn.
It can be noticed from these curves that the converter’s gain is controlled by
switching frequency. The load voltage reflected to the primary winding of the
transformer can be higher or lower than the input voltage, for switching frequency
greater or smaller than the resonance frequency fr1, respectively. The curves also
show that for 0 I0o 0:5 and 0:8 f n 1:2, the static gain is not very sensitive to
the load current.
Fig. 6.11 Voltage gain M 1.2

versus I0o for different values
of fn
0.8
1.1
0.9
1.0
M 1
1.1
1.2
0.9
0.8
0 0.1 0.2 0.3 0.4 0.5
6.3.1 Numerical Example 1
A LLC converter, with the transformer turns ratio equals to one, has the following
parameters:
• V1 = 400 V
• Lr = 14 lH
• Lm = 70 lH
• Cr = 47 nF
• fs = 170 kHz
• Io = 5 A
Find the voltage and the power in the load.
Solution
Lr 14 106
k¼ ¼ ¼ 0:2
Lm 70 106
1 1
f r1 ¼ pffiffiffiffiffiffiffiffiffi ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 196:2 kHz
2p Lr Cr 2p 14 106 47 109
xr1 ¼ 2pf r1 ¼ 1;232;748 rad/s
fs 170; 000
fn ¼ ¼ ¼ 0:866
f r1 196; 204
xr1 Lr 1;232;748 14 106

I0o ¼ Io ¼ 5 ¼ 0:216
V1 400
h i2
f 4n 64 p4
f 2n 1 I0o
M¼ ¼ 1:067
f 2n ðk þ 1Þ k
V0o ¼ MV1 ¼ 1:067 400 ¼ 426:78 V
Po ¼ V0o I0o ¼ 426:78 5 ¼ 2134 W
6.4 Static Gain Without Load (Open Circuit)
When the converter operates without load, the processed power is zero. In this case,
the parametrized load current is also zero. Consequently, the static gain, given by
(6.42) and shown in Fig. 6.12, can be deduced from the gain expression given by
(6.31).
f 2n
M¼ ð6:42Þ
f 2n ðk þ 1Þ k
It is observed that the static gain is greater than one when f n \1 and smaller than
one when f n [ 1. The converter operates properly without load and can have its
voltage controlled through the switching frequency.
This is one of the most important properties of the LLC converter, and one of its
advantages over the series and parallel resonant converters, which do not have these
properties.
Fig. 6.12 Static gain of a 1.2

LLC without load for different
values of k λ = 0.3
1.1 λ = 0.2
λ = 0.1
M 1
0.9
0.8
0.8 0.9 1 1.1 1.2
fn
6.5 Static Gain as a Function of Load Resistance
The expression (6.31), reproduced from now on as (6.43), represents the static gain
as a function of the parameterized value of the average load current reflected to the
primary side of the transformer.
h i2
f 4n p8 f 2n 1 I0o
2
M¼ ð6:43Þ
f 2n ðk þ 1Þ k
The parameterized current I0o is defined by
xs Lr 0
I0o ¼ I ð6:44Þ
V1 o
However:
V0o
I0o ¼ ð6:45Þ
R0o
The parameter R0o is defined as the load resistance reflected to the primary side of
the transformer.
Therefore:
xs Lr V0o
I0o ¼ ð6:46Þ
V1 R0o
Since
V0o
M¼ ð6:47Þ
V1
We obtain:
xn pffiffiffiffiffiffiffiffi
1 ffi
Lr
p2 Cr Lr
I0o ¼M ð6:48Þ
8 R0o p82
Defining
8
Rac ¼ R0o ð6:49Þ
p2
6.5 Static Gain as a Function of Load Resistance 153
And
qffiffiffiffiffi
Lr
Cr
Q¼ ð6:50Þ
Rac
Rac represents the load resistance reflected to the primary winding of the
transformer for sinusoidal current, and Q the quality factor.
Thus:
p2
I0o ¼ f n MQ ð6:51Þ
8
Substitution of (6.51) into (6.43), with appropriate algebraic manipulation, gives
f 2n
M ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 ð6:52Þ
2
f 2n ðk þ 1Þ k þ f n Q f 2n 1
Figure 6.13 is shown the static gain (M) given by Eq. (6.52), as function of fn,
for different values of the quality factor (Q).
Figure 6.14 shows the static gain (M) as a function of Q for different values of fn.
When the output power is zero, Q = 0 and the static gain expression is repre-
sented by (6.53). This same equation was found in (6.42) considering the para-
metrized load current as zero, which also implies in no power transferred to the
load.
f 2n
M¼ ð6:53Þ
f n ðk þ 1Þ
2
k
Fig. 6.13 Static gain as a 3

function of fn for different
λ = 0.2
values of Q 0.2
M
0.4
1 1.0
2.0
5.0
0
0 0.25 0.5 0.75 1 1.25 1.5 1.75
fn
Fig. 6.14 Static gain as 1.2

function of Q for different
values of fn
0.8
1.1
0.9
1.0
M 1
1.1
1.2
0.9
0.8
0.2 0.3 0.4 0.5 0.6
Q
A LLC converter, with transformer turns ratio a = 1, operates with the following
parameters:
• V1 = 400 V
• Lr = 14 lH
• Lm = 70 lH
• Cr = 47 nF
• fs = 220 kHz
• Ro = 50 X
Find the values of the voltage and the power in the load resistor.
Solution
Lr 14 106
k¼ ¼ ¼ 0:2
Lm 70 106
1 1
2p Lr Cr 2p 14 10 47 1096
xr1 ¼ 2pf r1 ¼ 1;232;748 rad/s
fs 220;000
fn ¼ ¼ ¼ 1:121
f r1 196;204
8 8
Rac ¼ Ro ¼ 2 50 ¼ 40:53 X
p2 p
6.5 Static Gain as a Function of Load Resistance 155
qffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffi
Lr 14106
Cr 47109
Q¼ ¼ ¼ 0:426
Rac 40:53
f 2n
2 2 ¼ 0:956
f 2n ðk þ 1Þ k þ f n Q f 2n 1
V0o ¼ MV1 ¼ 0:956 400 ¼ 382:59 V
0
ðV Þ2 2
Po ¼ Ro ¼ 382:59
50 ¼ 2928 W
o
6.6 Minimum Normalized Frequency
According to the curves plotted in Fig. 6.15, for each value of the parametrized
current I0o , the static gain (M) as a function of normalized frequency fn has a peak
value that defines the boundary between capacitive or inductive input impedance of
the LLC converter. The capacitive impedance happens when the converter operates
below the minimum allowed switching frequency and it must be avoided.
For a given value of I0o , at f n \f nmin , the input impedance becomes capacitive
and when f n [ f nmin , it becomes inductive.
To ensure ZVS operation, it is necessary an inductive impedance, so the current
is delayed in relation to the voltage Vab. The minimum normalized frequency can
be found by differentiation of (6.31) in relation to fn, as follows.
Fig. 6.15 Static gain of a 2

LLC converter for different
values of I0o 0.2
1.5
0.25
M 0.3
0.5
0.25 0.5 0.75 1 1.25 1.5 1.75
fn
2 2

dM I0o ; k; f n 2f n aI0o f 2n aI0o þ kf 2n
¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð6:54Þ
df n 2 4 2 2
kf 2n k + f 2n f n aI0o f 2n 1
where:
p4
a¼ ð6:55Þ
64
To make (6.54) equals to zero,

dM I0o ; k; f n
¼0 ð6:56Þ
df n
it is necessary that
2 2
aI0o f 2n aI0o þ kf 2n ¼ 0 ð6:57Þ
Therefore:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u
u aI0 2
f nmin ¼ t 2o ð6:58Þ
aI0o þ k
Then:
1
f nmin ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð6:59Þ
1 þ 64k0 2
p4 I o
Expression (6.59) is plotted in Fig. 6.16. The value of fmin for a given value of k
is determined for operations with maximum power or for the maximum value of
parametrized load current I0o .
For a given value of I0o , the value of fmin will be naturally respected.
6.6 Minimum Normalized Frequency 157
Fig. 6.16 Minimum 1

normalized frequency as a
function of parametrized
load current for different 0.8
values of k
= 0.2
0.6 = 0.3
fnmin = 0.4
0.4
0.2
0
0 0.1 0.2 0.3 0.4 0.5
A LLC converter operates with the following parameters:

• V1 = 400 V
• Lr = 14 lH
• Lm = 70 lH
• Cr = 47 nF
• a=1
• Io = 5 A (maximum value)
Find the minimum operating frequency required to the LLC input reactance be
inductive.
Solution
Lr 14 106
k¼ ¼ ¼ 0:2
Lm 70 106
1 1
2p Lr Cr 2p 14 10 47 1096
xr1 ¼ 2pf r1 ¼ 1;232;748 rad/s
xr1 Lr 1;232;748 14 106

I0omax ¼ Iomax ¼ 5 ¼ 0:216
V1 400
1
f nmin ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 0:511
1 þ 64k 0
2
p4 Iomax
f smin ¼ f nmin f r1 ¼ 0:511 196:2 ¼ 100:34 kHz
6.7 Commutation’s Analysis
In order to obtain ZVS commutation for the entire range of input voltage and output
power, it is necessary that the switching capacitors be fully charged or discharged
during the “dead time”.
Therefore, it is necessary that the current in the switch at the instant it is turned
off be higher than a minimum value needed to completely charge the commutation
equivalent capacitor.
The lowest current value occurs at the maximum operating frequency with no
load.
Figure 6.17 shows the equivalent circuit of the LLC with no load.
The typical waveforms of the LLC operating at no load are shown in Fig. 6.18.
At the instant that the switches turn off, the value of the current responsible for
charging and discharging the switching capacitor is Imp, which will be determined
as follows.
Fig. 6.17 Equivalent circuit

Lr Cr
of a LLC converter without a
load
iLm
+
+
V1 –
Inverter Vab Lm
-
b
6.7 Commutation’s Analysis 159
Fig. 6.18 Typical waveforms of a LLC operating without load
6.7.1 Current in the Switches During Commutation
During the interval [0, Ts/2] the current is represented by Eq. (6.60).
V1
iLm ðt) ¼ sinðx2 t) Imp cosðx2 t) ð6:60Þ
Z2
where:
Lr + Lm
Z2 ¼ ð6:61Þ
Cr
and
1
x2 ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð6:62Þ
Cr ðLr + Lm Þ
Then:
Z2 iLm ðt) Z2 Imp

¼ sinðx2 t) cosðx2 t) ð6:63Þ
V1 V1
Defining:
Z2 iLm ðt)
iLm ðt) ¼ ð6:64Þ
V1
and
Z2 Imp
Imp ¼ ð6:65Þ
V1
Then:
iLm ðt) ¼ sinðx2 t) Imp cosðx2 t) ð6:66Þ
At the instant t = T/2, iLm ðt) ¼ Imp .

Then:

T T
iLm ðt) ¼ sin x2 Imp cos x2 ð6:67Þ
2 2
However:
T 1
¼ ð6:68Þ
2 2f s
Thus:
T 1
x2 ¼ 2pf r2 ð6:69Þ
2 2f s
T pf r2
x2 ¼ ð6:70Þ
2 fs
Substituting (6.70) into (6.66) and manipulating algebraically, we obtain:

sin pff r2
Imp ¼ s ð6:71Þ
1 þ cos pff r2
s
It was previously determined that:

k
f r2 ¼ f r1 ð6:72Þ
kþ1
Thus:
f r2 f r1 k
¼ ð6:73Þ
fs fs kþ1
With:
fs
¼ fn ð6:74Þ
f r1
It is obtained:
f r2 1 k
¼ ð6:75Þ
fs fn kþ1
Substituting (6.75) into (6.71) gives (6.76).

qffiffiffiffiffiffiffiffi
sin fp k þk 1
Imp ¼
n
qffiffiffiffiffiffiffiffi ð6:76Þ
1 þ cos fp k þk 1
n
Equation (6.76) represents the parametrized current in the switch at the instant it
is turned-off, as a function of the normalized switching frequency f n and the ratio of
the resonant magnetizing inductance k.
In Fig. 6.19 the parameterized current Imp is plotted as a function of the nor-
malized switching frequency f n , for k ¼ 0:2.
Fig. 6.19 Parameterized 1.2

current Imp as a function of
the normalized switching
frequency
1
mp 0.8
0.6
0.4
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
fn
With appropriate algebraic manipulation of Eq. (6.76), Eq. (6.77) can be

obtained.
rffiffiffiffiffiffiffiffiffiffiffi!
p k
Imp ¼ tan ð6:77Þ
2f n kþ1
Figure 6.19 shows that the current at the switching instant decreases with the
increasing of the switching frequency.
6.7.2 Commutation Analysis
Figure 6.20 shows the topological states of a commutation leg of the converter
during a commutation time interval.
The corresponding relevant waveforms are shown in Fig. 6.21.
During the topological state “a”, before the commutation stage begins, S1 con-
ducts current Imp, IS2 = 0, VC1 = 0 and VC2 = V1.
Fig. 6.20 Topological states

(a) D1 C1 +
of a converter’s leg during a S1
commutation interval
- Imp VC1 = 0
Vi
+ VC2 = V1
–
S2 D2 C2 + IC1 = Imp
-
(b) S1 D1 C1 +
- Imp IS1 = IS2 = 0
Vi
+ IC1 = Imp/2
–
S2 D2 C2 + IC2 = -Imp/2
-
(c)
S1 D1 C1 +
- Imp VC2 = 0
Vi + VC1 = V1
–
S2 D2 C2 + IS1 = IS2 = 0
- ID2 = Imp
(a) (b) (c)
Fig. 6.21 Relevant waveforms during a commutation interval
During the topological state “b”, after turning off the switch S1 at the instant
t = 0 s, the current Imp charges the capacitor C1, whose voltage rises from zero to
Vi, while the capacitor C2 is completely discharged. Since Imp remains constant
during the switching interval, VC1 rises and VC2 falls linearly. This results in zero
voltage turn-off, since the voltage across the switch rises while its current is zero.
At the instant t = tc, the current Imp starts circulating through diode D2. At the
instant t = td, the switch S2 is gated on at zero voltage and current.
Since:
VC1 ðt) + VC2 ðt) = V1 ð6:78Þ
dVC1 ðt) dVC2 ðt)

þ ¼0 ð6:79Þ
dt dt
Assuming that C1 = C2 = C. Then:
dVC1 ðt) dVC2 ðt)

C + C ¼0 ð6:80Þ
dt dt
However:
dVC1 ðt)
iC1 ðt) = C ð6:81Þ
dt
and
dVC1 ðt)
iC2 ðt) = C ð6:82Þ
dt
As a consequence:
iC2 ðt) ¼ iC1 ðt) ð6:83Þ
Since:
iC1 ðt) + iC2 ðt) = Imp ð6:84Þ
We obtain:
Imp
iC1 ðt) ¼ ð6:85Þ
2
Imp
iC2 ðt) ¼ ð6:86Þ
2
Since:
V1
iC2 ðt) = C ð6:87Þ
t
Defining:
Imp V1
¼C ð6:88Þ
2 tc
Therefore, for the complete discharge of C2, it is necessary that:
V1
Imp 2C ð6:89Þ
td
According to (6.77):
p k
Imp ¼ tan ð6:90Þ
2f n kþ1
With:
Z2 Imp
Imp ¼ ð6:91Þ
Vi
V1
Imp2 ¼ Imp ð6:92Þ
Z2
Or also:
V1 p k
Imp ¼ tan ð6:93Þ
Z2 2f n kþ1
Combining (6.93) and (6.89) leads to (6.94):

V1 p k V1
tan 2C ð6:94Þ
Z2 2f n kþ1 td
Or also:
p k Z2
tan 2C ð6:95Þ
2f n kþ1 td
where:
Lr + Lm
Z2 ¼ ð6:96Þ
Cr
Find the needed gate signal dead-time for the LLC converter shown in Fig. 6.22
operating with no load and with the following parameters:
• V1 = 400 V
• Lr = 14 lH
• Lm = 70 lH
• Cr = 47 nF
• C = 2.2 nF (C1 = C2 = C3 = C4 = C)
• fn = 1
S1 D1 C1 S3 D3 C3
Cr Lr Lm iLm
+ b
V1 a
–
S2 D2 C2 S4 D4 C4
Fig. 6.22 Ideal equivalent LLC converter without load
Solution
Lr 14 106
k¼ ¼ ¼ 0:2
Lm 70 106
1 1
2p Lr Cr 2p 14 106 47 109
p k
Imp ¼ tan ¼ 0:747
2f n k þ 1
Lr + Lm
Z2 ¼ ¼ 42:27 X
Cr
V1 400
Imp ¼ Imp ¼ 0:747 ¼ 7:06 A
Z2 42:27
tc ¼ 2C V
I 250 ns
1
mp
The ZVS is achieved, provided that the dead time between the gate signals of the
switches of a leg, td, is larger than tc. Therefore:
td [ 250 ns
Figure 6.23 shows the relevant waveforms obtained by simulation, during the
turning off of switch S1. All components were considered ideal and a td = 400 ns
was adopted. During the commutation time interval, the ILr current remains prac-
tically constant, equals to Imp. Due to the high frequency operation, the dead time td
represents a significant portion of the switching period, and therefore has some
impact on the converter static gain.
6.8 Input Impedance 167
S1 S2
td
IS1
VS1
tc
Vab
ILr
Fig. 6.23 Relevant waveforms during commutation
6.8 Input Impedance
Figure 6.24 shows the equivalent circuit of the LLC converter for the fundamental
harmonics of voltage and current.
The input impedance is given by (6.97).
jxs Lm R 1
Z1 ¼ + jxs Lr þ ð6:97Þ
R + jxs Lm jxs Cr
We know that:
Lr
k¼ ð6:98Þ
Lm
Fig. 6.24 Equivalent LLC Cr i Lr

converter circuit for first order x1
harmonic
Vx1 Lm R
1
2p Cr Lr
xr Lr
Q¼ ð6:100Þ
R
fs
fn ¼ ð6:101Þ
f r1
Substituting (6.98) to (6.101) into (6.96), leads to (6.102),
Z1 ðk; f n ; Q) ¼ R1 ðk; f n ; Q) + j X1 ðk; f n ; Q) ð6:102Þ
where
Qf 2n
R1 ðk; f n ; Q) ¼ ð6:103Þ
Q2 f 2n þ k2
and
f 2n 1 kf n
X1 ðk; f n ; Q) ¼ þ 2 2 ð6:104Þ
fn Q f n þ k2
Z1 ðk; f n ; Q), R1 ðk; f n ; Q), R1 ðk; f n ; Q) and X1 ðk; f n ; Q) are defined as follows:
Z1 ðk; f n ; Q)
Z1 ðk; f n ; Q) ¼ ð6:105Þ
Zr1
R1 ðk; f n ; Q)
R1 ðk; f n ; Q) ¼ ð6:106Þ
Rr1
X1 ðk; f n ; Q)
X1 ðk; f n ; Q) ¼ ð6:107Þ
Xr1
rffiffiffiffiffi
Lr
Zr1 ¼ ð6:108Þ
Cr
Therefore, the impedance Z1 and its components R1 and X1 have been param-
eterized to the characteristic impedance Zr1.
Figure 6.25 shows curves of the module of the parametrized Z1 as a function of
fn for k ¼ 0:2 and different values of Q.
6.8 Input Impedance 169
10
λ = 0.2
1
0.1
Q=0 Q=
0.01
0.1 1 10
fn
Fig. 6.25 Normalized input impedance as a function of fn for different values of Q
(a) Cr i Lr (b) Cr i Lr
x x
Vx Vx Lm
Fig. 6.26 Equivalent circuits of the LLC converter at: a output short-circuit and b output
open-load
The output short-circuit condition implies R = 0 and Q = ∞. The corresponding

equivalent circuit is shown in Fig. 6.26a. The resonance occurs for fn = 1.
The output open-circuit, on the other hand, implies in R = ∞ and Q = 0. The
corresponding equivalent circuit is shown in Fig. 6.26b and the normalized reso-
nant frequency in given by (6.109).
k
f n2 ¼ ð6:109Þ
1þk
All impedance curves intersect themselves at the normalized frequency given by

(6.110).
rffiffiffiffiffiffiffiffiffiffiffiffiffi
2k
f n3 ¼ ð6:110Þ
1 þ 2k
6.9 Resonant Capacitor Current and Voltage
The peak current through Cr is given by (6.111).
Vxp
Ixp ¼ ð6:111Þ
jZ1 j
However:
4V1
Vxp ¼ ð6:112Þ
p
and

jZ1 j ¼ Zr1 Z1 ð6:113Þ
Then:
4V1 1
Ixp ¼ ð6:114Þ
p Zr1 Z1
Thus:
Zr1 Ixp 4
¼ ð6:115Þ
V1 p Z1
The parameterized current can be defined as (6.116).
Zr1 Ixp
Ixp ¼ ð6:116Þ
V1
Therefore:
4
Ixp ¼ ð6:117Þ
p Z1
Or also:
4
Ixp ðk; f n ; Q) ¼ ð6:118Þ
p Z1 ðk; f n ; Q)
6.9 Resonant Capacitor Current and Voltage 171
Fig. 6.27 Parametrized peak 10

current through Cr as a Q = 0.05 Q = 5.0
function of fn for different
values of Q
Ixp 1
0.1
0.1 1 10
fn
where:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!2 !2
u
u t Qf 2
f 2
1 kf
Z1 ðk; f n ; Q) ¼ n
þ n þ 2 2
n
ð6:119Þ
Q2 f 2n þ k2 fn Q f n þ k2
Figure 6.27 shows the parametrized peak current through the capacitor Cr, as a
function of the normalized switching frequency fn, for different values of the quality
factor Q.
Like what occurs with the input impedance, all curves of the current intersect at
fn = fn3.
The peak voltage across the resonant capacitor is defined by (6.120).
Ixp
Vcrp ¼ ð6:120Þ
xs Cr
Defining:
Vcrp
Vcrp ¼ ð6:121Þ
V1
Then:
Ixp
Vcrp ¼ ð6:122Þ
V1 xs Cr
Fig. 6.28 Parametrized peak 10

Q = 0.1 Q = 5.0
voltage across the resonant
capacitor Cr as a function of fn
for different values of Q
crp 1
0.1
0.1 1 10
fn
However,
V1
Ixp ¼ Ixp ð6:123Þ
Zr1
Then:
Ixp
Vcrp ¼ ð6:124Þ
Zr1 xs Cr
We know that
xs
Zr1 xs Cr ¼ ð6:125Þ
xr1
Which implies
Zr1 xs Cr ¼ f n ð6:126Þ
Therefore:
Ixp ðk; f n ; Q)
Vcrp ðk; f n ; Q) ¼ ð6:127Þ
fn
Figure 6.28 shows the curves generated by Eq. (6.127), where the normalized
value of the voltage across the resonant capacitor is represented as a function of the
normalized resonant frequency, for different values of the quality factor.
6.9 Resonant Capacitor Current and Voltage 173
A LLC converter operates with the following parameters:

• V1 = 400 V
• Lr = 14 lH
• Lm = 70 lH
• Cr = 47 nF
• fn = 1
• k = 0.2
• a=1
• Po = 2000 W
Find the input impedance, current, and voltage across the resonant capacitor at
the operation point.
Solution
(a) Calculation of the parameterized input impedance.
V2o 4002
Ro ¼ ¼ ¼ 80 X
Po 2000
8 8
Rac ¼ Ro ¼ 2 80 ¼ 64:85 X
p 2 p
qffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffi
Lr 14106
Cr 47109
Q¼ ¼ ¼ 0:266
Rac 64:85
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!2 !2ffi
u
t u Qf n 2
f 1
2
kf n
Z1 ¼ þ n þ 2 2 ¼ 3:004
Q fn þ k
2 2 2 f n Q f n þ k2
rffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Lr 14 106
Zr1 ¼ ¼ ¼ 17:26 X
Cr 47 109

jZ1 j ¼ Zr1 Z1 ¼ 17:26 3:004 ¼ 51:84 X
(b) Calculation of the peak value of the current in the resonant circuit.
V
Ixp ¼ Zxp ¼ p4V1
¼ 4400 ¼ 9:82 A
j 1j jZ1 j p51:84
(c) Calculation of the peak voltage across the resonant capacitor.

I
Vcp ¼ 2pfxpC ¼ 169:6 V
s r
The reader is encouraged to verify these results through numerical simulation.

We should know that these results are obtained considering the first harmonic
approximation converter equivalent circuit and that the simulation results may be
slightly different.
6.10 Design Methodology and Example
This numerical example provides a simplified design of a LLC converter, with the
following specifications:
• Po = 250 W
• V0o = 400 V
• V1max = 400 V
• V1min = 340 V
• k = 0.2
• fmax = 100 kHz
Simplifying, a transformer with unit turns ratio and ideal components will be
considered. To simplify the design method description, it will be divided in steps.
(a) First Step
Let’s adopt fnmax = 1 In this way, the converter will operate in discontinuous
conduction mode and the switching losses in the rectifier diodes of the output stage
will be theoretically be zero.
Therefore,
f r1 ¼ 100 kHz ð6:128Þ
Since
1
2p Cr Lr
it is obtained (6.130).
1
Cr Lr ¼ ð6:130Þ
4p2 1010
Thus, the first relation between Lr and Cr is obtained.

6.10 Design Methodology and Example 175
(b) Second Step

The minimum static gain is given by (6.131).
V0o
Mmin ¼ ¼1 ð6:131Þ
V1max
The maximum static gain is given by (6.132).
V0o
Mmax ¼ ¼ 1:176 ð6:132Þ
V1min
(c) Third Step

Let’s remind the expression of the parameterized static gain (6.133), previously
deduced.
f 2n
2 2 ð6:133Þ
f 2n ðk þ 1Þ k þ f n Q 1 f 2n
In the considered operation region, the static gain is maximum when the con-
verter has no load, which means Q = 0.
In this condition, the converter must operate with its minimum frequency. Then,
from (6.133), it is obtained:
f 2nmin
Mmax ¼ ð6:134Þ
f nmin ðk þ 1Þ
2
k
Then:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
kMmax
f nmin ¼ ð6:135Þ
ðk + 1)Mmax 1
With the values of k = 0.2 and Mmax = 1.176, we obtain:
f nmin ¼ 0:756 ð6:136Þ
f min ¼ f nmin f max ¼ 75:6 kHz ð6:137Þ
In Fig. 6.29, the static gain curves as a function of Q are shown for the extreme
values of fn, which are fnmin = 0.756 and fnmax = 1.
(d) Fourth Step
In this design step, the value of Qmax is chosen. With the relation (6.138),
(6.140) can be obtained.
Fig. 6.29 Static gain of the 1.2

converter as a function of Q
for values of fn between 0.756 0.756
and 1
1.1
1.0
M 1
0.9
0.8
0 0.2 0.4 0.6 0.8 1
Q
rffiffiffiffiffi
1 Lr
Qmax ¼ ð6:138Þ
Rac Cr
Lr
¼ ðQmax Rac Þ2 ð6:139Þ
Cr
2
4V0o 1
Rac ¼ ¼ 518:76 X ð6:140Þ
p 2Po
Rac represents the load resistance reflected to the primary side of the transformer.
The criteria to choose Qmax must be adopted. It has been shown that the peak
current in the resonant capacitor Cr is given by (6.141).
4V1max 1
I1p ðQ) ¼ ð6:141Þ
p jZ1 ðQ)j
where:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!2 !2
u
u 2 2
1 kf
jZ1 ðQ)j ¼ Zr ðQ)t 2 2 n 2 þ n
Qf f n
þ 2 2 ð6:142Þ
Q fn þ k fn Q f n þ k2
According to expressions (6.130) and (6.139), the parameters Cr, Lr, Lm, Z1 and
consequently the current value in the resonant circuit depend on Qmax. For the
parameters previously obtained in this design example, the curve of the peak current
value as a function of Qmax shown in Fig. 6.30 is generated.
6.10 Design Methodology and Example 177
Fig. 6.30 Peak value of the 3

resonant tank current as a
function of Qmax
2.4
1.8
I1p
1.2
0.6
0
0.1 0.16 0.22 0.28 0.34 0.4
Q max
Note that an increment of Qmax causes a reduction of I1p. However, this causes
an increment in the magnetizing inductance Lm and decreases the peak value of the
magnetizing current, given by (6.143).
rffiffiffiffiffiffiffiffiffiffiffi!rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
p k Cr
Imp ¼ V0o tan ð6:143Þ
2f n kþ1 Lr + Lm
For this design example, the value of Imp as a function of Qmax is represented in
Fig. 6.31.
Fig. 6.31 Peak value of the 3

magnetizing current as a
function of Qmax
2.4
1.8
Imp
1.2
0.6
0
0.1 0.16 0.22 0.28 0.34 0.4
Q max
The value of Imp must be larger than Impmin, to ensure soft switching with no
load. Let’s adopt Impmin = 1 A. Therefore, Qmax = 0.237. The values of Lr and Cr
can be found by employing (6.144) and (6.145).
1
Cr Lr ¼ ð6:144Þ
4p2 f 2max
Lr
¼ ðQmax Rac Þ2 ð6:145Þ
Cr
With the calculated parameters
f max ¼ 100 kHz ð6:146Þ
Rac ¼ 518:76 X ð6:147Þ
Qmax ¼ 0:237 ð6:148Þ
It is obtained:
Cr ¼ 12:94 nF ð6:149Þ
Lr ¼ 195:7 lH ð6:150Þ
Lm ¼ 978:4 lH ð6:151Þ
The reader is invited and encouraged to simulate the designed LLC converter to
verify the results.
6.11 Detailed Description of the LLC’s Operation Modes
The previous analysis considered the first harmonic approximation equivalent cir-
cuit of the LLC converter, where all voltages and currents were sinusoidal.
In this section, the topological states and the main waveforms of the LLC
converter for frequencies lower, equal or larger than the resonant frequency will be
described, for rectangular voltage waveforms.
6.11.1 Operation at the Resonance Frequency (fs = fr1)
The relevant waveforms for fs = fr1 are shown in Fig. 6.32.

6.11 Detailed Description of the LLC’s Operation Modes 179
Fig. 6.32 Relevant Vo

waveforms at resonance
Vab = Vcb
ILr
ILm
Io
TS
0 t1 t2
2
For this operating mode, the current io in the load is at the boundary between the
discontinuous and continuous mode and the voltage at the terminals of Lm is always
equal to ±Vo, or Vab.
In the interval [0, Ts/2], three topological states occur, represented in Fig. 6.33,
for the time intervals [0, t1], [t1, t2] and [t2, Ts/2], respectively.
All components are considered ideal and the parameters of the rectifier stage and
the load are all reflected to the primary side of the transformer.
(A) First Topological State (0, t1)
The voltage Vab is positive. The negative currents iLr and iLm rise sinusoidally
and linearly, respectively. This stage ends at the instant t1, when iLr = 0.
(B) Second Topological State (t1, t2)
During this topological state the resonant current is positive, increasing sinu-
soidally, while the magnetizing current, that is negative, increases linearly.

(a) Cr Lr iLr io
at resonance for the time
intervals a [0, t1], b [t1, t2] and
c [t2, Ts/2] iLm
+
Vab Lm –
Vo
(b) Cr Lr iLr io
iLm
+
Vab Lm –
Vo
(c) Cr Lr iLr io
iLm
+
Vab Lm –
Vo
(C) Third Topological State (t2, TS/2)

During this topological state, both currents iLr and iLm are positive; iLr is sinu-
soidal while iLm continues to rise linearly.
At low loads, the current io may become discontinuous and more topological
states may occur than those presented in Fig. 6.33.
6.11.2 Operation Below Resonant Frequency (fs < fr1)
The relevant waveforms for fs < fr1 are shown in Fig. 6.34.
In the interval [0, Ts/2], four topological states take place, represented in
Fig. 6.35, for the time intervals [0, t1], [t1, t2], [t2, t3] and [t3, Ts/2], respectively.

The voltages Vab and Vcb are positive and Vo > V1. The currents iLr and iLm are
negative. The current iLr grows sinusoidally as iLm grows linearly. This topological
state ends at the instant t1, when iLr = 0.
Fig. 6.34 Relevant Vo

waveforms for fs < fr1
Vab < Vcb
ILr
ILm
Io
TS
0 t1 t2 t3
2

The current iLr is sinusoidal and positive. It increases linearly, while iLm, neg-
ative, rises linearly. This topological state ends at the instant t2, when iLm = 0.
(C) Third Topological State (t2, t3)
During this time interval, iLr and iLm are positive. This stage ends at time t = t3,
when iLr = iLm and io = 0.
(D) Fourth Topological State (t3, TS/2)
During this topological state, io = 0 and iLr = iLm. It ends at t = TS/2, when the
voltage Vab changes polarity and becomes negative.
The operation for fs < fr1 differs from the operation of fs = fr1 in two aspects:
• The load voltage Vo is larger than the supply voltage V1;
• The current io at the output of the rectifier is discontinuous.

(a) Cr Lr iLr io
at switching frequency below
resonant frequency
iLm
+
Vab Lm –
Vo
(b) Cr Lr iLr io
iLm
+
Vab Lm –
Vo
(c) Cr Lr iLr io
iLm
+
Vab Lm –
Vo
(d) Cr Lr iLr
iLm
Vab iLr = iLm Lm
+
Vo
–
6.11.3 Operation Above Resonant Frequency (fs > fr1)
The relevant waveforms for fs > fr1 are shown in Fig. 6.36.
In the time interval [0, Ts/2], four topological states take place, represented in
Fig. 6.37, for the time subintervals [0, t1], [t1, t2], [t2, t3] and [t3, Ts/2], respectively.
During this time interval, Vab and Vcb are positive. The currents iLr and iLm are
negative. This interval ends at time t = t1, when iLr reaches zero.
During this time interval, Vab and Vcb remain positive. The current iLr is positive
while iLm remains negative and rises linearly. This topological state ends at time
t = t2, when the magnetizing current reaches zero.
Fig. 6.36 Relevant

waveforms at fs > fr1 Vo
Vab > Vcb
ILr
ILm
Io
TS
0 t1 t2 t3
2
(C) Third Topological State (t2, t3)

During this time, iLr and iLm are positive. This topological state ends at time
t = t3, when the input voltage Vab is inverted and becomes negative.
(D) Fourth Topological State (t3, TS/2)
During this topological state, the current iLr decreases until it becomes equal to
the magnetizing current iLm, at time t = TS/2.
In the operation description at fs > fr1, the time starts to be counted at the
moment the voltage Vcb becomes positive, which makes the description of the
converter operation more understandable. In this operation mode, the polarity
reversal of the voltage Vab occurs before the current io naturally reaches zero, which
causes forced blocking of the rectifier diodes, and consequently increases the
switching losses, sacrificing the efficiently. The operation for fs > fr1 is undesirable
for these reasons, in comparison to other operation modes, and should be avoided.
Cr Lr iLr io
(a)
iLm
+
Vab Lm –
Vo
(b)
Cr Lr iLr io
iLm
+
Vab Lm –
Vo
(c) Cr Lr iLr io
iLm
+
Vab Lm –
Vo
(d) Cr Lr iLr io
iLm
+
Vab Lm –
Vo
Fig. 6.37 Topological states above resonance fs > fr1
6.12 Summary of Properties of the LLC Converter
According to what has been studied in this chapter, the LLC converter has several
advantages over the other resonant converters, to be specific:
• It allows the regulation of the load voltage for large variations of input voltage
and power processed with a small variation of the switching frequency;
• With the appropriate combination of parameters, it can operate with soft
switching of the active switches from full to zero load;
• As the voltages and currents are sinusoidal, it requires smaller and lower cost
EMI filters to comply with EMI standards;
6.12 Summary of Properties of the LLC Converter 185
• All parasitic elements such as semiconductor junction capacitance, body diodes

and leakage and magnetizing inductances are beneficial for the correct operation
of the LLC converter and favors the soft commutation of the power switches.
6.13 Proposed Exercises
(1) The LLC converter shown in Fig. 6.1 operates with the following parameters:
• V1 = 100 V
• fs = 100 kHz
• Cr = 633 nF
• Lr = 4 µH
• Lm = 20 µH
• a = 10
• Ro = 1000 X
Calculate:
(a) The inductance’s ratio k;
(b) The quality factor Q;
(c) The resonant frequency fr1;
(d) The resonant frequency fr2;
(e) The normalized frequency fn;
(f) The load voltage Vo;
(g) The power transferred to the load resistor Ro;
(h) The peak value of the magnetizing current;
(i) The peak value of the current through the inductor Lr;
(j) The average value of the current in the power supply V1;
(k) The phase angle / between Vab and iLr;
(l) The peak value of the voltage across the resonant capacitor Cr;
(m) The average value of the current in an output rectifier diode;
(n) The rms current value in an inverter bridge switch.
Answers:
(a) k = 0.2; (b) Q = 0.31; (c) fr1 = 100 kHz; (d) fr2 = 40,830 kHz; (e) fn = 1;
(f) Vo = 1000 V; (g) Po = 1000 W; (h) Imp = 12.5 A; (i) Ip = 20.07 A;
(j) I1 = 10 A; (k) / = 0.672 rad; (l) Vcrp = 50.47 V; (m) IDaver = 0.5 A;
(n) Isrms = 10.04 A
(2) A LLC converter operates with the following parameters:
• V1 = 200 V
• fs = 150 kHz
• Cr = 100 nF
• Lr = 7 µH
• Lm = 35 µH
• a = 0.25
• Ro = 500 X
Using the equations deduced for the first harmonic approximation, determine:
(a) The voltage across the load resistor Ro;
(b) the power delivered to the load.
Answers: (a) Vo = 888 V and (b) Po = 1578 W.
The reader is encouraged to simulate the converter with the above parameters,
to verify the error introduced by the first harmonic approximation.
(3) A LLC converter operates at normalized frequency fn = 1. Demonstrate that the
peak value Ip of the sinusoidal current that flows through the inductor Lr is
given by expression
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
p 2
Ip ¼ I2mp þ Io
2
where Imp and Io are the value of the magnetizing current at the instant of
commutation, and the average value of the load current, respectively.
(4) Prove that the angle / between the sinusoidal current in the inductor Lr and the
voltage at the input of the resonant circuit is given by the following expression:
2 Imp
tanð/Þ ¼
p Io
(5) In the text of the present chapter it was demonstrated that for the first harmonic
approximation, M = 1 (static voltage gain) for fn = 1 (normalized switching
frequency). Prove that this result is also valid for rectangular voltages, as in a
real converter.
References
1. Schmidmer, E.G.: A new high frequency resonant converter topology. In: HFPC Conference
Record, pp. 9–16 (1988)
2. Sevems, R.P.: Topologies for three-element resonant converters. In: IEEE Transactions on
Power Electronics, vol. 1.7, no. 1, pp. 89–98 (1992)
3. Lazar, J.F., Martinelli, R.: Steady-state analysis of the LLC series resonant converter. In:
Sixteenth Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2001,
vol. 2, pp. 728–735 (2001)
4. Yang, B., Lee, F.C., Zhang, A.J., Huang, G.: LLC resonant converter for front end DC/DC
conversion. In: Seventeenth Annual IEEE Applied Power Electronics Conference and
Exposition, APEC 2002, vol. 2, pp. 1108–1112 (2002)
Chapter 7
Full-Bridge ZVS-PWM Converter
with Capacitive Output Filter
Nomenclature
Vi Input DC voltage
Po Output power
/ Angle between the leading leg and the lagging leg
q Static gain
D Duty cycle
Ts Switching period
td Dead time
io Output current
i0o C Output current referred to the primary in CCM
i0o D Output current referred to the primary in DCM

I0o I0o average output current referred to the primary and its
normalized
value
I0o C 0
Io C average output current in CCM referred to the
primary
I0o D I0o D average output current in DCM referred to the
primary and its normalized value

I0o L I0o L Average output current in the limit (critical conduction
mode) between CCM/DCM, referred to the primary winding
S1 and S2 Switches in the leading leg
S3 and S4 Switches in the lagging leg

188 7 Full-Bridge ZVS-PWM Converter with Capacitive Output Filter
vg1, vg2, vg3 and vg4 Switches S1, S2, S3 and S4 drive signals, respectively
D1, D2, D3 and D4 Diodes in anti-parallel to the switches (MOSFET—intrinsic
diodes)
C1, C2, C3 and C4 Capacitors in parallel to the switches (MOSFET—intrinsic
capacitors)
Lc Transformer leakage inductance or an additional inductor
iLc Inductor
current
ILc ILc inductor peak current and its normalized value,
commutation
current for S1 and S3
ILc C ILc C inductor peak current in CCM and its normalized
value

ILc D ILc D inductor peak current in DCM and its normalized
value
ILc RMS Inductor Lc normalized RMS current

ILc RMS C ILc RMS C inductor Lc RMS current in CCM and its
normalized value
ILc RMS_D ILc RMS D inductor Lc RMS current in DCM and its
normalized
value
I1 I1 inductor current at the end of the first and fourth step of
operation (commutation current for S2 and S4) and its
normalized value
vac Voltage at the ac side of the rectifier, between points “a” and
“c”
iS1, iS2, iS3 and iS4 Current in the switches
iC1, iC2, iC3 and iC4 Current in the capacitors
ΔT Time interval which vab = ±Vi
Δt1 Time interval of the first step of operation (t1–t0)
Δt5 Time interval of the fifth step of operation (t5–t4)
Δt6 Time interval of the sixth step of operation (t6–t5)
A1, A2 and A3 Areas
7.1 Introduction 189
7.1 Introduction
In this chapter, the Full-Bridge Zero-Voltage-Switching Pulse-Width-Modulation

Converter (FB-ZVS-PWM) with a Capacitive Output Filter is described [1]. Such
converter is suitable for high-power and high-voltage applications, such as indus-
trial, commercial or residential battery chargers as well as embedded battery
chargers for hybrid or electrical vehicles. The chapter is organized to present at first
the topology of the converter and its basic operation with ideal components, fol-
lowed by a detailed analysis of the operation of the converter in Continuous and
Discontinuous Conduction Modes as well as the Zero Voltage Switching operation
and a design example.
The schematics of the FB-ZVS-PWM Converter with capacitive output filter,
shown in Fig. 7.1, consists of a full bridge inverter, an inductor, a transformer, a full
bridge diode rectifier and a capacitive output filter. The diodes (D1, D2, D3 and D4)
in anti-parallel to the switches (S1, S2, S3 and S4) and the parallel capacitors (C1, C2,
C3 and C4) may be the parasitic components of a MOSFET or additional compo-
nents in parallel to the switches, as in case of IGBTs. The inductance Lc may be the
transformer leakage inductance or an additional inductor, when necessary. This
inductor is important to the power transfer to the load as well as to achieve soft
commutation. All the operation stages are linear, simplifying the analysis and the
design.
This converter operates with a fixed switching frequency and the voltages across
the switches are limited to the DC link voltage (Vi). To achieve zero voltage
switching (ZVS) the two legs operate with a phase-shift modulation and the
switches of each leg are gated complementary.
S1 D1 C1 C2 D2 S2 io
+
Lc
Vi
+ a b c
..
T
- S3 D3 C3 C4 D4 S4 iLc Co Ro Vo
Fig. 7.1 Full-bridge ZVS-PWM converter, with capacitive output filter

In this section, the converter shown in Fig. 7.2, without the capacitors in parallel to
the switches is analyzed (the soft commutation analysis is presented in Sect. 7.4).
The following assumptions are made:
• the diodes in anti-parallel to the switches conduct separately from the switches,
so the analysis is not limited to a MOSFET.
The switches’ drive signals with phase shift modulation are shown in Fig. 7.3 for
both the leading leg (S1 and S3) and the lagging leg (S2 and S4) as well as the
voltage vab. No dead time is considered at this point.
Fig. 7.2 Ideal equivalent

circuit Full-Bridge S1 D1 D2 S2
ZVS-PWM converter, with io’
Vo’ Lc
output capacitive filter + a c b
Vi
- S3 D3 iLc D4 S4
φ=0o φ=180o
vg1 TS φ
vg3 t
φ
vg2
vg4
vab
Vi
ΔΤ
ΔΤ
TS / 2
-Vi
Fig. 7.3 Phase shift modulation—basic operation of FB ZVS-PWM

In the phase shift modulation, the switching frequency is fixed and the switches
duty cycle are 50%. The lagging leg drive signals are shifted of an angle / in
relation to the leading leg drive signals, allowing the power transfer to be con-
trolled. If / = 0°, vab has its maximum RMS value since switches S1 and S4 always
conduct at the same time (vab = Vi), and switches S2 and S3 also conduct at the
same time (vab = −Vi). When / increases, the vab RMS value decreases because
switches S1 and S2 as well as S3 and S4 conduct at the same time resulting in
vab = 0. The / angle varies from 0° (maximum power) to 180° (zero power).
7.2.1 Continuous Conduction Mode
The operation of the converter is described during one switching period that is
divided into six time intervals, each one representing a different state of the
switches. In CCM, the rectifier diodes conduct the inductor current in the six time
intervals.
The first time interval (shown in Fig. 7.4) starts at t = to, when switch S1 is gated on
and switch S3 is turned off. Although switch S1 is gated on, the current does not
flows through it because iLc is negative (iLc(t0) = −ILc_C). Hence diode D1 conducts
the current together with switch S2 that was conducting prior to this time interval.
The voltage vab is zero and the inductor voltage vcb is V0o , leading the inductor to
deliver power to the load.
Fig. 7.4 Topological state in

CCM for time interval Δt1 S1 D1 D2 S2
io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

This time interval, shown in Fig. 7.5, starts at t = t1, when S4 is gated on and S2 is
turned off. As the inductor current is still negative (iLc(t1) = −I1), the current flows
through diodes D1 and D4, vab = Vi and the inductor voltage vcb ¼ Vi þ V0o . So, the
inductor delivers power to the load and to the DC link (Vi).
Figure 7.6 shows the topological state for time interval Δt3. It begins at t = t2 when
iLc reaches zero (iLc(t2) = 0), turning off diodes D1 and D4 and enabling switches S1
and S4 to conduct, as the inductor current evolves positively. The voltage vab is Vi
and the inductor voltage vcb is Vi V0o , leading the DC link to deliver energy to the
load and the inductor Lc.
This time interval starts at t = t3, when switch S1 is turned off and switch S3 is gated
on. The current does not flow through switch S3 because of its unidirectional
current flow assumption. The inductor current flows through diode D3 and switch

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4
S4, that was already conducting, as shown in Fig. 7.7. The voltage vab is zero and
the inductor voltage vcb is V0o , leading the inductor to deliver power to the load.
This time interval, shown in Fig. 7.8, begins at t = t4, when S4 is turned off and S2
is gated on. As the inductor current is still positive (iLc(t4) = +I1), the current flows
through diodes D2 and D3, vab = −Vi, and the inductor voltage vcb ¼ Vi V0o ,
leading the inductor to deliver power to the load and to the DC link (Vi).
Time interval Δt6 is shown in Fig. 7.9. It begins at t = t5 when iLc reaches zero
(iLc(t5) = 0), turning off diodes D2 and D3 and enabling switches S2 and S3 to
conduct, as the inductor current evolves negatively. The voltage vab is −Vi and the
inductor voltage vcb is Vi þ V0o , leading the DC link to deliver energy to the load
and the inductor Lc. The main waveforms for the continuous conduction mode are
shown in Fig. 7.10.
vg1 TS
vg3 t
φ
vg2
vg4
vab
Vi
ΔΤ
ΔΤ
-Vi
vcb
Vi + Vo’
Vi - Vo’
Vo’
-Vo’
-Vi + Vo’
-Vi - Vo’
iLc
ILc_C
I1
-I1
-ILc_C
vS1
Vi
ILc_C
iS1
vS2
Vi
ILc_C
iS2
I1
t0 t1 t2 t3 t4 t5 t6
Fig. 7.10 Main waveforms and time diagram for one cycle of operation in CCM
7.2.2 Discontinuous Conduction Mode
The converter is described during one switching period that is divided into six time
intervals, each one representing a different state of the switches. In DCM the
rectifier diodes conduct the inductor current only in four time intervals, because the
inductor current remains in zero in the time intervals Δt2 and Δt5.
Time Interval Δt1 (shown in Fig. 7.11) starts at t = to, when switch S1 is gated on
and switch S3 is turned off. Although the switch S1 is gated on, the current does not
flow through it because iLc is negative (iLc(t0) = −ILc_D), so diode D1 conducts the
current together with switch S2 that was conducting prior to this interval. The
voltage vab is zero and the inductor voltage vcb is V0o , leading the inductor to deliver
power to the load.
This time interval starts at t = t1, when the inductor current reaches zero
(iLc(t1) = 0), turning off D1 and S2. No current flows through the circuit as shown in
Fig. 7.12, and vab = 0 and vcb = 0.

in DCM for time interval Δt1 S1 D1 D2 S2
io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

This time interval, shown in Fig. 7.13, starts at t = t2, when S4 is gated on and S2 is
turned off. As the current is positive, it flows through switches S1 and S4. During
this interval vab = Vi, the inductor voltage vcb ¼ Vi V0o , and the DC link deliver
power to the inductor and to the load.
This time interval starts at t = t3 when switch S1 is turned off and switch S3 is gated
on. The current does not flow through switch S3 because of its unidirectional
current flow assumption. The inductor current flows through diode D3 and switch
S4 that was already conducting, as show in Fig. 7.14. The voltage vab is zero and
the inductor voltage vcb is V0o , leading the inductor to deliver power to the load.
Time interval Δt5 starts at t = t4, when the inductor current reaches zero
(iLc(t1) = 0). No current flows through the circuit as shown in Fig. 7.15. During this
time interval vab = 0 and vcb = 0.

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4

io’
Vo’ Lc
+ a c b
Vi
- S3 D3 iLc D4 S4
vg1 TS
vg3 t
φ
vg2
vg4
vab
Vi
ΔΤ
ΔΤ
-Vi
vcb
Vi - Vo’
Vo’
-Vo’
-Vi + Vo’
iLc
ILc_D
-ILc_D
vS1
Vi
ILc_D
iS1
vS2
Vi
ILc_D
iS2
t0 t1 t2 t3 t4 t5 t6
Fig. 7.17 Main waveforms and time diagram for one cycle of operation in DCM

The topological state for time interval Δt6 is shown in Fig. 7.16. It begins at t = t5
when S2 is turned off and S4 is gated on. The inductor current flows through
switches S2 and S3 and evolves negatively. The voltage vab is −Vi and the inductor
voltage vcb is Vi þ V0o , leading the DC link to deliver energy to the load and the
inductor. The main waveforms indicating the time intervals for thediscontinuous
conduction mode are shown in Fig. 7.17.
In this section the FB-ZVS-PWM commutation currents (I1 and ILc), the output
characteristics and the RMS inductor current are presented.
7.3.1 Commutation Currents
The commutation currents for the leading leg (ILc) and the lagging leg (I1) are
obtained analyzing the equations for the different intervals of operation for CCM
and DCM. The commutation intervals are not considered because these intervals are
very fast compared to the other ones, so the inductor current can be considered
constant during the commutation.
(A) Continuous Conduction Mode (CCM)
In CCM S1 and S3 commutate with the inductor peak current ILc C and S2 and S4
commutate with a smaller current I1, so this commutation is more critical.
Analyzing the second time interval (t1 t t2) in CCM (Sect. 7.2.1;
Fig. 7.5) the following equation is written:
diLc ðtÞ
Vi þ V0o ¼ Lc ð7:1Þ
dt
Integrating (7.1) from t1 to t2, (7.2) is obtained.

Zt2 Z0

Vi þ V0o dt ¼ Lc dt ð7:2Þ
t1 I1
Solving the integral and isolating I1:

Vi þ V0o
I1 ¼ Dt2 ð7:3Þ
Lk
In the third interval of operation (t2 t t3) in CCM (Sect. 7.2.1; Fig. 7.6)
the following equation derives:
diLc ðtÞ
Vi V0o ¼ Lc ð7:4Þ
dt
Integrating (7.3) from t2 to t3, (7.5) is obtained.
Zt3 IZ
Lc C

Vi V0o dt ¼ Lc dt ð7:5Þ
t2 0
Solving the integral and isolating the inductor peak current in CCM (ILc C),
(7.6) is obtained.
Vi V0o
ILc C ¼ Dt3 ð7:6Þ
Lc
In the fourth interval of operation (t3 t t4) in CCM (Sect. 7.2.1; Fig. 7.7)
the following equation is written:
diLc ðtÞ
V0o ¼ Lc ð7:7Þ
dt
Integrating (7.7) from t3 to t4:
Zt4 ZI1
V0o dt ¼ Lc di ð7:8Þ
t3 ILc C
Solving the integral and isolating I1:
V0o
I1 ¼ ILc C Dt4 ð7:9Þ
Lc
As the FB-ZVS-PWM is symmetric in one switching period, the following time

intervals are equal: Dt1 ¼ Dt4 ; Dt2 ¼ Dt5 ; Dt3 ¼ Dt6 .
The time interval which vab = ± Vi is defined as DT, as shown in Fig. 7.10, so
(7.10) and (7.11) may be written as:
DT ¼ Dt3 þ Dt2 ð7:10Þ
Ts
¼ DT þ Dt4 ð7:11Þ
2
Isolating Dt4 gives:
Ts
Dt4 ¼ DT ð7:12Þ
2
The static gain and the duty cycle are calculated as follows:
V0o
q¼ ð7:13Þ
Vi
2DT
D¼ ð7:14Þ
Ts
Substituting (7.3), (7.6) and (7.12) in (7.9):

Vi þ V0o Vi V0o V0 Ts
Dt2 ¼ Dt3 o DT ð7:15Þ
Lc Lc Lc 2
Substituting (7.10) in (7.15), Δt3 is obtained.
DT V0o Ts
Dt3 ¼ þ ð7:16Þ
2 Vi 4
Substituting (7.13) and (7.14) in (7.16) the normalized third interval of operation
is calculated as follows:
Dt3 D þ q
Dt3 ¼ ¼ ð7:17Þ
Ts 4
Substituting (7.17) and (7.14) in (7.10), the normalized fifth interval of operation
is obtained.
Dt5 D q
Dt5 ¼ ¼ ð7:18Þ
Ts 4
Substituting (7.17) in (7.6), the inductor peak current in CCM (ILc C) is

obtained in (7.19).
Vi V0o D þ q
ILc C ¼ Ts ð7:19Þ
Lc 4
Normalizing (7.19):
ILc C 4f s Lc
ILc C ¼ ¼ ð1 qÞ ðD þ qÞ ð7:20Þ
Vi
Substituting (7.18) in (7.3), the current I1 is obtained in (7.21).
Vi þ V0o D q
I1 ¼ Ts ð7:21Þ
Lc 4
Normalizing (7.21):
I1 4f s Lc
I1 ¼ ¼ ð1 þ qÞðD qÞ ð7:22Þ
Vi
(B) Discontinuous Conduction Mode (DCM)

In DCM S1 and S3 commutate with the inductor peak current ILc_D and when S2 and
S4 commutate the inductor current is zero, so there is no energy to charge/discharge
capacitors C2 and C4, leading to a dissipative commutation in this leg.
Analyzing the third time interval (t2 t t3) in DCM (Sect. 7.2.2; Fig. 7.13)
the following equation is written:
diLc ðtÞ Lc ILc

Vi V0o ¼ Lc
D
¼ ð7:23Þ
dt DT
Substituting (7.14) in (7.23):

Vi V0o DTs
ILc D ¼ ð7:24Þ
Lc 2
1.0
ILc
(S 1 e S 3) CCM 1.0
0.8
0.75
0.6
0.5
0.4
0.25
DCM
0.2
D=0.125
0
0 0.2 0.4 0.6 0.8 1.0
q
Fig. 7.18 Normalized commutation current in switches S1 and S3, as a function of the static gain
(q), taking the duty cycle (D) as a parameter, in CCM and DCM
1.0
I1 CCM
(S 2 e S 4 )
0.8
0.6
0.4
0.2
D=0.125 0.25 0.5 0.75 1.0
0
0 0.2 0.4 0.6 0.8 1.0
q
Fig. 7.19 Normalized commutation current in switches S2 and S4, as a function of the static gain
(q), taking the duty cycle (D) as a parameter, in CCM
Normalizing (7.24):
ILc D4 f s Lc
ILc D ¼ ¼ 2 ð1 qÞD ð7:25Þ
Vi

Figure 7.18 presents the normalized commutation current ILc for the switches S1
and S3, as a function of the static gain (q), taking the duty cycle (D) as a parameter, in
CCM and in DCM. For a given static gain, as the duty cycle decreases (lower output
power), the commutation current ILc also decreases, increasing the time to charge/
discharge the capacitors C1 and C3, and soft commutation may not be achieved in all
load range. If a low static gain is chosen (proper transformer turns ratio) soft com-
mutation may be obtained for a wider load range in the leading leg, however, the
switches conduction losses increase because a low static gain means higher currents.
Figure 7.19 presents the normalized commutation current I1 for the switches
S2 and S4, as a function of the static gain (q), taking the duty cycle (D) as a
parameter, in CCM. As I1 is smaller than the inductor peak current ILc, switches S2
and S4 have a more critical commutation comparing to switches S1 and S3. For a
given static gain, the commutation current I1 decreases, as the duty cycle decreases
(lower output power), increasing the time to charge/discharge the capacitor C2 and
C4, and soft commutation may not be achieved in all load range. If a lower static
gain is chosen, soft commutation may be obtained in a wider load range, as for the
leading leg. In DCM the inductor current is zero when switches S2 and S4 com-
mutate and no energy is available to charge/discharge the capacitors, leading to a
dissipative commutation.
The FB-ZVS-PWM output characteristics are obtained in this section, for contin-
uous and discontinuous conduction mode. The commutation time intervals are
disregarded.
(A) Continuous Conduction Mode (CCM)
The output current referred to the primary winding of the transformer in CCM is
shown in Fig. 7.20.
The normalized area A1 is calculated as follows:
2 ILc C Dt3
A1 ¼ ð7:26Þ
Ts 2
where Dt3 = t3–t2.

Substituting (7.17) and (7.20) in (7.26) gives:
Vi
A1 ¼ ð1 qÞ ðD þ qÞ2 ð7:27Þ
16 Lc f s
The normalized area A2 is given by
2 ðI1 þ ILc C ÞDt4

A2 ¼ ð7:28Þ
Ts 2
Substituting (7.14) in (7.12), the fourth time interval is calculated:
Ts Ts
Dt4 ¼ DT ¼ ð1 DÞ ð7:29Þ
2 2
Substitution of (7.19), (7.21) and (7.29) into (7.28), A2 lead to Eq. (7.30).
Vi
A2 ¼ ð1 DÞ½ð1 þ qÞ ðD qÞ þ ð1 qÞ ðD þ qÞ ð7:30Þ
8f s Lc
The normalized area A3 is calculated according to (7.31).
io’ C
ILc_ C
A3 /2
I1 A1 /2 A2 /2
t0 t1 t2 t3 t4 t5 t6 t
TS
Fig. 7.20 Load current in CCM referred to the transformer primary winding
2 I1 Dt5
A3 ¼ ð7:31Þ
Ts 2
Substituting (7.22) and (7.18) in (7.31), gives:
Vi
A3 ¼ ð1 þ qÞ ðD qÞ2 ð7:32Þ
16f s Lc
The average load current is the sum of the normalized areas A1 , A2 and A3 ,
which is represented by Eq. (7.33).
Vi 1
I0o C ¼ 2D D2 q2 ð7:33Þ
8 f s Lc
Normalizing (7.33) yields the result:
I0o C 4f s Lc Dð 2 DÞ q2
I0o C ¼ ¼ ð7:34Þ
Vi 2
Equation (7.34) gives the normalized load current, referred to the transformer
primary winding, as a function of the duty-cycle D and the static gain q, for
continuous conduction mode (CCM).
(B) Discontinuous Current Mode (DCM)
The output current referred to the primary of the transformer in DCM is shown in
Fig. 7.21.
Equation (7.35) is written for the fourth time interval:
diLc ðtÞ ILc

V0o ¼ Lr
D
¼ Lc ð7:35Þ
dt Dt4
Isolating the inductor peak current in DCM gives:
io’D
ILc_ D
t0 t1 t5 t6 t
ΔT
t2 t3 Δt4 t4
TS
Fig. 7.21 Load current referred to the transformer primary winding, in DCM
V0o Dt4
ILc D ¼ ð7:36Þ
Lc
Making (7.36) equals to (7.24) yields:
V0o Dt4 Vi V0o

ILc D ¼ ¼ DT ð7:37Þ
Lc Lc
Substituting (7.14) in (7.37), the fourth time interval is obtained:
1 q DTs
Dt4 ¼ ð7:38Þ
q 2
The average load current in DCM is calculated as follows:

2 ILc D DT ILc D Dt4
I0o D ¼ þ ð7:39Þ
Ts 2 2
Substituting (7.37) and (7.38) in (7.39) gives:
1 q Vi D2
I0o D ¼ ð7:40Þ
q Lc 4f s
Normalizing (7.40) yields:

I0o D 4Lc f s 1q
I0o D ¼ ¼ D2 ð7:41Þ
Vi q
Equation (7.41) gives the normalized load current, referred to the transformer
primary winding, as a function of the duty-cycle D and the static gain q, for
discontinuous conduction mode (DCM).
(C) Critical Conduction Mode
In critical conduction mode, the time interval Dt5 ¼ 0. Thus,
Dt5 D q
¼ ¼0 ð7:42Þ
Ts 4
From which we find Eq. (7.43) that represents the limit between CCM and
DCM.
D¼q ð7:43Þ
1.0
0.8
CCM
0.6
DCM
0.4
0.2
D=0.125 0.25 0.5 0.75 1.0

0
0 0.1 0.2 0.3 0.4 0.5
Io ’
Fig. 7.22 FB-ZVS-PWM normalized output characteristics
Substituting (7.43) in (7.41) or in (7.34), (7.44) is obtained, representing the

normalized average output current in critical conduction mode.
I0o L 4 Lc f s
I0o L ¼ ¼ q q2 ð7:44Þ
Vi
The FB-ZVS-PWM output characteristics for CCM (7.36) and DCM (7.41), as
well as the limit between the two conduction modes (7.44) (dashed line) are pre-
sented in Fig. 7.22. The smaller the static gain, the wider the CCM load range and
the soft commutation range. However, a low static gain implies in higher currents
and consequently higher conduction losses.
7.3.3 RMS Inductor Current
(A) CCM
The inductor RMS current in CCM is calculated as follows:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u 2 Dt3
3
u Z ZDt4
u2 4 t 2 t 2 5
ILc RMS C ðqÞ ¼ t ILc C dt þ ILc C þ ðI1 ILc C Þ dt
Ts Dt3 Dt4
0 0
ð7:45Þ
0.60 1.0
0.75
ILc RMS
0.5
CCM
0.40
0.25
0.20
D=0.125 DCM
0
0 0.2 0.4 0.6 0.8 1.0
q
Fig. 7.23 The inductor RMS current in CCM and in DCM, as a function of the static gain (q),
taking the duty cycle (D) as a parameter
Normalizing (7.45) gives:
ILc RMS C 4f s Lc ð1 qÞ2 ðD þ qÞ3 þ ð1 þ qÞ2 ðD qÞ3

ILc RMS C ðqÞ ¼ ¼
Vi 6
2
ð7:46Þ
4ð1 DÞðD q2 Þ
þ
3
(B) DCM
The inductor RMS current in DCM is calculated as follows:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u 0 DT 1
u Z ZDt2 2
u2 @ t 2 t
ILc RMS D ðqÞ ¼ t ILc D dt þ ILc D ILc D dtA
Ts DT Dt2
0 0
ð7:47Þ
Normalizing (7.47) gives:

sffiffiffiffiffi
ILc RMS D 4f s Lc pffiffiffi D
ILc RMS D ðqÞ ¼ ¼ 2 2D ð 1 qÞ ð7:48Þ
Vi 6q
The inductor RMS current for CCM and DCM as well for the critical conduction
mode (dashed line, making D = q) are presented in Fig. 7.23. As it can be
observed, the smaller static gain (wider soft commutation range) the higher the
inductor RMS current.
In this section, the capacitors are added in parallel to the switches and dead time is
considered, so the soft commutation phenomenon may be analyzed, adding another
four intervals to one switching period in CCM and in DCM. If properly designed,
the capacitors enable zero voltage switching (ZVS) in a wide load range.
7.4.1 Continuous Conduction Mode (CCM)
In CCM the leading leg (S1 and S3) commutates with the inductor peak current
ILc C and the lagging leg (S2 and S4,) commutates with a smaller current I1
(Fig. 7.10). Another four time intervals of operation are added to the ones presented
Sect. 7.2.1, these take place during the switches dead time. During the dead time
intervals, that are much shorter than the other six, the inductor current is considered
to remain constant and the capacitors in parallel to the switches must be fully
charged/discharged in order to achieve soft commutation.
Figure 7.24 presents the first commutation time interval that takes place between
time interval Δt1 and Δt2 of Sect. 7.2.1, when switch S2 is turned off but switch S4 is
not yet gated on (dead time). The inductor current during this time interval is I1 and
half of this current (I1/2) flows through each one of the capacitors, charging C2 from
vg2 dead
time
vg4 t
S1 D 1 C1 C2 D2 S2
io’ vs2
Vi iS2
Lc
+ a c b I1
Vi Vo’ iLc
- S 3 D3 C3 C4 D4 S4 vs4
Vi
iD4
I1
iC2
I1/2
vg1 dead
time
vg3 t
S1 D1 C1 C2 D2 S2
io’ vs1
Vi
Lc ILc_C
+ a c b iS1
Vi Vo’
- S3 D3 C3 iLc C4 D4 S4 vs3
Vi
ILc_C iD3
iC1
ILc_C /2
zero to Vi and discharging C4 from Vi to zero, linearly. Figure 7.24 also shows the
main waveforms where the soft commutation of switches S2 and S4 may be
observed. As soon as capacitor C4 is discharged, diode D4 conducts along with
diode D1 (time interval 2 of Sect. 7.2.1). To ensure soft commutation, the capacitors
charge/discharge must finish before the dead time ends.
The second commutation time interval, shown in Fig. 7.25, takes place between
time interval Δt3 and Δt4 of Sect. 7.2.1, when switch S1 is turned off but switch S3 is
not yet gated on (dead time). The inductor current during this time interval is at its
maximum value, ILc C, and half of this current (ILc_C/2) flows through each one of
the capacitors, charging C1 from zero to Vi and discharging C3 from Vi to zero,
linearly. As the inductor peak current is bigger than I1, the charge/discharge of
capacitors C1 and C3 are faster than the charge/discharge of capacitors C2 and C4.
Figure 7.25 also shows the main waveforms where the soft commutation of
switches S1 and S3 may be observed. At the instant capacitor C3 is fully discharged,
vg2 dead
time
vg4 t
S1 D1 C1 C2 D2 S2
io’ vs4
Vi
Lc iS4
+ a c b I1
Vi Vo’ iLc
- S3 D3 C3 C4 D4 S4 vs2
Vi
iD2
I1
iC4
I1/2
Fig. 7.26 Topological state and main waveforms for the third commutation time interval
vg1 dead
time
vg3 t
S1 D1 C1 C2 D2 S2
io’ vs3
Vi
Lc ILc_C
+ a c b iS3
Vi Vo’
- S3 D3 C3 iLc C4 D4 S4 vs1
Vi
ILc_C iD1
iC3
ILc_C /2
Fig. 7.27 Topological state and main waveforms for the fourth commutation time interval
diode D3 starts conducting the inductor current along with switch S4 (time interval
Δt4, Sect. 7.2.1).
Figure 7.26 shows the topological state and the main waveform for the third
commutation time interval that takes place between time interval Δt4 and Δt5 of
Sect. 7.2.1, when switch S4 is turned off but switch S2 is not yet gated on (dead
time). This time interval is similar to the first one shown in Fig. 7.24.
The fourth commutation time interval, presented in Fig. 7.27, takes place
between time interval Δt6 and Δt1 of Sect. 7.2.1, when switch S3 is turned off but
switch S1 is not yet gated on (dead time). This time interval is similar to the second
one shown in Fig. 7.25.
As it may be noticed in the description of the four commutation time intervals,
the lagging leg commutates with a smaller current (I1), so its commutation is more
critical. It is not possible to ensure soft commutation in both legs in all the CCM
load range, because I1 reaches zero at the critical conduction mode, and soft
commutation of switches S2 and S4 is no longer possible. For a given dead time and
load range, the capacitors must be calculated for the critical leg, as follows:
I1 t d
C1 ¼ C2 ¼ C3 ¼ C4 ¼ ð7:49Þ
Vi
7.4.2 Discontinuous Conduction Mode (DCM)
In DCM the leading leg (S1 and S3) commutates with the inductor peak current
ILc_D and the lagging leg (S2 and S4,) has a dissipative commutation, because the
inductor current is zero on its commutation, so no energy is available to charge/
discharge the capacitors.
7.5 Simplified Design Methodology and an Example of the Commutation Parameters 211
7.5 Simplified Design Methodology and an Example

of the Commutation Parameters
In this section a design methodology and an example are presented according to the
mathematical analysis presented in the previous sections. The converter is designed
according to the specifications presented in Table 7.1.
A low static gain (q) of 0.4 is chosen, so a wider load range in CCM is obtained,
resulting in a wider soft commutation load
range. The output DC voltage referred to
the primary side of the transformer V0o is calculated as follows:
V0o ¼ Vi q ¼ 400 0:4 ¼ 160 V
The transformer turns

ratio (n) and the output current referred to the primary side
of the transformer I0o are given by:
V0o 160
n¼ ¼ ¼ 3:2
Vo 50
Io 10
I0o ¼ ¼ ¼ 3:125 A
n 3:2
Assuming that in the nominal power the duty cycle (D) is 0.9, the normalized
output current referred to the primary side of the transformer is calculated:
I0o C 4f s Lc Dð2 DÞ q2 0:9 ð2 0:9Þ 0:42

I0o C ¼ ¼ ¼ ¼ 0:415
Vi 2 2
Resulting in an inductance of:
0:415 400
Lc ¼ ¼ 332 lH
3:125 4 40 103
Table 7.1 Design Specifications

Input DC voltage (Vi) 400 V
Output power (Po) 500 W
Switching frequency (fs) 40 kHz
Dead time (td) 500 ns
Leading leg (S1 and S3) soft commutation range 30–100% Po
The inductor RMS current is calculated as follows:
ð1 qÞ2 ðD þ qÞ3 þ ð1 þ qÞ2 ðD qÞ3

ILc RMS C ¼
6
2
4ð 1 D Þ ð D q2 Þ
þ ¼ 0:496
3
ILc RMS C Vi 400

ILc RMS C ¼ ¼ ¼ 3:732 A
4f s Lc 4 40 103 332 106
The switches S1 e S3 commutation current (ILc C) as well as switches S2 e S4

commutation current (I1), for nominal power, are given by:
ILc C ¼ ð1 qÞ ðD þ qÞ ¼ 0:78
ILc C Vi 0:78 400

ILc C ¼ ¼ ¼ 5:873 A
4f s Lc 4 40 103 332 106
I1 ¼ ð1 þ qÞ ðD qÞ ¼ 0:7
I1 Vi 0:7 400
I1 ¼ ¼ ¼ 5:271 A
4f s Lc 4 40 103 332 106
The limit between CCM and DCM (D = q) is:
qð 2 qÞ q2 Vi
I0o L ¼
2 4f s Lc
0:4 ð2 0:4Þ 0:42 400
I0o L ¼ ¼ 1:807 A
2 4 40 103 332 106
Resulting in an output power of:
PoL ¼ I0o L V0o ¼ 1:807 160 ¼ 289:16 W
The capacitors in parallel to the switches has to be calculated to ensure soft

commutation up to 30% of the nominal power (150 W) in the leading leg. As the
critical conduction mode is on 289.16 W, the lagging leg (S2 and S4) will have a
dissipative commutation on 30% of the nominal power, because the inductor cur-
rent is already zero and there is no energy to charge/discharge the capacitors (C2
and C4). To ensure soft commutation at the leading leg (S1 and S3) on 30% of the
nominal power, the capacitors have to be calculated as follows:
ILc D td 2:44 500 109

C1 ¼ C2 ¼ C3 ¼ C4 ¼ C ¼ ¼ ffi 1:5 nF
2 Vi 2 400
With these capacitors, the lagging leg soft commutation is achieved up to 70% of
the nominal power, as calculated bellow:
2CVi 2 1:5 109 400

I1 L ¼ ¼ ¼ 2:44 A
td 500 109
I1 L4Lc f s 2:44 4 332 106 40 103

I1 L ¼ ¼ ¼ 0:324
V1 400
The FB ZVS-PWM presented in Fig. 7.28 is simulated at the specified operation

point to verify the analysis and the calculation presented in the design example of
Sect. 7.5, with a dead time of 500 ns. Figure 7.29 presents the AC voltages vab, vac
and vbc, as well as the inductor current iLc and Table 7.2 presents the theoretical and
simulated parameters, for nominal power.
A detail of the soft commutation in the nominal power for switches S1 (leading
leg) and S2 (lagging leg) are presented in Figs. 7.30 and 7.31. As the capacitors
were designed to achieve soft commutation in the leading leg at 30% of the nominal
power, for both legs the capacitors charge/discharge finishes before the dead time
ends. As the lagging leg has a smaller current (I1/2) to charge/discharge the
capacitors, the commutation takes longer than in the leading leg.
Figure 7.32 shows a detail of switch S1 soft commutation at 30% of the nominal
power. As it may be noticed the charge of capacitor C1 takes all the dead time.
Below 30% of the nominal power switch S1 commutation is going to be dissipative.
Figure 7.33 the soft commutation limit for switch S2 at 70% of the nominal
power can be observed. The capacitor C2 charge takes all the dead time. Below
70% of the nominal power the lagging leg has a dissipative commutation.
Fig. 7.28 Simulated

S1 D1 C1 C2 D2 S2
converter io’
Vo’ Lc
+ a c b
Vi
- S3 D3 C3 iLc C4 D4 S4
1
vg1 vg3
td
1
vg4 vg2
td
vab
400
ΔT
0
-400
400 vbc
iLc x 50
0
-400
500 510 520 530 540 550

Time (μs)
Fig. 7.29 FB ZVS-PWM converter simulation waveforms: switches drive signals, voltages vab
and vbc and inductor Lc current
Table 7.2 Theoretical and Theoretical Simulated

simulated results in CCM
I0o C [A] 3.125 3.123
I1 [A] 5.271 5.286
ILc C [A] 5.873 5.849
ILc RMS_C [A] 3.732 3.589
Po [W] 500 499.783
1
vg1 vg3
td
400
iS1 x 50 vS1
200
0
4
iC1
2
511.6 512.0 512.4 512.8

Time (μs)
Fig. 7.30 Switch S1 soft commutation at nominal power: S1 and S3 drive signal, voltage and
current at switch S1 and capacitor C1 current at nominal power
1
vg2 vg4
td
400
iS2 x 50 vS2
200
0
4
iC2
2
525.4 525.8 526.2 526.6

Time (μs)
Fig. 7.31 Switch S2 soft commutation at nominal power: S2 and S4 drive signal, voltage and
current at switch S2 and capacitor C2 current at nominal power
1
vg1 vg3
td
400
vs1
200 is1 x 50
0
2
1
iC1
0
561.8 562.0 562.2 562.4 562.6

Time (μs)
Fig. 7.32 Switch S1 soft commutation at 30% of nominal power: S1 and S3 drive signal, voltage
and current at switch S1 and capacitor C1 current
1
vg2 vg4
td
400
vs2
200 is2 x 50
0
2
iC2
1
529.0 529.2 529.4 529.6 529.8

Time (μs)
Fig. 7.33 Switch S2 soft commutation at 70% of the nominal power: S2 and S4 drive signal,
voltage and current at switch S2 and capacitor C2 current
7.7 Problems 217
7.7 Problems
(1) The FB-ZVS-PWM converter with capacitive output filter has the following
specifications:
Vi = 400 V Vo = 50 V I0o ¼ 0:6
f s ¼ 50 103 Hz Io = 20 A
(a) Calculate the transformer turns ratio.
(b) Calculate the inductance Lc.
(c) What is the duty cycle?
Answers: (a) n = 4
(b) Lc = 120 µH
(c) D = 0.613
(2) The specification for a FB-ZVS-PWM converter with capacitive output filter
are:
Vi = 400 V Vo = 120 V Ns = Np (n = 1)
(a) For the critical conduction mode calculate the duty cycle, the load average
current and the output power.
(b) Draw the following curves: Io = f(D) e Po = f(D) para 0 D 1.
Answers: (a) D = 0.3, Io = 2.1 A, Po = 252 W
f s ¼ 100 103 Hz Lc = 100 µH
(3) A FB-ZVS-PWM converter with capacitive output filter have the following
specifications:
Vi = 400 V, Vo = 120 V, Ns = Np (a = 1)
f s ¼ 100 103 Hz Lc = 100 µH, D = 0.5
(a) Calculate the switches’ commutation currents.
(b) Considering a dead time of 500 ns, calculate the commutation capacitance
for each inverter leg.
Answers: (a) ILc C = 5.6 A, I1 = 2.6 A
(b) C13 = 3.5 nF, C24 = 1.625 nF
(4) Describe the FB-PWM converter with capacitive output filter steps of opera-
tion, representing the topological states and the main waveforms, considering
all components ideal, in CCM and in DCM.
(5) Obtain the expression of the normalized static gain as a function of the output
current Io, in CCM and in DCM.
(6) Describe the ZVS commutation steps of operation for the leading and lagging
leg.
Fig. 7.34 Half bridge PWM

converter + S1 D1
Vi io’
- Vo’
a c
Lc b
iLc S2 D2
+
Vi
-
(7) The Half-Bridge PWM converter presented in Fig. 7.34 operates with switches
S1 and S2 drive signals at 50% of duty cycle.
(a) Considering that all components are ideal, describe the time intervals for
the different topological states and present the main waveforms.
(b) Obtain the average load current i0o equation.

(c) Obtain the inverter output characteristics q ¼ f I0o , considering q ¼
V0o =Vi and I0o ¼ 4 LK IO =Vi .
(d) Considering the following specifications Vi = 100 V, Vo = 50 V,
fs = 20 kHz and Lc = 100 µH, calculate the average load current Io and the
output power Po.
Reference
1. Barbi, I., Filho, W.A.: A non-resonant zero-voltage switching pulse-width modulated full-
bridge DC-to-DC converter. In: IECON, pp. 1051–1056 (1990)
Chapter 8
Full-Bridge ZVS-PWM Converter
with Inductive Output Filter
Nomenclature
Vi Input DC voltage
Po Output power
Lo Output filter inductor
/ Angle between the leading leg and the lagging leg
q Static gain
D Duty cycle
Def Effective duty cycle
Ts Switching period
td Dead time
I0o Output DC current referred to the transformer primary side
v0o ðV0o Þ Output voltage referred to the transformer primary side and
its average value
io Output current
I0o I0o Average output current referred to the transformer primary
I0o crit Critical average output current referred to the primary side
S1 and S3 Switches in the leading leg
S2 and S4 Switches in the lagging leg
D1, D2, D3 and D4 Diodes in anti-parallel to the switches (MOSFET—intrinsic
diodes)
C1, C2, C3 and C4 Capacitors in parallel to the switches (MOSFET—intrinsic
capacitors); C = C1 = C2 = C3 = C4
vC1, vC2, vC3 and vC4 Capacitors voltage
vC Equivalent capacitors voltage

220 8 Full-Bridge ZVS-PWM Converter with Inductive Output Filter
Lc Transformer leakage inductance or an additional inductor,

if necessary
iLc Inductor current
Δ and b State plane angles
vac Voltage at the ac side of the rectifier, between points “a”
and “c”
iD1, iD2, iD3 and iD4 Current in the diodes
ΔT Time interval which vab = ±Vi
Δt1 Time interval of the first step of operation in CCM
Δt2 Time interval of the second step of operation in CCM
Δt3 Time interval of the third step of operation in CCM
Δt4 Time interval of the fourth step of operation in CCM
Δt5 Time interval of the fifth step of operation in CCM
Δt6 Time interval of the six step of operation in CCM
Δt7 Time interval of the seventh step of operation in CCM
Δt8 Time interval of the eighth step of operation in CCM
IS13 RMS IS13 RMS Switches S1 and S3 RMS current and its normalized value

IS24 RMS IS24 RMS Switches S2 and S4 RMS current in CCM and its
normalized value
ID13 ID13 Diodes D1 and D3 average current and its normalized value

ID24 ID24 Diodes D2 and D4 average current and its normalized value
8.1 Introduction
In this chapter, the Full-Bridge Zero-Voltage-Switching Pulse-Width-Modulation

Converter (FB-ZVS-PWM) with an Inductive Output Filter is studied. Such con-
verter is similar to the FB-ZVS-PWM studied in Chap. 7. However, instead of a
capacitive output filter, the output filter is inductive. This reduces the current ripple
after the output rectifier, so it may be considered an ideal current source. As a
consequence, in comparison to Chap. 7, the conduction losses are smaller,
increasing significantly the performance, being suitable for even higher power
applications. The chapter is organized to present at first the topology of the con-
verter and its basic operation (without soft commutation) followed by a detailed
analysis of the Zero Voltage Switching operation and a design example.
S1 D1 C1 C2 D2 S2 Lo io
+
Lc c T
Vi
+ a b
..
- S3 D3 C3 C4 D4 S4 iLc Co Ro Vo
Fig. 8.1 Full-bridge ZVS-PWM with inductive output filter
The schematics of the FB-ZVS-PWM Converter with inductive output filter,

shown in Fig. 8.1, consists of a single phase full bridge inverter, an inductor, an
isolating transformer, a full bridge diode rectifier and an inductive output filter.
Diodes (D1, D2, D3 and D4) in anti-parallel to the switches (S1, S2, S3 and S4) and
the parallel capacitors (C1, C2, C3 and C4) can be the parasitic components of a
MOSFET or additional components added in parallel to the switches, as in case of
IGBTs. The inductance Lc may be the transformer leakage inductance or an
additional one, if necessary. The main role of this inductor is to provide energy to
charge and discharge the commutation capacitors at the instant of the commutation
so that soft commutation can be achieved.
This converter operates with a fixed switching frequency and the voltage across
the switches is limited to the DC link voltage (Vi). To achieve zero voltage
switching (ZVS) the two legs operate with a phase-shift modulation, allowing the
capacitors to be discharged and the antiparallel diodes to conduct prior to the
switches conduction. At light load conditions, switches ZVS commutation may not
be achieved, because of the insufficient energy stored in the inductor Lc.
8.2 Converter Operation
In this section, the converter represented by the equivalent circuit shown in Fig. 8.2
without the commutation capacitors is analyzed (the soft commutation analysis is
presented in Sect. 8.3). To simplify, the following assumptions are made:
• the output filter is represented as a DC current source I0o , whose value is the
output current referred to the primary side of the transformer;
• the diodes in anti-parallel to the switches conduct separately from the switches,
so the analysis is not limited to MOSFET’s.
Fig. 8.2 Equivalent circuit of

the full-bridge ZVS PWM S1 D1 D2 S2
+
converter vo' Lc
+ a
Io' c b
Vi
- S3 D3 iLc D4 S4
-
Fig. 8.3 Phase shift PWM φ=0o φ=180o

used to control the FB vg1 TS φ
ZVS-PWM
vg3 t
φ
vg2
vg4
vab
Vi
ΔΤ
ΔΤ
TS / 2
-Vi
The basic principle of the phase shift PWM used to control this converter is
illustrated in Fig. 8.3. The switches drive signals are presented for both the leading
(S1 and S3) and the lagging leg (S2 and S4), along with the voltage vab. No dead
time is considered at this point.
In the phase shift modulation, the switching frequency is fixed and the switches
of each leg are gated complementary with duty cycle equal to 50%. The lagging leg
drive signals are shifted of an angle / in relation with to the leading leg drive
signals, allowing the power transfer to be controlled. If / = 0°, vab has its maxi-
mum RMS value since switches S1 and S4 always conduct at the same time
(vab = Vi), and switches S2 and S3 also conduct at the same time (vab = −Vi). When
/ increases the vab RMS value decreases because switches S1 and S2 as well as S3
and S4 conduct at the same time resulting in vab = 0. The / angle varies from 0°
(maximum power) to 180° (zero power).
The operation of the converter is described over one switching period that is
divided into eight time intervals, each one representing a different topological state.
The topological state during the time interval Δt1, shown in Fig. 8.4, starts at t = t0.
The output current source is short circuited by the rectifier diodes. The inductor Lc
current flows through diode D1 and switch S2. The voltage vab is zero.
8.2 Converter Operation 223

for time interval Δt1 S1 D1 D2 S2
+
vo' Lc
+ a
Io'
c b
Vi
- S3 D3 iLc D4 S4
-

+
vo' Lc
+ a c b
Vi Io'
- S3 D3 iLc D4 S4
-

This time interval, which topological state is shown in Fig. 8.5, starts at t = t1,
when S4 is driven on and S2 is driven off. As the inductor current is still negative
iLc ðt1 Þ ¼ I0o , it flows through diodes D1 and D4 increasing linearly until it
reaches zero. During this time interval, vab = Vi and vcb = Vi.
Figure 8.6 presents the topological state for time interval Δt3. It begins at t = t2
when iLc reaches zero (iLc(t2) = 0), turning off diodes D1 and D4 and enabling
switches S1 and S4 to conduct, as the inductor current increases linearly. The AC
voltage is vab = Vi and the inductor voltage is vcb = Vi.
Figure 8.7 shows
the topological
state for time interval Δt4. It begins at t = t3 when
0 0
iLc reaches Io iLc ðt3 Þ ¼ Io so the output rectifier does not short circuit the output
current anymore and energy is delivered to the load. The voltage vab = Vi.

+
vo' Lc
+ a c b
Vi Io'
- S3 D3 iLc D4 S4
-

+
vo' Lc
+ a c b
Vi Io'
- S3 D3 iLc D4 S4
-

+
vo' Lc
+ a c b
Vi Io'
- S3 D3 iLc D4 S4
-

The topological state for the time interval Δt5 is shown in Fig. 8.8. It starts at t = t4
when S3 is driven on and S1 is driven off. The output current source is short
circuited by the rectifier diodes. The inductor Lc current flows through diode D3 and
switch S4. The voltage vab is zero.
This time interval, which topological state is shown in Fig. 8.9, starts at t = t5,
when S2 is gated on and S4 is gated off. As the inductor current is still positive
(iLc(t) = I0o ), it flows through diodes D2 and D3 decreasing linearly until it reaches
zero. The AC voltage is vab = −Vi and the inductor voltage is vcb = −Vi.

+
vo' Lc
+ a c b
Vi Io'
- S3 D3 iLc D4 S4
-
8.2 Converter Operation 225

+
vo' Lc
+ a c b
Vi Io'
- S3 D3 iLc D4 S4
-

+
vo' Lc
+ a c b
Vi Io'
- S3 D3 iLc D4 S4
-

when iLc reaches zero (iLc(t) = 0), turning off diodes D2 and D3, and enabling
switches S2 and S3 to conduct, as the inductor current decreases linearly. The AC
voltage is vab = −Vi and the inductor voltage is vcb = −Vi.
when iLc reaches I0o . Thus, the output rectifier does not short circuit the output
current anymore and energy is delivered to the load. The AC voltage is vab = −Vi.
The main waveforms and the time diagram are shown in Fig. 8.12.
vg1 TS
vg3 t
φ
vg2
vg4
vab
Vi
ΔΤ
ΔΤ
-Vi
vac
Vi
-Vi
iLc
Io'
-Io'
vS1
Vi
Io'
iS1
vS2
Vi
Io' iS2
t0 t1 t2 t3 t4 t5 t6 t7 t8
Fig. 8.12 Main Waveforms and time diagram of the FB ZVS-PWM converter over an operation
cycle
In this section, the capacitors are added in parallel to the switches and dead time is
considered, so the soft commutation phenomenon may be analyzed, adding another
four intervals to one switching period. If properly designed, the capacitors enable
zero voltage switching (ZVS) in a wide load range.
The leading leg (S1 and S3) commutates when the output rectifier diodes are not
short circuited, so the output current I0o charge/discharge the capacitors in a linear
way. The lagging leg (S2 and S4) commutates when the output rectifier is short
circuited, and the charge/discharge of the commutation capacitors takes place in a
resonant way, being more critical because only the inductor’s (Lc) energy is
available to charge/discharge the capacitors.
The four commutation time intervals take place during the switches dead-time,
that are much shorter than the other eight time intervals. The capacitors in parallel
to the switches must be fully charged/discharged in order to achieve soft
commutation.
8.3.1 Leading Leg Commutation
During the leading leg commutations, the output rectifier is not short circuited, the
output current I0o charge/discharge the capacitors in a linear way.
Figure 8.13 shows the commutation time interval that takes place between time
intervals Δt4 and Δt5 of Sect. 8.2, when switch S1 is turned off but switch S3 is not
yet turned on (dead time). The inductor current during this time interval is the
output current I0o and half of this current flows through each of the capacitors,
charging C1 from zero to Vi and discharging C3 from Vi to zero in a linear way.
Figure 8.13 also shows the main waveforms where the soft commutation of
switches S1 and S3 may be observed. As soon as the capacitor C3 is discharged,
vg1 dead
time
vg3 t
S1 + D1 C1 C2 D2 S2
vS1 + vs1
Vi
- vo' Lc I o'
+ a c b iS1
Vi Io'
- S3 + D3 C3 iLc C4 D4 S4 vs3
vS3 Vi iD3
- I o'
-
iC1
Io'/2
Fig. 8.13 Topological state and key waveforms during dead-time between gate signals of
switches S1 and S3
vg1 dead
time
vg3 t
S1 + D1 C1 C2 D2 S2
vS1 + Vi
vs3
- vo' Lc I o'
+ a c b iS3
Vi Io'
- S3 + D3 C3 iLc C4 D4 S4 vs1
vS3 Vi iD1
- I o'
-
iC3
Io'/2
switches S3 and S1
diode D3 conducts along with switch S4 (time interval Δt5 of Sect. 8.2). To ensure
soft commutation, the capacitors charge/discharge must finish before the dead time
ends.
Figure 8.14 shows the commutation time interval that takes place between time
interval Δt8 and Δt1 of Sect. 8.2, when switch S3 is driven off but switch S1 is not
yet driven on (dead time). The inductor current during this time interval is the
output current I0o and half of this current flows through each of the capacitors,
charging C3 from zero to Vi and discharging C1 from Vi to zero in a linear way.
Figure 8.14 also shows the main waveforms and the time diagram, where the soft
commutation of switches S1 and S3 may be observed. As soon as the capacitor C1 is
discharged, diode D1 conducts along with switch S2 (time interval Δt1 of Sect. 8.2).
To ensure soft commutation, the capacitors charge/discharge must finish before the
dead time ends.
To ensure soft commutation in the leading leg (non-critical commutation), for a
given load current, the dead time td must satisfy the constraint given by Eq. (8.1).
C Vi
td ð8:1Þ
I0o
where C = C1 = C2 = C3 = C4 is the commutation capacitor.
8.3.2 Lagging Leg Commutation
During the lagging leg commutation, the output rectifier is short circuited, and only
the energy stored in inductance Lc is available to charge/discharge the commutation
capacitors, in a resonant way. Therefore, the ZVS range of the switches of this leg is
lower than the ZVS range of the leading leg.
vg2 dead
time
vg4 t
S1 D 1 C1 C2 D2 S2 +
+ vS2 Vi vs2
vo' Lc - I o'
a c iS2
+ b
Vi Io'
- S3 D 3 C3 iLc C4 D4 S4 vs4
+ Vi iD4
- vS4 I o'
-
iC2
Io'/2
switches S2 and S4
Figure 8.15 shows topological state and relevant waveforms during dead-time
between gate signals of switches S2 and S4 in which switch S2 is gated off but
switch S4 is not gated on yet. As the output rectifiers diodes are short circuited at
this time interval, only the energy stored in inductor Lc is available to the com-
mutation process. To ensure soft commutation, the capacitors charge/discharge
must finish before the dead time ends. It may be observed that the capacitors
voltage and the inductor current evolve in a resonant way.
During the commutation process the inductor current flows through each one of
the capacitors, charging one and discharging the other one. If the capacitor is
discharged before the dead time ends, the soft commutation is achieved. Inductance
Lc value is very important on this critical commutation, because only the energy
stored on it is available to charge/discharge the capacitors. However, the choice of a
high value of inductance, implies in a less effective duty cycle.
During the commutation time interval, the capacitor voltage and inductor current
follow the equations bellow, considering vC2 ð0Þ ¼ 0; vC4 ð0Þ ¼ Vi ; iLc ð0Þ ¼ I0o :
vC ðtÞ ¼ z I0o sen ðxo tÞ ð8:2Þ
I0o
iL c ðtÞ ¼ cos ðxo tÞ ð8:3Þ
x2o
qffiffiffiffiffiffiffiffi
where z ¼ Lc and x ¼ pffiffiffiffiffiffiffiffiffiffi
1 ffi.
2 C o
L c 2C
The state plane for the topological state of Fig. 8.15 is plotted in Fig. 8.16.
To ensure soft commutation, the constraint given by Eq. (8.4) must be satisfied:
z I0o Vi ð8:4Þ
Fig. 8.16 State plane for z iLc

topological state of Fig. 8.15
Vi
Δ vC
β
z Io’
Thus,
rffiffiffiffiffiffi
2C
I0o Vi ð8:5Þ
Lc
According to Fig. 8.16 we have

p
bþD ¼ ð8:6Þ
2
Hence,
p
b¼ D ¼ xDt ð8:7Þ
2
After appropriate algebraic manipulation it can be found
p=2 D p pffiffiffiffiffiffiffiffiffiffiffiffi
Dt ¼ ¼ D 2 CLc ð8:8Þ
x 2
where Dt is the commutation time.

The angle Δ is given by
rffiffiffiffiffiffiffi
1 Vi 1 Vi 2C
D ¼ cos ¼ cos ð8:9Þ
z I0o I0o Lc

p 1 Vi 2 C pffiffiffiffiffiffiffiffiffiffiffiffi
Dt ¼ cos 0 2 CLc ð8:10Þ
2 Io Lc
The dead-time between the gate signals of the switches of the lagging leg must
be larger than the time interval Dt. Otherwise, the ZVS commutation of the power
switches is not achieved.
vg2 dead
time
vg4 t
S1 D1 C1 C2 D2 S2 +
+ vS2 Vi vs4
vo' Lc - I o'
+ a c b iS4
Vi Io'
- S3 D3 C3 iLc C4 D4 S4 + V vs2
vS4 Ioi' iD2
-
-
iC4
Io'/2
switches S4 and S2
Figure 8.17 shows the topological state and relevant waveforms of the other
resonant commutation, that takes place between time intervals Δt5 and Δt6 of
Sect. 8.2, during the dead-time between the gate signal of switches S4 and S2. In this
commutation the capacitors voltages and the inductor current also evolve in a res-
onant way and only the energy stored in inductor Lc is available to the commutation
process, since the output rectifier is short-circuited again. To ensure soft commu-
tation, the capacitors charge/discharge must finish before the dead time ends.
The output characteristics of the FB-ZVS-PWM with an inductive output filter is

obtained in this section. The commutation time intervals are disregarded because
they are very short compared to the other time intervals and the inductor current
may be considered constant during the commutation.
As the converter is symmetric in one switching period, the following time
intervals are equal: Dt1 ¼ Dt5 ; Dt2 ¼ Dt6 and Dt3 ¼ Dt7 .
The time interval, which vab = ±Vi, is defined as Dt, as shown in Fig. 8.12.
Thus, Eqs. (8.11) and (8.12) may be written:
DT ¼ Dt2 þ Dt3 þ Dt4 ¼ Dt6 þ Dt7 þ Dt8 ð8:11Þ
Ts
2
The duty cycle is defined by

2 DT
D¼ ð8:13Þ
Ts
When the inductor Lc current evolves linearly in the time intervals Δt2, Δt3, Δt6
and Δt7, the output rectifier diodes are short circuited and the output voltage is zero,
as it may be observed in Fig. 8.12. So, the power transferred to the load only takes
place in the fourth and eight time intervals. The effective duty cycle is defined as
follows:
Ts
Dt4 ¼ Def ð8:14Þ
2
As it can be noticed in the second and third time intervals, the equivalent circuit
is the same and the voltage across inductor Lc is Vi, so these time intervals are equal
and given by Eq. (8.15).
Ts
Dt2 ¼ Dt3 ¼ ðD Def Þ ð8:15Þ
4
The first time interval be obtained as follows:
Ts
Dt1 ¼ ð1 DÞ ð8:16Þ
2
In the third time interval the current iLc ðtÞ is obtained from the following
equation:
diLc ðtÞ
Vi ¼ Lc ð8:17Þ
dt

Vi
iLc ðsÞ ¼ ð8:18Þ
s2Lc
Using the Inverse Laplace Transform the inductor current is obtained.
Vi
iLc ðtÞ ¼ t ð8:19Þ
Lc
This time interval ends when the inductor current reaches I0o , so time interval
three may be calculated.
I0o Lc
Dt3 ¼ ð8:20Þ
Vi
Substituting (8.14), (8.15) and (8.20) in (8.11), (8.21) is obtained.


characteristic of the q
FB-ZVS-PWM with an
inductive output filter 0.8
0.8
0.6
0.6
0.4
0.4
0.2
D=0.2
0
0 0.05 0.10 0.15
I o’
Ts 2 I0 Lc Ts
DT ¼ D ¼ Dt3 þ Dt4 þ Dt5 ¼ o þ Def ð8:21Þ
2 Vi 2
Thus, the effective duty cycle is
4 I0o Lc f s
Def ¼ D ð8:22Þ
Vi
Defining
4 I0o Lc f s
I0o ¼ ð8:23Þ
Vi
As it may be noticed in (8.22) and (8.23), I0o represents the duty cycle loss due to
the voltage drop in inductance Lc in time intervals Δt2, Δt3, Δt6 and Δt7, which is
directly proportional to the output current I0o and inductance Lc.
The average output voltage is defined by
V0o ¼ Def Vi ð8:24Þ
Hence,

4 I0o Lc f s
V0o ¼ D Vi ð8:25Þ
Vi
and
V0o
q¼ ¼ D I0o ð8:26Þ
Vi
where q is the converter static gain.

The FB-ZVS-PWM output characteristic, given by Eq. (8.26) is shown in
Fig. 8.18.
8.4.2 RMS Switches Current
The switches S1 and S3 RMS current is calculating by integrating the inductor

current in the third and fourth time interval (Sect. 8.2). Thus,
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
3ffi
u 2 Dt3 2 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u Z ZDt4
u1 t I0 D þ 5 Def
IS13 RMS ¼t 4 I0o dt þ I0o2 dt5 ¼ o ð8:27Þ
Ts Dt32 2 3
0 0
Substitution of (8.22) into (8.27) and normalizing:

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS13 RMS 1 5
IS13 RMS ¼ ¼ 2 D I0o ð8:28Þ
I0o 2 3
The switches S2 and S4 RMS current is calculated by integrating the inductor

current in the seventh, eight and first time interval (Sect. 8.2). Hence,
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u 2 Dt7 2
3
u Z ZDt8 ZDt1
u1 4 t
IS24 RMS ¼t I0o dt þ I0o2 dt þ I0o2 dt5
Ts Dt76
0 0 0
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
5 ðD Def Þ þ 6
¼ I0o ð8:29Þ
12
Substituting (8.22) in (8.29) and normalizing yields:

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS24 RMS 1 5
IS24 RMS ¼ ¼ 2 I0o ð8:30Þ
I0o 2 3
8.4.3 Average Diodes Current
The diodes D1 and D3 average current is calculated by integrating the inductor

current in the first and third time intervals. Thus,
2 Dt 3
Z1 ZDt3
1 4 0 0 0 t 5 I0o ðD þ Def Þ
ID13 ¼ Io dt þ Io Io dt ¼ 1 ð8:31Þ
Ts Dt3 2 2
0 0
After integration and appropriate algebraic manipulation, we find

" #
ID13 1 I0o
ID13 ¼ 0 ¼ 1 Dþ ð8:32Þ
Io 2 2
Similarly, the average value of the diodes D2 and D4 current is determined by

integration of the inductor current in the second time interval, according to
Eq. (8.32).
ZDt2 !
0
1 I ðD Def Þ
ID24 ¼ I0o o t dt ¼ I0o ð8:33Þ
Ts Dt2 8
0
Integration and algebraic manipulation gives
ID24 I0o
ID24 ¼ ¼ ð8:34Þ
I0o 8
8.5 Simplified Design Example and Methodology
In this section, a simplified design example is presented, using the analysis results
of previous sections. The converter specifications are given in Table 8.1.
The static gain is q ¼ 0:4. The output DC voltage referred to the primary side of
the transformer V0o is calculated as follows:
V0o ¼ Vi q ¼ 400 0:4 ¼ 160 V

specifications
The transformer turns ratio (n) and the output current referred to the primary side
of the transformer (I0o ) are:
V0o 160
n¼ ¼ ¼ 3:2
Vo 50
and
Io 10
I0o ¼ ¼ ¼ 3:125 A
n 3:2
Assuming that at nominal power the duty cycle reduction is 15%, the inductance
Lc is:
I0o Vi 0:15 400

Lc ¼ ¼ ¼ 120 lH
4 f s I0o 4 40 103 3:125
The nominal and effective duty cycles are calculated as follows:
V0o 160
Dnom ¼ þ I0o ¼ þ 0:15 ¼ 0:55
Vi 400
Def ¼ Dnom I0o ¼ 0:55 0:15 ¼ 0:4
The switches RMS current and the antiparallel diodes average current, for
nominal power, are:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS13 RMS 1 5 0 1 5
IS13 RMS ¼ ¼ 2D Io ¼ 2 0:55 0:15 ¼ 0:46
I0o 2 3 2 3
IS13 RMS ¼ 0:46 3:125 ¼ 1:44 A

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS24 RMS 1 5 0 1 5
IS24 RMS ¼ ¼ 2 Io ¼ 2 0:15 ¼ 0:66
I0o 2 3 2 3
IS24 RMS ¼ 0:66 3:125 ¼ 2:06 A

!
ID13 1 I0o 1 0:15
ID13 ¼ ¼ 1 Dþ ¼ 1 0:55 þ ¼ 0:26
I0o 2 2 2 2
ID13 ¼ 0:26 3:125 ¼ 0:82 A

8.5 Simplified Design Example and Methodology 237
ID24 I0o 0:15

ID24 ¼ ¼ ¼ ¼ 0:02
I0o 8 8
ID24 ¼ 0:02 3:125 ¼ 0:06 A
Assuming that the capacitances of the commutation capacitors are

C ¼ C1 ¼ C2 ¼ C3 ¼ C4 ¼ 0:5 nF.
The lagging leg soft commutation limit implies that angle Δ is zero. So, the
commutation time is:
p pffiffiffiffiffiffiffiffiffiffiffiffi p pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Dt ¼ 2 CLc ¼ 2 0:5 109 120 106 ¼ 544 ns
2 2
As it has already been demonstrated in previous sections, the accomplishment of

the ZVS commutation requires a dead-time larger than 544 ns.
As it may be noticed in Fig. 8.16, the soft commutation limit also implies that
zIo = Vi. So, the minimum output current that ensures soft commutation is
rffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2C 2 500 1012
I0o crit ¼ Vi ¼ 400 ¼ 1:15 A
Lc 120 106
This value is 37% of the rated current, which implies in ZVS commutation for
power range between 37% and 100% of the rated power.
The FB ZVS-PWM with an inductive output filter presented in Fig. 8.19 is sim-
ulated to validate the analysis, for a dead time of 550 ns. Figure 8.20 presents the
voltages vab, v0o , as well as the inductor voltage and current. Table 8.2 presents
theoretical and simulated parameters and component stresses, validating the
mathematical analysis.
S1 D1 C1 C2 D2 S2
+
v0' Lc
+ a c b
Vi I0'
- S3 D3 C3 iLc C4 D4 S4
-
Fig. 8.19 Simulated converter

1
vg1 vg3
td
1
vg2 vg4
td
400
vab
200
vo ◊
0
-200 ΔT
-400
400
iLc vcb
200
0
-200
-400
0.50 0.52 0.54
Time (ms)
Fig. 8.20 FB-ZVS-PWM converter simulation waveforms for nominal power: switches drive
signals, voltages vab, v0o and vcb, current iLc
Figures 8.21 and 8.22 present the leading leg and the lagging leg commutation at
nominal power. As it may be noticed soft commutation is achieved.

simulated results
V0o [V] 160 160.08
IS13 RMS_ [A] 1.44 1.44
IS24 RMS [A] 2.06 2.07
ID13 [A] 0.82 0.76
ID24 [A] 0.06 0.058
Po [W] 500 500.25
1
vg1 vg3
td
vS1
400
200 iS1 x 50
0
2
iC1
1
511.8 512.2 512.6

Time (μs)
Fig. 8.21 Switch S1 soft commutation at nominal power: S1 and S3 drive signals, voltage and
current at switch S1 and capacitor C1 current
1
vg2 vg4
td
vS2
400
200
iS2 x 50
0
2
iC2
1
530.0 530.4 530.8

Time (μs)
Figures 8.23 and 8.24 present the leading leg and the lagging leg commutation at
the minimum power. As it may be noticed soft commutation is on its limit at the
lagging leg.
1
vg1 vg3
td
400
vS1
200
iS1 x 50
0
0.4
iC1
511.8 512.2 512.6

Time (μs)
Fig. 8.23 Switch S1 soft commutation at minimum power: S1 and S3 drive signals, voltage and
1
vg2 vg4
td
400
vS2
200
iS2 x 50
0
iC2
0.4
iC2
530.0 530.4 530.8

Time ( μs)
Fig. 8.24 Switch S2 soft commutation at the minimum power: S2 and S4 drive signals, voltage
and current at switch S2 and capacitor C2 current
8.7 Problems
(1) The FB-PWM converter shown in Fig. 8.25 has a capacitor C to block vab
average value caused by not ideal components. Considering the following
specifications, draw the capacitor C voltage (vC) and calculate its peak value,
considering all components ideal.
8.7 Problems 241
Vi ¼ 400 V I0o ¼ 10 A f s ¼ 20 kHz Lc ¼ 40 lH C ¼ 10 lF
Answer: vC peak = 12 V
(2) For the ideal FB-PWM converter shown in Fig. 8.26: (a) obtain the expression
of the output voltage Vo and (b) calculate the average output voltage.
The parameters of the converter are:
Vi ¼ 400 V Lo ¼ 2 mH Co ¼ 100 lF N s ¼ N p ð n ¼ 1Þ
Ro ¼ 20 X f s ¼ 40 kHz Lc ¼ 40 lH D ¼ 0:75ðf ¼ 45 Þ
Answers: (a) Vo ¼ ðDRo Þ = ðRo þ 4 Lc f s Þ; (b) Vo = 227.27 V

(3) A FB-PWM converter and its drive signals are shown in Fig. 8.27. Due to the
asymmetric gate drive signals, the voltage vab contains a DC component, which
is blocked by the capacitor C. Calculate this DC voltage component, consid-
ering the following parameters:
Io ¼ 10 A C ¼ 10 lF Dt ¼ 1 ls Ns ¼ Np ða ¼ 1Þ
f s ¼ 40 kHz Lc ¼ 25 lH Lm ¼ 1 mH
Answer: Vc = 8 V
(4) For the FB-ZVS-PWM converter shown in Fig. 8.28 with the specifications
given below, calculate: (a) the minimum value of I0o and (b) the dead-time
required to enable ZVS commutation on all switches.
S1 D1 D2 S2
+
vo' C Lc
+ a
Io' c b
Vi
- S3 D3 + - iLc D4 S4
vC
-
Fig. 8.25 Full bridge ZVS PWM converter
S1 D1 D2 S2 Lo io
+
Lc
Vi
+ a b c
.T.
- S3 D3 D4 S4 iLc Co Ro Vo
Fig. 8.26 Full bridge PWM

Fig. 8.27 Full bridge

S1 D1 D2 S2
ZVS-PWM converter and its
drive signals C iLc Lc
Vi
+ a b c
.T. Io
- S3 D3 D4 S4 + - Lm
vC
Δt
vg1 TS / 2
vg3 t
vg2
vg4
TS
Vi ¼ 400 V C ¼ C1 ¼ C2 ¼ C3 ¼ C4 ¼ 0:5 nF f s ¼ 40 kHz

Lc ¼ 10 lH Dt ¼ 300 ns
Answers: (a) I0o = 2A; (b) td = 314.2 ns.

(5) The FB-PWM converter is shown in Fig. 8.29 with the transformer magne-
tizing inductance.
(a) Describe the converter operation during one switching period as well as the
main waveforms;
(b) Obtain the static gain expression;
(c) Obtain the magnetizing inductance peak current expression;
(d) Obtain the expression to calculate the switches current at the commutation
instant.

Answers: (b) q¼V Vi
o
¼ Lm
Lc þ Lm D 4 f s Lc Io
Vi ;

(c) Im peak ¼ 4 f LVþi L D 4 f s VLc Io ; (d) Is = Io + Im
sð c mÞ
peak peak
i
S1 D1 C1 C2 D2 S2
+
vo' Lc
+ a c b
Vi Io'
- S3 D3 C3 iLc C4 D4 S4
-
Fig. 8.28 Full bridge ZVS-PWM converter

8.7 Problems 243
Fig. 8.29 Full bridge

S1 D1 D2 S2
ZVS-PWM converter with
transformer magnetizing iLc Lc
+ a b c
inductance Vi Io
- S3 D3 D4 S4 Lm
(6) The FB-ZVS-PWM converter shown in Fig. 8.29 has the following parameters:
Vi ¼ 400 V Io ¼ 10 A f s ¼ 20 kHz
Lc ¼ 50 lH Lm ¼ 500 lH D ¼ 0:8
Find (a) the average value of the output voltage Vo, (b) the peak value of the
magnetizing current and (c) the peak value of the current in a power switch at
the instant of the commutation.
Answers: (a) Vo = 254.54 V; (b) Im peak = 6.36 A; (c) Is peak = 16.36 A
Chapter 9
Three-Level Neutral Point Clamped
ZVS-PWM Converter
Nomenclature
Vi Input DC voltage
Po Output power
PWM Pulse width modulation
q Static gain
D Duty cycle
Dnom Nominal duty cycle
Def Effective duty cycle
ΔD Duty cycle loss
Ts Switching period
td Dead time
T Transformer
v0o (V0o ) Output voltage referred to the transformer primary side
and its average value
io Output current
I0o I0o Average output current referred to the primary side and
I0o crit Critical average output current referred to the primary
side

246 9 Three-Level Neutral Point Clamped ZVS-PWM Converter
D1, D2, D3 and D4 Diodes in anti-parallel to the switches (MOSFET—
intrinsic diodes)
DC1, DC2 Clamping diodes
C = C1 = C2 = C3 = C4 Capacitors in parallel to the switches (MOSFET—
intrinsic capacitors)
Lr Resonant inductor
iLr peak Resonant inductor peak current
vCr peak Resonant inductor peak voltage
Lc Commutation inductor (may be the transformer leakage
inductance or an additional inductor, if necessary)
iLc Commutation inductor current
vC1, vC2, vC3 and vC4 Capacitors voltage
vab Ac voltage, between points “a” and “b”
vS1, vS2, vS3 and vS4 Voltage across the switches
ΔT Time interval in which vab = ±Vi
Δt2 Time interval of the first and fourth step of operation in
DCM
Δt10 Time interval of the first step of operation in CCM (t1–t0)
Δt21 Time interval of the second step of operation in CCM
(t2–t1)
Δt32 Time interval of the third step of operation in CCM
(t3–t2)
Δt43 Time interval of the fourth step of operation in CCM
(t4–t3)
Δt54 Time interval of the fifth step of operation in CCM
(t5–t4)
Δt65 Time interval of the sixth step of operation in CCM
(t6–t5)
Δt76 Time interval of the seventh step of operation in CCM
(t7–t6)
Δt87 Time interval of the eighth step of operation in CCM
(t8–t7)
9 Three-Level Neutral Point Clamped ZVS-PWM Converter 247

IS14 RMS IS14 RMS Switches S1 and S4 RMS current and its normalized
value
IS23 RMS IS23 RMS Switches S2 and S3 RMS current and its normalized
value
ID1234 ID1234 Diodes D1, D2, D3 and D4 average current and its
normalized value
IDC12 IDC12 Clamping diodes average current and its normalized
value
9.1 Introduction
The converters studied in the previous chapters are not suitable for applications in
which the DC bus voltage exceeds the maximum voltage that the power switches
can withstand.
In order to overcome this drawback, in 1993 [1] the Three-Level Neutral Point
Clamped ZVS-PWM converter, shown in Fig. 9.1, was proposed, which operates in
a similar way to the FB ZVS-PWM converter with an inductive output filter pre-
sented in Chap. 8.
The commutation of the power switches and the output characteristics of the
TL-ZVS-PWM converter are identical to the Full-Bridge ZVS-PWM converter.
However, the power switches are submitted to a voltage equal to half of the DC bus
voltage (Vi/2).
S1 D1 C1 +
Vi /2 Lo io
DC1 -
b +
S2 D2 C2 .T.
Co Ro Vo
a Lc
S3 C3 iLc
D3 -
DC2
S4 D4 C4 +
Vi /2
-
Fig. 9.1 Three-Level NPC ZVS-PWM converter with an inductive output filter
In this section, the ideal converter shown in Fig. 9.2, with all parameters referred to
the transformer primary winding is analyzed. To simplify, the following assump-
tions are made:
• the converter operates on steady-state condition;
• the output filter is represented as a DC current source I0o , whose value is the
output average current referred to the primary winding of the transformer;
• the converter is controlled by pulse width modulation (PWM), with switches S2
and S3 operating complementary with 50% duty cycle and switches S1 and S4
operating with variable duty cycle D to control the power transferred to the load.
The operation of the converter will be described for one switching period that is
divided into eight time intervals, each one representing a different state of the switches.
The time interval Δt1, shown in Fig. 9.3, starts at t = t0 when the inductor current is
equal I0o . Switches S1 and S2 conduct the output current, the voltage vab is equal to
Vi/2 and energy is being transferred to the load.
At the instant t = t1 switch S1 is turned off and the clamping diode Dc1 starts to
conduct the output current along with switch S2, as shown in Fig. 9.4. During this
time interval the voltage vab is zero and the output current source is short circuited
by the rectifier diodes.
The time interval Δt3 begins at t = t2 when switch S2 is turned off and switches S3
and S4 are gated on. As the inductor current is positive, the current flows through
diodes D3 and D4, as it can be seen in Fig. 9.5. The output current source remains
short circuited by the rectifier diodes. The voltage vab is equal to −Vi/2 and the Lc
inductor current decreases linearly.
Fig. 9.2 Equivalent circuit of

the ideal Three-Level S1 D1 +
Vi /2
NPC PWM converter DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

during time interval Δt1 S1 D1 +
Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

during the time interval Δt3 S1 D1 +
Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

This time interval begins at the instant t3, when inductor current iLc reaches zero.
Switches S3 and S4 start to conduct the inductor current iLc, that decreases linearly.
The output current source remains short circuited by the rectifier diodes. The
topological state for this time interval is shown in Fig. 9.6.
The time interval Δt5, shown in Fig. 9.7, starts at t = t4, when the inductor current
iLc reaches −I0o . Switches S1 and S2 conduct the output current −I0o , the voltage vab
is equal to −Vi/2 and energy is transferred to the load.
At t = t5 the switch S4 is turned off, the clamping diode Dc2 starts to conduct the
output current along with switch S3, as shown in Fig. 9.8. As the voltage vab is zero,
the output current source is short circuited again by the rectifier diodes.

during the time interval Δt4 S1 D1 +
Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

The time interval Δt7 begins at t = t6 when switch S3 is turned off and switches S1
and S2 are gated on. As the inductor current iLc is negative, it flows through diodes
D1 and D2, as shown in Fig. 9.9. The output current source is still short circuited by

Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-

Vi /2
DC1 -
S2 D2 +
vo'
a Lc
Io' b
S3 iLc
D3
DC2 -
S4 D4 +
Vi /2
-
the rectifier diodes. The voltage vab is equal to Vi/2, increasing linearly the inductor
current iLc.
This time interval, shown in Fig. 9.10, begins at the instant t7 when switches S1 and
S2 start to conduct the inductor current iLc, that increases linearly. The output
current source remains short circuited by the rectifier diodes.
The relevant waveforms and time diagram are shown in Fig. 9.11.
vg1 Ts
Ts / 2 t
vg2
vg3
vg4
vab
Vi
ΔΤ
-Vi
Vo’
Vi
iLc
Io’
-Io’
Vi / 2
vS1
iS1
Io’ Vi / 4
vS2
Vi / 2 iS2
Io’ Vi / 4
t0 t1 t2 t3 t4 t5 t6 t7 t8
Fig. 9.11 Relevant waveforms and time diagram over one cycle of operation
(A) Output Characteristics

As the converter is symmetric in one switching period, we have: Dt10 ¼ Dt54 ,
Dt21 ¼ Dt65 , Dt32 ¼ Dt76 , and Dt43 ¼ Dt87 .
According to the time diagram shown in Fig. 9.11, the time intervals in which
vab = ±Vi is given by
DT ¼ Dt32 þ Dt43 þ Dt54 ¼ Dt10 þ Dt76 þ Dt87 ð9:1Þ
The half cycle of a switching period is given by
Ts
2
According to the duty-cycle definition, we have
DT
D¼ ð9:3Þ
Ts =2
During the time interval in which the inductor iLc current evolves linearly, the
output voltage v0o is zero So, no power is transferred to the load in this time interval.
The effective duty cycle (Def) is defined by Eq. (9.4).
Dt10 Dt54
Def ¼ ¼ ð9:4Þ
Ts =2 Ts =2
The time intervals Δt32 and Δt21 are calculated as follows:
Ts
Dt32 ¼ ðD Def Þ ð9:5Þ
4
Ts
Dt21 ¼ ð1 DÞ ð9:6Þ
2
Based on the topological state for time interval Δt4 and Δt8, we have
Vi diLc ðtÞ
¼ Lc ð9:7Þ
2 dt
Applying the Laplace transformation to Eq. (9.7) we find
Vi =2
iLc ðsÞ ¼ ð9:8Þ
s2 Lc
Applying the inverse Laplace transformation to Eq. (9.8) gives
Vi =2
iLc ðtÞ ¼ t ð9:9Þ
Lc
Time intervals Δt43 and Δt87 ends when the inductor current reaches I0o and is
given by Eqs. (9.10).
I0o Lc
Dt43 ¼ Dt87 ¼ ð9:10Þ
Vi =2
Substituting (9.4) and (9.10) into (9.1) yields
Ts 2 I0 L c Ts
DT ¼ D ¼ Dt32 þ Dt43 þ Dt54 ¼ o þ Def ð9:11Þ
2 Vi =2 2
Thus, from Eq. (9.11),
4 I0o Lc f s
Def ¼ D ð9:12Þ
Vi =2
Equation (9.12) can also be written in the compact form
Def ¼ D I0o ð9:13Þ

0
4 Io Lc f s
where I0o ¼ V is the duty-cycle loss caused by the series inductance Lc.
i =2
From the above equations we find Eq. (9.14) that represents the converter output
voltage referred to the transformer primary winding.
Vi V
V0o ¼ Def ¼ D I0o
i
ð9:14Þ
2 2
Consequently, the static gain (q) is given by:
V0o
q¼ ¼ D I0o ð9:15Þ
Vi =2
The three-level ZVS-PWM converter theoretical output characteristics, given by

Eq. (9.15) (static gain as a function of the normalized output current, taking the
duty cycle as parameter) are shown in Fig. 9.12. As it may be noticed, the average
output voltage (V0o ) depends on the load current (I0o ), due to the voltage drop across
inductor Lc.
Fig. 9.12 Three-level 1.0

ZVS-PWM converter output q
characteristics
0.8
0.8
0.6
0.6
0.4
0.4
0.2
D=0.2
0
0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
Io’
(B) Switches RMS Current

The effective or RMS current that circulates through switches S1 and S4 is given by
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
3ffi
u 2 Dt87 2
u Z ZDt10
u1 t
IS14 RMS ¼t 4 I0o dt þ I0o2 dt5 ð9:16Þ
Ts Dt87
0 0
After integration in relation to t, yields

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I0 D þ 5 Def
IS14 RMS ¼ o ð9:17Þ
2 3
Substitution of Eqs. (9.12) into (9.17), with appropriate algebraic manipulation

gives the normalized RMS current in switches S1 and S4:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS14 RMS 1 5 I0
IS14 RMS ¼ ¼ 2D o ð9:18Þ
I0o 2 3
Similarly, the RMS value of current in switches S2 and S3 is given by

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ffi
u 0 Dt87 2
u Z ZDt10 ZDt21
u1 t
IS23 RMS ¼t @ I0o dt þ I0o2 dt þ I0o2 dtA ð9:19Þ
Ts Dt87
0 0 0
0.75
0.8
IS14 RMS 0.6
0.50
0.4
D=0.2
0.25
0
0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
Io’
Fig. 9.13 Switches S1 and S4 RMS current, as a function of the normalized output current, taking
D as a parameter
After integration in relation to time and algebraic manipulation it can be found

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
6 5 ðD Def Þ
IS23 RMS ¼ I0o ð9:20Þ
12
Substitution of Eq. (9.12) into Eq. (9.20) gives the normalized current on
switches S2 and S3:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS23 RMS 6 5 I0o
IS23 RMS ¼ ¼ ð9:21Þ
I0o 12
The curve of the normalized current IS14 RMS is shown in Fig. 9.13.
(C) Output Diodes Average Current
The output diodes average current is given by
ZDt32 !
1 I0o
ID1234 ¼ I0o t dt ð9:22Þ
Ts Dt32
0
Thus, after integration in relation to time we find
ðD Def Þ
ID1234 ¼ I0o ð9:23Þ
8
Substituting Eqs. (9.12) in (9.23) it can be obtained
ID1234 I0o
ID1234 ¼ ¼ ð9:24Þ
I0o 8
(D) Average Current in Clamping Diodes D5 and D6

The clamping diodes average current is
ZDt21
1
IDc12 ¼ I0o dt ð9:25Þ
Ts
0
Hence, after integration in relation to time and appropriate manipulation it can be
found
IDc12 ð1 DÞ
IDc12 ¼ ¼ ð9:26Þ
I0o 2
The corresponding curves are plotted in Fig. 9.14.
0.5
IDc12
D=0.2
0.4
0.6
0.3
0.6
0.2
0.8
0.1
0
0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
Io’
Fig. 9.14 Clamping diodes average current, as a function of the parameterized output current,
taking D as a parameter
In this section, commutation capacitors are added in parallel with the switches and
dead time is considered, so the soft commutation phenomenon may be analyzed.
Four commutation time intervals are added to one switching period. An appropriate
design of the commutation capacitors can enable zero voltage switching (ZVS) for
wide load range condition.
(A) Commutation of Switches S1 and S4
The first commutation time interval takes place between time intervals Δt1 and Δt2
described in Sect. 9.2. During time interval Δt1 the capacitors C1 and C2 are dis-
charged and capacitors C3 and C4 are both charged with initial voltage equal to +Vi/2.
At the instant the switch S1 is turned off, capacitor C1 starts to charge with constant
current and its voltage rises linearly towards +Vi/2. Simultaneously, capacitors C3 and
C4 are discharged at constant current with their voltages decreasing linearly to +Vi/4.
The converter topological state for this commutation time interval, along with the
relevant waveforms are shown in Fig. 9.15.
During this commutation time interval, the voltages across commutation
capacitors C1, C3 and C4 are represented by Eqs. (9.27) and (9.28).
I0o t
vC1 ðtÞ ¼ ð9:27Þ
1:5 C
I0o t
vC3 ðtÞ þ vC4 ðtÞ ¼ Vi ð9:28Þ
1:5 C
where C ¼ C1 ¼ C2 ¼ C3 ¼ C4 .
A similar commutation takes place in the second half of the switching period,
between time intervals Δt5 and Δt6 described in Sect. 9.2. This commutation time
interval and its main waveforms are shown in Fig. 9.16.
C1 iC1 +
S1 D1 +v vg1
C1 Vi /2
- DC1 -
vg2 t
S2 D2 C2 +v + vg3
C2
- vo'
a Lc vg4
Io' b
S3 C3 iLc
D3 +v vs1
- Vi/2
-
C3
DC2 iS1
Io’
S4 D4 C4 + iC1
+v
C4 Vi /2 2I o’/3
- -
S1 D1 C1 + vg1
+v Vi /2
C1
- DC1 - vg2 t
S2 D2 C2 vg3
+v +
C2
- vo' vg4
a Lc
Io' b
S3 C3 iLc vs4
D3 +v Vi/2
C3 - iS4
- DC2 Io’
iC4 iC4
S4 D4 C4 +v + 2I o’/3
C4 Vi /2
- -
Fig. 9.16 Topological state and main waveforms for the third commutation time interval
(B) Commutation of Switches S2 and S3

The two more critical commutations take place when the inner switches (S2 or S3)
are turned off.
First analyzing the commutation of switch S2 that starts at the instant it is gated
off. The converter topological state for this time interval is shown in Fig. 9.17.
Before the beginning of this commutation, capacitor C2 is discharged and capacitors
C3 and C4 are both charged with voltages equal to +Vi/4.
At the instant the switch S2 is turned off, capacitor C2 starts to charge and its
voltage rise towards +Vi/2 in a resonant way. Simultaneously, the capacitors C3 and
C4 also discharge in a resonant way. If, by the end of the dead time, the voltage in
capacitor C2 does not reach Vi/2, the soft commutation is not achieved.
This commutation time interval and its main waveforms are presented in
Fig. 9.17.
The voltage across capacitor C2 evolves according to Eq. (9.29) during this time
interval
Lr 0
vC2 ðtÞ ¼ I sen ðxo tÞ ð9:29Þ
1:5 C o
where xo ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi
1
.
1:5Lc C
In order to complete the charge of the capacitor C2 and consequently achieve the
desired commutation under zero voltage, the following constraint must be satisfied:
rffiffiffiffiffiffiffiffiffiffiffiffiffi
Lc Vi
I0o ð9:30Þ
1:5 C 2
S1 D1 C1 + + vg1 dead
time
vC1 Vi /2
- DC1 - vg2 t
vg3
S2 D2 C2 + +
vC2
- vo' vg4
a Lc
Io' b
vs2
S3 D3 C3 + iLc Vi/2
vC3 iS2
- DC2 - Io’
iC2
S4 D4 C4 + + 2I o’/3
vC4 Vi /2
- -
Thus, the minimum necessary load current reflected to the transformer primary
winding is
Vi 1:5 C
I0o crit ¼ ð9:31Þ
2 Lc
A similar commutation takes place in the second half of the switching period,
between time interval Δt6 and Δt7, described in Sect. 9.2. The time diagram, the
relevant waveforms and topological state for the commutation time interval are
shown in Fig. 9.18.
S1 D1 C1 + vg1
+v Vi /2
dead
time
C1
- DC1 -
vg2 t
S2 D2 C2 +v + vg3
C2
- vo'
a Lc vg4
Io' b
S3 C3 iLc
D3 +v vs3
Vi/2
-
C3
DC2 - iS3
Io’
iC3
S4 D4 C4 +v +
C4 Vi /2 2I o’/3
- -
Fig. 9.18 Topological state and main waveforms for the fourth commutation time interval
The commutation process or the voltage transition across the switch ends after a
time interval given by Eq. (9.31) that was deduced in the previous chapter, for the
FB-ZVS-PWM dc-dc converter. The same equation is valid for the TL-ZVS-PWM
converter, as long as we substitute equivalent capacitance Ceq = 2C with Ceq ¼ 3C2.
rffiffiffiffiffiffiffiffi
rffiffiffiffiffiffiffiffiffiffiffiffi
p 1 Vi 3C 3 CLc
Dt ¼ cos ð9:32Þ
2 2 I0o crit 2 Lc 2
The dead-time td between the gate signals must be longer than Dt to prevent
short circuit. Thus,
td Dt: ð9:33Þ

In this section it will be presented a simplified design methodology and an example

of the converter commutation parameters, using the analysis results obtained in the
previous sections. The specifications for this illustrative exercise are shown in
Table 9.1.
Let us begin by selecting a static gain q = 0.8. Thus, the output DC voltage
referred to the primary side of the transformer (V0o ) is:
Vi
V0o ¼ q ¼ 200 0:8 ¼ 160 V
2
The transformer turns ratio (n) is:
V0o 160
n¼ ¼ ¼ 3:2
Vo 50

specifications
The nominal load current reflected to the transformer primary winding is:
Io 10
I0o ¼ ¼ ¼ 3:125 A
n 3:2
Let us consider a duty-cycle reduction I0o of 10%. Hence, the inductance of the
series inductor Lc may be determined as follows:
I0o ðVi =2Þ 0:1 200

Lc ¼ ¼ ¼ 40 106 H
4 f s I0o 4 40 103 3:125
Let C = 222 pF (capacitances of the commutation capacitors associated in

parallel with the switches). Thus, the minimum load current reflected to the
transformer primary winding, necessary to achieve soft commutation of the inner
switches S2 and S3 is:
rffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Vi 1:5 C 1:5 222 1012
I0o crit ¼ ¼ 200 ¼ 0:577 A
2 Lc 40 106
This current is 18.6% of the rated current, and it transfers 93 W to the load. This
is the minimum load power necessary to achieve full realization of the ZVS
commutation.
The nominal duty-cycle is given by
V0o 160
Dnom ¼ þ I0o ¼ þ 0:1
Vi =2 200
Hence,
Dnom ¼ 0:9
The effective duty-cycle is
Def ¼ Dnom I0o ¼ 0:9 0:1 ¼ 0:8
The dead-time is given by

rffiffiffiffiffiffiffiffiffiffiffiffi
p 1 Vi 3C 3 CLc
td cos
2 2 I0o crit 2 Lc 2
Thus,
" sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!#rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
p 400 3 222p 3 222p 40l
td cos1
2 2 0:577 2 40l 2
td 181:3 ns
The design example of the Three-Level ZVS-PWM converter shown in Fig. 9.19
was simulated to validate the analysis presented in Sect. 9.5, with a dead time of
200 ns. Figure 9.20 presents the AC voltage vab and the output voltage v0o and the
inductor current. As it may be observed, the inductor current linear time intervals
make the rectifier diodes be short circuited (v0o = 0), decreasing the effective duty
cycle.
Table 9.2 presents theoretical and simulated parameters component stresses,
validating the mathematical analysis.
The commutation of switches S1 and S2, for the nominal power, are presented in
Figs. 9.21 and 9.23, respectively. A detail of the switches S1 and S2 turn off are
presented in Figs. 9.22 and 9.24. As it may be observed soft commutation is
achieved for both switches, and the inner switches S2 and S3 have a more critical
commutation due to the dead time.
A detail of the switch S2 turn off at the critical power is presented in Fig. 9.25.
As it may be observed ZVS commutation is on its limit.
Fig. 9.19 Simulated

converter S1 D1 C1 +
Vi /2
DC1 -
S2 D2 C2 +
vo'
a Lc
Io' b
S3 C3 iLc
D3
DC2 -
S4 D4 C4 +
Vi /2
-
1
vg1 vg2
1
vg4 vg3
200
vab
iLr x 50
0
-200
200
vo◊
ΔT
0
-200
0.90 0.91 0.92 0.93 0.94 0.95
Time (ms)
Fig. 9.20 Three-level ZVS-PWM converter simulation waveforms: switches drive signals,
voltages vab and v0o , and current iLc, for nominal power

simulated results
V0o (V) 160 159.9
iS14 RMS (A) 1.99 1.99
iS23 RMS (A) 2.12 2.12
ID1234 (A) 0.04 0.036
Po (W) 500 499.9
1
vg4 vg1
vS1
200
100
iS1 x 20
0
0.922 0.930 0.938

Time (ms)
current at switch S1
1
vg1
vg4
0
200
vS1
100 iS1 x 20
0
2
iC1
1
0.9355 0.9360 0.9365

Time (ms)
Fig. 9.22 A detail of switch S1 turn off at nominal power: S1 and S4 drive signals, voltage and
1
vg2 vg3
td
vS2
200
100
iS2 x 20
0
0.922 0.930 0.938

Time (ms)
Fig. 9.23 Switch S2 soft commutation at nominal power: S2 and S3 drive signals voltage and
current at switch S2
1
vg2 vg3
td
0
200
vS2
100 iS2 x 20
0
2
iC2
1
0.9368 0.9372 0.9376

Time (ms)
Fig. 9.24 A detail of switch S2 turn off at nominal power: S2 and S3 drive signals, voltage and
9.7 Problems 267
1
vg2 vg3
td
200
iS2 x 200 vS2
100
0.9368 0.9372 0.9376

Time (ms)
Fig. 9.25 A detail of switch S2 turn off at the ZVS commutation limit: S2 and S3 drive signals,
voltage and current at switch S2
9.7 Problems
(1) The three-level NPC ZVS-PWM converter with an inductive output filter, along
with its gate drive signals, is shown in Fig. 9.26. The converter has the fol-
lowing specifications:
Vi ¼ 800 V Np ¼ 3Ns f s ¼ 20 103 Hz Lo ¼ 200 lH Co ¼ 20 lF

Ro ¼ 2XLc ¼ 120 lH DT ¼ 15 ls
S1 D1 C1 +
Vi /2 Lo io vg1 ΔT
DC1 -
b +
S2 D2 C2 .T. vg2 t
Np Ns Co Ro Vo
Lc vg3
a
vg4 ΔT
S3 C3 iLc
D3 -
DC2 Ts/2 Ts
S4 D4 C4 +
Vi /2
-
Fig. 9.26 Three-level NPC ZVS-PWM converter

Assuming that all components are ideal, calculate:

(a) The output voltage Vo, the output current Io and the output power Po;
(b) The output inductor current ripple;
(c) The duty-cycle loss.
Answers: (a) Vo = 52 V, Io = 26 A, and Po = 1361 W; (b) ΔILo = 4 A;
(c) ΔD = 0.21
(2) The converter shown in Fig. 9.26 has commutation capacitors equal to
C = 4 nF and large inductance of inductor Lo, so that its current ripple can be
neglected. Calculate:
(a) The commutation time interval for switches S1 and S4;
(b) The commutation time interval for switches S2 and S3;
(c) The dead time to ensure soft commutation.
Answers: (a) Δt1 = 276 nS; (b) Δt2 = 281 ns; (c) td 281 µs.
(3) For the same converter and parameters of exercise 2:
(a) Considering that ZVS commutation must be realized, determine the maximum
value of resistance Ro and the output voltage and power on this condition;
(b) Simulate the converter and verify your results.
Answers: (a) Ro max = 8.36 Ω; Vo = 71 V; Po = 602 W.
(4) The three-level NPC ZVS-PWM with a capacitive output filter, with its gate
drive signals, is shown in Fig. 9.27. Consider all components ideal.
(a) Describe the converter operation, representing the topological states and the
main waveforms;
(b) Obtain the static gain equation and compare with the static gain of the FB
ZVS-PWM with a capacitive output filter studied in chapter VII;
(c) Simulate the converter and verify your results.
S1 D1 +
Vi /2
DC1 - vg1 ΔT
b +
T Io
S2 D2 .. vg2 t
Np Ns Co Ro Vo
a Lc vg3
S3 iLc vg4 ΔT
D3 -
DC2
Ts/2 Ts
S4 D4 +
Vi /2
-
Fig. 9.27 Three-level NPC ZVS-PWM converter with output capacitive filter
9.7 Problems 269
S1 D1 +
Vi /2
- td=100ns
DC1 S1
b +
Io
S2 D2 .T. S2 t
Np Ns Co Ro Vo
Lr Cr
a + - S3
S3 iLr S4
D3 -
DC2
Ts/2 Ts
S4 D4 +
Vi /2
-
Fig. 9.28 Three-level NPC series resonant converter
(5) The converter shown in Fig. 9.27 has the following parameters:
Vi ¼ 800 V Vo ¼ 200 V Np ¼ Ns
f s ¼ 50 103 Hz Lc ¼ 30 lH DT ¼ 8 ls
Calculate the value of the load current Io.

Answer: Io = 27.7 A
(6) A Three-level NPC Series Resonant converter, with its gate drive signals and
ideal components, is shown in Fig. 9.28. The converter operates with a constant
switching frequency and has the following parameters:
Vi ¼ 800 V Np ¼ Ns Cr ¼ 52:8 nF Lr ¼ 12 lH Ro ¼ 20 X Co ¼ 10 lF
(a) Calculate the load voltage Vo, the output power Po, the resonant capacitor peak
voltage Vcr peak and the peak value of the current in the inductor Lr;
(d) Describe the converter’s operation, by representing the topological states and
the main waveforms over a switching cycle.
Answers (a) Vo = 400 V, Po = 8 kW, Vcr peak = 473.61 V, ILr peak = 31.416 A.
Reference
1. Pinheiro, J.R., Barbi, I.: The Three-Level ZVS-PWM DC-to-DC converter. IEEE Trans. Power
Electron. 8(4), 486–492 (1993)
Chapter 10
Asymmetric Half-Bridge ZVS-PWM
Converter
Nomenclature
Vi Input dc voltage
Vo Output dc voltage
Po Output power
q Static gain
D Duty cycle
Ts Switching period
td Dead time
T Transformer
v0o (V0o ) Output DC voltage referred to the transformer primary
side, and its average value
Ce1, Ce2 DC bus capacitors
Ceq Equivalent DC bus capacitors (Ceq = Ce1 + Ce2)
vCe1, vCe2 (VCe1, VCe1) DC bus capacitors voltage and its average value
ΔvCeq Equivalent DC bus capacitors voltage ripple
io Output current
I0o Average output current referred to the primary side of the
transformer
I0o crit Critical average output current referred to the primary
side of the transformer
I1 Magnetizing inductance current at the end of time
interval 1
I2 Magnetizing inductance current at the end of time
interval 4
S1 and S2 Switches

272 10 Asymmetric Half-Bridge …
IS1 and IS2 Switches commutation current, respectively

vg1 and vg2 Switches S1 and S2 gate signals, respectively
D 1, D 2 Diodes in anti-parallel to the switches (MOSFET—
intrinsic diodes)
C1, C2 Capacitors in parallel to the switches (MOSFET—intrin-
sic capacitors)
C Capacitance in parallel to the switches C = C1 = C2
Lc Commutation inductance
vLc Commutation inductor voltage
iLm Transformer magnetizing inductance current
ILm Transformer magnetizing inductance average current
ΔiLm Transformer magnetizing inductance current ripple
vS1, vS2 Voltage across the switches
iS1, iS2 Current on the switches
iC1, iC2 Current in the capacitors
Δta Time interval of the first and second step of operation
Δtb Time interval of the fourth and fifth step of operation
Δtc Time interval of the third second step of operation
Δtd Time interval of the sixth step of operation
IS1 RMS IS1RMS Switch S1 RMS current and its normalized value

IS2 RMS IS2RMS Switch S2 RMS current and its normalized value
10.1 Introduction
The conventional half-bridge converter topology is widely used in middle power

level applications, due to its simplicity. Just as the double-ended forward converter,
it subjects the power switches to only the DC-bus input voltage and not twice that
as the singled forward converter. Its major advantage over the double-ended for-
ward converter is its symmetric operation, which means basically that the trans-
former average magnetizing current is zero.
However, despite these well-known advantages, the power switches commutate
under hard-commutation, which implies in commutation losses and reduction of the
converter efficiency.
To provide soft-commutation under ZVS in the half-bridge converter, the
asymmetric (complementary) control was proposed to achieve ZVS operation for
both switches [1]. Two drive signals are complementarily generated and applied to
the power switches so that they may be turned on at ZVS conditions due to the fact
C1 D1 S1 Lo io
Ce1 +
Lc
+ b a c T
..
Vi iLc
- C2 D2 S2 Co Ro Vo
Ce2
Fig. 10.1 Asymmetric half-bridge ZVS-PWM converter
that the transformer leakage inductance primary charges and discharges the com-
mutation capacitances.
The asymmetric half bridge ZVS-PWM converter is shown in Fig. 10.1.
The DC bus capacitors Ce1 and Ce2 have different DC voltages due to the
asymmetric drive signals. It will be shown later that the voltages across these
capacitors are given as a function of the duty-cycle D, by Eqs. (10.1) and (10.2),
respectively.
VCe2 ¼ D Vi ð10:1Þ
VCe1 ¼ ð 1 DÞ Vi ð10:2Þ
The converter will be analyzed for 0 D 0.5, because its behavior is the
same for 0.5 D 1.
In this section, it will be described the operation of the half-bridge converter shown
in Fig. 10.2. To simplify, it will be assumed that:
• all components are ideal;
• the converter operates on steady-state condition;
Fig. 10.2 Asymmetric

half-bridge ZVS-PWM S1
converter Ce1 + D1
-
Lm iLm
a
+ b
Vi iLc
- +
vo' Lc S2
Ce2 +
Io' D2
-
-

during time interval Δt1 S1
Ce1 + D1
-
Lm iLm
a
Vi + b
iLc
- +
vo' Lc S2
Ce2 +
Io' D2
-
-
• the output filter is replaced by a DC current source I0o , whose value is the output
average current referred to the primary winding of the transformer;
• The converter is controlled by asymmetric pulse width modulation (PWM);
• The magnetizing inductance is large enough so that its current ripple can be
neglected.
The operation of the converter is described over a switching cycle, which is
divided into six time intervals, each one representing a different topological state.
At t = t0, when switch S2 is turned off, diode D1 starts to conduct, as shown in
Fig. 10.3. During this time interval energy is returned to the DC bus. The voltage vab
is equal to +VCE1 and the inductor current increases linearly until it reaches zero.
This time interval, shown in Fig. 10.4, begins at the instant the commutation
inductor current reaches zero. At this instant the switch S1 starts to conduct and the
inductor current iLc increases linearly until it reaches +I0o +iLm.
The topological state for the time interval Δt3 is shown in Fig. 10.5. This time
interval starts at t = t2, when the inductor current reaches +I0o +iLm. Switch S1
conducts the current, the voltage vab is equal to VCe1 and energy is transferred from
the DC bus to the load. This time interval ends when switch S1 is turned off and
switch S2 is turned on.

Ce1 + D1
-
Lm iLm
a
+
Vi b
iLc
- +
vo' Lc S2
Ce2 +
Io' D2
-
-

Ce1 + D1
-
Lm iLm
a
+ b
Vi iLc
- +
vo' Lc S2
Ce2 +
Io' D2
-
-

Ce1 + D1
-
Lm iLm
a
+
Vi b
iLc
- +
vo' Lc S2
Ce2 +
Io' D2
-
-

At t = t3 switch S1 is turned off and diode D2 starts to conduct the current, as shown
in Fig. 10.6. Once again, the commutation inductor delivers energy to the DC bus.
The voltage vab is equal to −VCe2 and the inductor current iLc decreases linearly and
reaches zero at the instant t = t4.
This time interval, shown in Fig. 10.7, begins at the instant t4, when the commu-
tation inductor current reaches zero. At this instant switch S2 starts to conduct and
the inductor current decreases linearly.
The topological state for the time interval Δt6 is shown in Fig. 10.8. It starts at t5
when the inductor current reaches −I0o +iLm−. Switch S2 conducts the current, the

Ce1 + D1
-
Lm iLm
a
+
Vi b
iLc
- +
vo' Lc S2
Ce2 +
Io' D2
-
-

Ce1 + D1
-
Lm iLm
a
+ b
iLc
- +
vo' Lc S2
Ce2 +
Io' D2
-
-
voltage vab is equal to −VCe2 and energy is transferred from the DC bus to the load.
This time interval ends at t6, when switch S2 is turned off and switch S1 is gated on.
The main waveforms along with the time diagram, over a switching cycle, are
shown in Fig. 10.9.
vg1 TS
(1-D) T S
vg2 t
vab D TS
VCe1
-VCe2
vo’
VCe1
VCe2
iLc
Io’
-Io’
iLm
IL m
vS1
Vi
iS1
vS2
Vi
iS2
t0 t1t2 t3 t4 t5 t6
Fig. 10.9 Main waveforms and time diagram of the asymmetric half-bridge ZVS-PWM converter
(A) Output Characteristics

During the time intervals Dta and Dtb , as shown in Fig. 10.10, the inductor current
varies linearly, the voltage at the output of the rectifier stage is zero so no power is
transferred to the load. As the voltage applied to the inductor is asymmetric, the
rates of the inductor current iLc are unequal in the two time intervals.
During the time interval Δta the inductor Lc is subjected to the voltage given by
Eq. (10.3).
vLc ¼ ð1 DÞ Vi ð10:3Þ
The duration of this time interval is
2 I0o Lc
Dta ¼ ð10:4Þ
ð1 DÞ Vi
In a similar way, the voltage across the inductor Lc during the time interval Dtb is
given by
vLc ¼ D Vi ð10:5Þ
and the duration of this time interval is
2 I0o Lc
Dtb ¼ ð10:6Þ
D Vi
vLc
(1-D)Vi
-DVi t
iLc Δta Δtb

Io’+iLm
-(Io’+iLm)
Vo’
(1-D)Vi
DVi
D Ts
Ts
Fig. 10.10 Voltage and current in the inductor Lc and voltage at the output of the diode rectifier
The average value of the output voltage is determined by

2 3
ZD Ts ZTs
1 6 7
V0o ¼ 4 ð 1 DÞ Vi dt þ D Vi dt5 ð10:7Þ
Ts
Dta D Ts þ Dtb
Integrating Eq. (10.7) yields
1
V0o ¼ fð1 DÞVi ðD:Ts Dta Þ þ D Vi ½ð1 DÞ Ts Dtb g ð10:8Þ
Ts
With appropriate algebraic manipulation, the DC voltage gain can be found by

Eq. (10.9).

V0o 4 I0o Lc f s
q¼ ¼ 2Dð1 DÞ ð10:9Þ
Vi Vi
The duty cycle loss, defined by Eq. (10.18), is proportional to the output current.
4 I0o Lc f s
I0o ¼ ð10:10Þ
Vi
After substituting Eq. (10.10) into (10.9) we find the static gain given by
q ¼ 2 Dð1 D) I0o ð10:11Þ
The asymmetric half bridge ZVS-PWM converter output characteristics (static

gain as a function of the normalized output current, taking the duty cycle as a
parameter) are shown in Fig. 10.11. As it may be noticed, the average output
voltage (V0o ) depends on the load current (I0o ) as occurred with converters already
studied in the previous chapters.
The half bridge ZVS-PWM converter conversion ratio, considering Lc = 0, is
shown in Fig. 10.12. As there are two duty-cycle values for a given static gain, it is
usually limited to D = 0.5.

characteristics of the q
half-bridge ZVS-PWM
converter 0.4 D = 0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
I o’
Fig. 10.12 Voltage transfer 0.6

characteristics of the q
half-bridge ZVS-PWM
0.5
converter
0.4
0.3
0.2
0.1
0
0 0.2 0.4 0.6 0.8 1.0
D
(B) Magnetizing Inductance Average Current

Due to the asymmetric operation, the magnetizing inductance average current is not
zero and the transformer operates with magnetic flux bias, like occurs with all
asymmetric isolated dc–dc converters.
Figure 10.14 shows the typical waveform of the magnetizing inductance current
on steady-state condition for the asymmetrical half-bridge PWM converter pre-
sented in Fig. 10.13.
It was already demonstrated that the time intervals Dta and Dtb are determined by
Eqs. (10.12) and (10.13), respectively.
Fig. 10.13 Asymmetrical

half-bridge ZVS-PWM
+
S1
converter (1-D)Vi - D1
ILm
b a
iLc
Lc
+ S2
DVi - D2
Io´
2 Lc I0o
Dta ¼ ð10:12Þ
ð1 DÞVi
2 Lc I0o
Dtb ¼ ð10:13Þ
D Vi
Defining
2 Lc I0o
Dtc ¼ D Ts Dta ¼ D Ts ð10:14Þ
ð1 DÞ Vi
and
2 Lc I0o
Dtd ¼ ð1 DÞTs Dtb ¼ ð1 DÞ Ts ð10:15Þ
D Vi
The average value of the current iLc , as shown in Fig. 10.14 is determined by
Dtd Dtc
ILc ¼ I0o ð10:16Þ
Ts
After substitution of Eqs. (10.14) and (10.15) in Eq. (10.16), and knowing that
the average value of the magnetizing current ILm is equal to ILc , we find

2 Lc f s I0o
ILm ¼ I0o ð1 2 DÞ 1 ð10:17Þ
Vi D ð1 DÞ
As may be noticed in (10.17), the magnetizing inductance average current is zero

only when the duty cycle is 0.5, condition in which the converter is on symmetrical
operation. If the commutation inductance (Lc) is neglected, ILm ¼ I0o ð1 2 DÞ.
Ts
vg1
(1-D) Ts t
D Ts
vg2
t
Δta Δtc Δtb Δtd
iLc
Io’
-Io’
iLm
Fig. 10.14 Waveforms for analysis of the magnetizing current
(C) Switches RMS Current

According to the definition, the switches S1 and S2 RMS currents are determined by
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u ZD Ts
u 2
u1
IS1RMS ¼t 2 ð1 DÞ I0o dt ð10:18Þ
Ts
0
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u ð1DÞ Ts
u Z
u1 2
IS2RMS ¼t 2 D I0o dt ð10:19Þ
Ts
0
After integration and appropriate algebraic manipulation, Eqs. (10.20) and

(10.21) can be found
IS1RMS pffiffiffiffi
IS1RMS ¼ 0 ¼ 2 ð1 DÞ D ð10:20Þ
Io
IS2RMS pffiffiffiffiffiffiffiffiffiffiffiffi
IS2RMS ¼ 0 ¼ 2D 1 D ð10:21Þ
Io
The switches S1 and S2 RMS currents, as a function of the duty cycle, are plotted
in Fig. 10.15. The maximum RMS current for switch S1 takes place when the duty
cycle is 0.333 and for switch S2 when the duty cycle is 0.667. If the converter
operates with D = 0.5, the switches RMS currents become identical.
Fig. 10.15 Switches S1 and 0.8

S2 RMS currents, as a
function of the duty cycle (D) iS1RMS iS2RMS
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0
D
In this section, the capacitors are added in parallel to the switches and a dead time is
considered, so the soft commutation phenomenon may be analyzed. Four com-
mutation time intervals are added to one switching period.
Due to the converter asymmetrical operation, the commutations take place under
different conditions.
10.4.1 Switch S1 Commutation
The first commutation starts at the instant switch S1 is turned off and switch S2 is not
turned on yet (dead time). It has one linear time interval, followed by a resonant one,
as shown in Fig. 10.16. In the linear time interval, the inductor current is I0o , and
capacitors C1 and C2 are charged/discharged in a linear way, until capacitor C1
reaches the voltage (1 − D) Vi leading vab to zero. When vab reaches zero, the output
rectifier is short circuited and the resonant time interval begins, with the inductor
current and the capacitors voltage evolving in a resonant way, until the capacitor C2
is completely discharged.
(A) Linear Time Interval (Dt1a)
The peak value of the magnetizing inductance can be mathematically expressed as
DiLm
I1 ¼ ILm þ ð10:22Þ
2
(a) vg1 dead

time
S1 vg2 t
Ce1 + C1 D1
- vab
Lm iLm
+ b a (1-D) Vi
Vi iLc
- + vs1
vo' Lc S2 (1-D) Vi
Ce2 + C2
Io' D2 IS1 iS1
-
- iC1
IS1 /2
Δt1a
(b) vg1 dead
time
S1
Ce1 + C1 D1 vg2 t
-
Lm iLm vab
+ b a (1-D) Vi
Vi iLc
- + vs1
vo' Lc S2 Vi
Ce2 + C2
Io' D2 IS1 iS1
-
- iC1
IS1 /2
Δt1b
Fig. 10.16 Topological state and main waveforms for the switch S1 commutation: a linear time
interval and b resonant time interval
where the value of DiLm is given by
Vi
DiLm ¼ Dð1 DÞ ð10:23Þ
2Lm f s
The average value of the magnetizing current is

2 Lc f s I0o
ILm ¼ I0o ð1 2DÞ 1 ð10:24Þ
Vi D ð1 DÞ
The current in switch S1 at the instant of the commutation is mathematically

represented by
IS1 ¼ I0o þ I1 ð10:25Þ
Substitution of Eqs. (10.22), (10.23) and (10.24) in Eq. (10.25) yields

2 Lc f s I0o
IS1 ¼ I0o þ I0o ð1 2 D Þ 1
Vi Dð1 DÞ
Vi
þ D ð1 DÞ ð10:26Þ
2 Lm f s
During the commutation linear time interval, the switch S1 voltage evolves from
zero to (1 − D) Vi. The duration of this time interval is
Cð1 DÞVi
Dt1a ¼ ð10:27Þ
IC1
where IC1 is IS1/2 and C = C1 = C2.

(E) Resonant Time Interval (Dt1b)
The equivalent circuit for the resonant time interval is presented in Fig. 10.17.
The initial conditions are: iLc(0) = IS1, vC1(0) = (1 – D)Vi and vC2(0) = DVi.
The state plane trajectory for this resonant time interval is shown in Fig. 10.18.
The radius of the semi-circle, the characteristic impedance and the angular
frequency are given by Eqs. (10.28), (10.29) and (10.30), respectively.
R1 ¼ z IS1 ð10:28Þ
Lc
z¼ ð10:29Þ
2C

for the resonant time interval +
(1-D)Vi +
-
C1
-
Lc iLc
+ +
DVi - C2
-

the resonant time interval
DVi
φ1 vC
Δt1b
R1
z IS1
1
x ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð10:30Þ
2 C Lc
Substitution of Eq. (10.26) in (10.28) gives

DiLm
R1 ¼ z I0o þ ILm þ ð10:31Þ
2
By inspection, from Fig. 10.18 we can write
x Dt1b þ /1 ¼ p=2 ð10:32Þ
Thus

1 D Vi
/1 ¼ cos ð10:33Þ
R1
And
( " #)
1 p 1 D Vi
Dt1b ¼ cos ð10:34Þ
x 2 z I0o þ ILm þ DiLm =2
The duration of the commutation is
Dt1 ¼ Dt1a þ Dt1b ð10:35Þ
Hence, the dead time must satisfy the constraint
td1 Dt1a þ Dt1b ð10:36Þ
10.4.2 Switch S2 Commutation
In a similar way, the second commutation starts at the instant switch S2 is turned off
and switch S1 is not turned on yet (dead time). It also has one linear time interval,
followed by a resonant time interval, as shown in Fig. 10.19. In the linear time
interval, the inductor current is I0o , and capacitors C1 and C2 are discharged/charged
in a linear way, until capacitor C2 reaches the voltage DVi leading vab to zero.
When vab reaches zero, the output rectifier is short circuited and the resonant time
interval begins, with the inductor current and the capacitors voltage evolving in a
resonant way, until capacitor C1 is completely discharged. At the resonant time
interval, the magnetizing inductance current is subtracted from the load current, so
the commutation process takes longer compared to the switch S1 commutation.
(a) vg1 dead

time
S1
Ce1 + C1 D1 vg2 t
-
Lm iLm vab
+ b a
Vi iLc -D Vi
- + vs2
vo' Lc S2
Ce2 + C2 DVi
Io' D2
- IS2 iS2
-
iC2
IS2 /2
Δt2a
(b) vg1 dead

time
S1 vg2 t
Ce1 + C1 D1
-
Lm iLm vab
+ b a
Vi iLc -D Vi
- + vs2
vo' Lc S2 Vi
Ce2 + C2
Io' D2 IS2
- iS2
- iC2
IS2 /2
Δt2b
Fig. 10.19 Topological state and main waveforms for the switch S2 commutation: a linear time
interval and b resonant time interval
(A) Linear Time Interval (Dt2a)

The magnetizing current at the instant of the commutation can be mathematically
expressed as
DiLm
I2 ¼ ILm ð10:37Þ
2
The switch current at the same instant is

DiLm
IS2 ¼ I0o I2 ¼ I0o ILm ð10:38Þ
2
Hence,

2 Lc f s I0o
IS2 ¼ I0o I0o ð1 2 DÞ 1
Vi Dð1 DÞ
Vi
þ Dð1 DÞ ð10:39Þ
2 Lm f s
During the commutation linear time interval, switch S2 voltage evolves from
zero to (D Vi). The duration of this time interval is
C D Vi
Dt2a ¼ ð10:40Þ
IC2
where IC2 is IS2/2.

(B) Resonant Time Interval (Dt2b)
The equivalent circuit for the resonant time interval is presented in Fig. 10.20.
The initial conditions are: iLc(0) = IS2, vC1(0) = (1 − D)Vi and vC2(0) = DVi.
The state plane trajectory for this resonant time interval is shown in Fig. 10.21.
The radius of the semi-circle is given by Eq. (10.41).
R2 ¼ z IS2 ð10:41Þ
Thus,

DiLm
R2 ¼ z I0o ILm þ ð10:42Þ
2
For the realization of the soft-commutation, the radius R2 must satisfy the
constraint

for the resonant time interval +
(1-D)Vi +
-
C1
-
Lc iLc
+ +
DVi - C2
-

the resonant time interval
(1-D) Vi
φ2 vC
Δt2b
R2
z IS2
R2 ð1 DÞVi ð10:43Þ
Substituting Eq. (10.42) into (10.43) yields

DiLm
z I0o ILm ð1 DÞVi ð10:44Þ
2
As Is2 < Is1 the switch S2 commutation is the critical one.

Appropriate manipulation of Eq. (10.44) gives

ð1 DÞVi DiLm
I0o min ¼ þ ILm ð10:45Þ
z 2
where I0o min is the minimum load current referred to the transformer primary
winding, that ensures switch S2 soft commutation.
By inspection of the graphic shown in Fig. 10.21 we can write
x Dt2b þ /2 ¼ p=2 ð10:46Þ
Thus

1 ð1 DÞVi
/2 ¼ cos ð10:47Þ
R2
Substitution of (10.47) into (10.46) gives

p ð1 DÞVi
x Dt2b ¼ cos1 ð10:48Þ
2 R2
Hence,
8 2 39
<
1 p ð1 DÞ Vi 5=
Dt2b ¼ cos1 4 ð10:49Þ
x :2 I0o ILm þ Di2Lm ;
The duration of the commutation is
Dt2 ¼ Dt2a þ Dt2b ð10:50Þ
The dead-time must satisfy the constraint
td2 Dt2 ð10:51Þ


In this section a design methodology and an example are presented according to the
mathematical analysis presented in the previous sections. The converter is designed
according to the specifications shown in Table 10.1.
Considering a transformer turns ratio (n) of 3.2, the output current (I0o ) and the
output voltage (V0o ), both referred to the primary side of the transformer are cal-
culated as follows.
Io 10
I0o ¼ ¼ ¼ 3:125 A
n 3:2
V0o ¼ Vi n ¼ 50 3:2 ¼ 160 V
The static gain is
V0o 160
q¼ ¼ ¼ 0:4 V
Vi 400
Considering a duty cycle reduction of 5%, the commutation inductor is given by.
I0o Vi 0:05 400

Lc ¼ ¼ ¼ 40 lH
4 f s I0o 4 40 103 3:125
The nominal duty cycle is calculated using Eq. (10.19).

1 Vi 8 I0o Lc f s 2 Vi q
Dnom ¼ ¼ 0:342
2 4 Vi
The DC Bus capacitors average voltages are:
VCe1 ¼ Vi ð1 Dnom Þ ¼ 263:25 V

VCe2 ¼ Vi Dnom ¼ 136:75 V
The magnetizing inductance average and ripple current are determined by

Eqs. (10.17) and (10.23), respectively

specifications
2Lc f s I0o
ILm ¼ ð1 2 Dnom ÞI0o 1 ¼ 0:878 A
Vi Dnom ð1 Dnom Þ
Vi
DiLm ¼ Dnom ð1 Dnom Þ ¼ 0:562 A
Lm f s
Considering the commutation capacitance C = C1 = C2 = 4 pF, switch S1

commutation current and commutation time interval are calculated as follows:
1
x ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 5:59 106 rad=s
2 C Lc
Lc
z¼ ¼ 223:6
2C
0
I þ ILm þ DiLm =2
IS1 ¼ 2 IC1 ¼ 2 o ¼ 4:285 A
2
Cð1 Dnom Þ Vi
Dt1a ¼ ¼ 49:15 ns
I
( C1 " #)
1 p 1 D Vi
Dt1b ¼ cos ¼ 25:62 ns
x 2 z I0o þ ILm þ DiLm =2
Dt1 ¼ Dt1a þ Dt1b ¼ 74:77 ns
Switch S2 commutation current and commutation time interval are:

I0o ILm þ DiLm =2
IS2 ¼ 2 IC2 ¼ 2 ¼ 2:528 A
2
Cð1 Dnom Þ Vi
Dt2a ¼ ¼ 43:28 ns
I
( C2 " #)
1 p ð 1 D ÞV
cos1 0
nom i
Dt2b ¼ ¼ 86:66 ns
x 2 z Io ILm þ DiLm =2
Dt2 ¼ Dt2a þ Dt2b ¼ 129:9 ns
The minimum dead time is equal to Δt2.
tdmin ¼ Dt2 ¼ 129:9 ns
The design example of the asymmetrical half bridge ZVS-PWM converter, shown
in Fig. 10.22, is simulated to validate the analysis presented in Sect. 10.5, with a
dead time of 150 ns. Figure 10.23 presents the main waveforms for the nominal
power. As it may be noticed, capacitor Ce1 and Ce2 average voltages are different,
due to the asymmetry.
S1
Ce1 + C1 D1
-
Lm iLm
+ b
a
Vi iLc
- +
vo' Lc S2
Ce2 + C2
Io' D2
-
-
vab
200
-200
vo◊
200
-200
300
vCe1
200
vCe2
100
0
4
2
iLc
0
-2
-4
2
iLm
1
0
9.90 9.92 9.94 9.96
Time (ms)
Fig. 10.23 Asymmetrical half bridge ZVS-PWM converter simulation waveforms: voltages vab,
V0o , VCe1 and VCe2 and currents iLc and iLm, for nominal power

simulated results
V0o [V] 160 161.6
iS1 RMS [A] 2.40 2.26
iS2 RMS [A] 1.73 1.75
VCe1 [V] 263 263.2
VCe2 [V] 137 136.8
1
vg1 vg2 td
(1-D) TS
D TS
0
400
vS1 iS1 x 10
200
0
400
vS2 iS2 x 10
200
0
9.905 9.915 9.925 9.935
Time (ms)
Fig. 10.24 Switches S1 and S2 commutation: S1 and S2 drive signals, voltage and current at the
switches
1
vg2 vg1
td
400
vS2
iS2 x 50
200
0
iC2
1
992.46 992.47 992.48 992.49 992.50 992.51

Time (μs)
Fig. 10.25 A detail of switch S2 soft commutation: S1 and S2 drive signals, voltage and current
at the switch and capacitor C2 current
Table 10.2 presents the theoretical and simulated parameters and the component
stresses, validating the mathematical analysis.
The commutation of switch S1 and S2 are presented in Fig. 10.24. The current
available for the switch S2 commutation is smaller, so this is the critical commu-
tation. A detail of the switch S2 turn off is presented in Fig. 10.25. As it may be
observed soft commutation is achieved.
10.7 Problems
(1) The asymmetrical ZVS-PWM converter with an inductive output filter is pre-
sented in Fig. 10.26. The converter has the following specifications:
Vi ¼ 400 V Np =Ns ¼ 50 V Ro ¼ 2 X f s ¼ 40 103 Hz Lo ¼ 200 lH

Co ¼ 50 lF D ¼ 0:3 Lc ¼ 10 lH Lm ¼ 2 mH
Calculate:
(a) The average output voltage Vo, the output average output current Io and the
output power Po.
(b) The average magnetizing inductance current.
(c) The average voltage in the DC Bus capacitors.
(d) The magnetizing inductance ripple current.
Answers: (a) Vo = 31.1 V, Io = 15.56 A, Po = 484 W; (b) ILm = 1.15 A;
(c) VCe1 = 230 V, VCe2 = 120 V; (d) ΔiLm = 1.05 A.
(2) Considering the asymmetrical ZVS-PWM converter presented in Fig. 10.27,
with the commutation capacitors (C1 and C2) of 2 nF and a high leakage and
magnetizing inductance, calculate the commutation time of both switches, with
the following specifications:
D1 S1 Lo io
Ce1 +
Lk
+ b a c T
..
Vi iLk
- D2 S2 Co Ro Vo
Ce2
Fig. 10.26 Asymmetrical HB ZVS-PWM converter

C1 D1 S1 Lo io
Ce1 +
Lk
+ b a c T
..
Vi iLk
- C2 D2 S2 Co Ro Vo
Ce2
Fig. 10.27 Asymmetrical HB ZVS-PWM converter
Vi ¼ 400 V Np =Ns ¼ 50 V Ro ¼ 2 X f s ¼ 40 103 Hz

Co ¼ 50 lF D ¼ 0:3 Lk ¼ 10 lH
Answers: tc1 = 252.5 ns, tc2 = 357 ns.

(3) The asymmetrical ZVS-PWM converter presented in Fig. 10.27, has the fol-
lowing parameters:
Vi ¼ 400 V Np ¼ Ns C1 ¼ C2 ¼ 0:47 nF Ro ¼ 2 X Lm ¼ 10 mH
f s ¼ 40 10 Hz 3
Ce1 ¼ Ce2 ¼ 10 lF D ¼ 0:3 Lr ¼ 20 lH
Calculate:
(a) The minimum output current (Io min) to achieve ZVS commutation on both
switches.
(b) The dead time to obtain ZVS commutation.
Answers: (a) Io min = 3.1 A; (b) td = 216 ns.
D1 S1 Lo io
+
vCr - Lr
+ a + c T
..
Vi iLr
- D2 S2 Cr Co Ro Vo
Fig. 10.28 Topological variation of the asymmetrical HB ZVS-PWM converter

10.7 Problems 295
(4) A topological variation of the asymmetrical ZVS-PWM is presented in

Fig. 10.28. The converter has the following specifications:
Vi ¼ 400 V Np ¼ Ns ¼ 1 Ro ¼ 10 X f s ¼ 40 103 Hz Lo ¼ 500 lH

Co ¼ 50 lF D ¼ 0:3 Lr ¼ 20 lH Cr ¼ 10 lF Lm ¼ 20 mH
Calculate:
(a) The resonant capacitor voltage ripple.
(b) The resonant capacitor average voltage.
Answers: (a) ΔVCr = 13.64 V; (b) VCr = 120 V.
Reference
1. Imbertson, P., Mohan, N.: Asymmetrical duty cycle permits zero switching loss in PWM
circuits with no conduction loss penalty. In: IEEE, pp. 1061–1066 (1991 October)
Chapter 11
Active Clamp ZVS-PWM Forward
Converter
Nomenclature
Vi Input DC voltage
Po Output power
Co Output capacitor filter
Lo Output inductor filter
q Converter static gain
D Duty cycle
Ts Switching period
td Dead time
T Transformer
N1, N2 and N3 Transformer windings
Lc Commutation inductance (may be the transformer leakage
inductance or an additional inductor, if necessary)
iLm (ILm) Transformer magnetizing inductance current and its average
value
v0o V0o Output voltage referred to the transformer primary side and its
average value
vLm Magnetizing inductance voltage
VC3 VC3 Clamping capacitor voltage and its normalized value

I0o I0o Average output current referred to the primary and its
normalized value
ii (Ii) DC bus current and its average value
iLm (ILm) Magnetizing inductor current and its average value
ΔiLm Magnetizing inductor current ripple

298 11 Active Clamp ZVS-PWM Forward Converter
I1 Magnetizing inductor current at the end of time interval 4

I2 Magnetizing inductor current at the end of time interval 8
S1 Main switch
S2 Active clamp switch
D 1, D 2 Diodes in anti-parallel to the switches (MOSFET—intrinsic
diodes)
D 3, D 4 Output rectifier diodes
C1, C2 Capacitors in parallel to the switches (MOSFET—intrinsic
capacitors)
vab (Vab) Converter ac voltage, between points “a” and “b” and its
average value
vS1, vS2 Voltage across switches
iS1, iS2 Switches current
iC1, iC2, iC3 Capacitors current
Δt1 Time interval of the first and second step of operation (t2–t0)
Δt2 Time interval of the third and fourth step of operation (t4–t2)
Δt3 Time interval of the fifth, sixth and seventh step of operation
(t7–t4)
Δt32 Time interval of the third step of operation in CCM (t3–t2)
IS1 RMS , IS1 RMS Switch S1 RMS current and its normalized value
11.1 Introduction
The conventional forward converter is shown in Fig. 11.1. The isolating trans-
former T has an auxiliary winding (N3) to provide the transformer demagnetization.
However, the energy stored in the transformer leakage inductance (Lc) is not
removed by the auxiliary winding. To prevent overvoltage across the switch S1 at
the instant it is turned off, a passive dissipative clamping circuit (RCD) is usually
used to clamp the voltage and also to dissipate in the resistor R the energy stored in
the leakage inductances. However, it is obvious that this solution sacrifices the
efficiency of the converter.
Fig. 11.1 Power stage D2 Lo

diagram of the forward
N3 N1 . T . N2 +
converter with passive
dissipative clamping circuit D3 Co Ro Vo
+
.
-
Vi Lc
- D
D1
S1 C R
Fig. 11.2 Active clamp D3 Lo

forward converter .T . +
D4 Co Ro Vo
+
Vi -
S2 D2 Lc
- +
C3
-
S1 D1
Fig. 11.3 Active clamp D3 Lo

ZVS-PWM forward converter .T . +
D4 Co Ro Vo
+ D2 C1
Vi S2 -
- + Lc
C3
- D1
S1 C2
Figure 11.2 shows an active clamp forward converter [1]. Switch S2 and
capacitor C3 are added to the original circuit to provide the transformer demag-
netization and also to recycle the energy accumulated in the transformer leakage
inductance to the input voltage source Vi. The switch operates at constant switching
frequency with appropriate dead-time between the gate signals. The converter is
pulse-width-modulated (PWM). The efficiency of the active clamp forward con-
verter is higher than the conventional counterpart for the mentioned reasons.
If capacitors with appropriate capacitances are added in parallel to the switches
S1 and S2, as shown in Fig. 11.3, ZVS commutation may be achieved [2], con-
tributing even more to improve the converter’s efficiency. The transformer leakage
inductance is utilized in the soft commutation process and usually external
inductors are not necessary.
In this section, the converter shown in Fig. 11.4, without the capacitors in parallel
to the switches, is analyzed (the commutation analysis is presented in Sect. 11.4).
The following assumptions are made to simplify:
• all components are ideal;
• the converter operates on steady-state;
• the output filter is replaced by a DC current source I0o , whose value is the output
average current referred to the primary side of the transformer;
• The converter is controlled by pulse width modulation (PWM) without dead
time between the two switches gate pulses.
Fig. 11.4 Active clamp vo’

PWM Forward converter + -
referred to the transformer Io’
primary side
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-
The operation of the converter is described during one switching period that is
divided into eight time intervals, each one representing a different topological state
of the converter.
The time interval Δt1, shown in Fig. 11.5, starts at t = t0, when switch S1 is gated
on and switch S2 is turned off. Although switch S1 is gated on, current does not flow
through it because the DC bus current i1 is negative. Diode D1 conducts the current
and Lm is demagnetized while Lc is magnetized.
Fig. 11.5 Topological state vo’

during time interval Δt1 + -
Io’
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-

Io’
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-

Io’
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-

Io’
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-

This time interval, presented in Fig. 11.6, starts at t = t1, when the current in the DC
bus (ii) reaches zero and S1 is conducting. In this time interval Lm continues
demagnetizing and Lc magnetizing.
The time interval Δt3, shown in Fig. 11.7, begins when the commutation inductance
current reaches I0o , turning off diode D4. During this time interval Lm current
decreases linearly and the commutation inductor current is constant.
This time interval, shown in Fig. 11.8, starts at t = t3, when the magnetizing
inductance current reaches zero and increases linearly.
The time interval Δt5, shown in Fig. 11.9, starts at t = t4, when switch S2 is gated
on and switch S1 is turned off. Although switch S2 is gated on, current does not flow
through it because the DC bus current i1 is positive. Hence, diode D2 conducts the
current, beginning another time interval, in which Lm and Lc are demagnetized by
linear currents. Diode D4 shorts circuit the load.

Io’
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-

Io’
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-

Io’
D3 D4
S2
iLc D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-

Io’
D3 D4
S2
D2
Lc
a Lm
b +
C3 vC3
+ ii iLm S1 -
Vi D1
-
vg1 D TS
TS t
vg2
vab
Vi
Vi-VC3
vo’
Vi
Δt1 Δt3
iLc
Io’
Δt2
iLm
I1
ΔiLm
-I2
ii
Io’+I1
I3
-I2
iC3
Io’+I1
-I2
vS1
VC3
iS1
vS2
VC3
iS2
t0 t1 t2 t3 t4 t5 t6 t7 t8
Fig. 11.13 Main waveforms and time diagram of the active clamp forward converter

The time interval Δt6, shown in Fig. 11.10, starts at t = t5, when the magnetizing
inductor current becomes negative. The commutation inductor current increases
linearly during this time interval.
This time interval, presented in Fig. 11.11, stars at t = t6, when the current in the
DC bus (ii) reaches zero and S2 is conducting. Currents through Lm and Lc evolve
linearly.
The time interval Δt8, shown in Fig. 11.12, begins when the commutation induc-
tance current reaches zero, turning off diode D3. During this time interval Lm
current increases linearly.
The main waveforms indicating the time intervals are shown in Fig. 11.13.
(A) Capacitor C3 Average Voltage

As it can be observed in Fig. 11.13, the average value of the voltage across the
magnetizing inductance is Vab ¼ 0. This voltage is given by
2 3
ZD Ts Z Ts
ð 1DÞ
1 6 7
Vab ¼ 4 Vi dt þ ðVi VC3 Þ dt5 ¼ 0 ð11:1Þ
Ts
0 0
thus,
Vi DTs ¼ ðVi VC3 Þð1 DÞTs ð11:2Þ
and
VC3 1
VC3 ¼ ¼ ð11:3Þ
Vi 1D
where VC3 is the normalized voltage across the clamping capacitor C3.
Figure 11.14 shows VC3 as a function of the duty cycle (D).
Fig. 11.14 Normalized 10

capacitor C3 average voltage VC3
as a function of the duty cycle
8
0
0 0.2 0.4 0.6 0.8 1
D
(B) Output Characteristics

The average output voltage V0o is given by
ZDt2
1 1
V0o ¼ Vi dt ¼ Vi Dt2 ð11:4Þ
Ts Ts
0
The time intervals Dt1 and Dt2 , shown in Fig. 11.13, are given by Eqs. (11.5)
and (11.6) respectively.
Dt2 ¼ D Ts Dt1 ð11:5Þ
I0o Lc
Dt1 ¼ ð11:6Þ
Vi
V0o
q¼ ¼ D I0o ð11:7Þ
Vi
I0o Lc f s
where I0o ¼ Vi is the duty-cycle loss.
As it may be noticed in Eq. (11.7), the duty cycle loss I0o is proportional to the
average output current I0o . Figure 11.15 shows the output characteristics or the
normalized output voltage as a function of the normalized output current taking the
duty cycle as a parameter. Due to the duty cycle loss, the load voltage is dependent
on the load current.
characteristics of the clamp q

mode forward converter
0.8
D=0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
Io’
(C) Switch S1 RMS Current

Switch S1 RMS current is calculated disregarding the magnetizing inductance
current and is given by
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u Dt2
u Z
u1
IS1 RMS ¼t I02
o dt ð11:8Þ
Ts
0
Hence,
1.0
IS1 RMS
D=0.8
0.8
0.6
0.6
0.4
0.2
0.4
0.2
0
0 0.02 0.04 0.06 0.08 0.10 0.12 0.140.16
Io’
Fig. 11.16 Switch S1 RMS normalized current, as a function of the normalized output current,
taking the duty cycle as a parameter
qffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS1 RMS
IS1 RMS ¼ ¼ D I0o ð11:9Þ
I0o
The switch S1 RMS normalized current IS1 RMS , as a function of the normalized
output current, taking the duty cycle as a parameter, is shown in Fig. 11.16.
(D) Magnetizing Inductance Average Current
The forward converter operates asymmetrically. Consequently, the average mag-
netizing inductance current is not zero, as it may be noticed in the waveforms
shown in Fig. 11.17.
Applying the Kirchhoff current law to the average current of the circuit shown in
Fig. 11.4 it can be found
I1 ¼ ILc þ ILm ð11:10Þ
where I1 , ILc , and ILm are the average values of the input, commutation and mag-
netizing inductance currents.
The average commutation inductor current is obtained by inspection from
Fig. 11.17 and is given by
Dt3 Dt1
ILc ¼ I0o D þ I0o I0o ð11:11Þ
2TS 2TS
From the commutation inductor voltage equation, (11.12) may be written to

obtain Dt3 :
ð1 D Þ
Dt3 ¼ Lc I0o ð11:12Þ
DVi
According to the energy conservation principle we have
Fig. 11.17 Waveforms of: magnetizing inductor voltage (vLm), commutation inductor current
(iLc), and magnetizing inductor current (iLm)
Ii Vi ¼ I0o V0o ð11:13Þ

f s Lc I0o
Ii ¼ I0o D ð11:14Þ
Vi
Substituting (11.6), (11.12) and (11.14) into (11.10) yields

0
f s Lc Io2
ILm ¼ ð11:15Þ
2DVi
which represents the average value of the transformer magnetizing current.
In order to analyze the commutation process of the power switches, the commu-
tation capacitors are added in parallel with the switches and a dead time between the
power switches gate signal is considered. Four commutation time intervals are
found in a switching period.
Due to the converter asymmetrical operation, the commutations take place under
different conditions. At the instant switch S1 is turned off, the current available to
charge/discharge the commutation capacitors is the load current plus the magne-
tizing inductance current (I1), as shown in Fig. 11.18. However, at the instant
switch S2 is turned off, the current available to charge/discharge the commutation
capacitors is only the magnetizing inductance current (I2), since the load is short
circuited by diode D4, as shown in Fig. 11.19. Hence, the second commutation is
more critical than the first one. Both commutations take place under zero voltage
vo’
+ -
Io’
S1 dead
D3 D4 time
S2 C2 S2 t
iLc
Lc D2
a Lm C3 + vs1
b vC3
vC3
+ ii iLm S1 - I o '+ I1
iS1
C1
Vi iC1
- D1 I o '+ I1
2
vo’
+ -
Io’
S1 dead
D3 D4 time
S2 C2 S2 t
Lc D2
a Lm C3 + vs2
b vC3
vC3
+ ii iLm S1 - I2 iS2
C1
Vi iC2
- D1 I2
2
(ZVS), providing the appropriate parameter combination is use in the converter

design stage.
The magnetizing inductance current ripple is given by (11.16).
D Ts ð1 DÞ Vi DTs
DiLm ¼ Vi ¼ ð11:16Þ
ð1 DÞ Lm Lm
The commutation current I2 is calculated as follows:
DiLm
I2 ¼ ILm þ ð11:17Þ
2
Hence
f s Lc I02 Vi D
I2 ¼ o
þ ð11:18Þ
2 Vi 2 Lm f s
The minimum dead time needed to ensure ZVS commutation of switch S2 (the
critical commutation) is determined by
CVC3
td ¼ ð11:19Þ
I2 =2
where C1 = C2 = C.

In this section a design methodology and a simplified design example are provided,
using the mathematical analysis results obtained in the previous sections. The
converter specifications are shown in Table 11.1.
In this simplified design example,
it was chosen thetransformer
turns ration =
3.2. The output current I0o and the output voltage V0o , both referred to the
primary side of the transformer, are
Io 10
I0o ¼ ¼ ¼ 3:125 A
n 3:2
V0o ¼ Vi n ¼ 50 3:2 ¼ 160 V
The static gain is given by
V0o 160
q¼ ¼ ¼ 0:4 V
Vi 400
Consider a duty cycle loss of 5%. The commutation inductance, consequently, is

given by
I0o Vi 0:05 400

Lc ¼ ¼ ¼ 160 lH
f s I0o 40 103 3:125
According to (11.7), the duty cycle at the operation point is given by
D ¼ q þ I0o
Hence,
D ¼ 0:45

specifications
11.5 Simplified Design Methodology and an Example … 311
The average voltage of capacitor C3 is calculated as follows
Vi 400
VC3 ¼ ¼ ffi 728 V
1 Dnom 1 0:45
Switch S1 RMS current is calculated

qffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IS1 RMS ¼ I0o D I0o ¼ 3:125 0:45 0:05 ¼ 1:97 A
Assume that the magnetizing inductance of the transformer is 4 mH. Hence, the
magnetizing inductance current ripple is:
DiLm Vi D 400 0:45

¼ ¼ ¼ 0:56 A
2 2 Lm f s 2 4 103 40 103
The average value of the magnetizing inductance current is
f s Lc I02
o Vi D 40 103 160 106 3:1252
ILm ¼ ¼ ¼ 0:1736 A
2DVi 2 0:45 400
The current available for the commutation of the switch S2 is:
DiLm
jI2 j ¼ ILm þ ¼ 0:1736 þ 0:56 ¼ 0:7336 A
2
Assume that the capacitances of the commutation capacitors are

C1 = C2 = 200 pF. Consequently, the minimum dead time needed to accomplish
ZVS commutation is
2CVC3 2 200 1012 728

td ¼ ¼ ¼ 0:397 ls
I2 0:7336
The active clamp ZVS-PWM forward converter, shown in Fig. 11.20, is simulated
at the specified operation point to verify the analysis and the calculation presented
in the design example of Sect. 11.5, with a dead time of 450 ns. Figure 11.21
shows the voltage vab and the output voltage v0o , capacitor C3 voltage, the com-
mutation inductor current and the magnetizing inductance current.
Table 11.2 compares theoretical and simulated results, validating the mathe-
matical analysis.
vo’
+ -
Io’
D3 D4
S2 C1
iLc
Lc D2
a Lm C3 +
b
vC3
+ ii iLm S1 -
C2
Vi
- D1
1
vg1 vg2
td
800
vC3
400
vab
0
-400
800
,
vo
400
-400
4
iLc
iLm
0
5.00 5.01 5.02 5.03 5.04 5.05
Time (ms)
Fig. 11.21 Active clamp ZVS-PWM forward converter simulation waveforms: voltages vab, vC3
and v0o , commutation inductance current iLc and magnetizing inductance current iLm
Table 11.2 Theoretical and simulated results

V0o (V) 160 160.16
iS1 RMS (A) 1.97 1.91
VC3 (V) 728 719.8
I2 (A) 0.73 0.79
1
vg2 vg1
td
0
800
vS1
400
iS1 x 50
5.022 5.026 5.030 5.034 5.038

Time (ms)
Fig. 11.22 Switch S1 voltage and current waveforms
1
vg1 vg2
td
0
800
vS1
400
iS1 x 50
0
2
iC1
1
5.0355 5.0360 5.0365

Time (s)
Fig. 11.23 A detail of the switch S1 commutation: S1 and S2 drive signals, voltage and current at
switch S1 and capacitor C1 current
1
vg1 vg2
td
0
800
vS2
400
iS2 x 200
5.010 5.014 5.018 5.022 5.026

Time (ms)
Fig. 11.24 Switch S2 voltage and current waveforms
1
vg2 vg1
td
0
800
vS2
400
iS2 x 200
0
0.4
0.2
5.0240 5.0254
Time (ms)
Fig. 11.25 A detail of the switch S2 commutation: S1 and S2 drive signals, voltage and current at
switch S2 and capacitor C2 current
The commutation at switches S1 and S2 are presented in Fig. 11.22 and in

Fig. 11.24, respectively. A detail of the switches S1 and S2 turn off are presented in
Fig. 11.23 and in Fig. 11.25. As it may be observed soft commutation is achieved
on both switches. The current available for the switch S2 commutation is smaller,
so this is the critical commutation.
11.7 Problems 315
11.7 Problems
(1) The active clamp forward converter shown in Fig. 11.26 has the following
specifications:
Vi ¼ 100 V C3 ¼ 10 lF Ro ¼ 2 X f s ¼ 50 103 Hz Lm ¼ 1 mH
Co ¼ 10 lF D ¼ 0:4 Lr ¼ 10 lH Lo ¼ 500 lH Np ¼ Ns
(a) Describe the topological states and plot the relevant waveforms for one
switching period.
(b) Calculate the capacitor C3 average voltage.
(c) Calculate V0o and I0o and the output power.
(d) Calculate the magnetizing inductance average current.
(e) Calculate the magnetizing inductance current ripple.
Answers: (b) VC3 = 166.7 V; (c) V0o = 32 V, I0o = 16 A, Po = 512 W;
(d) ILm = 1.6 A; (e) ΔiLm = 4 A.
(2) Considering the converter presented in Fig. 11.26 with commutation capacitors
of 2 nF in parallel to the switches and disregarding the inductance Lo current
ripple, calculate:
(a) The switches current at the commutation instant.
(b) The commutation time intervals.
Answers: (a) iS1 = 15.7 A, iS2 = 354 A; (b) Δt1 = 42.46 ns, Δt2 = 188 ns.
(3) Figure 11.27 shows a topological variation of the active clamp forward
converter.
(a) Describe the topological states and plot the main waveforms for one
switching period.
(b) Obtain the equation for the capacitor C3 average voltage.
(c) Find the voltage across the power switches assuming that ΔVC3 = 0.
Lk D3 Lo
.T. +
Lm
D4 Co Ro Vo
+ -
Vi D2
- S2
+
C3
- D1
S1
Fig. 11.26 Active clamp forward converter

Fig. 11.27 Active clamp D2

+ S2
forward converter topological C3
-
variation D3
Lk Lo
.T. +
Lm D4 Co Ro Vo
+ S1 D1
Vi
-
(d) Find the output voltage average value for Np = Ns.

(e) Discuss the advantages and disadvantages of this topology compared to the
topology shown in Fig. 11.3.
(f) Simulate the proposed converter.
Answers: (b) VC3 ¼ ð1D Vi L r f s Io

Þ Vi ; (c) VS ¼ ð1DÞ; (d) Vo ¼ DV1 V
D
i
(4) The asymmetrical ZVS-PWM converter shown in Fig. 11.27 has the following
parameters:
Vi ¼ 400 V Np ¼ Ns C1 ¼ C2 ¼ 0:47 nF Ro ¼ 2 X Lm ¼ 10 mH
f s ¼ 40 103 Hz Ce1 ¼ Ce2 ¼ 10 lF D ¼ 0:3 Lr ¼ 20 lH
Calculate:
(a) The minimum output current (Io min) to achieve ZVS commutation on both
switches.
(b) The required dead time to obtain ZVS commutation.
Answers: (a) Io min = 3.1 A; (b) td = 216 ns.
(5) In the active clamp forward converter shown in Fig. 11.28, the leakage inductor
is represented in the primary winding of the transformer.
(a) Describe the topological states and plot the relevant waveforms for one
switching period.
(b) Assuming that Np = Ns, find the equation for the static gain and the
equation for the average voltage across the clamping capacitor C3.
Answers: (b) Vo ¼ DV1 LV

r f s Io
; VC3 ¼ ð1D
Vi
Þ
i
Fig. 11.28 Active clamp Lk D3 Lo

forward converter with the .T. +
leakage inductance in the Lm
D4 Co Ro Vo
primary side of the
transformer + -
Vi D2
- S2
+
C3
- D1
S1
11.7 Problems 317
Fig. 11.29 Active clamp Lk D3

flyback converter .T . +
Lm
Co Ro Vo
+ -
Vi D2
- S2
+
C3
- D1
S1
(6) An active clamp flyback converter [3] is shown in Fig. 11.29.

(a) Describe the topological states and plot the main waveforms for one
switching period.
(b) Find the output voltage equation, considering Np = Ns.
(c) Find the average current in the transformer magnetizing inductance.
Answers: (b) Vo ¼ Vi DDD , where DD ¼ 2Lr f s Io ; (c) I ¼ Io

½1ðDDDÞ Vi Lm 1ðDDDÞ
References
1. Jitaru, I.D., Cocina, G.: High efficiency DC-DC converter. In: IEEE APEC 1994, pp. 638–644
(1994)
2. Duarte, C.M.C., Barbi, I.: A family of ZVS-PWM active-clamping DC-to-DC converters:
synthesis, analysis, design, and experimentation. IEEE Trans. Circ. Syst. 44(8) (1997)
3. Watson, R., Lee, F.C., Hua, G.C.: Utilization of an active-clamp circuit to achieve soft
switching in flyback converters. IEEE Trans. Power Electron., 162–169 (1996)

Soft Commutation Isolated DC-DC Converters PDF

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Soft Commutation Isolated DC-DC Converters PDF

Hochgeladen von

Copyright:

Verfügbare Formate

Power Systems

Soft Commutation Isolated

ISSN 1612-1287 ISSN 1860-4676 (electronic)

Library of Congress Control Number: 2018948691

© Springer International Publishing AG, part of Springer Nature 2019

DC-DC converters are used in personal computers, mobiles, electrical vehicles,

To optimize the power efﬁciency of isolated DC-DC converters, soft commu-

The aim of the authors is to present a detailed description and a quantitative

power electronics engineers, graduate and undergraduate students, as well as

Florianópolis, Santa Catarina, Brazil Ivo Barbi

1 Basic Electric Circuits with Switches . . . . . . . . . . . . . . . . . . . . . . . 1

2.3.3 Normalized State Plane for One Half of the

4.4 Numerical Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.3 Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

10.4 Commutation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

CCM Continuous conduction mode

© Springer International Publishing AG, part of Springer Nature 2019 1

1.2 RC and RL DC Circuits

1.2.1 RC DC Circuit with a Series Thyristor

The electric circuit studied in this section is in Fig. 1.1.

Vi ¼ vC ðt) þ RiC ðt) ð1:1Þ

Substituting (1.2) in (1.1) gives

Fig. 1.1 Series RCT circuit T iC

Fig. 1.2 Capacitor voltage and current waveforms

Solving (1.3), it is found

The capacitor current is given by

where k = RC is the circuit time constant.

1.2.2 RL DC Circuit with a Series Thyristor

The electric circuit studied in this section is shown in Fig. 1.3.

Vi = vL ðt) + R iL ðt) ð1:6Þ

Fig. 1.3 Series RLT circuit iL

Substituting (1.7) into (1.6) gives

where k = L/R is the circuit time constant.

Fig. 1.4 Inductor voltage and current waveforms

1.2.3 RL DC Circuit with a Series Switch and Free

The electric circuit studied in this section is illustrated in Fig. 1.5.

Solving (1.14) gives

1.3 Inductor DC Circuits

1.3.1 Inductor DC Circuit with a Series Switch, Free-Wheel

In many applications, due to efﬁciency constrains, it is important to recover the

Fig. 1.7 Inductor DC circuit S iL

Solving (1.17) gives

1.3.2 Inductor DC Circuit with a Series Switch, Free-Wheel

Another circuit to recover the energy accumulated in an inductor is presented in

Fig. 1.9 DC circuit with a D

Considering an ideal transformer (no leakage inductance or parasitic resistance)

The expression for the current in the time interval 2 is given by

Fig. 1.10 Equivalent circuit S D

Fig. 1.11 Topological state S i1 D

Fig. 1.12 Topological state S i2 D

Fig. 1.13 Currents i1 and i2

At the end of time interval 2 the current reaches zero. Thus

Substituting (1.21) into (1.23), (1.24) it is obtained

Referring the magnetizing inductance to the primary side of the transformer

Substituting (1.20) into (1.25), (1.26) is found

During the time interval 2 the voltage across switch S is given by

Substituting (1.29) into (1.28) gives

1.4 Constant Current Capacitor Charging Circuit

Fig. 1.14 Constant current capacitor charging circuit

Fig. 1.16 Voltage across vC

The capacitor voltage waveform is shown in Fig. 1.16.

1.5 LC and RLC DC Circuits

1.5.1 LC DC Circuit with a Series Switch