Digital IC Design/ Digital VLSI Design

(Subject Code- EC1013/ EC725)

Instructor: Hemanta Kumar Mondal

Meeting: Wed & Thu 3:30PM @1st Floor, ECE Dept.
Source: https://www.indiatoday.in/education-today/featurephilia/story/engineering-employment-problems-329022-2016-07-13
Outline

 Course information

 Motivation

 Overview of digital systems & historical overview

 Recent trends
Course Information

 Instructor:
• Hemanta Kumar Mondal (hemanta.mondal@ece.nitdgp.ac.in)

 More on the course:

• Course web page: We will use PIAZZA for everything!
• Sign up link:
• https://piazza.com/nitdgp.ac.in/fall2019/ec1013ec725

 Textbooks:
• Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Tata McGraw-Hill Education,
2003.

 References:
• J. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd
Edition, Prentice Hall 2004.
• N. H. E. Weste and C. Harris, “Principles of CMOS VLSI Design: A System Perspective, 3rd Edition,
Pearson Education 2007.

 Lectures and discussions in class will cover basics of course

 Assignment will help you gain a deep understanding of the subject
 Grading Structure

UG PG

Assignment: 5% Assignment: 10%

Quiz: 5% Quiz: 10%
Midterm: 20% Midterm: 30%
Final: 70% Final: 50%

 Students are expected to work individually on the assignments.

 Zero tolerance towards violation of Academic Integrity

Purpose of this Course

 The student is able to evaluate characteristics of CMOS inverter and

interconnects specifically in terms of current and capacitance that are
essential for estimating delay and power.
 The student is able to quickly estimate the best number of stages for a
path, the minimum possible delay for the given topology, and the gate
sizes that achieve this delay using logical effort.
 The student is able to understand the fundamental theory behind
various sources of power dissipation in a CMOS chip and apply
techniques to minimize that.
 The student is able to optimize combinational circuits for lower delay
and/or energy; analyze sequential circuits including clocking and
latching techniques.
 The student is able to use Electronic Design Automation (EDA) tools in
VLSI and experiment with the current technology/process, and able to
design state-of-the-art CMOS circuits.
 Syllabus
 Overview of VLSI Design
 Fabrication of MOSFETs
 MOS Transistor
 Modelling of MOS Transistors
 MOS Inverter: Static Characteristics
 MOS Inverters: Switching Characteristics and Interconnect Effects
 Combinational MOS Logic Circuits
 Sequential MOS Logic Circuits
 Dynamic Logic Circuits
 Semiconductor Memories
 Recent Trends in VLSI Design & its research issues in industry
 Motivation

 Applications
 Scientific applications
• Astrophysics,
• Weather prediction,
• Bioinformatics
 Consumer electronics
 Cloud computing The Facebook server hall in the city of Lulea,
Sweden. Data centers now consume about 3 per

 Multimedia applications cent of the global electricity supply AFP/Getty

 Exascale Computing
“What matters most to the computer designers at google is not speed, but power,
 Defense, security,
low power, because DATA CENTERS can consume as much electricity as a city.”
Medical, IoT, AI, etc…..
----- Eric Schmidt, Former CEO Google
 Data center
“Global warming: Data centers to consume three times as much energy
in next decade, experts warn”The facilities of the Google data center in Taiwan
(AFP/Getty)
416.2 terawatt hours of electricity world’s data centers used last year was far higher than UK’s total
consumption
----- The Independent News (Saturday 23 January 2016 21:37 GMT)
8
 Recent trends

The key challenge to get 1000 cores/ processors or more is

energy/power
Krik Pruhs, “Energy as a computation resource”, NSF workshopefficiency.
on Research Directions in principles of parallel computation”,
2012.

9
OVERVIEW OF DIGITAL SYSTEMS
& HISTORICAL OVERVIEW
 Robert Noyce, 1927 - 1990

 Nicknamed “the Mayor of Silicon

Valley”

 Cofounded Fairchild Semiconductor in

1957

 Cofounded Intel in 1968

 Co-invented the integrated circuit

 Gordon Moore

 Cofounded Intel in 1968 with Robert Noyce.

 Moore’s Law: the number of transistors on a

computer chip doubles every 1.5 years
(observed in 1965)

 Since 1975, transistor counts have doubled

every two years
Full System
Principle of Abstraction
 Digital System

A D
Digital
D A
C Systems C
Analog Analog
In Subsystems Out

Modules

Basic Units
(Logic Gates)

Circuits
(Transistor,
Register)
 Applications of Digital Systems

• Digital ICs
• Digital Calculator
• Computer
• Audio recoding
• Image processing
• Telephone switching networks
• Many more………. • 32nm – 64 bit, 4 995 000 000 Transistors
• 3.5GHz, 216mm2

• 90nm process
• 8 processor
• Playstation

Sandy Bridge

 The semiconductor industry has grown from $21 billion in 1985 to $463
billion in 2018.
 EDA Tools
 Analog part:
Idea
o Schematic: Schematic Capture
Specifications
o Simulation: Spectra

o Layout: Virtuoso layout RTL

o DRC, LVS, and RCX: Assura

Gate Level Netlist

Physical
Implementation
 Digital part:
o Cadence tools- NCSim, Encounter RTL GDSII

compiler,
CHIP
o Synopsys tools- VCS, DC, ICC, PrimeTime
 Objectives
 What technologies are there?

 Why CMOS?

 How far we can go?

 What is the worldwide view of VLSI technology?

 What are the different implementation methods?

18

Source: Concordia VLSI Design Lab

The First Transistor 1948

19
Source: Concordia VLSI Design Lab
 Milestones of IC Development
 Beginning of Semiconductor Evolution 1948
 Passive and Active Components from Semiconductor
Materials 1958
 Planar Transistors 1959
 Planar Passive and Active Devices 1961
 Small Scale Integration (SSI)1964
 Medium Scale Integration (MSI) 1968
 Large Scale Integration(LSI) 1971
 Very Large Scale Integration (VLSI) / Ultra Large Scale
Integration (ULSI) 1980s
 System On Chip (SoC) 2000s and is continuing to get larger
and larger
20
Source: Concordia VLSI Design Lab
RECENT TRENDS
 WORLD OF SILICON

 IC applications are in
every aspects of our
lives:
 Computers
 Toys
 Consumer electronics
 Household items
 Automotive
 Industrial equipment's
 Military
 Communications
 Advertising and Displays
 Space and Exploration
 Etc.

22
Source: Concordia VLSI Design Lab
 Emerging-in-car systems

23
Source: Concordia VLSI Design Lab
 The Internet Big Bang

24
Source: Concordia VLSI Design Lab
 EVEN ATMs

25
Source: Concordia VLSI Design Lab
 ENIAC - The first electronic computer (1946)

20,000 Vacuum Tubes, it cost $500,000

It could Add, Subtract and store 10-digit decimal numbers in memory
It weighted 27 tons, had a size of 80 ft* 8.5 ft* 3 ft, and it required a room of 680 ft2
Consumed 150KW
26
Source: Concordia VLSI Design Lab Prentice Hall/Rabaey
 BUT NOW, a small cell phone

By the millions, more powerful, more functions, less

weight, less power consumption, less heat generation
Source: Concordia VLSI Design Lab
 Intel 4004 Micro-Processor 1971

 4-bit CPU
 2,300 transistors
 Area of 3 by 4 mm
 Employed a 10 μm
silicon-gate
 92,000 instructions/s
 740 KHz Clock 16 pin

28
Source: Concordia VLSI Design Lab Prentice Hall/Rabaey
 Intel Pentium (IV) microprocessor 2002
 A 'Northwood' core
Pentium 4 processor
(P4A)
 Northwood core at 2.2
GHz
 2nd cache 512 KB 55
million transistors, 130
nm Technology

29
Source: Concordia VLSI Design Lab Prentice Hall/Rabaey
MOORE’S LAW

30
 Intel announces 14 new Ivy Bridge
Processors
(May. 31, 2012 (8:31 am) By: Matthew Humphries In: Chips, Chips Picks, Geek Pick, News)

 Intel launched the 22nm Ivy Bridge processors that uses quad-core
chips.

 CPU frequency ranges from 2.6GHz to 2.9GHz and maxing out at

3.4GHz using Intel Turbo Boost on the Core i7 chip.

Source: Concordia VLSI Design Lab

 IBM Creates New Memory Technology
100 Times Faster Than Flash
by Bryan Vore on July 01, 2011

 IBM revealed its new phase-change memory (PCM) tech that could drastically
change computing and gaming.

 IBM says that PCM is able to write and retrieve data 100 times faster than
Flash memory.

Source: Concordia VLSI Design Lab

 IBM Promises Internet 400 times faster

 A new technology from IBM promises hyper-fast and energy

efficient connections to the Internet, as fast as 400 gigabits per second.

 Scientists in IBM Switzerland just unveiled a prototype tiny chip for an

energy efficient analog-to-digital converter (ADC), that’s 5,000 times faster
than the average U.S. connection, or 400 times faster than Google Fiber.

 This is fast enough to download a 2-hour ultra-high-definition movie (about

160 gigabytes) in seconds!
Source: Concordia VLSI Design Lab
TOSHIBA
SD Memory

SD-GU064G2 SD-GU032G2 SD- GU016G2

Capacity 32GB 64GB 16GB

Maximum read speed 95MB/ sec

Maximum write speed 60MB/ sec

Shipped in April
2014, with prices
ranging from
$120 to $300.

Source: Concordia VLSI Design Lab

 Toshiba develops, manufactures 19nm
generation NAND Flash Memory with world's
largest density and smallest die size
(128 Gb capacity in a 3-bit-per-cell chip on a 170mm2 die
23 Feb, 2012)

 In the 19 nanometer (nm) generation, Toshiba has developed a

3-bit-per-cell 128 gigabit (Gb) chip with the world's smallest[1]
die size—170mm2—and fastest write speed[2]—18MB/s of any 3-
bit-per-cell device. The chip entered mass production earlier this
month.

Source: Concordia VLSI Design Lab

What's the largest memory stick that you can buy?

It is 256GB. It is a Memory Stick/Flash

Drive/USB/Small Little Finger. It is Very Expensive.
128GB $1,499.99
Item# SDCFXP-128G-A91
SanDisk Extreme® Pro™ CompactFlash®
128GB Card with VPG
Jun 19, 2012 SANDISK I

Kingston 1TB USB3.0 DataTraveler HyperX

.
.

$899 Valid from Aug 05, 2014

Source: Concordia VLSI Design Lab

 Is 14nm the end of the road for silicon chips?

• Atoms are very small, but they still have a finite size. The
atoms used in silicon chip fabrication are around 0.2nm. A
human hair diameter is around 150 micron. A transistor in a
14 nm is around 80 nm.

• A process that Intel use with Ivy Bridge — the high-κ dielectric
layer is just 0.5nm thick; just two or three atoms!

• NOW no manufacturing technique is so accurate, since a

single, out-of-place atom can ruin an entire chip, it is going to
be extremely difficult to manufacture circuits that are both
reliable and cost effective.

Source: Concordia VLSI Design Lab

 What is in store for us

 Chipmakers are working hard to reach the 5nm node, but, the
industry has several challenges to overcome.

 Presently, the leading transistor candidates for 5nm are the usual
suspects— III-V FinFETs; gate-all-around; and nanowires.

 But the tunnel field-effect transistor (TFET) is also considered for

its low power and low voltage, about 0.5 –volt

 Putting TFETs and FinFETs into production is difficult and may

need III--‐V materials, nanowires and other complex
technologies.

Source: Concordia VLSI Design Lab

CHALLENGES MOUNT FOR
INTERCONNECT> By Mark LaPedus
 When asked what are the top challenges facing leading-
edge chip makers today, Gary Patton, vice president of the
Semiconductor Research and Development Center at IBM,
said it boils down to two major hurdles: lithography and the
interconnect.

ROUTING CONGESTION RETURNS

By Ed Sperling

 Routing congestion has returned.

 The advent of more third-party IP, more memory, a variety
of new features, as well as the inability to scale wires at the
same rate as transistors.
Source: Concordia VLSI Design Lab
 Example of Industrial foundry
 GLOBALFOUNDRIES provides advanced
semiconductor manufacturing excellence with
leading-edge (28nm), mainstream (65nm and 45nm)
and mature (0.35um to 0.11um) technology, on both
200mm and 300mm wafers.

 GLOBALFOUNDRIES has fabrication in Dresden, New

York and Singapore, with a network of design and
support centers in Silicon Valley, China, Japan,
Germany, Singapore, Taiwan and the U.K.

WWW.GLOBALFOUNDRIES.COM

Source: Concordia VLSI Design Lab

 3D design
 3D design opens up architectural possibilities for
engineering teams to realize much better performance
and far less power consumption.

 The greatest power savings in 3D designs are achieved

at the architectural level, and that may mean jumping in
at the deep end.

 Hot topic: Thermal integrity's effect on 3D-IC design

and analysis.

Source: Concordia VLSI Design Lab

 What Comes after FinFETs?

 The semiconductor industry is currently making a major

transition from conventional planar transistors to FinFETs
starting at 22nm.

 The question is what’s next? In the lab, IBM, Intel and

others have demonstrated the ability to scale FinFETs down
to 5nm or so. If or when FinFETs runs out of steam, there
are no less than 18 different next generation candidates
that could one day replace today’s CMOS-based FinFET
transistors.

 Mayberry said the eventual winners and losers in the next-

generation transistor race will be determined by cost,
manufacturability and functionality.
Source: Concordia VLSI Design Lab
 How about interconnect and Memory

 New materials and processes for advanced interconnects

Although on chip interconnects have not been scaling at the same
speed as other parts of the chip, new capabilities enabled by
Graphene and CNTs, among other materials, could soon change
that.

 3D memory for future nanoelectronic systems

3D memory will generally cost more than 2D memory, so generally
a system must demand high speed or small size to mandate 3D.

 When it comes to memory manufacturing, consolidation is king.

Today only three major DRAM manufacturers remain MICRON,
SAMSUNG, and SK HYNIX

Source: Concordia VLSI Design Lab

 All optical transistors

 The Max Planck Institute of Quantum Optics has taken a step

towards devising the long-awaited optical transistor.

 http://semiengineering.com/manufacturing-bits-august-5/

Source: Concordia VLSI Design Lab

10TH GEN 10 NM ‘ICE LAKE’ PROCESSORS

 INTEL OFFICIALLY LAUNCHES ITS 10TH GEN 10 NM ‘ICE LAKE’ PROCESSORS

FOR LAPTOPS

-- TECH2 NEWS STAFF AUG 03, 2019 23:48:03 IST

 10th Gen Core i3/i5/i7 processors are meant for thin-and-light laptops.
 Coming soon!!!
 After bringing its 7-nm technology to volume production,
TSMC is developing 5-nm and 3-nm technology.

 TSMC plans to ramp 5nm production during the first half of

next year.
-- EETimes, 26th July 2019.
 AIMs
 What the customers want:
 High Quality
 Low Cost
 Small Size/Weight
 What the Employer wants
 Design the:
 Best
 Cheapest
 In shortest time
 Follow the Spec or better.

 What you (chip designer) should do:

 Design a chip with:
 High speed
 Small area
 Low power
 Testable and reliable
 Delivered in a short time

47
 The Best Resources for Digital IC Design?
1- First learn digital design concept
 combination digital design
 multiplexer, decoder, encoder, number system, optimization of
code
2- Sequential logic design
 flip flops, counters, finite state machine, PLL, CPLD, FPGA
3- Knowledge of C programming
4- Verilog design implementation on FPGA .
5- UVM, SystemVerilog
6- Data structure / advanced computer architecture
7- Basic knowledge of CMOS.
8- Scripting languages: Perl, Python, and TCL……..
 Reading Assignment #01

 International Technology Roadmap for Semiconductors - ITRS

2.0, 2015