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Introduction to

Microcontroller
Microcontroller versus general-purpose
microprocessor
Microcontroller versus general-purpose
microprocessor
º A microprocessor generally º A microcontroller is 'all in one',
does not have RAM, ROM and the processor, ram, IO all on
IO pins; a complete functional the one chip; a complete
CPU functional microcomputer

º Often at least 16-bit, and º Typically 8-bit, but may be 4-,


typically 32-bit or 64-bit, though 16- or 32-bit
8-bit still has a big market share
º Fixed amount is critical in terms
º Versatility on amount of RAM, of utility and space
ROM, I/O ports
º Price/unit are critical than
º Add-ons make system bulkier computation and power
and expensive consumption
Microcontroller versus general-purpose
microprocessor
VON NEUMANN ARHITECTURE

Programs and data share the same memory


space. Ex:Motorola 68HC11Microcontroller
HARVARD ARHITECTURE

It uses separate memory for program and


data with their independent address and data
buses. Ex:8051 and PIC Microcontroller
VON NEUMANN vs HARVARD ARHITECTURE

º Content of memory is organized, a º Two memories with two buses allow


single sequential numeric address parallel access to data and instructions
linearly addresses memory º Control unit for two buses is more
º One bus is simple for control unit complicated and thus expensive and
design; thus cheaper, faster and less time consuming
time consuming architecture º Program cannot rewrite itself
º Error in a program can rewrite º Both memories can use different sizes
instruction and crash program
º Free data memory cannot be used for
execution
instructions and vice-versa
º Data and instruction is accessed in the
º Processor can complete an instruction
same way
in one cycle by implementing
º Processor needs two clock cycles to pipelining strategies
complete an instruction
º One bus is a bottleneck, so only one
information can be accessed at same
time
Criteria for Choosing a microcontroller
 Speed: Clockwork oscillated by crystal
 Packaging: PDIP, SOIC, QFP packaging format in terms of spacing,
assembling and prototyping the end product
 Power Consumption: Critical for battery-powered products
 The amount of RAM & ROM on chip
 The number of I/O pins and the timer on the chip
 Easy upgradation to higher-performance or lower power-consumption
versions
 Cost per unit
 Availability of assembler, debugger, a code-efficient C language
compiler, emulator, technical-support, both in-house and outside
expertise
 Ready availability in needed quantities for present and future
Choosing a microcontroller
In 1981, Intel Corporation
introduced an 8-bit
microcontroller called the 8051.
Comparison of the 8051 Family
Members
89XX ROM RAM Timer Int IO pin Other
Source
8951 4k 128 2 5 32 -

8952 8k 256 3 8 32 -

8953 12k 256 3 9 32 WD

8955 20k 256 3 8 32 WD

898252 8k 256 3 9 32 ISP

891051 1k 64 1 3 16 AC

892051 2k 128 2 6 16 AC

WD: Watch Dog Timer


AC: Analog Comparator
ISP: In System Programable
The Architecture of8051
Microcontroller
8051 Basic Component
4K bytes internal ROM (Program)
128 bytes internal RAM (Data)
Four 8-bit I/O ports (P0 - P3).
Two 16-bit timers/counters
One serial interface

CPU RAM ROM


A single chip
I/O Serial
Timer COM Microcontroller
Port
Port
Salient Features
(( (1).High-performance CMOS Technology.
(2). Contains Total 40 pins.
(3). Address bus is of 16 bit & data bus is of 8 bit.
(4). 4K bytes internal ROM (program).
(5). 256 bytes internal data memory.
(6) 8051 has 21 special function registers (SFRs).
(7). Four 8-bit I/O ports, total 32 I/O lines .
(8). Two 16-bit timers.
(9). Serial interface Communication.
(10). 64K external code & data memory space.
(11). 210 bit-addressable locations.
(12). Internal memory consists of on-chip ROM and on-chip
data RAM.
(13) Boolean Processor, Carry flag acts as accumulator
(14). +5V Regulated DC power supply is required to operate .
(15) 5-interrupts .
Block Diagram
External Interrupts

Interrupt 4k 128 bytes Timer 1


Control ROM RAM Timer 2

CPU

OSC Bus
4 I/O Ports Serial
Control

P0 P2 P1 P3 TXD RXD
Addr/Data
8051 Internal Block Diagram
8051
Schematic
Pin out
8051 P1.0 1 40 Vcc

Foot Print
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9
8051 32 P0.7(AD7)
(RXD)P3.0 10 (8031) 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12
(8751) 29 PSEN
(INT1)P3.3 13 (8951) 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
XTAL Connection to 8051

Using a quartz crystal oscillator with frequency


11.0592 MHz
We can observe the frequency on the XTAL2 pin.
C2
XTAL2
30pF

C1
XTAL1
30pF

GND
XTAL Connection to an External Clock Source

Using a TTL oscillator


XTAL2 is unconnected.

N XTAL2
C

EXTERNAL
OSCILLATOR
SIGNAL XTAL1

GND
RST Pin of 8051

 RST(pin 9):reset
 input pin and active high(normally low).
The high pulse must be high at least 2
machine cycles.
 power-on reset.
Upon applying a high pulse to RST, the
microcontroller will reset and all values in
registers will be lost.
Reset values of some 8051 registers
 power-on reset circuit
Power-On RESET
Vcc

31
EA/VPP
X1
10 uF 30 pF

X2
RST
9
8.2 K
RESET Value of Some 8051 Registers:

Register Reset Value


PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000

RAM are all zero



Some pin functions
 PSEN or program store enable is an output pin, provided by
controller pin 29 acting as strobe to read the external program
memory
 ALE/PROG is an output pin, provided by controller pin 30
to demultiplex address and data while external memory
access
 EA/VPP is a control pin, provided by controller pin 31 to
access source code
 EA/VPP=0: Execute program on external memory
 EA/VPP=1: Execute program on internal memory

2
4
On-Chip Memory
Internal RAM
Registers
1F

Bank 3 Four Register Banks


18
17
Each bank has R0-R7
Selectable by psw.2,3
Bank 2
10
0F

Bank 1
08
07 R7
06 R6
05 R5
04 R4
03 R3 Bank 0
02 R2
01 R1
00 R0
Register banks in the 8051 Microcontroller

2
7
Bit Addressable Memory
2F 7F 78 20h – 2Fh (16 locations X
2E 8-bits = 128 bits)
2D
2C Bit addressing:
2B
mov C, 1Ah
2A
29
or
28 mov C, 23h.2
27
26
25
24
23 1A

22 10

21 0F 08
20 07 06 05 04 03 02 01 00
Bit Addressable RAM

Figure 2-6
Summary
of the 8051
on-chip
data
memory
(RAM)
Special Function Registers
(1). 8051 has 21 special function registers (SFRs) at the top of internal RAM from
address 80H to FFH.

(2). Most of the addresses from 80H to FFH are not defined, except for 21 of
them.

(3). Some SFR’s are both bit-addressable and byte addressable, depending on the
instruction accessing the register.

(4). This area consists of a series of memory-mapped ports and registers.

(5). All 8051 CPU registers, I/O ports, timers and other architecture components
are accessible in 8051 C through SFRs

3
0
Special Function Registers
(1). ACC
(2). B
(3). PSW( Program Status Word)
(4). SP
(5). DPTR
(5). IP (Interrupt Priority Register)
(8). TMOD (Timer Mode Control Register)
(9). TCON (Timer Control Register) etc.

3
1
8051 CPU Registers
A (Accumulator)
B
PSW (Program Status Word)
SP (Stack Pointer)
PC (Program Counter)
DPTR (Data Pointer)

Used in assembler
instructions
Bit Addressable RAM

Figure 2-6
Summary
of the 8051
on-chip
data
memory
(Special
Function
Registers)
B Register
(1). B register or accumulator B is used along with the accumulator
for multiply and divide operations.

(2). MUL AB: multiplies 8 bit unsigned values in A and B. and leaves
the 16 bit result in A (low byte) and B (high byte).

(3). DIV AB: divided A by B, leaving the integer result in A and


remainder in B.

(4). B register is bit-addressable.

10
PSW (Program Status word) / Flag Register

11
Stack Pointer
(1). Stack pointer (SP) is an 8-bit register at address 81H.
(2). It contains the address of the data item currently on top of the
stack.
(3). Stack operations include pushing data on the stack andpopping
data off the stack.
(4). 8051 stack is kept in the internal RAM
(5). Depending on the initial value of the SP, stack can have different sizes
(6). Example: MOV SP,#5FH
(7). On 8051 this would limit the stack to 32 bytes since the
uppermost address of on chip RAM is 7FH.
Data pointer (DPTR)
(1). Data pointer (DPTR): is used to access external data or code.

(2). DPTR is a 16 bit register at addresses 82H (low byte) and 83H
(high byte).

(3). The data pointer is used in operations regarding external RAM


and some instructions involving code memory.

(4). Example: the following instructions write 55H into external


RAM location 1000H:
•MOV A,#55H
•MOV DPTR,#1000H
•MOVX @DPTR,A
I/O Ports
(1). One of the major features of a microcontroller is the versatility built into the
I/O circuits that connect the microcontroller to the outside world .
(2). To be commercially viable, the 8051 had to incorporate as many I/O functions
as were technically and economically possible.
(3). One of the most useful features of the 8051 is four bidirectional I/O ports.
(4). Each port has an 8-bit latch in the SFR space as mentioned earlier. (5). To
reduce the overall package pin count, the 8051 employs multiple
functions for each port.
(6). Each port also has an output drive and an input buffer.
(7). These ports can be used to general purpose I/O, as an address and data
lines.
(8). The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins
I/O Ports
PORT 0
(1). Port 0 is 8-bitbidirectional I/O port.

(2). Port 0 is also the multiplexed low-order address and


data
bus during accesses to external program and data
memory.

(3). We are using pins no. from 32 to 39.


All the ports are bit addressable as well as byte
addressable.
PORT 1
(1). Port 1 is an 8-bit bidirectional I/0 port.
(2). We are using pins no. from 1 to 8.

(3). Port 1 have no dual functions.

(4). When used as an output the pin latches are


programmed to 0.

(5). When used as an input the pin latches are


programmed to 1.
PORT 2
(1). Port 2 is an 8-bit bidirectional I/O port.

(2). Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).

(3). When used as an output the pin latches are programmed to 0.

(4). When used as an input the pin latches are programmed to 1.

(5). We are using pins no. from 21 to 28.


PORT 3
(1). Port 3 is an 8-bit bi-directional I/0 port. (2).
We are using pins no. from 10 to 17.

•RXD (P3.0): Serial input,


•TXD (P3.1): Serial output,
•INT0’ (P3.2): External interrupt 0,
•INT1’ (P3.3): External interrupt 1,
•T0 (P3.4): Timer 0 external input,
•T1 (P3.5): Timer 1 external input,
•WR’ (P3.6): External data memory write strobe,
•RD’ (P3.7): External data memory read strobe,
Timers and Counters
(1). Many microcontroller applications require the counting of external events, such as
frequency of a pulse train, or the generation of precise internal time delays between
actions.

(2). Both of these tasks can be accomplished using software techniques.

(3). The 8051 has two 16-bit registers that can be used as either timers or counters.

(4). These two up counters are name T0 and T1 and are provided for general use of the
programmer.

(5). Each counter may be programmed to count internal clock pulses, act as a timer, or
programmed to count external events as a counter.

(6). The counters are divided into two 8-bit registers called the timer low (TL0, TL1) and
timer high (TH0, TH1) bytes.
TIMER/COUNTER IN 8051
º TCON, an 8-bit bit-addressable register, controls timer/counter
controls

(TR bits )TR0 and TR1 flags start the timer counting(it is used to turn
on and off the timer).
TF1 and TF0 are Timer overflow flags , set when timer overflows(falls
from FFh to 00h)
IT0= Timer 0 interrupt flag(Enabled or disabled SETB TCON.5 or
CLR TCON.5)
IE0= External Interrupt 0 Flag

◊ The frequency for the timer is always 1/12th the frequency of crystal
attached, regardless of 8051 versions
Interrupts
Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.

• There are total 5 interrupt sources in 8051 Microprocessor as follows. (1).


Timer Interrupt 0, (2). Timer Interrupt 1 (when overflow of Timer 1 occurs),
(TF1 & TF2 are Timer Flag Interrupts). (3). INT 0, (4). INT 1, (INT 0 & INT 1 are
external interrupts).
 (5). Serial Port Interrupt (when either RI or TI flag is set. Transmit
Interrupt(TI), Receive Interrupt(RI)).

 1,2 and 5 are internal interrupts.


Interrupts Priorities
Interrupt Destinations
Interrupt Address
(Hex)
1 INT0 0003H

2 TF0 000BH

3 INT1 0013H

4 TF1 001BH

5 SERIAL 0023H
26
Interrupt Priority (IP) SFR
Interrupt Enable (IE) SFR

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