02 Introduction To Microcontrollers

MCS – 51
Microcontrollers
8051 Microcontroller
• An 8-bit microcontroller introduced by Intel in
1981, the original member of family.
• The core was equipped with all essential
components required for embedded system.
• Became very popular after Intel allowed other
manufacturer to make any flavor of 8051,
provided they remain code compatible.
• The 8-bit arena is the growth segment of market.
An Introduction to 8051 – Manish Tiwari 2

8051 Core Pin Description
Simplified Logic Diagram

8051 Core Architecture

Features of 8051
• Available in large volume every where on the globe.
• In its simplest form, it offers 58-pin functionality, while available
in 40-pin IC package.
• Sold in almost all types of IC packages for any type of design.
• Also available as a 20-pin IC package, offering low cost solution
for Embedded System designs.
• Cheaper OTP versions with lesser number of pins is one among
the most popular choice for low cost design.
• A vast variety of ROM deices, such as EPROM/UVPROM,
EEPROM, Flash, NVRAM are supplied in market, so that it is
suited for every Embedded System we can think of.
MCS – 51 Family
8051 Family Members
Feature 8031 8051 8052 8751
On Chip ROM 0K 4K 8K 4 K (EPROM)
RAM 128 128 256 128
Timers 2 2 3 2
I/O Pins 32 32 32 32
Serial Port 1 1 1 1
Interrupt Source 6 6 8 6
• ROM less parts are advantageous in development cycle of an embedded

system.
• ROM versions are cost effective solution for mass production of end
products.
• For small volumes cheaper OTP (EPROM) versions are the popular choice.
• UVPROM parts are use full when debugging, runtime data logging,
change in operating parameters etc are essential in an embedded system.
What's in Part Number
Here is the naming convention you must know
8 PMT PM C
Program Memory Type Memory Capacity

0 ROM C ROM RAM
7 EPROM 1 4K 128
9 FLASH 2 8K 256
4 16 K 256
Program Memory ?
3 No on-chip Program Memory
5 On-chip Program Memory
Example
8052 8051 with 8 KB PROM and 3 Timers. A superset of 8051.
8752 8051 with 8 KB EPROM and 3 Timers. A variant of 8052.
8051 Core Pin Description

8051 Example Reset Circuit
• Initially Capacitor is discharged.

• When power is first applied Vcc drops across resistor and Logic 1 is
applied. When Capacitor is fully charged drop across resistor is 0.
• When Reset switch pressed current flows through 8.2 K resistor, so
Logic 1 is applied. When switch is released drop across resistor is 0.
Clocking Circuit
18
XTAL 2
19
XTAL 1
T= (1/frequency)*C*12
• XTAL 1 is input to input to inverting oscillator amplifier and XTAL 2

is output from inverting oscillator amplifier.
• Two ALE Pulses each M/c Cycle means two Opcode reads i.e. faster
code execution.

8051 External Memory Connection
Program memory interface
Data memory interface

8051 External Memory Connection
• Two memory interfaces (Program & Data) making it Harvard Architecture.

• Two interfaces with single address & data bus makes it Modified Harvard
Architecture.
Internal Memory Organization
FFFH
Used to access various on
chip functionalities
FFH
Special
Function 128 bytes
Registers Internal 4K bytes
(SFRs) Program
80H Memory
7FH
General (ROM)
Purpose 128 bytes
RAM
(GPR)
00H
Available to User 000H

Internal Data RAM Organization
General
Purpose
RAM
(GPR)

Internal Data RAM Organization

SFR Organization

Internal RAM Organization-8052
Both 8051, 8052.
8052 Only. Only DIRECTLY Accessible.
Only INDIRECTLY Accessible.
FFH FFH
General Special
128 bytes Purpose Function 128 bytes
RAM Registers
(GPR) (SFRs)
80H 80H
7FH
General
Purpose 128 bytes
RAM
(GPR)
Both 8051, 8052.
00H
Accessible through ANY
ADDRESSING Mode.

Power Saving Modes
SM0D - - - GF1 GF0 PD IDL
SM0D PCON.7 Serial baud rate modify bit.

GF1 PCON.3 General purpose user flag bit 1.
GF0 PCON.2 General purpose user flag bit 0.
PD PCON.1 Power down bit.
IDL PCON.0 Idle mode bit.
Embedded Systems – Manish Tiwari 18

Power Down Mode
PD =1 Invokes Power Down Mode
• On-chip oscillator is stopped.
• All the on chip functional units such as Timers,
UART etc. and Program execution are halted.
• I/O ports continue to output the status stored in
their latch.
• Draws a current of 100 uA against the normal
consumption of 20 mA.

Power Down Mode (Contd.)
• On-chip RAM and SFRs retains their values as
long as 2V is supplied.
• Power Down mode is terminated by RESET.
• After RESET, PD bit in PCON is cleared to 0 and
program counter is cleared i.e. PC=0000H.
• RESET redefine SFRs but does not changes the
on-chip RAM.

IDLE Mode
IDL =1 Invokes IDLE Mode of 8051
• On-chip oscillator continues to work.
• Clock is prohibited from CPU so program execution stops.
• All the on-chip functional units such as Timers, UART etc.
continues to work.
• Content of on-chip RAM and SFRs are preserved.
• Draws a current of 5 mA compared to 20 mA consumption
in normal operating conditions.

IDLE Mode (Contd.)
• Idle mode is terminated by either an Interrupt or by a
RESET.
• In either the case, IDL bit in PCON (i.e. PCON.0) is
cleared.
• When terminated by Interrupt, then first ISS is executed
then it resumes normal execution.
• When terminated by RESET, execution starts from the very
next instruction that invoked IDLE mode i.e. PC is also
preserved in IDLE mode. This is an exception as after
RESET, PC=0000H.

8051 Program Status Word
CY (Carry) - 1, if carry generated during arithmetic operation else set to

0 (Math Flag).
AC (Auxiliary Carry) - 1, if carry generated from bit b3 to b4 during
arithmetic operation else set to 0 (Math Flag).
OV (Overflow) – 1, when result overflow during signed arithmetic
operation else set to 0 (Math Flag).
P (Parity) – 1, when ODD number of 1s are present in Accumulator else
set to 0.
RS1, RS0 – Register bank select bit. 00 for Bank 0, and so on.
F0 – User definable flag 0.
INSTRUCTIONS
&
ADDRESSING MODES

MOV
MOV means copy operation. The general format for
MOV is
MOV DESTINATION, SOURCE
Copy the source data to destination.
• There are a variety of ways in which the source
data i.e. source operand and destination operand
can be specified.
• The methods specifying these data operands is
referred as Data Addressing Mode.
Register Addressing
In this addressing mode, certain registers (A, R0 to
R7, DPTR) may be used as data operands.
e.g.
MOV A, Ri (Ri – Any register R0 to R7)
- MOV A, R4 ; Copy content of R4 into A.
- MOV R7, A ; Copy content of A into R7.
MOV R5, R7 ; Error - Ri to Ri is not allowed.

- MOV A, R7 ; Copy content of R4 into A.
- MOV R5, A ; Copy content of A into R5.
Immediate Addressing
In this mode, data is part of the instruction and follows the
Opcode immediately.
e.g.
MOV A, #20 ; Copy 20 into A.
MOV R4, #20H ; Copy hex 20 into R4.
MOV R5, #F0H ; Error - a constant must start with
a number.
MOV R5, #0F0H ; Copy F0H into R5.
MOV DPTR, #2050H ; Copy 2050H in DPTR.
* Immediate operand can not be destination.
A Simple Program
P1: Write an 8051 ALP (Assembly
Language Program) to clear all the
registers (R0 to R7) of current register
bank.

P1: Clearing Registers
ORG 0000H ; Store my program at code
location 0000H.
START: MOV A, #00H ; Load Value to clear in A.
MOV R0, A ; Clear R0. Register Addressing.
MOV R1, A ; Clear R1.
HERE: SJMP HERE ; STOP
Alternate P1: Clearing Registers
location 0000H.
START: MOV R0, #00H ; Clear R0. Immediate Addressing
MOV R1, #00H ; Clear R1.
Direct Addressing
In this mode, data is present in internal data RAM or
SFR location and the address of location can be
specified directly in the instruction.
e.g.
MOV A, 20H ; Copy data from (direct) location 20H into A
MOV R4, 20H ; Copy direct byte from 20H into R4.
MOV 04H, 20H ; Same as above. Copy into R4 from 20H.
MOV 25H, 25H ; Copy to it self is Unpredictable.
* The SFRs can only be addressed using direct addressing.

A Simple Program
bank using direct addressing mode.

ORG 0000H ; Store my program at code location
0000H.
* After RESET Register Bank 0 is selected by default.
START: MOV A, #00H ; Load Value to clear in A.
MOV 00H, A ; Clear R0.
Alternate P2: Clearing Registers
location 0000H.
* After RESET Register Bank 0 is selected by default.
START: MOV 00H, #00H ; Clear R0.
MOV 01H, #00H ; Clear R1.
Indirect Addressing
In this mode, data is present in internal data RAM or
and the address of data can be specified through a
pointer register in the instruction.
Only R0 and R1 can be specified as the pointer
register (Rp).
MOV A, @R0 ; Copy data from the location specified by
the content of R0 into A.
MOV @R1, 20H ; Copy direct byte from 20H to the
location specified by R1.
Valid MOV Opcodes
MOV A, Ri MOV Addr, Ri
MOV A, Addr MOV Addr1, Addr2
MOV A, #DATA8 MOV Addr, #DATA8
MOV A, @Rp MOV Addr, @Rp
MOV DPTR, #DATA16 MOV A, Addr
MOV Ri, A MOV @Rp, A

MOV Ri, Addr MOV @Rp, Addr
MOV Ri, #DATA8 MOV @Rp, #DATA8

INC – Increment by 1
INC OPR : OPR ← OPR + 1
None of the Maths flags are affected by INC.
- INC A ; Increment A by 1, A ← A + 1.
- INC Ri ; Increment Ri by 1, Ri ← Ri + 1.
- INC Addr ; Increment Direct byte, (Addr) ← (Addr) + 1.
- INC @Rp ;Increment Indirect byte, ((Rp)) ← ((Rp)) + 1
- INC DPTR ; Increment DPTR by 1, DPTR ← DPTR + 1.
- INC #50 ; ERROR – A constant can not be incremented.

DEC – Decrement by 1
DEC OPR : OPR ← OPR - 1
None of the Maths flags are affected by DEC.
- DEC A ; Decrement A by 1, A ← A - 1.
- DEC Ri ; Decrement Ri by 1, Ri ← Ri - 1.
- DEC Addr ; Decrement Direct byte, (Addr) ← (Addr) - 1.
- DEC @Rp ;Decrement Indirect byte, ((Rp)) ← ((Rp)) - 1
- DEC #50 ;ERROR – A constant can not be decremented.
* There is no decrement for DPTR.

Useful Jumps
JZ LABEL ; Jump to symbol LABEL, to execute
next instruction, if A=0.
JNZ LABEL ; Jump to symbol LABEL, to execute
next instruction, if A≠0.
DJNZ Ri, LABEL ; Decrement the register Ri by 1 and
Jump to LABEL, to execute, if Ri≠0.
DJNZ Addr, LABEL ; Decrement direct byte by 1 and Jump
to LABEL, to execute, if ((Addr)≠0.
SJMP LABEL ; Unconditionally (short) Jump to LABEL
to execute next instruction.
A Simple Program
Language Program) to clear RAM
locations 50H to 5FH.

P3: Clearimg RAM Locations
location 0000H.
START: MOV R0, #50H ; Load Source Pointer.
MOV R7, #10H ; Load count in R7 (10H=16).
MOV A, #00 ; Load Value to clear in A.
AGAIN: MOV @R0, A ; Clear the RAM
INC R0 ; Point to next location.
DJNZ R7, AGAIN ; Do it AGAIN if all RAM
locations are not cleared.

A Simple Program
bank using indirect addressing mode.

location 0000H.
; After RESET Register Bank 0 is selected by default.
START: MOV R0, #00H ; Lord Source Pointer.
MOV R7, #08H ; Load count in R7, 8 Registers.
AGAIN: MOV @R0, A ; Clear the Register.
INC R0 ; Point to next register location.
DJNZ R7, AGAIN ; Do it AGAIN if all Registers
are not cleared.
; However, the program has logical errors. IDENTIFY?
P4: Clearing Registers - Correct
location 0000H.
; After RESET Register Bank 0 is selected by default.
START: MOV R0, #06H ; Lord Source Pointer (Addr R6).
MOV R7, #06H ; Load count in R7, 6 Registers.
AGAIN: MOV @R0, A ; Clear the Register.
DEC R0 ; Point to next register location.
DJNZ R7, AGAIN ; Do it AGAIN if all Registers
are not cleared.
P4: Correct (Contd.)
• R7 = 06, as after decrementing 6 times R7=0.
• R0 = 06, start from R6 and decrement to go up to R1,
so that after 6 decrements R0=0.
• Hence R0 to R7 are cleared.
• Execute both the previous programs manually to
understand the logical errors in first program and how
the data flows in second program.
• It is a good practice to manually execute some of the
assemble language programs so that such kind of
logical errors can be identified and minimized.

A Simple Program
Language Program) to copy a data block
of 8 bytes from RAM locations 50H to
70H.

P5: Copy Data Block
ORG 0000H ; Store program at 0000H.
START: MOV R0, #50H ; Initialize Source Pointer.
MOV R1, #70H ; Initialize Target Pointer.
MOV R7, #08H ; Load count in R7.
AGAIN: MOV A, @R0 ; Read from source.
MOV @R1, A ; Store at target.
INC R0 ; Increment source pointer.
INC R1 ; Increment target pointer.
DJNZ R7, AGAIN ; Do it AGAIN if all are not
copied.
END ; End of program file.

External Data MOVs
External data can be accessed (both read and write) only
indirectly and through the Accumulator only. To specify
indirect addresses R0, R1 and DPTR may be used.
MOVX A, @Rp ; Copy the content of external data location

into A, indirectly through Rp.
MOVX @Rp, A ; Copy the content of A into external data
location, indirectly through Rp.
MOVX A, @DPTR ; Copy the content of external data
location into A, indirectly through DPTR.

External Data MOVs (Contd.)
MOVX @DPTR, A ; Copy the content of A into external data
location, indirectly through Rp.
• Execution of MOVX, activates the RD / WR to access

external data RAM.
• Use of R0 and R1 can access only 28 = 256 Bytes of
external RAM only.
• Use of DPTR can access entire 64KB = 65536 Bytes of
external RAM.

A Simple Program
Language Program) to copy an array of
10 bytes from data location 8000H RAM
locations 50H.

P6: Copy External Data Array
ARRAY1 EQU 8000H
ARRAY2 EQU 50H
COUNT EQU 10
ORG 0000H
START: MOV R7, #COUNT ; Load count in R7.
MOV DPTR, #ARRAY1 ; Initialize Source Pointer.
MOV R0, #ARRAY2 ; Initialize Target Pointer.
AGAIN: MOVX A, @DPTR ; Read from source.
MOV @R0, A ; Store at target.
INC DPTR ; Increment source pointer.
DJNZ R7, AGAIN ; Do it AGAIN if all are not copied.
Code Memory MOVs
A data byte can be read out from the code memory only
indirectly and through the Accumulator only.
MOVC A, @A+PC ; Copy a code byte into A from the

address formed by adding contents
of A & PC.
* Value of PC would be the address of next instruction.
MOVC A, @A+DPTR ; Copy a code byte into A from the

address formed by adding contents
of A & DPTR.

Code Memory MOVs (Contd.)
• Execution of MOVC
• always activates the PSEN if memory to be accessed
has address > 0FFFH.
• does not activates PSEN if memory to be accessed
has address ≤ 0FFFH and EA  1 .
• always activates the PSEN if EA  0 .
• For 8052, the address limit is 1FFFH (8KB Program ROM).

A Simple Program
P7: Store a lookup table containing
square of hexadecimal digits (0 to 9 and
A to F) at code location 400H and Write
an 8051 ALP that reads hexadecimal
digit from P0 and send its square at P1,
continuously using the lookup table.

Using Look-Up Table
ADDRESS DATA Comments

• Adding the integer to
0400 00H Square of 0
base address would
give the address of
: : :
memory where square
is stored. : : :
040A 64H Square of A
040B 79H Square of B
040C :
040D :
040E :
040F E1H Square of F
P7: LOOK-UP Table
ORG 0000H
START: MOV DPTR, #LOOK_UP ; Init lookup table Pointer.
MOV A, #0FFH ; Configure P0 as input port.
MOV P0, A
AGAIN: MOV A, P0 ; Read Port 0 into A.
MOVC A, @A+DPTR ; Get square from lookup table.
MOV P2, A ; Send Square at Port 2.
SJMP AGAIN ; STOP.
ORG 400H ; Store lookup table at code location 400H.

LOOK_UP DB 0,1,4,9,16,25,36,49,64,81,100,121,144,169,196,225

A Simple Program
Language Program) to copy the string
“INDIA” from code location 500H to RAM
location 50H.

P8: String Copy
ORG 0000H
START: MOV R7, 05 ; Load count in R7.
MOV DPTR, #S_DATA ; Init Source Pointer.
MOV R0, #50H ; Init Target Pointer.
AGAIN: MOV A, #00 ; Clear A.
MOVC A, @A+DPTR ; Read from source.
MOV @R0, A ; Copy at target.
HERE: SJMP HERE ; STOP.
ORG 500H ; Store string at code location 500H.
S_DATA DB ‘I’,’N’,’D’,’I’,’A’

A Simple Program
P9: Repeat previous program with NULL
character at the end of string.

P9: String Copy with NULL Character
ORG 0000H
START: MOV DPTR, #S_DATA ; Init Source Pointer.
MOV R0, #50H ; Init Target Pointer.
AGAIN: MOV A, #00 ; Clear A.
MOVC A, @A+DPTR ; Read from source.
MOV @R0, A ; Copy at target.
JNZ AGAIN ; Is ACC=NULL i.e. 00
; NO, Do it AGAIN YES stop.
HERE: SJMP HERE ; STOP.
ORG 500H ; Store string at code location 500H.
S_DATA DB ‘I’,’N’,’D’,’I’,’A’,0

XCH - Exchange
• All the exchanges are internal to 8051 and must use A.
- XCH A, Ri ; Exchange A with Register.
- XCH A, Addr ; Exchange A with the Direct byte.
- XCH A, @Rp ; Exchange A with the Indirect byte.
- XCH A, #50 ; ERROR – Immediate data can not be
exchanged.
- XCHD A, @Rp ; Exchange lower nibble of A with indirect

byte.

PUSH & POP
• PUSH & POP accesses an area of internal RAM called
STACK with the help of Stack Pointer SP.
• Content of SP is used as an address in STACK called
STACK TOP i.e. the location from where data can be read
out from STACK.
• After the RESET, SP is Addr Data
loaded with 07. WHY? SP 08 FFH
STACK TOP
07 07 ABH
06
05 20
04 EA
PUSH & POP (Contd.)
• A read from the STACK is POP operation i.e. POPing off
the data from STACK.
• A write into the STACK is referred as a PUSH operation
i.e. PUSHing the data into the STACK.
• In 8051, every POP retrieves 8-bit data from the stack.
• In 8051, every PUSH stores 8-bit data into the stack.
• Since a STACK has to be LIFO, every PUSH nullifies the
effect of POP and vice versa.
• Both PUSH & POP uses only Direct Addressing.

PUSH & POP (Contd.)
PUSH Addr ; Incerment SP by 1 and store the direct byte
into stack. i.e. PUSH direct byte at STACK TOP.
SP ← SP + 1
((SP)) ← (Addr)
Observe execution of PUSH 05
Addr Data Addr Data

SP
SP 08 FFH 08 08 20H
07 07 ABH 07 ABH
NEW STACK
STACK TOP 06 TOP 06
05 20H 05 20H
04 EAH 04 EAH
PUSH & POP (Contd.)
POP Addr ; Copy a bye from stack to direct address and
decerment SP by 1. i.e. POP off from STACK TOP
(Addr) ← ((SP))
SP ← SP - 1
Observe execution of POP 04
SP Addr Data Addr Data

08 08 20H SP 08 20H
STACK TOP 07 ABH 07 07 ABH
06 NEW STACK 06
05 20H TOP 05 20H
04 EAH 04 20H
Program P10
Write an 8051 ALP to clear RAM

locations 50H to 5FH using PUSH
instruction.

P10: Clear RAM using PUSH
ORG 0000H
START: MOV SP, #4FH ; Load Stack Top. SP=4F because SP
is incremented before PUSH.
MOV R7, #16 ; Load count, 16 locations to be
cleared.
MOV 00, #00 ; Load Value to clear at addr 00.
AGAIN: PUSH 00 ; Clear the RAM locations.
DJNZ R7, AGAIN ; Do it AGAIN if all RAM locations
are not cleared.
END

Program P11
Write an 8051 ALP copy an array of 10

bytes from data location 8000H to data
location 9000H.

P11: Copy External RAM
• External Data can only be addressed using DPTR.
• In below program,
– DPTR holds source pointer to read data and then stores it in Stack, for next
source read.
– Target pointer is stored in R0 & R1 which is then loaded in DPTR to write the
target. After writing at target, pointer is stored back in R0 & R1 for next target
write.
ARRAY1 EQU 8000H

ARRAY2 EQU 9000H
COUNT EQU 10
ORG 0000H
START: MOV R7, #COUNT ; Load count in R7.
MOV DPTR, #ARRAY2 ; Store target Pointer in R0 & R1.
MOV R0, DPL
MOV R1, DPH
MOV DPTR, #ARRAY1 ; Initialize Source Pointer. ….. CONTD.
P11: Copy External RAM (Contd.)
AGAIN: MOVX A, @DPTR ; Read from source.
PUSH DPH ; Store DPTR in stack for next read.
PUSH DPL
MOV DPH, R1 ; Get target pointer in DPTR.
MOV DPL, R0
MOVX @DPTR, A ; Store data at target location.
INC DPTR ; Increment target pointer.
MOV R1,DPH ; Store target pointer in R0 & R1.
MOV R0, DPL
POP DPL ; Retrieve source pointer from stack.
POP DPH
Bit Manipulation Instructions
─ MOV C, bit Copy direct bit into carry.
─ MOV C, 40H ; Copy a bit from bit addressable location 40H.
─ MOV bit, C Copy carry into direct bit.
─ CLR C Clear Carry.

─ SETB C Set the Carry.
─ CPL C Complement the carry.
─ CLR bit Clear direct bit.

─ CLR 5FH ; Clear the bit at bit addressable location 5FH.
─ SETB bit Set the direct bit.
─ CPL bit Complement the direct bit.
Bit Manipulation Instructions (Contd.)
─ JC LABEL Jump to LABEL on carry i.e. if CY=1.
─ JNC LABEL Jump to LABEL on no carry i.e. if CY=0.
─ JB bit, LABEL Jump to LABEL if bit i.e. if bit=1.

─ JNB bit, LABEL Jump to LABEL if no bit i.e. if bit=0.
─ JBC bit, LABEL Jump to LABEL if bit i.e. if bit=1 and
complement the bit before jump.
Also referred as Jump to LABEL if bit=1
and clear the bit.

Program P12
A data table containing 10 data is

stored at 50H. Write an 8051 ALP to
count negative numbers in this table
and store the negative count at 60H.

P12: Count Negative Numbers
TABLE1 EQU 50H
COUNT EQU 10
ORG 0000H
START: MOV R7, #COUNT ; Count in R7.
MOV R0, #TABLE1 ; Table Pointer in R0.
MOV 60H, #00 ; Initial count at 60H.
AGAIN: MOV A, @R0 ; Get number in A.
JNB 0E7H, NEXT ; Check MS bit of A (i.e. A.7) for 1.
; Is A.7=1? NO, go to test next number
INC 60H ; YES, Increment negative count.
NEXT: INC R0 ; Point to next number in table.
DJNZ R7, AGAIN ; Do it AGAIN if all are not tested.

Addition
All the additions should be performed with A.
ADD A, OPR A  A + OPR

All the Math flags are affected.
All the addressing modes are applicable.
─ ADD A, Ri A  A + Ri
─ ADD A, #DATA8 A  A + #DATA8
─ ADD A, Addr A  A + (Addr)
─ ADD A, @Rp A  A + ((Rp))

Addition with Carry
Additions with carry is very much suitable for multibyte
arithmetic.
ADDC A, OPR A  A + OPR + CY

─ ADDC A, Ri A  A + Ri + CY
─ ADDC A, #DATA8 A  A + #DATA8 + CY
─ ADDC A, Addr A  A + (Addr) + CY
─ ADDC A, @Rp A  A + ((Rp)) + CY

Subtraction
All the subtractions should be performed with A. All the
subtractions are performed with BORROW (i.e. CY)
using 2’s complement method.
SUBB A, OPR A  A - OPR - CY

─ SUBB A, Ri A  A - Ri - CY
─ SUBB A, #DATA8 A  A - #DATA8 - CY
─ SUBB A, Addr A  A - (Addr) - CY
─ SUBB A, @Rp A  A - ((Rp)) - CY

Program P13
Two data tables are stored at 50H and

60H. Write an 8051 ALP to add the data
of these tables and store at locations
starting from 70H. Assume result of
addition is 8-bit.

P13: Table Addition
Addr Data Addr Data Addr Data

50H 91H 60H 21H 70H B2H
51H 28H 61H 57H 71H 7FH
52H 86H 62H 15H 72H 9BH
53H 45H 63H A2H 73H E7H
54H 97H + 64H 01H = 74H 98H
55H 53H 65H 35H 75H 88H
56H 98H 66H 33H 76H CBH
57H 53H 67H 47H 77H 9AH
58H 53H 68H 28H 78H 7BH
59H 44H 69H 31H 79H 75H
P13: Table Addition (Contd.)
• Only two registers R0 and R1 can be used as table pointers where as
we require three pointers to address three tables.
– We use R0 and R1 of current register bank (Bank 0) two point TABLE1 and
TABLE2 and we use R0 of next register bank (Bank 1) to point result table RES.
TABLE1 EQU 50H

TABLE2 EQU 60H
RES EQU 70H
COUNT EQU 10
ORG 0000H
MOV R0, #TABLE1 ; Init Table Pointers.
MOV R1, #TABLE2
MOV 08H, #RES ; R0 of Bank1 as result pointer. …..Contd.

P13: Table Addition (Contd.)
AGAIN: MOV A, @R0 ; Add two data bytes.
ADD A, @R1
INC R0 ; Provision for next data in tables.
INC R1
SETB RS0 ; Switch to Bank1.
MOV @R0, A ; Store the result of addition.
INC R0 ; Provision for next result byte.
CLR RS0 ; Switch back to Bank0.
DJNZ R7, AGAIN ; Repeat if all bytes are not added.

DAA – Decimal Adjust Accumulator
DA A A ← BCD (A) after ADD

– Used after ADD instruction.
– Checks both the Nibbles of Accumulator
• Lower Nibble > 9 OR Flag AC=1 then
Lower Nibble ← Lower Nibble + 6
• Higher Nibble > 9 OR Flag CY=1 then
Higher Nibble ← Higher Nibble + 6

P14: BCD Addition
BCD1 EQU 55H
BCD2 EQU 39H
ORG 0000H
START: MOV A, #BCD1 ; Get first BCD in A
ADD A, #BCD2 ; Perform binary addition.
DA A ; Adjust the result for BCD.
MOV 20H, A ; Store result at 20H
END
Note: DAA adjusts for BCD, only & only when addition (ADD)
was done on Valid BCD No.

P15: BCD Subtraction
LOGIC: BCD1 – BCD2 = BCD1 + 10’s Complement of BCD2
BCD1 EQU 50H

BCD2 EQU 39H
ORG 0000H
START: MOV R0, #BCD2 ; Get first BCD in A
MOV A, #99H
CLR C
SUBB A, R0 ; 9’s complement of BCD2.
ADD A, #01 ; 10’s complement of BCD2.
DA A ; Adjust 10’s complement for BCD.
ADD A, #BCD1 ; Perform decimal subtraction.
DA A ; Adjust the result of subtraction for BCD.
MOV 20H, A ; Store result at 20H.
END
Multiplication
Multiplication is performed with registers A & B only.
MUL AB
B-A A*B
A  Lower byte of product.
B  Higher byte of product.
After multiplication
─ CY = 0, always.
─ If OV = 0, result ≤ FFH i.e. result is 8-bit only and B=0.
─ If OV = 1, result > FFH i.e. result is 16-bit.

P16: Factorial of an Integer
NUM EQU 5
ORG 0000H
START: MOV A, #01 ; Initial Factorial in A.
MOV R2, #NUM ; Get integer in R2.
AGAIN: MOV B, R2 ; Get multiplicand in B.
MUL AB ; Perform multiplication.
DJNZ R2, AGAIN ; Get multiplicand for next iteration
MOV 20H, A ; Store the result of factorial.
Using MUL as above only up to 6! can be obtained.

Division
Division is performed with registers A & B only.
DIV AB
Operation performed is A/B
A  Quotient after division.
B  Remainder after division.
After division
─ CY = 0, always.
─ If OV = 0, Normal division.
─ If OV = 1, Divide by zero.

Misc. with Accumulator
SWAP A Swap the nibbles of Accumulator.
if A = 5F
after SWAP A
A = F5
CLR A Clear the Accumulator.

after CLR A
A = 00
CPL A Complement the Accumulator.

if A = 01
after CPL A
A = FE
Rotate Accumulator Left
• RLC A Rotate Acc Left through Carry

CY ← A7, A7 ← A6, ….. A1 ← A0 , A0 ← CY
CY A7 A6 A5 A4 A3 A2 A1 A0
• RL A Rotate Acc Left without Carry

CY ← A7, A7 ← A6, ….. A1 ← A0 , A0 ← A7
CY A7 A6 A5 A4 A3 A2 A1 A0
Rotate Accumulator Right
• RRC A Rotate Acc Right through Carry

CY  A7, A7  A6, ….. A1  A0 , A0  CY
CY A7 A6 A5 A4 A3 A2 A1 A0
• RR A Rotate Acc Right without Carry

A7  A6, ….. A1  A0 , A0  A7 , A0  CY
CY A7 A6 A5 A4 A3 A2 A1 A0
Program P17
A data table containing 10 data is

stored at 50H. Write an 8051 ALP to
count odd numbers in this table and
store the odd count at 60H.

P17: Count ODD Numbers
TABLE1 EQU 50H
COUNT EQU 10
ORG 0000H
MOV R0, #TABLE1 ; Table Pointer in R0.
MOV 60H, #00 ; Initial count at 60H.
AGAIN: MOV A, @R0 ; Get number in A.
RR A ; Get LS bit in carry flag.
JNC NEXT ; Check carry for 1.
; Is CY=1? NO, go to test next number
INC 60H ; YES, Increment ODD count.
NEXT: INC R0 ; Point to next number in table.
DJNZ R7, AGAIN ; Do it AGAIN if all are not tested.

Logical ANDing
ANL A, OPR A  A AND OPR
None of the Math flags are affected.
─ ANL A, Ri A  A AND Ri
─ ANL A, #DATA8 A  A AND #DATA8
─ ANL A, Addr A  A AND (Addr)
─ ANL A, @Rp A  A AND ((Rp))
Special ANDing.
─ ANL Addr, A (Addr)  (Addr) AND A
─ ANL Addr, #DATA8 (Addr)  (Addr) AND #DATA8

Logical ORing
ORL A, OPR A  A OR OPR
─ ORL A, Ri A  A OR Ri
─ ORL A, #DATA8 A  A OR #DATA8
─ ORL A, Addr A  A OR (Addr)
─ ORL A, @Rp A  A OR ((Rp))
Special ORing.
─ ORL Addr, A (Addr)  (Addr) OR A
─ ORL Addr, #DATA8 (Addr)  (Addr) OR #DATA8

Logical XORing
XRL A, OPR A  A XOR OPR
─ XRL A, Ri A  A XOR Ri
─ XRL A, #DATA8 A  A XOR #DATA8
─ XRL A, Addr A  A XOR (Addr)
─ XRL A, @Rp A  A XOR ((Rp))
Special XORing.
─ XRL Addr, A (Addr)  (Addr) XOR A
─ XRL Addr, #DATA8 (Addr)  (Addr) XOR #DATA8

Program P18
Write an 8051 ALP to unpack a packed
BCD number stored at 50H. Store the
unpacked digits (lower digit) at 51H
and (upper digit) 52H.
Packed BCD Unpacked BCD

0 0 1 1 0 1 0 1 U U U U 0 1 0 1
3 5 UUUU 5
U U U U 0 0 1 1
UUUU 3

P18: Packed to Unpacked
ORG 0000H
START: MOV A, 50H ; Packed BCD in A i.e. A=35.
ANL A, #0FH ; Mask off upper nibble i.e. A=05.
MOV 51H, A ; Store lower digit at 51H.
MOV A, 50H ; Packed BCD in A i.e. A=35.
ANL A, #0F0H ; Mask off lower nibble i.e. A=30.
SWAP A ; Adjust digit in A i.e. A=03.
MOV 52H, A ; Store upper digit at 52H.

Program P19
Write an 8051 ALP to pack the two
unpacked BCD digits stored at 51H and
50H. Store the packed BCD at 50H.
Unpacked BCD Packed BCD
U U U U 0 1 0 1 0 0 1 1 0 1 0 1
UUUU 5 3 5
U U U U 0 0 1 1
UUUU 3

P19: Unpacked to Packed
ORG 0000H
START: MOV A, 52H ; Get upper digit i.e. A=03.
SWAP A ; Adjust upper digit in A i.e. A=30.
MOV R0, A ; Upper digit in R0 i.e. R0=30.
MOV A, 51H ; Get lower digit i.e. A=05.
ORL A, R0 ; Pack the BCD digits i.e. A=35.
MOV 50H, A ; Store packed BCD at 50H.

Misc. Bit level Logical Operation
ANL C, bit CY  CY AND bit

ANL C, bit CY  CY AND bit
ORL C, bit CY  CY OR bit

ORL C, bit CY  CY OR bit

Comparison
CJNE – Compare and jump if not equal to.
CJNE OPR1, OPR2, LABEL

Compare OPR1 & OPR2 and jump to LABEL if
OPR1  OPR2.
CY= 0 if OPR1  OPR2

CY= 1 if OPR1  OPR2
─ CJNE A, Addr, LABEL
─ CJNE A, #DATA8, LABEL
─ CJNE Ri, #DATA8, LABEL
─ CJNE @Rp, #DATA8, LABEL

Program P20
A data table containing 10 data items

is stored at 50H. Write an 8051 ALP to
find largest number from this table and
store at 60H.

P20: Largest Number (Contd.)
• We have to write our program with the options available with
CJNE.
– We load register B with smallest number i.e. B=00.
– We read the data from table into A.
– After comparison, if number in A>B then greater number is shifted in B.
– After execution of program, register B holds the largest number.
TABLE1 EQU 50H

COUNT EQU 10
ORG 0000H
MOV R0, #TABLE1 ; Init Table Pointers.
MOV B, #00 ; B=00 for initial comparison.
…..Contd.

P20: Largest Number (Contd.)
AGAIN: MOV A, @R0 ; Get data from table in A.
CJNE A, B, DN1 ; Compare A & B.
DN1: JC NEXT ; Is A  B? NO, go to test next data.
MOV B, A ; YES, get largest in B.
NEXT: INC R0 ; Provision to test next data item.
DJNZ R7, AGAIN ; Compare again if all are not tested.
MOV 60H, B ; Store largest number.
Try for smallest number in the table.

Final Word on JUMPs
There are three type of JUMPs in 8051.
1. Short Jump - Adds an 8-bit 2’s complement number to
Program counter. So it is a relative jump. It can jump 127
bytes in forward direction and 128 bytes in reverse
direction.
– All the conditional jumps in 8051 are conditional jump.
– Length of the instruction is 2-bytes.
2. Absolute Jump – It’s a modulo 2KB absolute jump. It
can jump within the current 2KB memory page.
– AJMP Addr
3. Long Jump – It can jump anywhere in memory map i.e.
complete 64KB jump is possible.
– LJMP Addr
Calling Subroutines & Return
There are two type of CALLs in 8051.
1. Absolute CALL – It’s a modulo 2KB absolute call. It can
call a subroutine anywhere within the current 2KB memory
page.
– ACALL Addr
– PUSHes two byte return address in STACK.
2. Long CALL – It can call a subroutine stored anywhere in
the 64 KB memory map.
– LCALL Addr
– PUSHes two byte return address in STACK.
3. Return – It retrieves two byte return address from
STACK TOP and returns to the caller.
– RET
– POP off two byte return address from STACK.

USEFUL PROGRAMS
SOME PRACTICALLY USEFUL

PROFRAMS

Program P21
Write an 8051 subroutine to convert a
BCD number stored at 50H into Binary.
Store the Binary at 51H.
Let the BCD in 8-bit = 98

= 9*10 + 8
= 9*A + 8
= 5A + 8
= 62H

P21: BCD to Binary
BCD_BIN: PUSH A ; Store registers in stack before using.
PUSH B
PUSH R0
MOV A, 50H ; Get BCD in A i.e. A=98.
ANL A, #0F0H ; Mask off lower nibble i.e. A=90.
SWAP A ; Adjust digit in A i.e. A=09.
MOV B, #0AH ; Get multiplier in B.
MUL AB ; A = A * B = 09*0A = 5AH
MOV R0, A ; Store in R0 for later use, R0=5A.
MOV A, 50H ; Get BCD again in A i.e. A=98.
ADD A, R0 ; Get binary i.e. A=62H.
MOV 51H, A ; Store binary at 51H.
POP R0 ; Retrieve registers from stack.
POP B
POP A
RET ; Back to caller.
Program P22
Write an 8051 subroutine to convert a
Binary number stored at 60H into BCD.
Store the BCD at 61H & 62H.
Let the 8-bit Binary is = FEH = 254 BCD

Q R
FEH/A 19H 04 1st BCD Digit
19H/A 02 05 2nd BCD Digit
02/A 00 02 3rd BCD Digit
For 254BCD, store 54 at 61H and 02 at 62H.
Note that 3rd division is not necessary. After second division,
quotient itself is highest digit.
P22: Binary to BCD
BIN_BCD: PUSH A ; Store registers in stack before using.
PUSH B
PUSH R0
MOV A, 60H ; Get Binary in A i.e. A=FEH.
MOV B, #0AH ; Get divisor in B i.e. B=0A.
DIV AB ; 1st Division, A=19H & B=04.
MOV R0, B ; Store in R0 for later use, R0=04.
MOV B, #0AH ; Get divisor in B.
DIV AB ; 2nd Division, A=02H & B=05.
MOV 62H, A ; Store highest BCD digit at 62H.
MOV A, B ; Get 2nd BCD digit in A i.e. A=05.
SWAP A ; Adjust 2nd BCD digit in A i.e. A=50.
ORL A, R0 ; Combine BCD digits i.e. A=54H.
MOV 51H, A ; Store lower BCD digits at at 61H.
POP R0 ; Retrieve registers from stack.
POP B
POP A
Program P23
5 BCD nibbles are stored in memory

from 50H to 54H. Write a program that
converts these BCD nibbles into ASCII
codes and store them in memory from
50H to 54H.

P23: BCD to ASCII
BCD Nibbles ASCII Codes
ADDRESS DATA ADDRESS DATA

50H 06 50H 36H
51H 05 51H 35H
52H 00 52H 30H
53H 01 53H 31H
54H 07 54H 37H
ASCII Code of 0 = 30H

So ASCII of 7 = 30H + 07 = 37H

P23: BCD to ASCII (Contd.)
BCD_ASCII:
PUSH R0
PUSH R6
PUSH A
MOV R6,#05 ; Initialize Counter.
MOV R0,#50H ; Initialize Memory Pointer.
NEXT: MOV A,@R0 ; Get BCD into A.
ADD A,#30H ; Convert to ASCII.
MOV @R0,A ; Store ASCII into memory.
INC R0 ; Point to next BCD
DJNZ R6,NEXT ;Go back if not done.
POP A
POP R6
POP R0
RET ; Back to caller

ASCII Code Look-Up Table
• Base Address of the ADDRESS DATA Comments
Look-Up Table is 2600. 25FFH 30H ASCII of 0
• Adding the Hex integer to 2600H 31H ASCII of 1
base address would give : : :

the address of memory 2604H 35H ASCII of 5
where the corresponding : : :
ASCII code is stored. 2608H 39H ASCII of 9
2609H 41H ASCII of A
• Subtracting the base
address of table from the 260AH 42H ASCII of B
memory location of code 260BH 43H ASCII of C

gives Hex Integer 260CH 44H ASCII of D
corresponding to the 260DH 45H ASCII of E
given ASCII code. 260EH 46H ASCII of F
Program P24
ASCII table of hexadecimal integers is

stored at code location 25FFH. Write a
subroutine that find out the ASCII code
of an integer stored at location 50H
and store the obtained ASCII code at
location 51H.

P24: HEXADECIMAL to ASCII
TO_ASCII:
PUSH A
MOV DPTR, #LOOK_UP ; Init lookup table Pointer.
MOV A, 50H ; Get Hex integer in A.
MOVC A, @A+DPTR ; Get ASCII from lookup table.
MOV 51, A ; Store ASCII code 51H.
POP A

Program P25
An ASCII code is stored at location

51H. Write a subroutine that finds out
hexadecimal integer corresponding to
this code and store it at location 50H.
Use the ASCII look up table of
hexadecimal integers stored at code
location 25FFH.

P25: ASCII to HEXADECIMAL
TO_HEX:
PUSH A
PUSH B
PUSH R0
MOV DPTR, #LOOK_UP ; Init lookup table Pointer.
MOV R0, DPL ; Lower byte of base address in R0
MOV B, 51H ; Get ASCII code in B.
BACK: CLR A
MOVC A, @A+DPTR ; Get ASCII from lookup table.
CJNE A, B, NEXT ; Compare ASCII code for equal.
SJMP HEX_INT ; Codes are equal, go to get HEX
NEXT: INC DPTR ; Code not found search again.
SJMP BACK

P25: ASCII to HEXADECIMAL
HEX_INT: CLR C
MOV A, DPL ; Lower byte of current DPTR in A.
SUBB A, R0 ; Subtract with lower byte of base addr.
MOV 50H, A ; Store hexadecimal integer at 50H.
POP R0
POP B
POP A

02 Introduction To Microcontrollers

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

02 Introduction To Microcontrollers

Hochgeladen von

Copyright:

Verfügbare Formate

MCS – 51

An Introduction to 8051 – Manish Tiwari 2

Simplified Logic Diagram

An Introduction to 8051 – Manish Tiwari 3

An Introduction to 8051 – Manish Tiwari 4

• ROM less parts are advantageous in development cycle of an embedded

Program Memory Type Memory Capacity

An Introduction to 8051 – Manish Tiwari 8

• Initially Capacitor is discharged.

• XTAL 1 is input to input to inverting oscillator amplifier and XTAL 2

An Introduction to 8051 – Manish Tiwari 10

Program memory interface

Data memory interface

An Introduction to 8051 – Manish Tiwari 11

• Two memory interfaces (Program & Data) making it Harvard Architecture.

Available to User 000H

An Introduction to 8051 – Manish Tiwari 13

An Introduction to 8051 – Manish Tiwari 14

An Introduction to 8051 – Manish Tiwari 15

An Introduction to 8051 – Manish Tiwari 16

An Introduction to 8051 – Manish Tiwari 17

SM0D - - - GF1 GF0 PD IDL

SM0D PCON.7 Serial baud rate modify bit.

Embedded Systems – Manish Tiwari 18

An Introduction to 8051 – Manish Tiwari 19

An Introduction to 8051 – Manish Tiwari 20

An Introduction to 8051 – Manish Tiwari 21

An Introduction to 8051 – Manish Tiwari 22

CY (Carry) - 1, if carry generated during arithmetic operation else set to

An Introduction to 8051 – Manish Tiwari 24

MOV R5, R7 ; Error - Ri to Ri is not allowed.

An Introduction to 8051 – Manish Tiwari 28

An Introduction to 8051 – Manish Tiwari 31

An Introduction to 8051 – Manish Tiwari 32

MOV Ri, A MOV @Rp, A

An Introduction to 8051 – Manish Tiwari 36

An Introduction to 8051 – Manish Tiwari 37

* There is no decrement for DPTR.

An Introduction to 8051 – Manish Tiwari 38

An Introduction to 8051 – Manish Tiwari 40

An Introduction to 8051 – Manish Tiwari 41

An Introduction to 8051 – Manish Tiwari 42

An Introduction to 8051 – Manish Tiwari 45

An Introduction to 8051 – Manish Tiwari 46

END ; End of program file.

MOVX A, @Rp ; Copy the content of external data location

An Introduction to 8051 – Manish Tiwari 48

• Execution of MOVX, activates the RD / WR to access

An Introduction to 8051 – Manish Tiwari 49

An Introduction to 8051 – Manish Tiwari 50

MOVC A, @A+PC ; Copy a code byte into A from the

MOVC A, @A+DPTR ; Copy a code byte into A from the

An Introduction to 8051 – Manish Tiwari 52

• For 8052, the address limit is 1FFFH (8KB Program ROM).

An Introduction to 8051 – Manish Tiwari 53

An Introduction to 8051 – Manish Tiwari 54

ADDRESS DATA Comments

ORG 400H ; Store lookup table at code location 400H.

An Introduction to 8051 – Manish Tiwari 56

An Introduction to 8051 – Manish Tiwari 57

An Introduction to 8051 – Manish Tiwari 58

An Introduction to 8051 – Manish Tiwari 59

An Introduction to 8051 – Manish Tiwari 60