Mnemonics Assembler Editor AMAC EASMD # MAC/65 SynAssemblerATMAS I & IIEdit 6502 DATASM/65130XE Macro-Assembler # MADS

ADC 1 1 1 1 1 1
ANC *
AND 1 1 1 1 1 1
ARR *
ASL 1 1 1 1 1 1
ASR
ASX *
AX7 *
AXE *
BCC 1 1 1 1 1 1
BCS 1 1 1 1 1 1
BEQ 1 1 1 1 1 1
BIT 1 1 1 1 1 1
BMI 1 1 1 1 1 1
BNE 1 1 1 1 1 1
BPL 1 1 1 1 1 1
BRA ! 1
BRK 1 1 1 1 1 1
BVC 1 1 1 1 1 1
BVS 1 1 1 1 1 1
CLC 1 1 1 1 1 1
CLD 1 1 1 1 1 1
CLI 1 1 1 1 1 1
CLV 1 1 1 1 1 1
CMP 1 1 1 1 1 1
CPX 1 1 1 1 1 1
CPY 1 1 1 1 1 1
DEA ! 1
DCP *
DEC 1 1 1 1 1 1
DEX 1 1 1 1 1 1
DEY 1 1 1 1 1 1
EOR 1 1 1 1 1 1
INA ! 1
INC 1 1 1 1 1 1
INX 1 1 1 1 1 1
INY 1 1 1 1 1 1
ISB *
JAM *
JMP 1 1 1 1 1 1
JSR 1 1 1 1 1 1
LAS *
LAX *
LDA 1 1 1 1 1 1
LDX 1 1 1 1 1 1
LDY 1 1 1 1 1 1
LSR 1 1 1 1 1 1
NOP 1 1 1 1 1 1
ORA 1 1 1 1 1 1
PHA 1 1 1 1 1 1
PHP 1 1 1 1 1 1
PHX ! 1
PHY ! 1
PLA 1 1 1 1 1 1
PLP 1 1 1 1 1 1
PLX ! 1
PLY ! 1
RLA *
ROL 1 1 1 1 1 1
ROR 1 1 1 1 1 1
RRA *
RTI 1 1 1 1 1 1
RTS 1 1 1 1 1 1
SAX *
SBC SBC * 1 1 1 1 1 1
SEC 1 1 1 1 1 1
SED 1 1 1 1 1 1
SEI 1 1 1 1 1 1
SRA *
SLO *
STA 1 1 1 1 1 1
STX 1 1 1 1 1 1
STY 1 1 1 1 1 1
STZ ! 1
SX7 *
SY7 *
TAX 1 1 1 1 1 1
TAY 1 1 1 1 1 1
TRB ! 1
TSB ! 1
TSX 1 1 1 1 1 1
TXA 1 1 1 1 1 1
TXS 1 1 1 1 1 1
TYA 1 1 1 1 1 1
XEA *
XS7 *

Summe: 86 56 56 56 66 56 0 0 0 56 0
Prozent: 65.12% 65.12% 65.12% 76.74% 65.12% 0.00% 0.00% 0.00% 65.12% 0.00%

* Undocumented instruction. The behavior of these opcodes was observed on an Atari 800. It may vary with other 6502-based CPU's.
# OpCodes not in manual => assumption of standard MOS 6502 commands
! OpCodes for 65C02 processors on

$C000 for Mosaic Card

CHAPT
ER 7:
ADDED
65C02
INSTR
UCTIO
NS

MAC/65 as 
originall
y 
produced, 
supported 
the 
"standard
" 6502 
instructi
on set as 
well as 
the 
directive
s and 
addressin
g mode 
designato
rs 
recommend
ed by MOS 
Technolog
y (the 
originato
rs of the 
6502 
by NCR 
chip).
Corporati
on. We 
describe 
here the 
primary 
added 
addressin
g mode, 
the 
instructi
on with 
variants 
added, 
and the 
completel
y new 
instructi
ons. But 
before we 
start, we 
should 
note that 
these 
instructi
ons would 
only work 
properly 
on your 
computer 
if you 
chapter 6 Table of Contents

Sectio
n 7.1   
(A Major 
Added 
Addressi
ng Mode)

The 
standard 
6502 chip 
supports 
two forms 
of 
indirect 
addressin
g for 
what 
might be 
considere
d its 
primary 
instructi
ons. The 
forms 
appear in 
assembly 
listings 
as:
  lda 
(indirect
,X)
    and
  lda 
(indirect
,Y)

(where 
"lda" is 
only one 
of 
several 
valid 
mnemonics 
that can 
be used 
with 
these 
addressin
g modes).
­Y" mode, 
is 
perhaps 
the most 
useful 
and 
flexible 
of all 
6502 
addressin
g modes. 
And, yet, 
it 
suffers 
from one 
flaw: it 
ties up 
two 
registers 
(A and 
Y). And, 
as 
important
ly, 
probably 
a full 
50% or 
more of 
the time 
the Y­
register 
The NCR 
6502 
instructi
ons set 
as 
supported 
by MAC/65 
provides 
a help 
here: You 
may code 
instructi
ons 
allowing 
Indirect­
Y 
addressin
g in 
"Indirect
" mode as 
well. 
With 
Indirect 
mode, the 
assembler 
format is 
simply
  lda 
(indirect
)
where, as 
with 
Indirect­
Y, the 
indirect 
location 
must be 
in zero 
page.
Generally
, the 
effect of 
using 
this 
instructi
on will 
be the 
same as 
coding 
the 
sequence:
  LDY #0
  lda 
(indirect
),Y
EXCEPTING 
that the 
Y­
register 
remains 
intact 
and 
untouched 
and may 
be used 
for other 
purposes. 
The 
following
, then, 
are ALL 
of the 
65C02 
instructi
ons which 
allow and 
support 
this new 
addressin
g mode:
  ADC 
(indirect
)  ;ADd 
with 
Carry
  AND 
(indirect
)  ;bit 
wise AND
  CMP 
(indirect
)  
;compare 
with A­
reg
  EOR 
(indirect
)  
;Exclusiv
e OR
  LDA 
(indirect
)  ;LoaD 
the A­
register
  ORA 
(indirect
)  
;inclusiv
e OR
  SBC 
(indirect
)  
;SuBtract 
with 
Carry
  STA 
(indirect
)  ;STore 
the A­
register
REMINDER: 
while the 
"indirect
" 
location 
may be 
any zero 
page 
location, 
you 
should 
probably 
restrict 
yourself 
to the 
available 
locations 
documente
d in the 
DDT 
manual. 
 OpCode OpCode Atari Assembler AMAC EASMD MAC/65SynAssemblerATMAS I & IIE dit 6502DATASM/65 MADS
DEZ HEX BIN OCT PEN ROM (original) from Excel 2013
(Vorschlag)
BRK BR K
0 00 00000000 00000000 0 - 1 1 1 1 1 =BASIS(A2;5)
a a
BPL BPL
1 01 00000001 00000001 1 I 1 1 1 1 1
r r
JSR JSR
2 02 00000010 00000002 2 II 1 1 1 1 1
a a
BMI BMI
3 03 00000011 00000003 3 III 1 1 1 1 1
r r
RT I RT I
4 04 00000100 00000004 4 IV 1 1 1 1 1
s s
BVC BVC
5 05 00000101 00000005 10 V 1 1 1 1 1
r r
RTS RTS
6 06 00000110 00000006 11 VI 1 1 1 1 1
s s
BVS BVS
7 07 00000111 00000007 12 VII 1 1 1 1 1
r r
BRA BR A
8 08 00001000 00000010 13 VIII 1
r• r•
BC C BCC
9 09 00001001 00000011 14 IX 1 1 1 1 1
r r
LDY LDY
10 0A 00001010 00000012 20 X 1 1 1 1 1
# #
BCS BC S
11 0B 00001011 00000013 21 XI 1 1 1 1 1
r r
CPY CPY
12 0C 00001100 00000014 22 XII 1 1 1 1 1
# #
BNE BN E
13 0D 00001101 00000015 23 XIII 1 1 1 1 1
r r
CPX CPX
14 0E 00001110 00000016 24 XIV 1 1 1 1 1
# #
BEQ BEQ
15 0F 00001111 00000017 30 XV 1 1 1 1 1
r r
ORA ORA
16 10 00010000 00000020 31 XVI 1 1 1 1 1
(zp,x) (zp,x)
ORA ORA
17 11 00010001 00000021 32 XVII 1 1 1 1 1
(zp),y (zp),y
AN D AND
18 12 00010010 00000022 33 XVIII 1 1 1 1 1
(zp,x) (zp,x)
AN D AND
19 13 00010011 00000023 34 XIX 1 1 1 1 1
(zp),y (zp),y
40 EOR EOR
20 14 00010100 00000024 XX 1 1 1 1 1
(zp,x) (zp,x)
41 EOR EOR
21 15 00010101 00000025 XXI 1 1 1 1 1
(zp),y (zp),y
42 AD C ADC
22 16 00010110 00000026 XXII 1 1 1 1 1
(zp,x) (zp,x)
43 AD C ADC
23 17 00010111 00000027 XXIII 1 1 1 1 1
(zp),y (zp),y
44 STA STA
24 18 00011000 00000030 XXIV 1 1 1 1 1
(zp,x) (zp,x)
100 STA STA
25 19 00011001 00000031 XXV 1 1 1 1 1
(zp),y (zp),y
101 LDA LDA
26 1A 00011010 00000032 XXVI 1 1 1 1 1
(zp,x) (zp,x)
102 LDA LDA
27 1B 00011011 00000033 XXVII 1 1 1 1 1
(zp),y (zp),y
103 CMP CMP
28 1C 00011100 00000034 XXVIII 1 1 1 1 1
(zp,x) (zp,x)
104 CMP CMP
29 1D 00011101 00000035 XXIX 1 1 1 1 1
(zp),y (zp),y
110 SBC SBC
30 1E 00011110 00000036 XXX 1 1 1 1 1
(zp,x) (zp,x)
111 SBC SBC
31 1F 00011111 00000037 XXXI 1 1 1 1 1
(zp),y (zp),y
32 20 00100000 00000040 112 XXXII
113 ORA ORA
33 21 00100001 00000041 XXXIII 1
(zp) ∗ (zp) ∗
34 22 00100010 00000042 114 XXXIV
120 AN D AND
35 23 00100011 00000043 XXXV 1
(zp) ∗ (zp) ∗
36 24 00100100 00000044 121 XXXVI
122 EOR EOR
37 25 00100101 00000045 XXXVII 1
(zp) ∗ (zp) ∗
38 26 00100110 00000046 123 XXXVIII
124 AD C ADC
39 27 00100111 00000047 XXXIX 1
(zp) ∗ (zp) ∗
40 28 00101000 00000050 130 XL
131 STA STA
41 29 00101001 00000051 XLI 1
(zp) ∗ (zp) ∗
132 LDX LDX
42 2A 00101010 00000052 XLII 1 1 1 1 1
#∗ #∗
133 LDA LDA
43 2B 00101011 00000053 XLIII 1
(zp) ∗ (zp) ∗
44 2C 00101100 00000054 134 XLIV
140 CMP CMP
45 2D 00101101 00000055 XLV 1
(zp) ∗ (zp) ∗
46 2E 00101110 00000056 141 XLVI
142 SBC SBC
47 2F 00101111 00000057 XLVII 1
(zp) ∗ (zp) ∗
48 30 00110000 00000060 143 XLVIII
49 31 00110001 00000061 144 XLIX
50 32 00110010 00000062 200 L
51 33 00110011 00000063 201 LI
52 34 00110100 00000064 202 LII
53 35 00110101 00000065 203 LIII
54 36 00110110 00000066 204 LIV
55 37 00110111 00000067 210 LV
56 38 00111000 00000070 211 LVI
57 39 00111001 00000071 212 LVII
58 3A 00111010 00000072 213 LVIII
59 3B 00111011 00000073 214 LIX
60 3C 00111100 00000074 220 LX
61 3D 00111101 00000075 221 LXI
62 3E 00111110 00000076 222 LXII
63 3F 00111111 00000077 223 LXIII
224 T SB TSB
64 40 01000000 00000100 LXIV 1
zp • zp •
230 TR B TRB
65 41 01000001 00000101 LXV 1
zp • zp •
231 BIT BIT
66 42 01000010 00000102 LXVI 1 1 1 1 1
zp zp
232 BIT BIT
67 43 01000011 00000103 LXVII 1
zp,x • zp,x •
68 44 01000100 00000104 233 LXVIII
69 45 01000101 00000105 234 LXIX
240 ST Z STZ
70 46 01000110 00000106 LXX 1
zp • zp •
241 ST Z STZ
71 47 01000111 00000107 LXXI 1
zp,x • zp,x •
242 STY STY
72 48 01001000 00000110 LXXII 1 1 1 1 1
zp zp
243 STY STY
73 49 01001001 00000111 LXXIII 1 1 1 1 1
zp,x zp,x
244 LDY LDY
74 4A 01001010 00000112 LXXIV 1 1 1 1 1
zp zp
300 LDY LDY
75 4B 01001011 00000113 LXXV 1 1 1 1 1
zp,x zp,x
301 CPY CPY
76 4C 01001100 00000114 LXXVI 1 1 1 1 1
zp zp
77 4D 01001101 00000115 302 LXXVII
303 CPX CPX
78 4E 01001110 00000116 LXXVIII 1 1 1 1 1
zp zp
79 4F 01001111 00000117 304 LXXIX
310 ORA ORA
80 50 01010000 00000120 LXXX 1 1 1 1 1
zp zp
311 ORA ORA
81 51 01010001 00000121 LXXXI 1 1 1 1 1
zp,x zp,x
312 AN D AND
82 52 01010010 00000122 LXXXII 1 1 1 1 1
zp zp
313 AN D AND
83 53 01010011 00000123 LXXXIII 1 1 1 1 1
zp,x zp,x
314 EOR EOR
84 54 01010100 00000124 LXXXIV 1 1 1 1 1
zp zp
320 EOR EOR
85 55 01010101 00000125 LXXXV 1 1 1 1 1
zp,x zp,x
321 AD C ADC
86 56 01010110 00000126 LXXXVI 1 1 1 1 1
zp zp
322 AD C ADC
87 57 01010111 00000127 LXXXVII 1 1 1 1 1
zp,x zp,x
323 STA STA
88 58 01011000 00000130 LXXXVIII 1 1 1 1 1
zp zp
324 STA STA
89 59 01011001 00000131 LXXXIX 1 1 1 1 1
zp,x zp,x
330 LDA LDA
90 5A 01011010 00000132 XC 1 1 1 1 1
zp zp
331 LDA LDA
91 5B 01011011 00000133 XCI 1 1 1 1 1
zp,x zp,x
332 CMP CMP
92 5C 01011100 00000134 XCII 1 1 1 1 1
zp zp
333 CMP CMP
93 5D 01011101 00000135 XCIII 1 1 1 1 1
zp,x zp,x
334 SBC SBC
94 5E 01011110 00000136 XCIV 1 1 1 1 1
zp zp
340 SBC SBC
95 5F 01011111 00000137 XCV 1 1 1 1 1
zp,x zp,x
341 ASL ASL
96 60 01100000 00000140 XCVI 1 1 1 1 1
zp zp
342 ASL ASL
97 61 01100001 00000141 XCVII 1 1 1 1 1
zp,x zp,x
343 ROL ROL
98 62 01100010 00000142 XCVIII 1 1 1 1 1
zp zp
344 ROL ROL
99 63 01100011 00000143 XCIX 1 1 1 1 1
zp,x zp,x
400 LSR LSR
100 64 01100100 00000144 C 1 1 1 1 1
zp zp
401 LSR LSR
101 65 01100101 00000145 CI 1 1 1 1 1
zp,x zp,x
402 ROR ROR
102 66 01100110 00000146 CII 1 1 1 1 1
zp zp
403 ROR ROR
103 67 01100111 00000147 CIII 1 1 1 1 1
zp,x zp,x
404 ST Z STZ
104 68 01101000 00000150 CIV 1 1 1 1 1
zp zp
410 ST Z STZ
105 69 01101001 00000151 CV 1 1 1 1 1
zp,y zp,y
411 LDX LDX
106 6A 01101010 00000152 CVI 1 1 1 1 1
zp zp
412 LDX LDX
107 6B 01101011 00000153 CVII 1 1 1 1 1
zp,y zp,y
413 DEC D EC
108 6C 01101100 00000154 CVIII 1 1 1 1 1
zp zp
414 DEC D EC
109 6D 01101101 00000155 CIX 1 1 1 1 1
zp,x zp,x
420 INC INC
110 6E 01101110 00000156 CX 1 1 1 1 1
zp zp
421 INC INC
111 6F 01101111 00000157 CXI 1 1 1 1 1
zp,x zp,x
422 RMB0 RB0
112 70 01110000 00000160 CXII
zp • zp •
423 RMB1 RB1
113 71 01110001 00000161 CXIII
zp • zp •
424 RMB2 RB2
114 72 01110010 00000162 CXIV
zp • zp •
430 RMB3 RB3
115 73 01110011 00000163 CXV
zp • zp •
431 RMB4 RB4
116 74 01110100 00000164 CXVI
zp • zp •
432 RMB5 RB5
117 75 01110101 00000165 CXVII
zp • zp •
433 RMB6 RB6
118 76 01110110 00000166 CXVIII
zp • zp •
434 RMB7 RB7
119 77 01110111 00000167 CXIX
zp • zp •
440 SMB0 SB0
120 78 01111000 00000170 CXX
zp • zp •
441 SMB1 SB1
121 79 01111001 00000171 CXXI
zp • zp •
442 SMB2 SB2
122 7A 01111010 00000172 CXXII
zp • zp •
443 SMB3 SB3
123 7B 01111011 00000173 CXXIII
zp • zp •
444 SMB4 SB4
124 7C 01111100 00000174 CXXIV
zp • zp •
1000 SMB5 SB5
125 7D 01111101 00000175 CXXV
zp • zp •
1001 SMB6 SB6
126 7E 01111110 00000176 CXXVI
zp • zp •
1002 SMB7 SB7
127 7F 01111111 00000177 CXXVII
zp • zp •
1003 PHP PH P
128 80 10000000 00000200 CXXVIII 1 1 1 1 1
s s
1004 CLC CLC
129 81 10000001 00000201 CXXIX 1 1 1 1 1
i i
1010 PLP PLP
130 82 10000010 00000202 CXXX 1 1 1 1 1
s s
131 83 10000011 00000203 1011 CXXXI SEC I SEC I 1 1 1 1 1
1012 PHA PH A
132 84 10000100 00000204 CXXXII 1 1 1 1 1
s s
1013 CLI C LI
133 85 10000101 00000205 CXXXIII 1 1 1 1 1
i i
1014 PLA PLA
134 86 10000110 00000206 CXXXIV 1 1 1 1 1
s s
1020 SEI SEI
135 87 10000111 00000207 CXXXV 1 1 1 1 1
i i
1021 DEY DEY
136 88 10001000 00000210 CXXXVI 1 1 1 1 1
i i
1022 T YA T YA
137 89 10001001 00000211 CXXXVII 1 1 1 1 1
i i
1023 TAY TAY
138 8A 10001010 00000212 CXXXVIII 1 1 1 1 1
i i
1024 C LV CLV
139 8B 10001011 00000213 CXXXIX 1 1 1 1 1
i i
1030 INY INY
140 8C 10001100 00000214 CXL 1 1 1 1 1
i i
1031 CLD CLD
141 8D 10001101 00000215 CXLI 1 1 1 1 1
i i
1032 INX INX
142 8E 10001110 00000216 CXLII 1 1 1 1 1
i i
1033 SED SED
143 8F 10001111 00000217 CXLIII 1 1 1 1 1
i i
1034 ORA ORA
144 90 10010000 00000220 CXLIV 1 1 1 1 1
# #
1040 ORA ORA
145 91 10010001 00000221 CXLV 1 1 1 1 1
a,y a,y
1041 AN D AND
146 92 10010010 00000222 CXLVI 1 1 1 1 1
# #
1042 AN D AND
147 93 10010011 00000223 CXLVII 1 1 1 1 1
a,y a,y
1043 EOR EOR
148 94 10010100 00000224 CXLVIII 1 1 1 1 1
# #
1044 EOR EOR
149 95 10010101 00000225 CXLIX 1 1 1 1 1
a,y a,y
1100 AD C ADC
150 96 10010110 00000226 CL 1 1 1 1 1
# #
1101 AD C ADC
151 97 10010111 00000227 CLI 1 1 1 1 1
a,y a,y
1102 BIT BIT
152 98 10011000 00000230 CLII
# #
1103 STA STA
153 99 10011001 00000231 CLIII 1 1 1 1 1
a,y a,y
1104 LDA LDA
154 9A 10011010 00000232 CLIV 1 1 1 1 1
# #
1110 LDA LDA
155 9B 10011011 00000233 CLV 1 1 1 1 1
A,y A,y
1111 CMP CMP
156 9C 10011100 00000234 CLVI 1 1 1 1 1
# #
1112 CMP CMP
157 9D 10011101 00000235 CLVII 1 1 1 1 1
a,y a,y
1113 SBC SBC
158 9E 10011110 00000236 CLVIII 1 1 1 1 1
# #
1114 SBC SBC
159 9F 10011111 00000237 CLIX 1 1 1 1 1
a,y a,y
160 A0 10100000 00000240 1120 CLX ASLA ASLA 1 1 1 1 1
1121 INC INC
161 A1 10100001 00000241 CLXI 1
A∗ A∗
162 A2 10100010 00000242 1122 CLXII ROLA ROLA 1 1 1 1 1
163 A3 10100011 00000243 1123 CLXIII DEC A DEC A 1
1124 LSR LSR
164 A4 10100100 00000244 CLXIV 1 1 1 1 1
A∗ A∗
1130 PHY PH Y
165 A5 10100101 00000245 CLXV 1
s• s•
166 A6 10100110 00000246 1131 CLXVI ROR A ROR A 1 1 1 1 1
1132 PLY PLY
167 A7 10100111 00000247 CLXVII 1
s• s•
1133 T XA TXA
168 A8 10101000 00000250 CLXVIII 1 1 1 1 1
i i
1134 T SX TSX
169 A9 10101001 00000251 CLXIX 1 1 1 1 1
i i
1140 TAX TAX
170 AA 10101010 00000252 CLXX 1 1 1 1 1
i i
1141 T SX TSX
171 AB 10101011 00000253 CLXXI 1 1 1 1 1
i i
1142 DEX DEX
172 AC 10101100 00000254 CLXXII 1 1 1 1 1
i i
1143 PHX PH X
173 AD 10101101 00000255 CLXXIII 1
s• s•
1144 N OP NOP
174 AE 10101110 00000256 CLXXIV 1 1 1 1 1
i i
1200 PLX PLX
175 AF 10101111 00000257 CLXXV 1
s• s•
176 B0 10110000 00000260 1201 CLXXVI
177 B1 10110001 00000261 1202 CLXXVII
178 B2 10110010 00000262 1203 CLXXVIII
179 B3 10110011 00000263 1204 CLXXIX
180 B4 10110100 00000264 1210 CLXXX
181 B5 10110101 00000265 1211 CLXXXI
182 B6 10110110 00000266 1212 CLXXXII
183 B7 10110111 00000267 1213 CLXXXIII
184 B8 10111000 00000270 1214 CLXXXIV
185 B9 10111001 00000271 1220 CLXXXV
186 BA 10111010 00000272 1221 CLXXXVI
187 BB 10111011 00000273 1222 CLXXXVII
1223 WAI WAI
188 BC 10111100 00000274 CLXXXVIII
I• I•
1224 STP STP
189 BD 10111101 00000275 CLXXXIX
I• I•
190 BE 10111110 00000276 1230 CXC
191 BF 10111111 00000277 1231 CXCI
1232 T SB TSB
192 C0 11000000 00000300 CXCII 1
a• a•
1233 TR B TRB
193 C1 11000001 00000301 CXCIII 1
a• a•
1234 BIT BIT
194 C2 11000010 00000302 CXCIV 1 1 1 1 1
a a
1240 BIT BIT
195 C3 11000011 00000303 CXCV 1
a,x ∗ a,x ∗
1241 JMP JMP
196 C4 11000100 00000304 CXCVI 1 1 1 1 1
a a
197 C5 11000101 00000305 1242 CXCVII
1243 JMP JMP
198 C6 11000110 00000306 CXCVIII 1 1 1 1 1
(a) (a)
1244 JMP JMP
199 C7 11000111 00000307 CXCIX 1
(a.x) ∗ (a.x) ∗
1300 STY STY
200 C8 11001000 00000310 CC 1 1 1 1 1
a• a•
1301 ST Z STZ
201 C9 11001001 00000311 CCI 1
a a
1302 LDY LDY
202 CA 11001010 00000312 CCII 1 1 1 1 1
a a
1303 LDY LDY
203 CB 11001011 00000313 CCIII 1 1 1 1 1
a,x a,x
1304 CPY CPY
204 CC 11001100 00000314 CCIV 1 1 1 1 1
a a
205 CD 11001101 00000315 1310 CCV
1311 CPX CPX
206 CE 11001110 00000316 CCVI 1 1 1 1 1
a a
207 CF 11001111 00000317 1312 CCVII
1313 ORA ORA
208 D0 11010000 00000320 CCVIII 1 1 1 1 1
a a
1314 ORA ORA
209 D1 11010001 00000321 CCIX 1 1 1 1 1
a,x a,x
1320 AN D AND
210 D2 11010010 00000322 CCX 1 1 1 1 1
a a
1321 AN D AND
211 D3 11010011 00000323 CCXI 1 1 1 1 1
a,x a,x
1322 EOR EOR
212 D4 11010100 00000324 CCXII 1 1 1 1 1
a a
1323 EOR EOR
213 D5 11010101 00000325 CCXIII 1 1 1 1 1
a,x a,x
1324 AD C ADC
214 D6 11010110 00000326 CCXIV 1 1 1 1 1
a a
1330 AD C ADC
215 D7 11010111 00000327 CCXV 1 1 1 1 1
a,x a,x
 1331 STA STA
216 D8 11011000 00000330 CCXVI 1 1 1 1 1
a a
1332 STA STA
217 D9 11011001 00000331 CCXVII 1 1 1 1 1
a,x a,x
1333 LDA LDA
218 DA 11011010 00000332 CCXVIII 1 1 1 1 1
a a
1334 LDA LDA
219 DB 11011011 00000333 CCXIX 1 1 1 1 1
a,x a,x
1340 CMP CMP
220 DC 11011100 00000334 CCXX 1 1 1 1 1
a a
1341 CMP CMP
221 DD 11011101 00000335 CCXXI 1 1 1 1 1
a,x a,x
1342 SBC SBC
222 DE 11011110 00000336 CCXXII 1 1 1 1 1
a a
1343 SBC SBC
223 DF 11011111 00000337 CCXXIII 1 1 1 1 1
a,x a,x
1344 ASL ASL
224 E0 11100000 00000340 CCXXIV 1 1 1 1 1
a a
1400 ASL ASL
225 E1 11100001 00000341 CCXXV 1 1 1 1 1
a,x a,x
1401 ROL ROL
226 E2 11100010 00000342 CCXXVI 1 1 1 1 1
a a
1402 ROL ROL
227 E3 11100011 00000343 CCXXVII 1 1 1 1 1
a,x a,x
1403 LSR LSR
228 E4 11100100 00000344 CCXXVIII 1 1 1 1 1
a a
1404 LSR LSR
229 E5 11100101 00000345 CCXXIX 1 1 1 1 1
a,x a,x
1410 ROR ROR
230 E6 11100110 00000346 CCXXX 1 1 1 1 1
a a
1411 ROR ROR
231 E7 11100111 00000347 CCXXXI 1 1 1 1 1
a,x a,x
1412 STX STX
232 E8 11101000 00000350 CCXXXII 1 1 1 1 1
a a
1413 ST Z STZ
233 E9 11101001 00000351 CCXXXIII 1
a,x • a,x •
1414 LDX LDX
234 EA 11101010 00000352 CCXXXIV 1 1 1 1 1
a a
1420 LDX LDX
235 EB 11101011 00000353 CCXXXV 1 1 1 1 1
a,x a,x
1421 DEC D EC
236 EC 11101100 00000354 CCXXXVI 1 1 1 1 1
a a
1422 DEC D EC
237 ED 11101101 00000355 CCXXXVII 1 1 1 1 1
a,x a,x
1423 INC INC
238 EE 11101110 00000356 CCXXXVIII 1 1 1 1 1
a a
1424 INC INC
239 EF 11101111 00000357 CCXXXIX 1 1 1 1 1
a,x a,x
1430 BBR 0 BR0
240 F0 11110000 00000360 CCXL
r• r•
1431 BBR 1 BR1
241 F1 11110001 00000361 CCXLI
r• r•
1432 BBR 2 BR2
242 F2 11110010 00000362 CCXLII
r• r•
1433 BBR 3 BR3
243 F3 11110011 00000363 CCXLIII
r• r•
1434 BBR 4 BR4
244 F4 11110100 00000364 CCXLIV
r• r•
1440 BBR 5 BR5
245 F5 11110101 00000365 CCXLV
r• r•
1441 BBR 6 BR6
246 F6 11110110 00000366 CCXLVI
r• r•
1442 BBR 7 BR7
247 F7 11110111 00000367 CCXLVII
r• r•
1443 BBS0 BS0
248 F8 11111000 00000370 CCXLVIII
r• r•
1444 BBS1 BS1
249 F9 11111001 00000371 CCXLIX
r• r•
2000 BBS2 BS2
250 FA 11111010 00000372 CCL
r• r•
2001 BBS3 BS3
251 FB 11111011 00000373 CCLI
r• r•
2002 BBS4 BS4
252 FC 11111100 00000374 CCLII
r• r•
2003 BBS5 BS5
253 FD 11111101 00000375 CCLIII
r• r•
2004 BBS6 BS6
254 FE 11111110 00000376 CCLIV
r• r•
2010 BBS7 BS7
255 FF 11111111 00000377 CCLV
r• r•

Summe OpCodes: 256 256 151 151 151 177 151 0 0 0 0

Prozent (%): 100 100 58.98% ### ### 69.14% 58.98% 0.00% 0.00% 0.00% 0.00%

OpCode OpCode
(original) (Vorschlag) Atari Assembler AMAC EASMD MAC/65SynAssemblerATMAS I & IIE dit 6502DATASM/65 MADS
Table 5-2 W65C02S OpCode Matrix
MSD W65C02S OpCode Matrix MSD

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 BRK ORA TSB ORA ASL RMB0 PHP ORA ASL A TSB ORA ASL BBR0 0
a (zp,x) zp • zp zp zp • s # a• a a r•
1 BPL ORA ORA TRB ORA ASL RMB1 CLC ORA INC TRB ORA ASL BBR1 1
r (zp),y (zp) ∗ zp • zp,x zp,x zp • i a,y A∗ a• a,x a,x r•

2 JSR AND BIT AND ROL RMB2 PLP AND ROL A BIT AND ROL BBR2 2
a (zp,x) zp zp zp zp • s # a a a r•

3 BMI AND AND BIT AND ROL RMB3 SEC I AND DEC A BIT AND ROL BBR3 3
r (zp),y (zp) ∗ zp,x • zp,x zp,x zp • a,y a,x ∗ a,x a,x r•
4 RTI EOR EOR LSR RMB4 PHA EOR LSR JMP EOR LSR BBR4 4
s (zp,x) zp zp zp • s # A∗ a a a r•

5 BVC EOR EOR EOR LSR RMB5 CLI EOR PHY EOR LSR BBR5 5
r (zp),y (zp) ∗ zp,x zp,x zp • i a,y s• a,x a,x r•

6 RTS ADC STZ ADC ROR RMB6 PLA ADC ROR A JMP ADC ROR BBR6 6
s (zp,x) zp • zp zp zp • s # (a) a a r•
7 BVS ADC ADC STZ ADC ROR RMB7 SEI ADC PLY JMP ADC ROR BBR7 7
r (zp),y (zp) ∗ zp,x • zp,x zp,x zp • i a,y s• (a.x) ∗ a,x a,x r•

8 BRA STA STY STA STZ SMB0 DEY BIT TXA STY STA STX BBS0 8
r• (zp,x) zp zp zp zp • i # i a• a a r•

9 BCC STA STA STY STA STZ SMB1 TYA STA TSX STZ STA STZ BBS1 9
r (zp),y (zp) ∗ zp,x zp,x zp,y zp • i a,y i a a,x a,x • r•
A LDY LDA LDX LDY LDA LDX SMB2 TAY LDA TAX LDY LDA LDX BBS2 A
# (zp,x) #∗ zp zp zp zp • i # i a a a r•

B BCS LDA LDA LDY LDA LDX SMB3 CLV LDA TSX LDY LDA LDX BBS3 B
r (zp),y (zp) ∗ zp,x zp,x zp,y zp • i A,y i a,x a,x a,x r•

C CPY CMP CPY CMP DEC SMB4 INY CMP DEX WAI CPY CMP DEC BBS4 C
# (zp,x) zp zp zp zp • i # i I• a a a r•
D BNE CMP CMP CMP DEC SMB5 CLD CMP PHX STP CMP DEC BBS5 D
r (zp),y (zp) ∗ zp,x zp,x zp • i a,y s• I• a,x a,x r•

E CPX SBC CPX SBC INC SMB6 INX SBC NOP CPX SBC INC BBS6 E
# (zp,x) zp zp zp zp • i # i a a a r•

F BEQ SBC SBC SBC INC SMB7 SED SBC PLX SBC INC BBS7 F
r (zp),y (zp) ∗ zp,x zp,x zp • i a,y s• a,x a,x r•
0 1 2 3 4 5 6 7 8 9 A B C D E F

∗ = Old instruction with new addressing modes

• = New Instruction
Atari "Sally" (6502) Instruction Set
Op-Code Table (listed by instruction):
IMPLIED ACCUM. IMMEDIATE Z PAGE Z PAGE, Z PAGE, (IND, X) (IND), Y ABS, X ABS, Y ABSOLU INDIREC RELATIV
X Y TE T E
MNEMONIC OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ OP B µ

ADC 69 2 2 65 2 3 75 2 4 61 2 6 71 2 5 7D 3 4 79 3 4 6D 3 4

0B 2 2
ANC * 2B

AND 29 2 2 25 2 3 35 2 4 21 2 6 31 2 5 3D 3 4 39 3 4 2D 3 4

ARR * 6B 2 2

ASL 0A 1 2 06 2 5 16 2 6 1E 3 7 0E 3 6

ASR 4B 2 2

ASX * CB 2 2

AX7 * 93 2 5 9F 3 5

AXE * 8B 2 2

BCC 90 2 †

BCS B0 2 †

BEQ F0 2 †

BIT 24 2 3 2C 3 4

BMI 30 2 †

BNE D0 2 †

BPL 10 2 †

BRK 00 1 7

BVC 50 2 †

BVS 70 2 †

CLC 18 1 2

CLD D8 1 2

CLI 58 1 2

CLV B8 1 2

CMP C9 2 2 C5 2 3 D5 2 4 C1 2 6 D1 2 5 DD 3 4 D9 3 4 CD 3 4

CPX E0 2 2 E4 2 3 EC 3 4

CPY C0 2 2 C4 2 3 CC 3 4

DCP * C7 2 5 D7 2 6 C3 2 8 D3 2 8 DF 3 7 DB 3 7 CF 3 6

DEC C6 2 5 D6 2 6 DE 3 7 CE 3 6

DEX CA 1 2

DEY 88 1 2

EOR 49 2 2 45 2 3 55 2 4 41 2 6 51 2 5 5D 3 4 59 3 4 4D 3 4

INC E6 2 5 F6 2 6 FE 3 7 EE 3 6

INX E8 1 2

INY C8 1 2

ISB * E7 2 5 F7 2 6 E3 2 8 F3 2 8 FF 3 7 FB 3 7 EF 3 6

JAM * ¤ 1 00

JMP 4C 3 3 6C 3 5

JSR 20 3 6

LAS * BB 3 4

LAX * A7 2 3 B7 2 4 A3 2 6 B3 2 5 BF 3 4 AF 3 4

LDA A9 2 2 A5 2 3 B5 2 4 A1 2 6 B1 2 5 BD 3 4 B9 3 4 AD 3 4

LDX A2 2 2 A6 2 3 B6 2 4 BE 3 4 AE 3 4

LDY A0 2 2 A4 2 3 B4 2 4 BC 3 4 AC 3 4

LSR 4A 1 2 46 2 5 56 2 6 5E 3 7 4E 3 6

NOP EA 1 2 § 2 2 § 2 3 § 2 4 § 3 4 § 3 4

ORA 09 2 2 05 2 3 15 2 4 01 2 6 11 2 5 1D 3 4 19 3 4 0D 3 4

PHA 48 1 3

PHP 08 1 3

PLA 68 1 4

PLP 28 1 4

RLA * 27 2 5 37 2 6 23 2 8 33 2 8 3F 3 7 3B 3 7 2F 3 6

ROL 2A 1 2 26 2 5 36 2 6 3E 3 7 2E 3 6

ROR 6A 1 2 66 2 5 76 2 6 7E 3 7 6E 3 6

RRA * 67 2 5 77 2 6 63 2 8 73 2 8 7F 3 7 7B 3 7 6F 3 6

RTI 40 1 6

RTS 60 1 6

SAX * 87 2 3 97 2 4 83 2 6 8F 3 4

E9 EB 2 2 E5 2 3 F5 2 4 E1 2 6 F1 2 5 FD 3 4 F9 3 4 ED 3 4
SBC SBC * 2 2

SEC 38 1 2

SED F8 1 2

SEI 78 1 2

SRA * 07 2 5 17 2 6 03 2 8 13 2 8 1F 3 7 1B 3 7 0F 3 6

SLO * 47 2 5 57 2 6 43 2 8 53 2 8 5F 3 7 5B 3 7 4F 3 6

STA 85 2 3 95 2 4 81 2 6 91 2 6 9D 3 5 99 3 5 8D 3 4

STX 86 2 3 96 2 4 8E 3 4

STY 84 2 3 94 2 4 8C 3 4

SX7 * 9E 3 5

SY7 * 9C 3 5

TAX AA 1 2

TAY A8 1 2

TSX BA 1 2

TXA 8A 1 2

TXS 9A 1 2

TYA 98 1 2

XEA * AB 2 2

XS7 * 9B 3 5

Legend:
OP: Op-code

B: Number of bytes required

µ: Number of cycles used to execute the instruction

Addressing modes:
IMPLIED: The operands are indicated in the mnemonic.

ACCUM. (A): The operand is the accumulator.

IMMEDIATE (IMM): The operand is the byte following the opcode.

Z PAGE: The byte following the opcode is the address on page 0 of the operand.

Z PAGE,X: The byte following the opcode is added to register X to give the address on page 0 of the operand.

Z PAGE,Y: The byte following the opcode is added to register Y to give the address on page 0 of the operand.

(IND,X): The byte following the opcode is added to register X to give the address on page 0 which contains the address of the operand.
(IND),Y: The byte following the opcode is an address on page 0. This word at this address is added to register Y (as an unsigned word) to give the address of the operand.

ABS,X: The word following the opcode is added to register X (as an unsigned word) to give the address of the operand.

ABS,Y: The word following the opcode is added to register Y (as an unsigned word) to give the address of the operand.

ABSOLUTE (ABS): The word following the opcode is the address of the operand.
INDIRECT: The word following the opcode is the address of a word which is the address of the operand.

RELATIVE: The byte following the opcode is added (as a signed word) to the Program Counter to give the address of the operand.

Notes:

* Undocumented instruction. The behavior of these opcodes was observed on an Atari 800. It may vary with other 6502-based CPU's.
† Branch instructions take 2 cycles if branch is not taken, 3 cycles if branch is taken within the same page, 4 cycles if branch is taken to another page.

¤ There are multiple opcodes for the JAM instruction: 02, 12, 32, 42, 52, 62, 72, 92, B2, D2, and F2.

§ There are multiple opcodes for the NOP instruction; EA is the official one. For implied mode: 1A, 3A, 5A, 7A, DA, EA, and FA. For immediate mode: 80, 82, 89, C2, and E2. For Zero Page mode:

04, 44, and 64. For Zero Page, X mode: 14, 34, 54, 74, D4, and F4. For Absolute, X mode: 1C, 3C, 5C, 7C, DC, and FC. For Absolute mode: 0C.

Back to Atari Technical Information page

 Instruction Chart

x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
adc
0x BRK b ORA (d,X) cop b ora d,S Tsb d ORA d ASL d ora [d] PHP ORA # ASL A phd Tsb a ORA a ASL a ora al ADC (d,X) Adc (d)
(d,S),Y
1x BPL r ORA (d),Y Ora (d) ora (d,S),Y Trb d ORA d,X ASL d,X ora [d],Y CLC ORA a,Y Inc A tcs Trb a ORA a,X ASL a,X ora al,X ADC (d),Y And (d) adc [d]
2x JSR a AND (d,X) jsl al and d,S BIT d AND d ROL d and [d] PLP AND # ROL A pld BIT a AND a ROL a and al ADC # Bit # adc [d],Y
3x BMI r AND (d),Y And (d) and (d,S),Y Bit d,X AND d,X ROL d,X and [d],Y SEC AND a,Y Dec A tsc Bit a,X AND a,X ROL a,X and al,X ADC a Bit a,X adc al
4x RTI EOR (d,X) wdm eor d,S mvp s,d EOR d LSR d eor [d] PHA EOR # LSR A phk JMP a EOR a LSR a eor al ADC a,X Bit d,X adc al,X
5x BVC r EOR (d),Y Eor (d) eor (d,S),Y mvn s,d EOR d,X LSR d,X eor [d],Y CLI EOR a,Y Phy tcd jmp al EOR a,X LSR a,X eor al,X ADC a,Y Bra r adc d,S
and
6x RTS ADC (d,X) per rl adc d,S Stz d ADC d ROR d adc [d] PLA ADC # ROR A rtl JMP (a) ADC a ROR a adc al ADC d Cmp (d)
(d,S),Y
7x BVS r ADC (d),Y Adc (d) adc (d,S),Y Stz d,X ADC d,X ROR d,X adc [d],Y SEI ADC a,Y Ply tdc Jmp (a,X) ADC a,X ROR a,X adc al,X ADC d,X Dec A and [d]
8x Bra r STA (d,X) brl rl sta d,S STY d STA d STX d sta [d] DEY Bit # TXA phb STY a STA a STX a sta al AND (d,X) Eor (d) and [d],Y
9x BCC r STA (d),Y Sta (d) sta (d,S),Y STY d,X STA d,X STX d,Y sta [d],Y TYA STA a,Y TXS txy Stz a STA a,X Stz a,X sta al,X AND (d),Y Inc A and al
Ax LDY # LDA (d,X) LDX # lda d,S LDY d LDA d LDX d lda [d] TAY LDA # TAX plb LDY a LDA a LDX a lda al AND # Jmp (a,X) and al,X
Bx BCS r LDA (d),Y Lda (d) lda (d,S),Y LDY d,X LDA d,X LDX d,Y lda [d],Y CLV LDA a,Y TSX tyx LDY a,X LDA a,X LDX a,Y lda al,X AND a Lda (d) and d,S
Cx CPY # CMP (d,X) rep # cmp d,S CPY d CMP d DEC d cmp [d] INY CMP # DEX wai CPY a CMP a DEC a cmp al AND a,X Ora (d) brl rl
cmp
Dx BNE r CMP (d),Y Cmp (d) cmp (d,S),Y pei d CMP d,X DEC d,X cmp [d],Y CLD CMP a,Y Phx stp jml (a) CMP a,X DEC a,X cmp al,X AND a,Y Phx
(d,S),Y
Ex CPX # SBC (d,X) sep # sbc d,S CPX d SBC d INC d sbc [d] INX SBC # NOP xba CPX a SBC a INC a sbc al AND d Phy cmp [d]
Fx BEQ r SBC (d),Y Sbc (d) sbc (d,S),Y pea a SBC d,X INC d,X sbc [d],Y SED SBC a,Y Plx xce jsr (a,X) SBC a,X INC a,X sbc al,X AND d,X Plx cmp [d],Y
ASL A Ply cmp al
ASL a Sbc (d) cmp al,X
ASL a,X Sta (d) cmp d,S
ASL d Stz a cop b
eor
6502, 65C02, and 65C81 alle Atari ASL d,X Stz a,X
(d,S),Y
65C02 and 65C816 XL / XE BCC r Stz d eor [d]
65C816 - BCS r Stz d,X eor [d],Y
MAC/65 72 ADC (indirect) ADd with Carry BEQ r Trb a eor al
65C02 32 AND (indirect) bitwise AND BIT a Trb d eor al,X
plus 3C BIT absolute,X BIT d Tsb a eor d,S
3F BIT zeropage,X BMI r Tsb d jml (a)
177 80 BRA addr where addr must be in the range *-126 to *+1 (* is the current value of the location counter) BNE r jmp al
Befehle D2 CMP (indirect) compare with A-register BPL r 27 jsl al
3A DEA DEcrement Accumulator BRK b jsr (a,X)
52 EOR (indirect) Exclusive OR BVC r lda (d,S),Y
1A INA INcrement Accumulator BVS r lda [d]
7C JMP (indirect,X) CLC lda [d],Y
B2 LDA (indirect) LoaD the A-register CLD lda al
12 ORA (indirect) inclusive OR CLI lda al,X
DA PHX PusH X onto CPU stack CLV lda d,S
5A PHY PusH Y onto CPU stack CMP (d,X) mvn s,d
FA PLX PulL X from CPU stack CMP (d),Y mvp s,d
ora
7A PLY PulL Y from CPU stack CMP #
(d,S),Y
F2 SBC (indirect) SuBtract with Carry CMP a ora [d]
92 STA (indirect) STore the A-register CMP a,X ora [d],Y
9C STZ absolute CMP a,Y ora al
9E STZ absolute, X CMP d ora al,X
64 STZ zeropage CMP d,X ora d,S
74 STZ zeropage,X CPX # pea a
1C TRB absolute CPX a pei d
14 TRB zeropage CPX d per rl
0C TSB absolute CPY # phb
04 TSB zeropage CPY a phd
CPY d phk
89 BIT # fehlt!!! DEC a plb
DEC a,X pld
DEC d rep #
DEC d,X rtl
sbc
DEX
(d,S),Y
DEY sbc [d]
EOR (d,X) sbc [d],Y
EOR (d),Y sbc al
EOR # sbc al,X
EOR a sbc d,S
EOR a,X sep #
EOR a,Y sta (d,S),Y
EOR d sta [d]
EOR d,X sta [d],Y
INC a sta al
INC a,X sta al,X
INC d sta d,S
INC d,X stp
INX tcd
INY tcs
JMP (a) tdc
JMP a tsc
JSR a txy
LDA (d,X) tyx
LDA (d),Y wai
LDA # wdm
LDA a xba
LDA a,X xce
LDA a,Y
LDA d 78
LDA d,X
LDX #
LDX a
LDX a,Y
LDX d
LDX d,Y
LDY #
LDY a
LDY a,X
LDY d
LDY d,X
LSR A
LSR a
LSR a,X
LSR d
LSR d,X
NOP
ORA (d,X)
ORA (d),Y
ORA #
ORA a
ORA a,X
ORA a,Y
ORA d
ORA d,X
PHA
PHP
PLA
PLP
ROL A
ROL a
ROL a,X
ROL d
ROL d,X
ROR A
ROR a
ROR a,X
ROR d
ROR d,X
RTI
RTS
SBC (d,X)
SBC (d),Y
SBC #
SBC a
SBC a,X
SBC a,Y
SBC d
SBC d,X
SEC
SED
SEI
STA (d,X)
STA (d),Y
STA a
STA a,X
STA a,Y
STA d
STA d,X
STX a
STX d
STX d,Y
STY a
STY d
STY d,X
TAX
TAY
TSX
TXA
TXS
TYA

Summe: 151

Seite 6 von 13
 MOS 6502 Instruction Set

ADC ADC Add Memory to Accumulator with Carry

AND AND AND Accumulator with Memory
ASL ASL Shift Left (Accumulator or Memory)
BCC BCC Branch if Carry Clear
BCS BCS Branch if Carry Set
BEQ BEQ Branch if Result = Zero
BIT BIT Test Memory Against Accumulator
BMI BMI Branch if Minus Result
BNE BNE Branch if Result ≠ Zero
BPL BPL Branch on Plus Result
BRK BRK Break
BVC BVC Branch if V Flag Clear
BVS BVS Branch if V Flag Set
CLC CLC Clear Carry Flag
CLD CLD Clear Decimal Mode Flag
CLI CLI Clear Interrupt Disable flag (Enable Interrupt)
CLV CLV Clear V Flag
CMP CMP Compare Accumulator and Memory
CPX CPX Compare Register X and Memory
CPY CPY Compare Register Y and Memory
DEC DEC Decrement Memory
DEX DEX Decrement Register X
DEY DEY Decrement Register Y
EOR EOR Exclusive-OR Accumulator with Memory
INC INC Increment Memory
INX INX Increment Register X
INY INY Increment Register Y
JMP JMP Jump to New Location
JSR JSR Jump to Subroutine
LDA LDA Load Accumulator
LDX LDX Load Register X
LDY LDY Load Register Y
LSR LSR Shift Right (Accumulator or Memory)
NOP NOP No Operation
ORA ORA OR Accumulator with Memory
PHA PHA Push Accumulator on Stack
PHP PHP Push Processor Status Register (P) onto Stack
PLA PLA Pull Accumulator from Stack
PLP PLP Pull Processor Status Register (P) from Stack
ROL ROL Rotate Left (Accumulator or Memory)
ROR ROR Rotate Right (Accumulator or Memory)
RTI RTI Return from Interrupt
RTS RTS Return from Subroutine
SBC SBC Subtract Memory from Accumulator with Borrow
SEC SEC Set Carry Flag
SED SED Set Decimal Mode Flag
SEI SEI Set Interrupt Disable Flag (Disable Interrupt)
STA STA Store Accumulator
STX STX Store Register X
STY STY Store Register Y
TAX TAX Transfer Accumulator to Register X
TAY TAY Transfer Accumulator to Register Y
TSX TSX Transfer Register SP to Register X
TXA TXA Transfer Register X to Accumulator
TXS TXS Transfer Register X to Register SP
TYA TYA Transfer Register Y to Accumulator

Seite 7 von 13
 Atari Assembler

ADC ADC Add Memory to Accumulator with Carry

AND AND AND Accumulator with Memory
ASL ASL Shift Left (Accumulator or Memory)
BCC BCC Branch if Carry Clear
BCS BCS Branch if Carry Set
BEQ BEQ Branch if Result = Zero
BIT BIT Test Memory Against Accumulator
BMI BMI Branch if Minus Result
BNE BNE Branch if Result ≠ Zero
BPL BPL Branch on Plus Result
BRK BRK Break
BVC BVC Branch if V Flag Clear
BVS BVS Branch if V Flag Set
CLC CLC Clear Carry Flag
CLD CLD Clear Decimal Mode Flag
CLI CLI Clear Interrupt Disable flag (Enable Interrupt)
CLV CLV Clear V Flag
CMP CMP Compare Accumulator and Memory
CPX CPX Compare Register X and Memory
CPY CPY Compare Register Y and Memory
DEC DEC Decrement Memory
DEX DEX Decrement Register X
DEY DEY Decrement Register Y
EOR EOR Exclusive-OR Accumulator with Memory
INC INC Increment Memory
INX INX Increment Register X
INY INY Increment Register Y
JMP JMP Jump to New Location
JSR JSR Jump to Subroutine
LDA LDA Load Accumulator
LDX LDX Load Register X
LDY LDY Load Register Y
LSR LSR Shift Right (Accumulator or Memory)
NOP NOP No Operation
ORA ORA OR Accumulator with Memory
PHA PHA Push Accumulator on Stack
PHP PHP Push Processor Status Register (P) onto Stack
PLA PLA Pull Accumulator from Stack
PLP PLP Pull Processor Status Register (P) from Stack
ROL ROL Rotate Left (Accumulator or Memory)
ROR ROR Rotate Right (Accumulator or Memory)
RTI RTI Return from Interrupt
RTS RTS Return from Subroutine
SBC SBC Subtract Memory from Accumulator with Borrow
SEC SEC Set Carry Flag
SED SED Set Decimal Mode Flag
SEI SEI Set Interrupt Disable Flag (Disable Interrupt)
STA STA Store Accumulator
STX STX Store Register X
STY STY Store Register Y
TAX TAX Transfer Accumulator to Register X
TAY TAY Transfer Accumulator to Register Y
TSX TSX Transfer Register SP to Register X
TXA TXA Transfer Register X to Accumulator
TXS TXS Transfer Register X to Register SP
TYA TYA Transfer Register Y to Accumulator

Seite 8 von 13
 AMAC

AMAC Befehlssatz: 151 Befehle Unsorted: Alphabetic: Alphabetic without duplicates:

TAX ADC ADC

DATA MOVEMENT TAY ADC AND
TSX ADC ASL
Register to register transfer TXA ADC BCC
AA TAX Transfer A to X TXS ADC BCS
A8 TAY Transfer A to Y TYA ADC BEQ
BA TSX Transfer S to X LDA ADC BIT
8A TXA Transfer X to A LDX ADC BMI
9A TXS Transfer A to Y LDY AND BNE
98 TYA Transfer A to Y LDA AND BPL
LDA AND BRK
Load constant into memory LDA AND BVC
A9 LDA #nn LDA AND BVS
A2 LDX #nn LDA AND CLC
A0 LDY #nn LDA AND CLD
LDA AND CLI
Load register from memory LDX ASL CLV
A5 LDA zz LDX ASL CMP
B5 LDA zz,X LDX ASL CPX
A1 LDA (zz,X) LDX ASL CPY
B1 LDA (zz),Y LDY ASL DEC
AD LDA mmmm LDY BCC DEX
BD LDA mmmm,X LDY BCS DEY
B9 LDA mmmm,Y LDY BEQ EOR
A6 LDX zz STA BIT INC
B6 LDX zz,Y STA BIT INX
AE LDX mmmm STA BMI INY
BE LDX mmmm,Y STA BNE JMP
A4 LDY zz STA BPL JSR
B4 LDY zz,X STA BRK LDA
AC LDY mmmm STA BVC LDX
BC LDY mmmm,X STX BVS LDY
STX CLC LSR
Store register into memory STX CLD NOP
85 STA zz STY CLI ORA
95 STA zz,X STY CLV PHA
81 STA (zz,X) STY CMP PHP
91 STA (zz),Y PHA CMP PLA
8D STA mmmm PHP CMP PLP
9D STA mmmm,X PLA CMP ROL
99 STA mmmm,Y PLP CMP ROR
86 STX zz ADC CMP RTI
96 STX zz,Y ADC CMP RTS
8E STX mmmm ADC CMP SBC
84 STY zz ADC CPX SEC
94 STY zz,X ADC CPX SED
8C STY mmmm ADC CPX SEI
ADC CPY STA
Stack load/stores ADC CPY STX
48 PHA ;Push accumulator SBC CPY STY
8 PHP ;Push processor status SBC DEC TAX
68 PLA ;Pop accumulator SBC DEC TAY
28 PLP ;Pop processor status SBC DEC TSX
SBC DEC TXA
SBC DEX TXS
DYADIC ARITHMETIC SBC DEY TYA
SBC EOR
Add operand and carry CMP EOR
69 ADC #nn CMP EOR
65 ADC zz CMP EOR
75 ADC zz,X CMP EOR
61 ADC (zz,X) CMP EOR
71 ADC (zz),Y CMP EOR
6D ADC mmmm CMP EOR
7D ADC mmmm,X CMP INC
79 ADC mmmm,Y CPX INC
CPX INC
Subtract operand and borrow CPX INC
E9 SBC #nn CPY INX
ES SBC zz CPY INY
FS SBC zz,X CPY JMP
E1 SBC (zz,X) DEC JMP
F1 SBC (zz),Y DEC JSR
ED SBC mmmm DEC LDA
FD SBC mmmm,X DEC LDA
F9 SBC mmmm,Y DEX LDA
DEY LDA
Compare 8-bit operand with accumulator INC LDA
Set flags as if subtracting, but do not alter accumulator INC LDA
C9 CMP #nn INC LDA
C5 CMP zz INC LDA
D5 CMP zz,X INX LDX
C1 CMP (zz,X) INY LDX
D1 CMP (zz),Y CLC LDX
CD CMP mmmm CLD LDX
DD CMP mmmm,X CLV LDX
D9 CMP mmmm,Y SEC LDY
SED LDY
Compare 8-bit operand with index register AND LDY
E0 CPX #nn AND LDY
E4 CPX zz AND LDY
EC CPX mmmm AND LSR
C0 CPY #nn AND LSR
C4 CPY zz AND LSR
CC CPY mmmm AND LSR
AND LSR
ORA NOP
MONADIC ARITHMETIC ORA ORA
ORA ORA
Decrement by 1 ORA ORA
C6 DEC zz ORA ORA
D6 DEC zz,X ORA ORA
CE DEC mmmm ORA ORA
DE DEC mmmm,X ORA ORA
CA DEX EOR ORA
88 DEY EOR PHA
EOR PHP
Increment by 1 EOR PLA
E6 INC zz EOR PLP
F6 INC zz,X EOR ROL
EE INC mmmm EOR ROL
FE INC mmmm,X EOR ROL
E8 INX BIT ROL
C8 INY BIT ROL
ASL ROR
Arithmetic control ASL ROR
18 CLC ;Clear carry flag ASL ROR
D8 CLD ;Clear decimal mode ASL ROR
B8 CLV ;Set overflow flag ASL ROR
38 SEC ;Set carry flag LSR RTI
F8 SED ;Set decimal mode LSR RTS
LSR SBC
LSR SBC
DYADIC LOGICAL/BOOLEAN OPERATIONS LSR SBC
ROL SBC
8-bit logical product, conjunction ROL SBC
29 AND #nn ROL SBC
25 AND zz ROL SBC
35 AND zz,X ROL SBC
21 AND (zz,X) ROR SEC
31 AND (zz), Y ROR SED
2D AND mm mm ROR SEI
3D AND mmmm,X ROR STA
39 AND mmmm,Y ROR STA
BCC STA
Logical sum, disjunction, inclusive OR BCS STA
9 ORA #nn BEQ STA
5 ORA zz BMI STA
15 ORA zz,X BNE STA
1 ORA (zz,X) BPL STX
11 ORA (zz),Y BVC STX
0D ORA mmmm BVS STX
1D ORA mmmm,X JMP STY
19 ORA mmmm,Y JMP STY
BRK STY
Logical difference, inequivalence, exclusive OR JSR TAX
49 EOR #nn RTI TAY
45 EOR zz RTS TSX
55 EOR zz,X CLI TXA
41 EOR (zz,X) NOP TXS
51 EOR (zz),Y SEI TYA
4D EOR mmmm
5D EOR mmmm,X
59 EOR mmmm,Y

Logical compare
Set flags as follows:
Z=1 if A AND mem = 0
Z=O if A AND mem = 1
S=bit 7 of mem
V=bit 6 of mem
(mem = mmmm or zz)

24 BIT zz
2C BIT mmmm

ROTATE AND SHIFT

Arithmetic shift left

0A ASL A
6 ASL zz
16 ASL zz,X
0E ASL mmmm
1E ASL mmmm,X

Logical shift right

4A LSR A
46 LSR zz
56 LSR zz,X
4E LSR mmmm
5E LSR mmmm,X

Rotate left
2A ROL A
26 ROL zz
36 ROL zz,X
2E ROL mmmm
3E ROL mmmm,X

Rotate right
6A ROR A
66 ROR zz
76 ROR zz,X
6E ROR mmmm
7E ROR mmmm,X

JUMPS

90 BCC ;If carry clear

B0 BCS ; If carry set
F0 BEQ ;If equal (=O)
30 BMI ;If minus
D0 BNE ;If not equal (<>0)
10 BPL ;If plus
50 BVC ;If overflow clear
70 BVS ;If overflow set
4C JMP mmmm
6C JMP (mmmm)

CALL SUBROUTINE

0 BRK ;Software interrupt

20 JSR mmmm;Jump subroutine

RETURN FROM SUBROUTINE

40 RTI ;Return from interrupt

60 RTS ;Return from subroutine

MISCELLANEOUS CPU CONTROL

58 CLI ;Clear interrupt mask (El)

EA NOP
78 SEI ;Set interrupt mask (DI)

Seite 9 von 13
 AMAC sortiert

69 ADC #nn
65 ADC zz
75 ADC zz,X 151 Befehle
61 ADC (zz,X)
71 ADC (zz),Y
6D ADC mmmm
7D ADC mmmm,X
79 ADC mmmm,Y
29 AND #nn
25 AND zz
35 AND zz,X
21 AND (zz,X)
31 AND (zz), Y
2D AND mm mm
3D AND mmmm,X
39 AND mmmm,Y
0A ASL A
6 ASL zz
16 ASL zz,X
0E ASL mmmm
1E ASL mmmm,X
90 BCC ;If carry clear
B0 BCS ; If carry set
F0 BEQ ;If equal (=O)
24 BIT zz
2C BIT mmmm
30 BMI ;If minus
D0 BNE ;If not equal (<>0)
10 BPL ;If plus
0 BRK ;Software interrupt
50 BVC ;If overflow clear
70 BVS ;If overflow set
18 CLC ;Clear carry flag
D8 CLD ;Clear decimal mode
58 CLI ;Clear interrupt mask (El)
B8 CLV ;Set overflow flag
C9 CMP #nn
C5 CMP zz
D5 CMP zz,X
C1 CMP (zz,X)
D1 CMP (zz),Y
CD CMP mmmm
DD CMP mmmm,X
D9 CMP mmmm,Y
E0 CPX #nn
E4 CPX zz
EC CPX mmmm
C0 CPY #nn
C4 CPY zz
CC CPY mmmm
C6 DEC zz
D6 DEC zz,X
CE DEC mmmm
DE DEC mmmm,X
CA DEX
88 DEY
49 EOR #nn
45 EOR zz
55 EOR zz,X
41 EOR (zz,X)
51 EOR (zz),Y
4D EOR mmmm
5D EOR mmmm,X
59 EOR mmmm,Y
E6 INC zz
F6 INC zz,X
EE INC mmmm
FE INC mmmm,X
E8 INX
C8 INY
4C JMP mmmm
6C JMP (mmmm)
20 JSR mmmm;Jump subroutine
A9 LDA #nn
A5 LDA zz
B5 LDA zz,X
A1 LDA (zz,X)
B1 LDA (zz),Y
AD LDA mmmm
BD LDA mmmm,X
B9 LDA mmmm,Y
A2 LDX #nn
A6 LDX zz
B6 LDX zz,Y
AE LDX mmmm
BE LDX mmmm,Y
A0 LDY #nn
A4 LDY zz
B4 LDY zz,X
AC LDY mmmm
BC LDY mmmm,X
4A LSR A
46 LSR zz
56 LSR zz,X
4E LSR mmmm
5E LSR mmmm,X
EA NOP
9 ORA #nn
5 ORA zz
15 ORA zz,X
1 ORA (zz,X)
11 ORA (zz),Y
0D ORA mmmm
1D ORA mmmm,X
19 ORA mmmm,Y
48 PHA ;Push accumulator
8 PHP ;Push processor status
68 PLA ;Pop accumulator
28 PLP ;Pop processor status
2A ROL A
26 ROL zz
36 ROL zz,X
2E ROL mmmm
3E ROL mmmm,X
6A ROR A
66 ROR zz
76 ROR zz,X
6E ROR mmmm
7E ROR mmmm,X
40 RTI ;Return from interrupt
60 RTS ;Return from subroutine
E9 SBC #nn
ES SBC zz
FS SBC zz,X
E1 SBC (zz,X)
F1 SBC (zz),Y
ED SBC mmmm
FD SBC mmmm,X
F9 SBC mmmm,Y
38 SEC ;Set carry flag
F8 SED ;Set decimal mode
78 SEI ;Set interrupt mask (DI)
85 STA zz
95 STA zz,X
81 STA (zz,X)
91 STA (zz),Y
8D STA mmmm
9D STA mmmm,X
99 STA mmmm,Y
86 STX zz
96 STX zz,Y
8E STX mmmm
84 STY zz
94 STY zz,X
8C STY mmmm
AA TAX Transfer A to X
A8 TAY Transfer A to Y
BA TSX Transfer S to X
8A TXA Transfer X to A
9A TXS Transfer A to Y
98 TYA Transfer A to Y

Seite 10 von 13
 MAC-65

AMAC Befehlssatz: 177 Befehle Unsorted: Alphabetic: Alphabetic without duplicates:

TAX ADC ADC

DATA MOVEMENT TAY ADC AND
TSX ADC ASL
Register to register transfer TXA ADC BCC
AA TAX Transfer A to X TXS ADC BCS
A8 TAY Transfer A to Y TYA ADC BEQ
BA TSX Transfer S to X LDA ADC BIT
8A TXA Transfer X to A LDX ADC BMI
9A TXS Transfer A to Y LDY AND BNE
98 TYA Transfer A to Y LDA AND BPL
LDA AND BRA
Load constant into memory LDA AND BRK
A9 LDA #nn LDA AND BVC
A2 LDX #nn LDA AND BVS
A0 LDY #nn LDA AND CLC
LDA AND CLD
Load register from memory LDX ASL CLI
A5 LDA zz LDX ASL CLV
B5 LDA zz,X LDX ASL CMP
A1 LDA (zz,X) LDX ASL CPX
B1 LDA (zz),Y LDY ASL CPY
AD LDA mmmm LDY BCC DEA
BD LDA mmmm,X LDY BCS DEC
B9 LDA mmmm,Y LDY BEQ DEX
A6 LDX zz STA BIT DEY
B6 LDX zz,Y STA BIT EOR
AE LDX mmmm STA BMI INA
BE LDX mmmm,Y STA BNE INC
A4 LDY zz STA BPL INX
B4 LDY zz,X STA BRA INY
AC LDY mmmm STA BRK JMP
BC LDY mmmm,X STX BVC JSR
STX BVS LDA
Store register into memory STX CLC LDX
85 STA zz STY CLD LDY
95 STA zz,X STY CLI LSR
81 STA (zz,X) STY CLV NOP
91 STA (zz),Y PHA CMP ORA
8D STA mmmm PHP CMP PHA
9D STA mmmm,X PLA CMP PHP
99 STA mmmm,Y PLP CMP PHX
86 STX zz ADC CMP PHY
96 STX zz,Y ADC CMP PLA
8E STX mmmm ADC CMP PLP
84 STY zz ADC CMP PLX
94 STY zz,X ADC CPX PLY
8C STY mmmm ADC CPX ROL
ADC CPX ROR
Stack load/stores ADC CPY RTI
48 PHA ;Push accumulator SBC CPY RTS
8 PHP ;Push processor status SBC CPY SBC
68 PLA ;Pop accumulator SBC DEA SEC
28 PLP ;Pop processor status SBC DEC SED
SBC DEC SEI
SBC DEC STA
DYADIC ARITHMETIC SBC DEC STX
SBC DEX STY
Add operand and carry CMP DEY STZ
69 ADC #nn CMP EOR TAX
65 ADC zz CMP EOR TAY
75 ADC zz,X CMP EOR TRB
61 ADC (zz,X) CMP EOR TSB
71 ADC (zz),Y CMP EOR TSX
6D ADC mmmm CMP EOR TXA
7D ADC mmmm,X CMP EOR TXS
79 ADC mmmm,Y CPX EOR TYA
CPX INA
Subtract operand and borrow CPX INC
E9 SBC #nn CPY INC
ES SBC zz CPY INC
FS SBC zz,X CPY INC
E1 SBC (zz,X) DEC INX
F1 SBC (zz),Y DEC INY
ED SBC mmmm DEC JMP
FD SBC mmmm,X DEC JMP
F9 SBC mmmm,Y DEX JSR
DEY LDA
Compare 8-bit operand with accumulator INC LDA
Set flags as if subtracting, but do not alter accumulator INC LDA
C9 CMP #nn INC LDA
C5 CMP zz INC LDA
D5 CMP zz,X INX LDA
C1 CMP (zz,X) INY LDA
D1 CMP (zz),Y CLC LDA
CD CMP mmmm CLD LDA
DD CMP mmmm,X CLV LDX
D9 CMP mmmm,Y SEC LDX
SED LDX
Compare 8-bit operand with index register AND LDX
E0 CPX #nn AND LDX
E4 CPX zz AND LDY
EC CPX mmmm AND LDY
C0 CPY #nn AND LDY
C4 CPY zz AND LDY
CC CPY mmmm AND LDY
AND LSR
ORA LSR
MONADIC ARITHMETIC ORA LSR
ORA LSR
Decrement by 1 ORA LSR
C6 DEC zz ORA NOP
D6 DEC zz,X ORA ORA
CE DEC mmmm ORA ORA
DE DEC mmmm,X ORA ORA
CA DEX EOR ORA
88 DEY EOR ORA
EOR ORA
Increment by 1 EOR ORA
E6 INC zz EOR ORA
F6 INC zz,X EOR PHA
EE INC mmmm EOR PHP
FE INC mmmm,X EOR PHX
E8 INX BIT PHY
C8 INY BIT PLA
ASL PLP
Arithmetic control ASL PLX
18 CLC ;Clear carry flag ASL PLY
D8 CLD ;Clear decimal mode ASL ROL
B8 CLV ;Set overflow flag ASL ROL
38 SEC ;Set carry flag LSR ROL
F8 SED ;Set decimal mode LSR ROL
LSR ROL
LSR ROR
DYADIC LOGICAL/BOOLEAN OPERATIONS LSR ROR
ROL ROR
8-bit logical product, conjunction ROL ROR
29 AND #nn ROL ROR
25 AND zz ROL RTI
35 AND zz,X ROL RTS
21 AND (zz,X) ROR SBC
31 AND (zz), Y ROR SBC
2D AND mm mm ROR SBC
3D AND mmmm,X ROR SBC
39 AND mmmm,Y ROR SBC
BCC SBC
Logical sum, disjunction, inclusive OR BCS SBC
9 ORA #nn BEQ SBC
5 ORA zz BMI SEC
15 ORA zz,X BNE SED
1 ORA (zz,X) BPL SEI
11 ORA (zz),Y BVC STA
0D ORA mmmm BVS STA
1D ORA mmmm,X JMP STA
19 ORA mmmm,Y JMP STA
BRK STA
Logical difference, inequivalence, exclusive OR JSR STA
49 EOR #nn RTI STA
45 EOR zz RTS STX
55 EOR zz,X CLI STX
41 EOR (zz,X) NOP STX
51 EOR (zz),Y SEI STY
4D EOR mmmm STY
5D EOR mmmm,X 6502C STY
59 EOR mmmm,Y BRA STZ
DEA TAX
Logical compare INA TAY
Set flags as follows: PHX TRB
Z=1 if A AND mem = 0 PHY TSB
Z=O if A AND mem = 1 PLX TSX
S=bit 7 of mem PLY TXA
V=bit 6 of mem STZ TXS
(mem = mmmm or zz) TRB TYA
TSB
24 BIT zz
2C BIT mmmm

ROTATE AND SHIFT

Arithmetic shift left

0A ASL A
6 ASL zz
16 ASL zz,X
0E ASL mmmm
1E ASL mmmm,X

Logical shift right

4A LSR A
46 LSR zz
56 LSR zz,X
4E LSR mmmm
5E LSR mmmm,X

Rotate left
2A ROL A
26 ROL zz
36 ROL zz,X
2E ROL mmmm
3E ROL mmmm,X

Rotate right
6A ROR A
66 ROR zz
76 ROR zz,X
6E ROR mmmm
7E ROR mmmm,X

JUMPS

90 BCC ;If carry clear

B0 BCS ; If carry set
F0 BEQ ;If equal (=O)
30 BMI ;If minus
D0 BNE ;If not equal (<>0)
10 BPL ;If plus
50 BVC ;If overflow clear
70 BVS ;If overflow set
4C JMP mmmm
6C JMP (mmmm)

CALL SUBROUTINE

0 BRK ;Software interrupt

20 JSR mmmm;Jump subroutine

RETURN FROM SUBROUTINE

40 RTI ;Return from interrupt

60 RTS ;Return from subroutine

MISCELLANEOUS CPU CONTROL

58 CLI ;Clear interrupt mask (El)

EA NOP
78 SEI ;Set interrupt mask (DI)

6502C only
72 ADC (indirect) ADd with Carry
32 AND (indirect) bitwise AND
3C BIT absolute,X
3F BIT zeropage,X
80 BRA addr where addr must be in the range *-126 to *+ (* is the current value of the location counter)
D2 CMP (indirect) compare with A-register
3A DEA DEcrement Accumulator
52 EOR (indirect) Exclusive OR
1A INA INcrement Accumulator
7C JMP (indirect,X)
B2 LDA (indirect) LoaD the A-register
12 ORA (indirect) inclusive OR
DA PHX PusH X onto CPU stack
5A PHY PusH Y onto CPU stack
FA PLX PulL X from CPU stack
7A PLY PulL Y from CPU stack
F2 SBC (indirect) SuBtract with Carry
92 STA (indirect) STore the A-register
9C STZ absolute
9E STZ absolute, X
64 STZ zeropage
74 STZ zeropage,X
1C TRB absolute
14 TRB zeropage
0C TSB absolute
04 TSB zeropage

89 BIT # fehlt!!!

Seite 11 von 13
 SynAssembler

ADC ADC Add Memory to Accumulator with Carry

AND AND AND Accumulator with Memory
ASL ASL Shift Left (Accumulator or Memory)
BCC/BGE* BCC Branch if Carry Clear page 42 in the manual
BCS/BLT* BCS Branch if Carry Set page 42 in the manual
BEQ BEQ Branch if Result = Zero
BIT BIT Test Memory Against Accumulator
BMI BMI Branch if Minus Result
BNE BNE Branch if Result ≠ Zero
BPL BPL Branch on Plus Result
BRK BRK Break
BVC BVC Branch if V Flag Clear
BVS BVS Branch if V Flag Set
CLC CLC Clear Carry Flag
CLD CLD Clear Decimal Mode Flag
CLI CLI Clear Interrupt Disable flag (Enable Interrupt)
CLV CLV Clear V Flag
CMP CMP Compare Accumulator and Memory
CPX CPX Compare Register X and Memory
CPY CPY Compare Register Y and Memory
DEC DEC Decrement Memory
DEX DEX Decrement Register X
DEY DEY Decrement Register Y
EOR EOR Exclusive-OR Accumulator with Memory
INC INC Increment Memory
INX INX Increment Register X
INY INY Increment Register Y
JMP JMP Jump to New Location
JSR JSR Jump to Subroutine
LDA LDA Load Accumulator
LDX LDX Load Register X
LDY LDY Load Register Y
LSR LSR Shift Right (Accumulator or Memory)
NOP NOP No Operation
ORA ORA OR Accumulator with Memory
PHA PHA Push Accumulator on Stack
PHP PHP Push Processor Status Register (P) onto Stack
PLA PLA Pull Accumulator from Stack
PLP PLP Pull Processor Status Register (P) from Stack
ROL ROL Rotate Left (Accumulator or Memory)
ROR ROR Rotate Right (Accumulator or Memory)
RTI RTI Return from Interrupt
RTS RTS Return from Subroutine
SBC SBC Subtract Memory from Accumulator with Borrow
SEC SEC Set Carry Flag
SED SED Set Decimal Mode Flag
SEI SEI Set Interrupt Disable Flag (Disable Interrupt)
STA STA Store Accumulator
STX STX Store Register X
STY STY Store Register Y
TAX TAX Transfer Accumulator to Register X
TAY TAY Transfer Accumulator to Register Y
TSX TSX Transfer Register SP to Register X
TXA TXA Transfer Register X to Accumulator
TXS TXS Transfer Register X to Register SP
TYA TYA Transfer Register Y to Accumulator

Seite 12 von 13
 Pental->Dezimal

BASE: 5
-> BASE10 Ergebnis = 437 Dezimal

390625 78125 15625 3125 625 125 25 5 1

b^8 b^7 b^6 b^5 b^4 b^3 b^2 b^1 b^0
BASE-Zahl: 3 2 2 2

Seite 13 von 13