Slide 2

Summary

Slide 3

CMOS technology is most prevalent (wide - spread) in manufacturing digital integrated circuits

The goal and reason in studying CMOS circuits: to see how they are built and what are their
behavior, their features and performances.

CMOS technology uses pairs of n channel (nMOS) and p channel (pMOS) arranged in rows and
columns

NMOS transistor is built in the p substrate and for pMOS device a n-well is created in order to act
as a bulk for the p+ difused regions

The transistor dimensions are the dimensions of the conducting channel and become smaller every
decade allowing a larger number of transistors to be implemented in a single chip (billions)

Slide 4

CMOS structures implementation principle

- the inverter which is the simplest structure, a fundamental circuit

- it consists of a pair of transistors: one NMOS and the other PMOS
- one switch driven by ‘0’ creates a short-circuit to VDD – pMOS switch
- one switch driven by ‘1’ creates a short-circuit to GND – nMOS switch

The behavior is based on the principle of existing 2 paths: the pull-up and pull-down path. When
one is ON the other must be OFF and vice versa ( and conversely).

Slide 5

When Vin ( input signal voltage) varies from LOW to HIGH, the transistors pass through three
states, described by the following equations
The n channel transistor is blocked at the beginning and after input voltage overpasses the Vth
( threshold voltage), the transistor switches ON, conductind at saturation first and then passing in
the linear region.

as the input voltage drops

The p channel transistor is in the linear region when the input logic level is ‘0’ and blocked at the
beginning and after input voltage overpasses the Vth ( threshold voltage), the transistor switches
ON, conductind at saturation first and then passing.
  blocked: VGS  Vth ; I D  0
 saturation:

 linear: VDS  VGS  Vth ; I D  VGS  Vth  2
2

 V 
VDS  VGS  Vth ; I D   VGS  Vth  DS   VDS
 2 

Slide 6

There are five different regions.

The steady states are A and E.

Region A – in this region, the input voltage is greater than zero but smaller than VTN , the threshold
voltage of the transistor with n-channel. The transistor T1 is off, while T2 is in the linear region –
situation in figure a. There is no current through the transistors, so the output voltage is Vout = VDD.

Region E – this region corresponds to the input voltages domains that respect:
Vin  VDD - |VTP| (9.16)

Where the transistor p is off while the n transistor conducts linearly. The output voltage is Vout = 0.
Also here There is no current through the transistors

The consequence is the most important feature of CMOS circuits: there is no power consumption
in steady states. But this is ideally, because real circuits , as we can see later, there is small leakage
current between positive rail and ground, which sometimes could be an important component.

Slide 7

In the other 3 regions a current will be present in the inverter.

Region B – in this region, the input voltage is greater than V TN, but smaller than VDD/2, in this case,
transistor T2 is in the not saturated region (V DS#0) and T1 in saturated conduction. This case is
shown in figure 9.3.b, where the transistor p is drawn as a resistor and the nMOS transistor as a
current source.

Region C – in this region, both transistors work in saturation, so the model that describes it is given
in figure 9.3.c. This model contains two current sources serially connected

Region D – in this region, the input voltage satisfies the condition:

Tranzistor T2 is saturated while T1 linearilly conducts, situation described by the model in figure
9.3.d

The inverter will pas through all these regions only at transitions: from LOW to HIGH or
conversely.
Slide 8

Noise margin

We know an inverter is able to operate with input signals equal with 0V and VDD in order to obtain a
‘1’ or a ‘0’ to the output respectively.

Now is the time to see what is happened if the input voltage is not 0V, but 0.1 V for example.

When transmitting LOW level from an inverter to another:

The domain of the input voltages considered a logic „0” is limited by V ILmax,= 0,3VDD. ( this
is the value above the NMOS transistor comes out of blocking state.
The CMOS output circuits assure a maximum voltage level VOLmax = 0,1V, that is sufficient
for obtaining a „0” logic level to the input of the next gate, where practically, a potential is assured,
smaller than VTN. In this case also, the noise margin is given as the difference between the two
levels and is equal to 0,3VDD.

When transmitting HIGH level from an inverter to another:

A question that appears is, in case of connecting two inverters as shown in figure, the output
of the first inverter supplys to the second inverter a voltage big enough so that it can be seen at the
second input as a logic „1”?

The answer is given by the following: CMOS circuits have a minimal guaranteed output
level VOHmin = VDD - 0,1V, so that this assures a logic „1” at the input gate but also there is a reserve
equal to 0,3VDD called noise margin. The same problem can appear when transmitting the logic
level „0” to the input of the next gate.

As we showed when describing the CMOS inverter functioning (paragraph 9.2), if at the
device’s input a voltage is applied greater than V DD-|VTP|, the input signal is interpreted as logic „1”
and the output is approximatively 0V and (v out≤0,1V) and will have the logic level „0”. V IHmin is the
minimal admitted input voltage for the level „HIGH” and is equal to 0,7VDD.

The importance of the noise margin parameter is given by the fact that, on the path from the
putput to the corresponding input a voltage can get lost or being added, the voltage being equal to
the noise margin. This phenomenon does not affect the logic level submission.

The potential changes through the signals are due to resistive causes (great lenght of the conductors
having a big resistance, switches woth big resistances, etc), or capacitive causes, due to parasitic
capacitances between the conductors. Another cause represents the influence of the electromagnetic
fields nearby the signal traces (conducting wires of great currents, engines or electric field
generators), influence that manifests itself by inducing electrical voltages through the small signal
conductors
These voltages can be positive or negative, their value has to be covered by the noise margin.

Slide 9

Noise margin

In figure a synthetized description of the noise margin problem is given, with the remark
that the level values differ for each logic circuit family.
Slide 10

Fan - Out

The fan-out notion refers to the circuit input numbers that can connect to a single output,
without deteriorating the correct functioning of the controlling circuit. This number is stated for the
HIGH level and, as well for the LOW level. There is a fan-out for transmitting the HIGH logic
level and another one for the LOW logic level. A global fan-out is defined as the minimum value
between the two.
For a CMOS circuit of the HC series, the maximal input current for both logic levels is
±1μA. For the same circuits, the maximum current admitted at the output is the same for the
transmission of both levels: IOLmax=IOHmax=20 μA.
It results that the fan-out is equal to 10, that means an HC CMOS family output can control
a maximal number of 10 gate outputs of the same family.
This limit needs to be respected, otherwise the transition times of the output and the signal
propagation times become bigger than the given catalog allowable values. As well, because of
modifying the warranted voltages, the noise margin of the circuit decreases, endangering the well
functioning of the digital circuit.
Noteworthy that in the VLSI technology, when designing a CMOS circuit, a fan-out bigger
than 3-4 is avoided, because the supplementary capacitive charges strongly deteriorate the dynamic
circuit characteristics ( see figure 9.6).

Slide 11

The power consumption determines the consumption of energy from the supply rails and causes
heat dissipation; power consumption is a key factor in calculating energy consumption.

Knowledge of this parameter is important in order to determine:

- the capacity of the supply source,
- the battery lifetime,
- sizing the supply rails,
- the packaging
- the way of cooling the package

The power consumption consists of three components:

 Pstat – static power dissipated due to the current which flows during the steady states
 Pdyn – dynamic power dissipated caused by charging and discharging of the load
capacitance (during switching)
 Pdp – dynamic power dissipated due to the simultaneous conduction of the nMOS
and pMOS transistors

Ptot  Pstat  Pdyn  Pdp

Slide 12

The static power

- During the steady states (models 1 and 5) one of the transistors is blocked and no current
closes between VDD and GND. It results, ideally, the inverter doesn’t dissipate power

- In reality, a leakage current leaks through the reverse-biased drain-bulk and source-bulk
junctions,
 - as well as a sub-threshold conduction current, (when the gate-substrate voltage is positive
but less than threshold voltage)

- This current is about tens of nA, that lead to a power static component around tens of nW.

- This is not a large value but in a hip there about one billion transistors pairs and the total
amount of static power could reach easily tens of watts.

- This component became more and more important during the last 2 decades

Slide 13

 The static power – two components

Pstat  I stat  VDD  ( I leak  I subth )  VDD
 Subthreshold current – between drain and source
 Leakage current – from gate / drain / source to body

Slide 14

 In processes with feature sizes above 180 nm, leakage was typically insignificant
except in very low power applications
 In 90 and 65 nm processes, threshold voltage has reduced to the point that subthreshold
leakage reaches levels of 1s to 10s of nA per transistor,
 In 45 nm processes, oxide thickness reduces to the point that gate leakage becomes
comparable to subthreshold leakage
 Static power consumption becomes more significant when multiplied by millions or billions
of transistors on a chip
 Leakage has become an important design goal in nanometer technologies: nowadays nearly
one-third of the power is leakage.

Slide 15
- The most important power dissipation components emerge at transition.
- The first dynamic component is caused by the charging and discharging the load
capacitance.
- There is a current flowing through the capacitor. This current varies according to the
exponential law. After integration of current expression, we achieve:
2
Pdyn  f  C L  VDD
where
 f – inverter switching frequency
 CL – load capacitance
 VDD – supply voltage

The above relation shows how the dynamic power depends on frequency and power supply voltage
value.
The dissipated power increases linearly with the frequency, that means at high frequencies the
CMOS consume consume a significant amount of energy.

Slide 16

Another component is the dynamic power dissipated due to the simultaneous conduction of
the nMOS and pMOS transistors.
During switching, when one transistor (models 2 and 4) or both (model 3) are in saturation,
a current path is closed between VDD and GND
 Using an approximation, the estimated second component dynamic power is:
 3 t
Pdp  I Dmed VDD   VDD  2Vth   r
12 T

Also in this situation there is a frequency-dependent power consumption. Also, power supply
voltage influences the dissipated power.

Slide 17
 f = ‘1’ → short-circuit to VDD, for either a = ‘0’ OR b = ‘0’
 2 parallel pMOS transistors
 f = ‘0’ → short-circuit to GND, for both a = ‘1’ AND b = ‘1’
 2 series nMOS transistors

Slide 18
MOS transistor – ideal switch model
 pMOS, VG = LOW → ON
 pMOS, VG = HIGH → off
 nMOS, VG = LOW → off
 nMOS, VG = HIGH → ON

Slide 19

 f = ‘1’ → short-circuit to VDD, for both a = ‘1’ AND b = ‘1’

 2 series pMOS transistors
 f = ‘0’ → short-circuit to GND, for either a = ‘1’ OR b = ‘1’
 2 parallel nMOS transistors

Slide 20

MOS transistor – ideal switch model

 pMOS, VG = LOW → ON
 pMOS, VG = HIGH → off
 nMOS, VG = LOW → off
 nMOS, VG = HIGH → ON

Slide 21

As a review, how to build multiple inputs gates?

Here are summarized the design examples described so far.

How to generalize this method?

Slide 22

Another design example: NAND and NOR 3 inputs gates.

For a NAND 3 inputs gate, the number of inputs is increased: we have the same configuration: 3
NMOS transistors in series and 3 P channel transistors in parallel. We know the NAND function is
‘0’ only when all inputs are ‘1’. In all other cases, the output must be ‘1’.
That means the generalization for this method implies a number of 2n transistors, n of NMOS type
and another n of p channel MOS type. The NMOS transistors are disposed in a serial connection
and the others in a parallel configuration

Very similar is the implementation of NOR logic function. The output is ‘1’ only when all inputs are
‘0’. This means the p channel transistors must be connected in series and the N transistors block
consists of a network with n parallel NMOS devices.

Slide 23
 Implementation of multiple inputs CMOS logic gates → the nMOS and pMOS transistors
are in complementary deployment
 short-circuit to GND – nMOS “pull-down” network
 the “pull-down” network implements if logic function in direct logic
 short-circuit to VDD – pMOS “pull-up” network
 the “pull-up” network implements the logic function in complementary logic
 “pull-up” and “pull-down” are complementary
 the function variables are connected to both networks
 pull-up – n transistors
 pull-down – n transistors
 the function output is the common node of the two networks
 Important: CMOS logic gates always implement the inverted function

Slide 24
 The MOS transistor can be regarded as a controlled switch
 series connection → AND → the input signal reaches the output if both switches
are closed
 parallel connection → OR → the input signal reaches the output if at least one
switch is closed

Slide 25

The method presented before could be used to implement any logic function written as a sum of
products.
First example is a 3 variable function f defined as it follows: f = ab + c

pull-down → 2 series nMOS transistors and 1 nMOS transistor in parallel with the ab series group
pull-up → 2 parallel pMOS transistorand 1 pMOS transistor in series with the ab parallel group

Slide 26

Second example is a 3 variable function f defined as it follows: f = a·(b + c)

pull-down → 2 parallel nMOS transistors and 1 nMOS transistor series with the a b parallel group
pull-up → 2 serial pMOS transistoras and 1 pMOS transistor in parallel with the a b serial group

Slide 27

The previous examples show to implement the negated sum of products.

The implementation of logic gates in direct logic require the connection of an inverter to the CMOS
gate output.

Examples: AND and OR 2 inputs gates

Slide 28

example 3 – the 4-input AND-OR and OR-AND gates

AND - OR f1 = ab + cd
OR - AND
f2 = (a+b) · (c+d)

Conclusions

- To get a n variables function we need a 2n transistors circuit: n NMOS devices are placed in
a pull-down network and the other p NMOS transistors are placed in a pull-up network
- The networks are complementary but also they are dual: for a serial connection of NMOS
transistors corresponds a parallel network of PMOS devices and vice versa.
- It is true that any logic function given as sum of products can be implemented in this way
- When the literal number increases, it is obvious that the number of the transistors is also
increasing and thus, as we will see later, the circuits will become slower, needing the
transistors to be resized for not excessively slowing down the processing speed.
- When increasing the dimensions, the circuits will need a bigger surface, so that is has to be
avoided the direct implementation of a function with many variables.
- This kind of function will be implemented by cascaded circuits, each of them having fewer
inputs.

Slide 29

Transmission gate

The transmission gate is a circuit that allows or not the transmission between two points
inside a circuit.
In figure the structure of such a circuit is drawn. This contains two transistors, an nMOS and
a pMOS, having the grids separately controlled but the sources connected together.
The signals applied on the grid are in opposite phases, operation realized with the aid of an
inverter.
 When the selection signal A is equal to logic ‚1” , both transistors work, and the input X is
transmitted to the output Y. If A=0, both transistors are cutoff, the circuit offering in this situation a
high impedance to the output.

In figure 9.21 are given the symbols of the transmission gate used in the design of VLSI
circuits. The first, (figure 9.21,b), describes the fact that the transmission gate is an bidirectional
element used as such, while the second, (figure 9.21,c) is used for showing that inside the respective
aplication, the direction of the data transmitted is only one, the one given by the symbol.

The transmission gate is a fundamental structure in CMOS structures. It appears in

multiplexing signals configurations, latch flip-flops or as an analogic switch. Therewith, it can
operate as a resistor controlled between the input and output terminals.

Slide 30

The three state inverter (three-state or tri-state) is obtained by cascading an inverter and a
transmission gate, as shown in figure.
When the control signal A is in logic state LOW, the inverter is in logic state HIGH, the
transmission gate is off, and the inverter output Y is in high impedance state Z.
If A = HIGH and its inverse, LOW, the output Y follows the value of the input X .
In figure the symbol of the three-state inverter is given , which works in the way described above.

Using two buffers and an inverter, like seen in figure 9.23.a, a two channel multiplexer is realized.
One can see that, if A=0, at the output X0 is transmitted and if A=1, at the output X1 is transmitted.
So we can recognize the functioning of the classical two channel multiplexer, described by the
equation:
Y = A�
X0 + A �
X1

Slide 31
A fundamental sequential circuit is the D flip-flop. It is used in many aplications as a
component cell of the registers with serial or parallel shift, but also as a memory cell. In figure 9.24
the princeiple scheme of the D flip-flop is presented, flip-flop that works on the clock rising edge,
realized with a specific VLSI circuit technique. The flip-flop contains two 2:1 multiplexers, the one
is the MASTER, actioned on the rising edge of the clock and the other, the SLAVE, actioned on the
falling edge of the clock.
When the signal CK=0, the MASTER multiplexer follows the D input , while the SLAVE
multiplexer keeps the previous state. At a transition of the clock signal from 0 to 1, the first
multiplexer keeps the previous state, stopping to follow the D input. The second multiplexer follows
the value QM, which is equal to the D signal, existing at the input, at the positive transition of the
clock. At a negative transition, the MASTER multiplexer starts again to follow the input signal, and
the whole process is repeating.
Thus, this circuit allows the data reading at the input on the clock rising edge. If we want a
circuit working on the clock falling edge, we have to invert the two multiplexers, process that can
be equal with the change of the labels X1-X0 for each multiplexer.