DIGITAL SIGNAL PROCESSORS

AND ARCHITECTURES
Subject Code:(A80437)
Regulations : R16 JNTUH
Class:IV Year B.Tech ECE II Semester

Department of Electronics and communication Engineering

BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY
Ibrahimpatnam -501 510, Hyderabad
 DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
(A80437)
COURSE PLANNER
I. COURSE OVERVIEW:
Digital Signal Processing (DSP) is being used very widely in applications that include
telecommunication equipment, multimedia systems, electronic and bio-medical
instrumentation, automotive systems and many military and weapon systems. DSP chips,
general processors or dedicated ASIC chips, are now able to process wide bandwidth signal
of all sorts in real-time.
Digital Signal Processors take real-world signals like voice, audio, video, temperature,
pressure, or position that have been digitized and then mathematically manipulate them. A
DSP is designed for performing mathematical functions like "add", "subtract", "multiply"
and "divide" very quickly. The application of DSP is only limited by our imagination
instead of DSP technology itself.
II. PREREQUISITS:
1. Digital Electronics
2. Microprocessors
3. Digital Signal Processing
III. COURSE OBJECTIVES:

1. To recall digital transform techniques.

To introduce architectural features of programmable DSP Processors of TI and
2.
Analog Devices.
To give practical examples of DSP Processor architectures for better
3.
understanding.
To develop the programming knowledge using Instruction set of DSP
4.
Processors.
5. To understand interfacing techniques to memory and I/O devices.

IV. COURSE OUTCOMES:

S.No. Description Bloom’s Taxonomy
Level
1. Understand the basics of Digital Signal Processing and Knowledge,
transforms. Understand
(Level1, Level2)
2. Able to distinguish between the architectural features of Apply, Create
General purpose processors and DSP processors. (Level 3, Level 6)
3. Understand the architectures of TMS320C54xx devices. Analyze (Level 4)
4. Understand the architectures of ADSP 2100 DSP Analyze (Level 4)
devices.

IV Yr-ECE – II Sem. 54
 5.Able to write simple assembly language programs using Knowledge,
instruction set of TMS320C54xx. Understand
(Level1, Level2)
6. Can interface various devices to DSP Processors. Analyze (Level 4)
V. HOW PROGRAM OUTCOMES ARE ASSESSED:
Proficien
Lev cy
Program Outcomes (PO)
el assessed
by
Engineering knowledge: Apply the knowledge of
mathematics, science, engineering fundamentals, and an Assignme
PO1 engineering specialization to the solution of complex 3 nts,
engineering problems related to Electronics & Exercises
Communication and Engineering.
Problem analysis: Identify, formulate, review research
literature, and analyze complex engineering problems related
Assignme
PO2 to Electronics & Communication Engineering and reaching 3
nts
substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
Design/development of solutions: Design solutions for
complex engineering problems related to Electronics &
Assignme
Communication Engineering and design system components
PO3 3 nts,
or processes that meet the specified needs with appropriate
Exercises
consideration for the public health and safety, and the
cultural, societal, and environmental considerations.
Conduct investigations of complex problems: Use
research-based knowledge and research methods including Assignme
PO4 3
design of experiments, analysis and interpretation of data, nts
and synthesis of the information to provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate
Assignme
techniques, resources, and modern engineering and IT tools
PO5 3 nts,
including prediction and modeling to complex engineering
Seminars
activities with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the
contextual knowledge to assess societal, health, safety, legal
PO6 and cultural issues and the consequent responsibilities 2 Seminars
relevant to the Electronics & Communication Engineering
professional engineering practice.
Environment and sustainability: Understand the impact of
the Electronics & Communication Engineering professional Assignme
PO7 engineering solutions in societal and environmental contexts, 3 nts,
and demonstrate the knowledge of, and need for sustainable Seminars
development.
IV Yr-ECE – II Sem. 55
 Proficien
Lev cy
Program Outcomes (PO)
el assessed
by
Ethics: Apply ethical principles and commit to professional
PO8 ethics and responsibilities and norms of the engineering - -
practice.
Individual and team work: Function effectively as an Oral
PO9 individual, and as a member or leader in diverse teams, and 2 Discussi
in multidisciplinary settings. ons
Communication: Communicate effectively on complex
Documen
engineering activities with the engineering community and
t
with society at large, such as, being able to comprehend and
PO10 2 Preparati
write effective reports and design documentation, make
on,
effective presentations, and give and receive clear
Presentati
instructions.
on
Project management and finance: Demonstrate knowledge
and understanding of the engineering and management
Assignm
PO11 principles and apply these to one’s own work, as a member 3
ents
and leader in a team, to manage projects and in
multidisciplinary environments.
Life-long learning: Recognize the need for, and have the
Assignme
PO12 preparation and ability to engage in independent and life- 3
nts
long learning in the broadest context of technological change.
1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None
VI. HOW PROGRAM SPECIFIC OUTCOMES ARE ASSESSED:

Proficienc
Leve
Program Specific Outcomes y assessed
l
by
Professional Skills: An ability to understand the basic
concepts in Electronics & Communication Engineering and to
Lectures,
PS apply them to various areas, like Electronics,
3 Assignment
O1 Communications, Signal processing, VLSI, Embedded
s
systems etc., in the design and implementation of complex
systems.
Problem-Solving Skills: An ability to solve complex
PS Electronics and communication Engineering problems, using
3 Tutorials
O2 latest hardware and software tools, along with analytical skills
to arrive cost effective and appropriate solutions.

IV Yr-ECE – II Sem. 56
 Successful Career and Entrepreneurship: An understanding
of social-awareness & environmental-wisdom along with
PS Seminars,
ethical responsibility to have a successful career and to sustain 2
O3 Projects
passion and zeal for real-world applications using optimal
resources as an Entrepreneur.
1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None

VII. SYLLABU:
UNIT – I: Introduction to Digital Signal Processing: Introduction, A Digital signal-processing
system, The sampling process, Discrete time sequences, Discrete Fourier Transform (DFT) and
Fast Fourier Transform (FFT), Linear time-invariant systems, Digital filters, Decimation and
interpolation.
Computational Accuracy in DSP Implementations: Number formats for signals and
coefficients in DSP systems, Dynamic Range and Precision, Sources of error in DSP
implementations, A/D Conversion errors, DSP Computational errors, D/A Conversion Errors,
Compensating filter.
UNIT – II: Architectures for Programmable DSP Devices: Basic Architectural features, DSP
Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities,
Address Generation Unit, Programmability and Program Execution, Speed Issues, Features for
External interfacing.
UNIT-III: Programmable Digital Signal Processors: Commercial digital signal processing
devices, Data Addressing modes of TMS320C54XX DSps, data Addressing moes of
TMS320C54XX Processors, Memory space of TMS320C54XX processors, program control,
TMS320C54XX instructions and programming, On-Chip Peripherals, Interrupts of
TMS320C54XX processors, pipeline Operation of TMS320C54XX Processors.
UNIT – IV: Analog Devices Family of DSP Devices: Analog Devices Family of DSP Devices-
ALU and MAC block diagram, Shifter Instruction, Base Architecture of ADSP 2100, ADSP-
2181 high performance processor.
Introduction to Blackfin Processor- The Blackfin Processor, Introduction to Micro signal
Architecture, Overview of Hardware Processing Units and Register files, Address Arithmetic
Unit, Control Unit, Bus Architecture and Memory, Basic Peripherals.
UNIT – V: Interfacing Memory and I/O Peripherals to Programmable DSP Devices:
Memory space organization, External bus interfacing signals, Memory interface, Parallel I/O
interface, Programmed I/O, Interrupts and I/O, Direct memory access (DMA).
TEXT BOOKS:
1. Digital Signal Processing – Avtar Singh and S. Srinivasan, Thomson Publications, 2004.
2. A Practical Approach To Digital Signal Processing - K Padmanabhan, R. Vijayarajeswaran,
Ananthi. S, New Age International, 2006/2009
3. Embedded Signal Processing with the Micro Signal Architecture Publisher: Woon-Seng Gan,
Sen M. Kuo, Wiley-IEEE Press, 2007
REFERENCE BOOKS:
1. Digital Signal Processors, Architecture, Programming and Applications–B. Venkataramani
and M. Bhaskar, 2002, TMH.

IV Yr-ECE – II Sem. 57
2. Digital Signal Processing – Jonatham Stein, 2005, John Wiley.
3. DSP Processor Fundamentals, Architectures & Features – Lapsley et al., S. Chand & Co.
4. Digital Signal Processing Applications Using the ADSP-2100 Family, Amy Mar, PHI
5. The Scientist and Engineer's Guide to Digital Signal Processing by Steven W. Smith,
California Technical Publishing
6. Embedded Media Processing, David J. Katz and Rick Gentile of Analog Devices, Newnes
NPTEL Web Course: -NA-
NPTEL Video Course: -NA-
GATE SYLLABUS: -NA-
IES SYLLABUS: -NA-
VIII. COURSE PLAN (WEEK-WISE):

Methodolo
Teaching

Reference
Session

Week

Unit

Course Learning

gy
Topics
Outcomes

Unit-I: Introduction, Know about digital T1

Chalk and
1 A Digital signal- signal processing ,
Talk
processing system system. T2
The sampling Understand the T1
Chalk and
2 process, Discrete sampling process and ,
Talk
time sequences discrete time sequences. T2
Explain Discrete T1
Discrete Fourier Chalk and
3 Fourier Transform ,
1 Transform (DFT) Talk
(DFT). T2
T1
Fast Fourier Explain Fast Fourier Chalk and
4 ,
Transform (FFT) Transform (FFT). Talk
T2
Analyze Linear time-
Linear time- T1
invariant systems and Chalk and
5 1 invariant systems, ,
realize various digital Talk
Digital filters T2
filters.
Know about decimation T1
Decimation and Chalk and
6 and interpolation ,
interpolation Talk
processes. T2
Analyze and design T1
*. DSP using
7 DSP systems using Discussion ,
MATLAB
MATLAB. T2
2
Number formats for Identify various number
T1
signals and formats for signals and Chalk and
8 ,
coefficients in DSP coefficients in DSP Talk
T2
systems systems.
Dynamic Range and Understand dynamic Chalk and T1
9
Precision range and precision in Talk ,

IV Yr-ECE – II Sem. 58
 DSP systems. T2
Sources of error in Know about various T1
Chalk and
10 DSP sources of error in DSP ,
Talk
implementations implementations. T2
A/D Conversion Explain A/D conversion
T1
errors, DSP errors and DSP
11 PPTs ,
Computational computational errors.
T2
3 errors
D/A Conversion Explain D/A conversion T1
12 Errors, errors and compensating PPTs ,
Compensating filter filter. T2
Summarize and solve T1
Revision/ Problems Chalk and
13 problems on above ,
and Discussion Talk
topics. T2
Summarize and solve T1
Revision/ Problems Chalk and
14 problems on above ,
and Discussion Talk
topics. T2
15 Mock Test-I
Unit-II: Basic Understand the basic T1
16 Architectural architectural features of PPTs ,
features DSP devices. T2
DSP Computational Study about DSP
T1
Building Blocks, computational building
17 PPTs ,
4 Bus Architecture blocks, bus architecture
T2
and Memory and memory.
Data Addressing Analyze data addressing
T1
Capabilities, capabilities and address
18 PPTs ,
Address Generation generation unit.
T2
Unit
2 Understand
Programmability and T1
programmability and
19 Program Execution, PPTs ,
program execution and
Speed Issues T2
their speed issues.
20 Bridge Class
Illustrate the features T1
Features for external Chalk and
21 5 for external interfacing. ,
interfacing Talk
T2
Summarize above T1
PPTs,
22 Revision topics. ,
discussions
T2
Unit-III: Know about various Chalk and T1
23 3 commercial digital
Commercial Digital Talk ,

IV Yr-ECE – II Sem. 59
 signal-processing signal-processing T2
Devices devices.
Explain various data T1
Data Addressing
addressing modes of ,
24,2 modes of Chalk and
TMS320C54XX DSPs. T2
5 TMS320C54XX Talk
,
DSPs
R1
26 Bridge Class
Explain various data T1
Data Addressing
addressing modes of ,
6 modes of Chalk and
27 TMS320C54XX T2
TMS320C54XX Talk
processors ,
Processors
R1
Understand memory T1
Memory space of space of ,
Chalk and
28 TMS320C54XX TMS320C54XX T2
Talk
Processors processors. ,
R1
Understand program T1
control of ,
29 Program Control TMS320C54XX PPTs T2
processors. ,
R1
Understand T1
TMS320C54XX TMS320C54XX ,
30 instructions and instructions and its PPTs T2
7 Programming programming. ,
R1
31 Bridge Class
Understand T1
TMS320C54XX TMS320C54XX ,
Chalk and
32 instructions and instructions and its T2
Talk
Programming programming. ,
R1
Understand T1
TMS320C54XX TMS320C54XX ,
Chalk and
33 instructions and instructions and its T2
Talk
Programming programming. ,
8 R1
Know about on-chip T1
34, peripherals of TMS ,
On-Chip Peripherals PPTs
35 processors. T2
,
IV Yr-ECE – II Sem. 60
 R1
9 I Mid Examinations (Week 9)
Know about various T1
Interrupts of interrupts of ,
Chalk and
36 TMS320C54XX TMS320C54XX T2
Talk
processors processors. ,
R1
10
Understand the pipeline T1
Pipeline Operation operation of ,
Chalk and
37 of TMS320C54XX TMS320C54XX T2
Talk
Processors. processors. ,
R1
Know about various T1
Unit-IV: Analog Analog Devices family ,
Chalk and
38 Devices Family of of DSP devices and T2
Talk
DSP Devices- ALU ALU. ,
R1
Demonstrate about the T1
block diagram of MAC. ,
MAC block
39 PPTs T2
diagram
,
R1
40 Bridge Class
Explain about shifter T1
instruction of AD ,
Chalk and
41 Shifter Instruction devices. T2
Talk
,
4 R1
Explain the base T1
11 architecture of ADSP ,
Base Architecture of
42 2100. PPTs T2
ADSP 2100
,
R1
Explain about the T1
ADSP-2181 high architecture of ADSP ,
43 performance 2181 high performance PPTs T2
Processor processor. ,
R1
44 Bridge Class
12 Know about the basics T1
Introduction to
45 of Blackfin processors. PPTs ,
Blackfin Processor
T2
IV Yr-ECE – II Sem. 61
 ,
R1
Explain the architecture T1
of the Blackfin ,
The Blackfin
46 processors. PPTs T2
Processor
,
R1
Explain the micro signal T1
Introduction to architecture of the ,
47 Micro Signal Blackfin processors. PPTs T2
Architecture ,
R1
Summarize various T1
Overview of
hardware processing ,
Hardware
48 units and register files of PPTs T2
Processing Units and
Blackfin processor. ,
Register files
R1
13
Illustrate address T1
arithmetic unit and ,
Address Arithmetic
49 control unit of Blackfin PPTs T2
Unit, Control Unit
processor. ,
R1
Explain bus T1
Bus Architecture architecture, memory ,
50 and Memory, Basic and basic peripherals of PPTs T2
Peripherals Blackfin processor. ,
R1
51 Bridge Class
52 Mock Test-II
T1
Know about memory ,
Unit-V: Memory Chalk and
53 space organization in T2
space organization Talk
DSP devices. ,
R3
14 T1
,
5 External bus Understand external Chalk and
54 T2
interfacing signals bus interfacing signals. Talk
,
R3
T1
Explain about
Chalk and ,
55 Memory interface interfacing memory to
Talk T2
DSP devices.
,

IV Yr-ECE – II Sem. 62
 R3

Explain various T1
memory mapping ,
*. Memory Mapping Chalk and
56 methods. T2
Methods Talk
,
R3
57 Bridge Class
Solve problems on T1
15 memory interfacing. ,
Problems on Chalk and
58 T2
memory interface Talk
,
R3
T1
,
Understand parallel I/O Chalk and
59 Parallel I/O interface T2
.interface. Talk
,
R3
T1
,
Understand
60 Programmed I/O PPTs T2
programmed I/O.
,
R3
T1
,
Understand about
61 Interrupts and I/O PPTs T2
16 interrupts and I/O.
,
R3
62 Bridge Class
Know about DMA T1
operation. ,
Direct memory
63 PPTs T2
access (DMA).
,
R3
Solve problems on T1
DMA. ,
Chalk and
64 Problems on DMA T2
Talk
,
17 R3
Revise above topics. T1
PPTs,
Revision/ Problems ,
65 Discussion
and Discussion T2
s
,

IV Yr-ECE – II Sem. 63
 R3
18 II Mid Examinations (Week 18)
IX. MAPPING COURSE OUTCOMES LEADING TO THE ACHIEVEMENT OF
PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES:
Cour Program Outcomes Program
se Specific
Outc Outcomes
omes P P P P
PO P PO PO PO PO P PO PS PS PS
O O O O
2 O3 4 5 6 7 O8 9 O1 O2 O3
1 10 11 12
CO1 3 3 3 3 3 2 2 - 2 2 3 3 1 1 1
CO2 - 3 3 2 2 2 2 - 2 2 3 2 2 2 2
CO3 3 3 - 3 2 - - - - - 3 - - - 2
CO4 - - 3 - 3 2 3 - 2 2 - 3 3 3 2
CO5 3 3 3 - 2 - - 2 2 3 3 3 3 2
CO6 3 3 3 3 3 - 3 - 2 - 3 2 3 - 2
Aver 2. 2.2 1.8
3 3 3 2.8 2.6 2 2.5 - 2 2 3 2.4
age 6 5 3
Aver
age
3 3 3 3 3 2 3 - 2 2 3 3 3 3 2
(Rou
nded)
1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None
X. JUSTIFICATIONS FOR CO-PO MAPPING:
Mapping Low Justification
(1),
Mediu
m (2),
High(3
)
CO1- Students will be able to understand Digital Signal
3
PO1 Processing and transforms.
CO1- Analyze the Digital Signal Processing and transforms.
3
PO2
CO1- Students will be able to know the concept of DFT and
3
PO3 FFT.
CO1- Understand the sampling process and discrete time
3
PO4 sequences.
CO1- Analyze Linear time-invariant systems and realize various
3
PO5 digital filters.
CO1- 2 Know about decimation and interpolation processes.

IV Yr-ECE – II Sem. 64
 PO6
CO1- Analyze and design DSP systems using MATLAB.
2
PO7
CO1- Identify various number formats for signals and
2
PO9 coefficients in DSP systems.
CO1- Understand dynamic range and precision in DSP systems.
2
PO10
CO1- Know about various sources of error in DSP
3
PO11 implementations.
CO1- Explain A/D conversion errors and DSP computational
3
PO12 errors.
Explain D/A conversion errors and compensating
CO1-
1 filter.Derive various field configurations in rectangular
PSO1
waveguides.
CO1- Analyze Linear time-invariant systems and realize various
1
PSO2 digital filters.
CO1- Know about decimation and interpolation processes.
1
PSO3
CO2- Analyze and design DSP systems using MATLAB.
3
PO2
CO2- Identify various number formats for signals and
3
PO3 coefficients in DSP systems.
CO2- Understand the basic architectural features of DSP
2
PO4 devices.
CO2- Study about DSP computational building blocks, bus
2
PO5 architecture and memory.
CO2- Analyze data addressing capabilities and address
2
PO6 generation unit.
CO2- Understand programmability and program execution and
2
PO7 their speed issues.
CO2- Illustrate the features for external interfacing.
2
PO9
CO2- Know about various commercial digital signal-processing
2
PO10 devices.
CO2- Explain various data addressing modes of
3
PO11 TMS320C54XX DSPs.
CO2- Understand memory space of TMS320C54XX processors.
2
PO12
CO2- Understand program control of TMS320C54XX
2
PSO1 processors.
CO2- Understand TMS320C54XX instructions and its
2
PSO2 programming.
CO2- 2 Know about on-chip peripherals of TMS processors.
IV Yr-ECE – II Sem. 65
 PSO3
CO3- Know about various interrupts of TMS320C54XX
3
PO1 processors.
CO3- Understand the pipeline operation of TMS320C54XX
3
PO2 processors.
CO3- Know about various Analog Devices family of DSP
3
PO4 devices and ALU.
CO3- Demonstrate about the block diagram of MAC.
2
PO5
CO3- Explain about shifter instruction of AD devices.
3
PO11
CO3- Explain the base architecture of ADSP 2100.
2
PSO3
CO4- Explain about the architecture of ADSP 2181 high
3
PO3 performance processor.
CO4- Explain the architecture of the Blackfin processors.
3
PO5
CO4- Explain the micro signal architecture of the Blackfin
2
PO6 processors.
CO4- Summarize various hardware processing units and register
3
PO7 files of Blackfin processor.
CO4- Illustrate address arithmetic unit and control unit of
2
PO9 Blackfin processor.
CO4- Explain bus architecture, memory and basic peripherals of
2
PO10 Blackfin processor.
CO4- Know about memory space organization in DSP devices.
3
PO12
CO4- Understand external bus interfacing signals.
3
PSO1
CO4- Explain about interfacing memory to DSP devices.
3
PSO2
CO4- Explain various memory mapping methods.
2
PSO3
CO5- Solve problems on memory interfacing.
3
PO1
CO5- Understand parallel I/O interface.
3
PO3
CO5- Know about DMA operation.
3
PO4
CO5- Understand the basic architectural features of DSP
2
PO6 devices.
CO5- Study about DSP computational building blocks, bus
2
PO9 architecture and memory.
IV Yr-ECE – II Sem. 66
 CO5- Analyze data addressing capabilities and address
2
PO10 generation unit.
CO5- Demonstrate about the block diagram of MAC.
3
PO11
CO5- Explain about shifter instruction of AD devices.
3
PO12
CO5- Explain the base architecture of ADSP 2100.
3
PSO1
CO5- Explain about the architecture of ADSP 2181 high
3
PSO2 performance processor.
CO5- Explain the architecture of the Blackfin processors.
2
PSO3
CO6- Explain the micro signal architecture of the Blackfin
3
PO1 processors.
CO6- Summarize various hardware processing units and register
3
PO2 files of Blackfin processor.
CO6- Illustrate address arithmetic unit and control unit of
3
PO3 Blackfin processor.
CO6- Explain bus architecture, memory and basic peripherals of
3
PO4 Blackfin processor.
CO6- Know about memory space organization in DSP devices.
3
PO5
CO6- Understand external bus interfacing signals.
3
PO7
CO6- Explain about interfacing memory to DSP devices.
2
PO9
CO6- Explain various memory mapping methods.
3
PO11
CO6- Solve problems on memory interfacing.
2
PO12
CO6- Understand parallel I/O interface.
3
PSO1
CO6- Know about DMA operation.
2
PSO3
XI. QUESTION BANK (JNTUH) :
UNIT - I
Long Answer Questions:
S.N Question Blooms Cou
o. Taxonomy rse
Level Out
com
e

IV Yr-ECE – II Sem. 67
 Draw the block diagram of a DSP System and
1. Remember 1
explain in detail the function of each block.
Compare FIR and IIR filters with diagrams
2. Remember 1
(Apr/May 2009).
Explain in detail about Decimation filter and
3. Understand 1
Interpolation filter. (May 2010).
Explain the term Aliasing with an illustration .How
4. Remember 1
can Aliasing be overcome in a DSP system.
Write Notes on Analysis and Design tools for DSP
5. Understand 1
systems (Sept 2008).
Compute the dynamic range and percentage
resolution of Signal that uses a) 16 point Fixed
6. point format b) 32 point floating Point with 24 bits Apply 1
for the mantissa and 8 bits for the exponent.
(May 2010).
Calculate the dynamic range and precision of each
of the following number representation formats a)
7. 48 bit double precision fixed point format b) a Apply 1
floating point format with a 16 bit mantissa and a 8
bit exponent. (May 2010)
Explain about A/D conversion errors in a DSP
8. system and derive expressions for mean, variance Understand 1
and SNR. (May 2010)
Find the degradation in amplitude gain when a sine
wave of unit amplitude and 50 HZ frequency,
9. Apply 1
sampled at 400 HZ , is reconstructed using a Zero
order Hold. (May 2010)
Explain about the different number formats for
10. Understand 1
signals & coefficients
Short Answer Questions:
S. Question Blooms Cours
No Taxonomy e
. Level Outco
me
1. Draw the block diagram of a DSP System. Remember 1

2. Discuss the sampling process. Understand 1

List various sources of error in DSP
3. Understand 1
implementations.
Define dynamic range and precision of a DSP
4. Remember 1
system.
5. Give the formula for DTFT. Understand 1

IV Yr-ECE – II Sem. 68
 With suitable mathematical expression, define
6. Remember 1
Discrete Fourier Transform (DFT).
7. What is twiddle factor? Evaluate 1

8. Prove any two properties of DFT. Remember 1

9. Discuss the computational complexity of DFT. Understand 1

10. Write short notes on compensating filter. Understand 1

UNIT - II
Long Answer Questions:

S.N Question Blooms Course

o. Taxonomy Outcome
Level
What are the DSP computational building blocks?
1.
Explain with diagrams any two of them. Knowledge 2
(Apr/May 2009)
Explain with a neat diagram the functioning of a
2. Understand 2
Barrel Shifter.
Explain with a neat diagram the functioning of a
3. Understand 2
Braun Multiplier.
List the major architectural features used in a DSP
4. to achieve high speed of program. (Apr/ May Understand 2
2009)
Explain the functioning multiply and Accumulator
5. Remember 2
unit with a Diagram. (Apr/May 2009)
Explain the DSP addressing modes with suitable
6. Understand 2
examples.
Explain the architectural differences between DSP
7. Understand 2
processors and Microprocessors.
Explain in detail different techniques adopted for
8. increasing the number of memory Analyze 2
accesses/instruction cycle.
Explain the function of a MAC unit and also explain
9. how overflow and underflow conditions can be Knowledge 2
avoided in MAC operations.
Explain how bit reversed addressing is achieved in
10. Analyse 2
TMS320C54XX Processor.
Short Answer Questions:
S.No Question Blooms Course
. Taxonomy Outcome

IV Yr-ECE – II Sem. 69
 Level
Explain why a MAC operation is implemented in
1. Remember 2
hardware in programmable DSPs.
Explain the difference between Von Neumann and
2. Understand 2
Harvard architecture for the computer.
3. Mention some applications of on-chip timer in P-DSPs. Understand 2
What are the different ways in which the operand for
4. instructions can be specified using indirect addressing Understand 2
mode?
5. Explain what is meant by instruction pipelining. Evaluate 2
6. What is the use of host port in P-DSPs? Evaluate 2
7. List various DSP computational building blocks. Remember 2
8. Define interlocking. Understand 2
9. Differentiate between stack and pipeline. Remember 2
10. List the features of external interfacing. Understand 2
UNIT - III
Long Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcome
Level
Explain about the various Pipe lining models with
1. emphasis on interlocking, branching effects and Remember 3
interrupt effects. (May 2010)
What is Hardware looping? Explain in detail various
2. Understand 4
nestings (May 2010)
Write short notes on a) Interrupts b) interrupt vectors
3. Understand 3
c) Interrupt latency d) stacks
Explain the DSP addressing modes with suitable
4. Understand 3
examples.
Write a sequence of TMS320C54xx instructions to
configure a circular buffer with a start address at 0200h
5. Understand 4
and an end address at 021fh with current buffer pointer
(AR6) pointing to address 0205h.
What will be the contents of accumulator A after the
execution of the instruction LD * AR4, 4, A if the
6. current AR4 points to a memory location whose Analysis 4
contents are 8b0eh and the SXM bit of the status register
STI is set?
7. Briefly explain about program control unit of Understand 4
IV Yr-ECE – II Sem. 70
 TMS320C54XX processor.
Briefly explain about circular addressing mode of
8. Understand 4
TMS320C54XX with suitable example.
Write a program for the implementation of the
9. Understand 4
decimation filter using TMS320C54XX.
10. Write a program for the second order IIR filter. Remember 4
Short Answer Questions:
S.No. Question Blooms Course
Taxonomy Outco
Level me
List various commercial digital signal
1. Remember 3
processing devices.
Can you load the T register using immediate
2. Remember 3
addressing mode? if so give an example.
Explain the operation parallel instructions of
3. Understand 3
54XX.
Compare address and data buses of 54X and
4. Remember 3
5X.
5. What is the use of guard bits in accumulators? Analyze 3
Explain the operation of parallel instructions of
6. Understand 4
54X.
Give the interrupts of TMS320C54XX
7. Remember 4
processors.
List out various peripherals of TMS320C54XX
8. Remember 4
processors.
List out various groups of instructions of
9. Remember 4
TMS320C54XX processors.
List out various addressing modes of
10. Remember 4
TMS320C54XX processors.
UNIT - IV
Long Answer Questions:
S.No Question Blooms Course
. Taxonomy Outco
Level me
Give the architecture of analog DSP device
1. Understand 5
ADSP21XX.
Compare the performance of ADSP 21XX
2. Remember 5
with TMS320C54XX family.
List the registers of ADSP family
3. Understand 5
architectures.
4. Describe the procedure to implementation of Understand 5

IV Yr-ECE – II Sem. 71
 FIR filter design using ADSP21XX.
Write about on-chip peripherals of DASP
5. Analyze 5
21XX.
6. Write about Blackfin processor architecture. Remember 5
7.
Discuss on Blackfin processor applications. Remember 5
Draw and discuss on ALU data flow of
8. Analysis 5
Blackfin processor.
Describe in detail about the memory
9. Understand 5
operations of Blackfin processors.
Discuss the bus architecture of Blackfin
10. Remember 5
processors.
Short Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcom
Level e
What is the Data Memory (RAM) available for
1. Remember 5
ADSP 21XX features?
What is the Program Memory (RAM) available
2. Remember 5
for ADSP 21XX features?
List out the capabilities if serial port of ADSP
3. Understand 5
21XX families.
Write about various pin definitions of ADSP
4. Remember 5
21XX.
5. Compare various Analog DSPs. Remember 5
6. Draw the block diagram of ALU. Understand 5
7. Draw the block diagram of MAC. Remember 5
List various hardware processing unit of
8. Understand 5
Blackfin processor.
List various hardware register files of Blackfin
9. Understand 5
processor.
List various basic peripherals of Blackfin
10. Understand 5
processor.
UNIT - V
Long Answer Questions:
S.No. Question Blooms Cours
Taxonomy e
Level Outco
me
Explain the use of DMA Register. Write
1. Understand 6
code to show how the DMA channel 5

IV Yr-ECE – II Sem. 72
 context registers can be initialized. Choose
arbitrary values to be written in the registers.
Write the flow chart of interrupt handling by
2. Understand 6
the processor. Explain the operation.
Draw the block diagram for the A/D
converter interface in the programmed I/o
3. Understand 6
mode. Show the flow chart diagram for the
software polling for the above.
Write short notes on (a) Direct Memory
4. Access (b) Flash Memory Interface to DSP Remember 6
Processor.
Explain memory space organization in DSP
5. Remember 6
processors using suitable sketches.
Draw the memory interface block diagram of
6. TMS320C5416 processor and explain its Understand 6
operation.
Explain with example the flash memory
7. Understand 6
interface for the TMS320C54XX DSP.
Design a circuit to interface 64k words of the
program memory space from 0FFFFFh to
8. Understand 6
0F0000h for the TMS320C5416 processor
using 16K x 16 memory chips.
Draw the timing diagram for memory
interface for read-read-write sequence of
9. Understand 6
operation. Explain the purpose of each signal
involved.
What are interrupts? How interrupts are
10. Remember 6
handled by C54xx DSP Processors.

Short Answer Questions:

S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. What are interrupts? Remember 6
Describe DMA with respect to
2. Remember 6
TMS320C54XX processors.
Explain an interface between an A/D
3. converter and the TMS320C54XX Understand 6
processor in the programmed I/O mode.
Explain the memory interface block
4. Analyze 6
diagram for the TMS 320 C54xx processor.

IV Yr-ECE – II Sem. 73
 Draw the I/O interface timing diagram for
5. Analyze 6
read – write read sequence of operation.
List various external bus interfacing
6. Understand 6
signals.
7. Write short notes on memory interfacing. Remember 6
8. Discuss parallel I/O interface. Remember 6
9. Write short notes on programmed I/O.. Understand 6
10. Give the advantages of DMA. Understand 6
OBJECTIVE QUESTIONS:
UNIT-I
1. The minimum sampling rate required to reconstruct the signal f(t) = 21000t from its
samples is ………… [ ]
a)1kHz b) 2kHz c) 500Hz d) 10 kHz
2. A multi-rate system is required for converting the sampling rate from 48K samples to
42.1 K samples. The interpolation factor, decimation factor to be used is….[ ]
a) 147, 160 b) 160, 147 c)480, 421 d) 421, 480
3. Which of the following properties are true for an IIR filter designed using impulse
invariant technique? [ ]
a) Requires the use of anti-aliasing filter
b) Required prewarping the filter cutoff frequencies.
c) Not suited for the design of HP filters
d) Results in unique mapping from analog to digital frequencies
4. The cut off frequency of the reconstruction filter for a signal sampled at a frequency of fs
is ………….. [ ]
a) fs/2 b) fs c) 2fs d) fm
5. The number of stages of FFT computations required for the computation of the DFT of a
512 point sequence is ….. [ ]
6. The number of multiplications required for performing the convolution of two sequences
with identical length 8 using the direct method is……………………………
7. At the fifth stages of FFT computations required for the computation of the DFT of a
512- point sequence is………………………………….
a) 9 b)3 c) 7 d) 6
8. The number of complex additions required in computing an N-point DFT is ……………
9. Truncation error is given as …………….
10. The ……………..of a signal is the ratio of the maximum value to the minimum value
that the signal can take in the given number representation.
UNIT-II
1. A P-DSP has four pipeline stages and uses four phase clock. The number of clock cycles
required for executing a program with 25 instruction is …………… [ ]
a) 29 b) 28 c) 25 d) 26

IV Yr-ECE – II Sem. 74
 2. The number of instruction cycles required for executing a program in a microprocessors
with no pipelining is ……….. [ ]
a) 1 b)2 c)3 d)4
3. The addressing that permits the content in internal register of the CPU & I/O to be
accessed as memory location is …………. [ ]
a) Indirect addressing b) Bit reversed addressing
c) Memory mapped d) Circular mode
4. The serial port that permits the data from a number of I/O devices to be sent using a
single serial port is called ………..…. [ ]
a) Comm port b) Host port
c) Time division multiplexing d) Bit I/O port
5. Which of the following characteristics are true for a RISC processor? [ ]
a) Smaller control unit b) Small instruction set
c) Short program length d) Less traffic between CPU & memory
6. The feature in which PDSP is superior to advanced microprocessor is …………
7. VLIW architecture differs from conventional P-DSP in the aspect of………………
8. Number of memory accesses/ clock/ period that can be achieved using on chip DARAM
of a P-DSP is……………
9. In modified Harvard architecture for fetching the content of program and data memory, a
separate bus is used for …………..memory and a single bus is used for……………
10. The addressing mode that is convenient for FFT computation is ……………………
UNIT-III
1. Which of the following are available in 54X but not in 5X? [ ]
a) SP b) 16 bit timer c) XPC d) 8-bit HPI
2. In LD || MAC parallel instruction, the register where the MAC result is stored is………
[ ]
a) A b) B c) Either a or b d) T register
3. Which of the following registers are present in 5X but not in 54X? [ ]
a) PC b) SP c) PREG d) INDX
4. Number of address in 54X is………… [ ]
a) 1 b) 2 c) 3 d) 4
5. …………..is used to store the result of multiplier units in the ALU of 54X.[ ]
a) Accumulator A b) Accumulator B c) Either A or B d) PREG
6. Number of Auxiliary ALUs in 54X is ………………and number of data buses which can
be used for reading data from data memory is………………
7. Number of data bus in 54X is………..
8. ……………is used to store the result of adder units in the ALU of 54X.
9. The maximum number of wait states that software generator can produce
is………………..
10. ……………..is used to store the result of multiplier units in ALU 54X.
UNIT-IV
1. Blackfin Processors are ideal for …………………………………. [ ]
a) Portable and networked digital media appliances

IV Yr-ECE – II Sem. 75
 b) Consumer communications and networks
c) Automotive telematics, safety driver assistant, and infotainment
d) Industrial instrumentation and medical equipment
The ADSP-2100 family instruction set is grouped into the following computational
category. [ ]
a) ALU, MAC, Shifter b) Move c) Program Flow
d) Multifunction e) All the above
2. In DSP processors, which among the following maintains the track of addresses of input
data as well as the coefficients stored in data and program memories?[ ]
a) Data Address Generators (DAGs) b) Program sequences
c) Barrel Shifter d) MAC
3. In Von Neumann architecture, which among the following handles all the operations of
the system that are inside and outside the processor? [ ]
a) Input Unit b) Output Unit c) Control Unit d) Memory Unit
4. In ADSP 21xx architecture, which notation represents ALU overflow condition?[ ]
a) AC b) AV c) NE d) EQ
5. In ADSP 21 xx architecture, ……….. number of previously executed instructions are
stored in instruction cache of cache memory.
6. The 24-bit instruction word allows a high degree of …………in performing operations.
7. ADSP 21XX provides ……….guard bits.
8. In DSP Processor, ……….. kind of queuing is undertaken/executed through instruction
register and instruction cache.
9. The ADSP-2183 can respond to …………………….possible interrupts.
UNIT-V
1. What is the meaning of RAM, and what is its primary role? [ ]
a) Readily Available Memory; it is the first level of memory used by the computer in
all of its operations
b) Random Access Memory; it is memory that can be reached by any sub- system within
a computer, and at any time.\
c) Random Access Memory; it is the memory used for short-term temporary data storage
within the computer.
d) Resettable Automatic Memory; it is memory that can be used and then automatically
reset, or cleared, after being read from or written to.
2. The time interval between adjacent bits is called the……. [ ]
a) Word time b) Bit-time c) Turnaround time d) Slice time
3. Process that periodically checks status of an I/O devices, is known as ……. [
]
a) Cold swapping b) I/O instructions c) Polling d) Dealing
4. A bus connecting processor and memory, is known as ………. [ ]
a) Processor transaction b) Bus transaction c) Backplane bus d) Synchronous bus
5. In direct memory access mode, the data transfer takes place …… [ ]
a) directly b) indirectly c) directly and indirectly d) None
6. A bus connecting processor and memory is known as…………..

IV Yr-ECE – II Sem. 76
 7. A unit on bus that initiates bus requests is called ……………………
8. Request, which is used for indicating a read request for memory, is known as…………..
9. The check sum method of testing a ROM………….
10. The storage element for a static RAM is the…………………….
XII. WEBSITES:
1. https://www.dspguide.com
2. https://www.analog.com
3. www.ti.com › Processors
4. bwrcs.eecs.berkeley.edu/Classes/CS252/Notes/Lec09-DSP.pdf
5. https://www.oreilly.com/library/view/vlsi-digital-signal
6. www.usrmodem.ru/files/tms320.pdf
XIII. EXPERT DETAILS:
1. Mr. S. Srinivasan, Professor, Indian Institute of Technology, Madras
2. Dr. P. V. D. Somasekhar Rao (JNTUH)
3. Dr. T.Satya Savithri (JNTUH)
4. Mrs N Mangala Gouri (JNTUH)
5. Dr.D.Rama Krishna (O.U)
6. Dr.K.Chandra Bhushana Rao (JNTUK)
7. Dr. V. Sumalatha (JNTUA)
8. Dr. M.N Giriprasad (JNTUA)
XIV. JOURNALS:
INTERNATIONAL
1. International Journal of Advanced Research in Electrical, Electronics and Instrumentation
Engineering
2. International Journal of Embedded Systems
3. IEEE Transactions. Acoustics, Speech and Signal Processing.
4. TMS 320C54XXDSP Reference Set Vol.1, Texas Instruments Inc.
5. TMS 320 VC 5416 DSK Technical Reference, Spectrum Digital Inc., 506 005 – 0001
NATIONAL
1. Journal on Digital Signal Processing
2. ICTACT Journal On Communication Technology
3. IETE Journal of Research
4. Journal of Electrical Engineering and Electronic Technology
XV. LIST OF TOPICS FOR STUDENT SEMINARS:
1. DSP Based Biotelemetry Receiver
2. ECG Signal Processing for Heart Rate Determination
3. Digital Model for Production of Speech Signal
4. Image Processing System
5. JPEG Algorithm Overview
XVII. CASE STUDIES / SMALL PROJECTS:
1. The Industrial Application of DSP.
2. Speech Recognition using DSP.
3. VLSI Structures for DSP., 4. Biomedical Applications of DSP.

IV Yr-ECE – II Sem. 77