‫‪Ain Shams University‬‬

‫‪Faculty of Engineering‬‬
‫‪3rd year CSE Department‬‬

‫‪MIPS Processor Project Report‬‬

‫‪Submitted to‬‬
‫‪Prof. Ashraf Salem‬‬
‫‪Eng. Ahmad Fathy‬‬

‫‪Submitted by‬‬
‫‪ID‬‬ ‫‪Name‬‬
‫‪1600008‬‬ ‫إبراهيم حسن إبراهيم محمد‬
‫‪1600766‬‬ ‫عبد هللا خالد أحمد محمود‬
‫‪1600813‬‬ ‫عبد هللا ناصر عبد هللا عبد المقصود‬
‫‪1600885‬‬ ‫عمر عبد العزيز مرجان عبد العزيز‬
‫‪1600888‬‬ ‫عمر عبد الباسط عبد المقصود عبد الفتاح‬
‫‪1600890‬‬ ‫عمر عبد الوهاب عبد المنعم على‬
‫‪1600899‬‬ ‫عمر فتحي حامد محمود‬

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 List of contents
What Does Our Project Support? ………………………………. 2
Overall mention to all modules ………………….……….…...… 2
Brief description of each module …………………….…………. 3
The MIPS connections ………….………………..….….………. 5
The synthesizer output …………………………………….…….. 8
Brief description of the design ……………………………..…… 10
Design extensions ……………………………………………..… 10
Some used assumptions …………………………………….…...10
Test cases ………………………………………………………….11
MIPS processor & assembler test bench ……………………….16
Contribution of each member of the team ………………………19

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What Does Our Project Support?
Our design supports the following:
1- Implementation of MIPS single cycle processor using Verilog HDL. Our
MIPS processor is fully synthesizable (Xilinix synthesizer gives no warnings
at all).
2- Implementation of MIPS assembler in C++. The assembler itself supports
comment writing, branching labels and writing instructions in uppercase
or lowercase letters.
3- A GUI that accepts assembly code in form of files or line by line writing.
This GUI also calls Verilog (iverilog) code directly.
4- Automated testing procedure in which tester only have to click on one
single button then the program will run five test cases that are mentioned
in this report, and finally it will indicate whether the result is correct or
not. The program also informs on what test cases has failed in case of
failure.

Overall Mention to All Modules

The design consists of the following modules:
-PC
-PC_add
-Instruction_memory
-Register_file
-ALU
-Data_memory
-Control
-ALU_Control
-Branch_add
-shift_left_extender
-Mux_regdst
-Mux_jal
-Sign_extend
-Mux_alusrc
-Mux_pcsrc
-Mux_memtoreg
-Mux_jaddress
- Shift_left
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Brief Description of Each Module
PC
PC module has 2 inputs (clock and next instruction) and 2 outputs (instruction
and last instruction). On positive edge of clock, it sets the instruction address to
the value of next instruction address and sets the last instruction address to the
value of last executed instruction address.
PC_add:
PC_add has 1 input(instruction) and 1 output (next instruction). It sets the value
of next instruction address to the value of instruction address + 4.
Instruction_memory
Instruction_memory has 4 inputs (instruction, address, instructioninput, write
memory clock) and 1 output (instruction data). It’s a memory that holds the
instructions that will be executed it receives those instruction in simulation by
simply reading a text file but in hardware it has 3 ports 1 called address one
called instruction and write memory clock, by the write memory clock positive
edge the instruction input is written in the memory address using the write
memory clock ,instruction input and address ports consecutively.
To obtain data from the instruction memory, the instruction port is used for
address and data is written in instruction data the output port.
Register_file
Register_file has 6 inputs (read reg1, read reg2, write reg, write data, reg write,
clk) and has 2 outputs (read data1, read data2). It holds the value of 32 registers
the first 1 is zero and can't be changed the 29th (counting from zero) is the stack
pointer. We choose which registers to read using the read reg1 and read reg2
ports and choose which register to write using write reg and the write data port
is used to write the data entering it and the write occurs on positive edge clock
cycle only when reg write equals 1. The data read is found on the output ports
read data1 and read data2
ALU
ALU has 4 inputs (read_data1, read_data2, shamt, ALU_op) and has 2 outputs
(result, zero_flag). read_data1 and read_data2 are the two data lines that the
alu will operate on, shamt determines the shift value that will be used by
shifting operations and alu_op determines the operation that the alu will do.

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The operation output is written in result and if data1 equal to data2 then zero
flag is automatically set to 1, else it is set to zero.
Data_memory
Data_memory has 5 inputs (address, write_data, mem_write, mem_read, clk)
and 1 output (read_data). Memory stores 1024 word each word is 32 bits. It can
be read from or written in using address port to select the memory address to
write in it. For writing operation, mem_write must equal 1 and data is written
by write_data port. For reading operation, mem_read must equal 1 and data is
written on read_data port. Writing occurs at positive clock edge.
Control
Control has 2 inputs (instruction, function) and has 11 outputs (Jr, Jal, Jump,
RegDst, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite).
Control unit is the brain of the processor. It sets its output signals depending on
the instruction and function inputs. By means of its output signals, the
processor knows what to do.
ALU_Control
ALU_control has 2 inputs (instruction, ALUOp) and 1 output (ALU_op).
Depending on the instruction and the ALUOp, ALU_Control gives as an output
the ALU_op signal to ALU specifying the operation the ALU should do.
Branch_add
Branch_add has 2 inputs (incremented instruction address, extended instruction
address) and 1 output (branch instruction address). It simply adds the
incremented instruction to the shifted left instruction to do the branching part
(connections will be stated later after defining all the modules).
Shift_left_extender
shift_left_extender has 1 input (shift) and 1 output (shifted). It assigns the
output to the input but connects 2 zeros on the right.
Sign_extend
Sign_extend has 1 input (instruction) and 1 output (extended_instruction). It
extends the instruction from 16 bit to 32 bit it does a logic extend keeping the
sign.
Shift_left
Shift_left has 1 input(shift) and 1 output (shifted). It shifts the input 2 digits left
and puts the result in shifted.
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Mux_jal
Mux_jal has 2 inputs (b_write_register,Jal) and 1 output (write_register).
It’s present before the register write data port. If the instruction is jal, it writes
to the register Ra which is the register that has number 31, else it writes the
register number coming from port b_write_register
Mux_regdst
Mux_jal
Mux_alusrc
Mux_pcsrc
Mux_memtoreg
Mux_jaddress
All muxes do the same thing, they have 3 inputs (choice1, choice2 and selector)
and 1 output (result). By the result signal they choose one of the inputs and
puts it on the output. They differ in locations and number of bits they are
dealing with.
The MIPS Connections
Connections will be stated as follows: inputs and outputs for each module in
order of their pin numbers stated in each module.
Module Name Inputs Outputs
shift_left_extender instruction_data[25: extendedinst
0]
PC ninstruction instruction
clk last_instruction
Instruction_memory instruction[11:2] instruction_data
address
instruction_input
writememclk
PC_add instruction incinstruction
Mux_regdst instruction_data[20: b_write_register
16]
instruction_data[15:
11]
RegDst
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Mux_jal b_write_register write_register
Jal
Register_file instruction_data[25: read_data1
21] read_data2
instruction_data[20:
16]
write_register
write_data
RegWrite
clk
Sign_extend instruction_data[15: extended
0]
Mux_alusrc read_data2
extended
ALUSrc
Mux_pcsrc incinstruction n_instruction
binstruction
PCSrc
and gate Branch PCSrc
zero_flag
ALU read_data1 result
data2 zero_flag
instruction_data[10:
6]
ALU_op
Data_memory result[11:2] read_data
read_data2
MemWrite
MemRead
clk
Mux_memtoreg read_data b_write_data
result
MemtoReg
Control instruction_data[31: Jr
26] Jal
instruction_data[5:0 Jump
] RegDst
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 Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
ALU_Control ALUOp ALU_op
instruction_data[5:0
]
Branch_add incinstruction binstruction
extended_shifted
Mux_jaddress jaddress b_ninstruction
n_instruction
Jump
Mux_alusrc (2)(just a b_write_data write_data
normal mux but used incinstruction
an existing module) Jal
Mux_alusrc (3)(just a b_ninstruction ninstruction
normal mux but used read_data1
an existing module) Jr

shift_left extended[29:0] extended_shifted

The jump address takes the incremented instruction from bit 31-28 and connect
it to extended instruction which is 28 bits only.

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The Synthesizer Output:
Xilinix Synthesizer is used.

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9|Page
Brief Description of The Design:
The design of our MIPS processor is the same design of the MIPS we studied
with certain extensions. The design does the first instruction before the first
positive edge of clock, but it does not write anything until the positive clock
edge occurs. The instructions addresses are in byte addressing so as for the
memory addressing. It supports the following instructions add - sw - lw - sll - and -
or - beq - J - JAL - JR - addi - ori - slt the instruction memory is written from the
outside by a clock and address and the instructions. The data memory and the
instruction memory are both 1024 words, so they are addressed only by 10 bits.
The design receives its operation clock from the outside.
Design Extensions:
A shamt port is added to the alu that takes the instruction bits 10-6 and a new
alu control output signal is made to tell the ALU to shift left and shift left is
included in ALU to support the SLL as it shifts left by that shamt input. To
support JAL instruction added a new control Jal signal to the control unit and 2
muxes 1 special mux that has the value of Ra register and gets the value of the
register needed to be written if the Jal signal is 1 it outputs register Ra address
else chooses the other register address and the output goes to write register
port in register file. The other mux takes the value of the next instruction
address and the value of the data to be written also if jal is 1, its output will be
the next instruction address and output goes to write data port in register file to
be written. To support JR instruction, we made the control get the function
space in the instruction now the input to the control is added by instruction bits
5-0 and added a new signal Jr and a new mux the mux gets the value of the true
next instruction whether its branch incremented jumped whatever and the
value of read data1 from the register file and if the value of Jr signal is 1 the mux
chooses the read data1 value which is an address and sends it to the PC.
The Assumptions Used:
We assumed that the instruction memory is from the outside by a fast clock an
address value and an input value and it’s written before the processor starts
operation by its normal clock.
The stack pointer is pointing to the last memory address.

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Test Cases:
Test Case 1:
Test case purpose: Testing LW & SW instructions.
Assembly C++
addi $s3,$zero,20 int A[]={1,2,3,4,5};
addi $t1,$zero,1 int i = 0;
sw $t1,0($s3)
addi $t1,$zero,2 int sum = 0;
sw $t1,4($s3) int n=4;
addi $t1,$zero,3 do
sw $t1,8($s3)
addi $t1,$zero,4 {
sw $t1,12($s3)
addi $t1,$zero,5 sum += A[i++];
sw $t1,16($s3)
}
addi $s0, $zero, 0
addi $s1, $zero, 0 while (i < =n);
addi $s2, $zero,4
loop: sll $t0, $s0, 2
add $t0, $t0, $s3
lw $t0, 0($t0)
add $s1, $s1, $t0
addi $s0, $s0, 1
slt $t0, $s2, $s0
beq $t0, $zero, loop
Assume $s3 is memory location of A, $s0 is i, $s1 is sum, $s2 is n
Expected output is 15 at sum at $s1
Outputs:
register file: data memory:

PC: 0x50
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Test Case 2:
Test case purpose: This test case is used to make sure that values stored in
memory can be read in the next iteration and the same for the register file.
Assembly C++
addi $s2,$zero,20 int t;
addi $s4,$zero,6 int a=20;
addi $s3,$zero,16 int b=6;
addi $t1,$zero,50 int A[20];
sw $t1,32($s3) A[8]=50;
lw $t0,32($s3) t=A[8];
add $t0,$s2,$t0 t+=a;
add $t1,$s4,$s4 A[6]=t;
add $t1,$t1,$t1
add $t1,$t1,$s3
sw $t0,0($t1)
Assume $s3 is memory location of A, $s2 is a, $s4 is b expected output is 70 at
A[6] at memory location 0x28 and 50 at A[8] at memory location 0x30 and 20 at
$s2 and 6 at $s4
Outputs:
register file: data memory:

PC: 0x28

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Test Case 3:
Test case purpose: Test the case when beq branches up & testing all arithmetic
operations.
Assembly C++
addi $s1,$zero,10 int t,t2;
addi $s2,$zero,50 int a=10; //s1
add $s3,$s1,$s2 int b=50; //s2
addi $s4,$zero,60 int c=a+b; //s3
and $s5,$s4,$s2 int d=60; //s4
or $s6,$s4,$s2 int e=d & b; //s5
ori $s7,$s5,40 int f=d | b; //s6
j main int g=e | 40; //s7
test:sll $t5,$s7,2 int A[5];
sw $t5,($s4) if(g<f)
sw $s7,4($s4) {
lw $t7,4($s4) t=g*4;
j exit A[0]=t;
main:slt $t1,$s7,$s6 A[1]=g;
addi $t2,$zero,1 t2=A[1];
beq $t2,$t1,test
exit: }
Assume $s1 is a, $s2 is b, $s3 is c, $s4 is d, $s5 is e, $s6 is f, $s7 is g, also assume
that $s4 before the j main instruction holds the value of base address of A.
Expected output $s1=10, $s2=50, $s3=60, $s4=60, $s5=48, $s6=62, $s7=56, and
$t7=56, and A[0]=224 which is address 0x3C in data memory.
Outputs:
register file: data memory:

PC: 0x30

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Test Case 4:
Test case purpose: Test the instructions j, jal & testing pushing needed values of
registers in stack.
Assembly C++
addi $s0,$zero,5 int sum(int p, int q)
addi $s1,$zero,3 {
main: add $a0, $s0, $zero int m;
add $a1, $s1, $zero m = p + q;
jal sum2 return(m);
add $s2, $v0, $zero }
j exit int sum2(int x, int y)
sum2: addi $sp, $sp, -8 {
sw $ra, 4 ($sp) return(sum(x,x) + y);
sw $a1, 0 ($sp) }
add $a1, $a0, $zero
jal sum int main()
lw $a1, 0 ($sp) {
lw $ra, 4 ($sp) int a=5,b=3,c;
addi $sp, $sp, 8 c = sum2(a,b);
add $v0, $v0, $a1
jr $ra }
sum: addi $sp, $sp, -4
sw $s0, 0 ($sp)
add $s0, $a0, $a1
add $v0, $s0, $zero
lw $s0, 0 ($sp)
addi $sp, $sp, 4
jr $ra
exit:
Assume $s0 is a and $s1 is b and $s2 is c
Expected output in c is 13 which is $s2

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Outputs:
register file: data memory (stack):

PC: 0x18

Test Case 5: Our MOST POWERFUL Test Case.

Test case purpose: Test the overall functionality of our MIPS processor with
recursive call of fib function (Fibonacci). The code tests arithmetic instructions,
pushing needed registers onto stack, branching and jumping.
Assembly C++
addi $s0, $zero, 5 int fib(int N) {
or $a0, $zero, $s0 if (N == 0) return 0;
jal fib if (N == 1) return 1;
or $s0, $zero, $v0 return fib(N-1) + fib(N-2);
j exit }
fib:addi $sp, $sp, -4
sw $ra, 0($sp) int main()
or $v0, $zero, $zero {
beq $a0, $zero, end int a=5;
ori $v0, $zero, 1 a=fib(a);
beq $a0, $v0, end }
addi $sp, $sp, -8
sw $s0, 0($sp)
sw $s1, 4($sp)
or $s0, $zero, $a0
addi $a0, $s0, -1
jal fib
or $s1, $v0, $zero
addi $a0, $s0, -2
jal fib
or $s2, $v0, $zero
add $v0, $s1, $s2
lw $s0, 0($sp)
lw $s1, 4($sp)
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 addi $sp, $sp, 8
end:lw $ra, 0($sp)
addi $sp, $sp, 4
jr $ra
exit:
Assume $s0 is a.
Expected output is a=5 $s0=5
Outputs:
register file: data memory (stack):

PC: 0x10

MIPS Processor Assembler Test bench:

MIPS test bench is a program that enables the user to assemble
MIPS assembly code to machine code and run this machine code on a
model of MIPS processor written in Verilog and Compiled by Icarus
Verilog. The Program also enable the user to test his Verilog model of
the processor via comparing the output of specific tests to a trusted
output to those tests. In case of success the program will inform the
user that all cases passed the tests otherwise it will inform the user
which test cases failed.
Giving input to the program:
The input can be given in two ways:
• Writing the code directly to the GUI
• Opening a text file that contains the code

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Test your model:

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• In case of success:

• In case of failure:

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Contribution of each member of the team
ID Contribution
1600008 Making all the processor from A to Z in parallel with
the delivered processor to insure that our idea is
correct.
1600766 Writing GUI code using QT, interfacing GUI with
verilog & making automated test strategy and code.
1600813 Writing Control unit module.
1600885 Making MIPS assembler (idea and implementation in
C++).
1600888 Providing two cases & making instruction memory,
Data memory & test bench modules.
1600890 Assembling all modules, testing the whole MIPS
processor module, doing synthesizer work, and
providing test cases.
1600899 Making ALU, ALU_Control, Register_file modules.

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