Novatek MCU

NT68400 Series
NT68400 System Design Guidelines
Application Notice
V0.1
TABLE OF CONTENTS
1 Document History ....................................................................................................................................4
2 System Layout Guide ..............................................................................................................................5
2.1 Layout placement recommendations ..........................................................................5
2.2 Power and Ground Guidelines .....................................................................................7
2.3 ADC Signal Guidelines..................................................................................................7
2.4 DP/HDMI/DVI Interface Guidelines .............................................................................9
2.5 Vx1 / eDP / LVDS Interface Guidelines .................................................................... 11
2.6 Un-used and Reserved signals Guidelines ..............................................................13
2.7 DDR3 Interface Guidelines .........................................................................................13
2.8 System Power Structure .............................................................................................19
3 Product ID ...............................................................................................................................................19
4 Register optimum setting ......................................................................................................................19
4.1 ADC Operating Setting: ..............................................................................................19
4.2 DisplayPort Receiver ...................................................................................................23
4.3 DisplayPort Transmitter ..............................................................................................24
4.4 TMDS/HDMI Receiver Operating Setting: ...............................................................27
4.5 HDMI / TMDS Transmitter Operating Setting: .........................................................35
4.6 LVDS/DPLL Operating Setting: .................................................................................41
4.7 MPLL Operating Setting: ............................................................................................45
4.8 Other Operating Setting: .............................................................................................47
4.9 MAU Operating Setting: ..............................................................................................49
4.10 DDR3_PHY Operating Setting:..................................................................................53
4.11 OD Operating Setting: .................................................................................................58
4.12 USB Type C BMC IO Operating Setting: ......................................................................58
4.13 HDR Application Setting: ...........................................................................................60
4.14 LDC (Local dimming control) Application Setting: .......................................................62
4.15 LDC GPIO Pins control Setting: ....................................................................................65
5 OD Application Guide ............................................................................................................................66
5.1 OD engine block diagram ...........................................................................................66
5.2 OD control register mapping ......................................................................................66
5.3 OD frame definition ......................................................................................................66
5.4 OD Window Control (Reg. 0x4B80~0x4B88) ..........................................................67
5.5 OD compression mode ...............................................................................................67
5.6 OD S/W setting sequence ..........................................................................................67
5.7 OD Threshold Setting ..................................................................................................67
5.8 OD Response Time Measurement Setting ..............................................................68
6 Audio Application Guide ........................................................................................................................69
6.1 Audio Setup Block .......................................................................................................69
6.2 Audio PLL Function .....................................................................................................69
6.3 Setup Audio General Control .....................................................................................70
7 Vx1 TX Control .......................................................................................................................................79
7.1 Control Registers .........................................................................................................79
7.2 Vx1 TX pin assignment ...............................................................................................79
7.3 Vx1 TX Data mapping and lane control ....................................................................79
7.4 S/W control flow. ..........................................................................................................81
8 Vx1 RX Control.......................................................................................................................................82
8.1 Control Registers .........................................................................................................82
8.2 Vx1 RX Data mapping and lane control ...................................................................82
8.3 Vx1 RX default setting ...................................................................................................83
8.4 S/W control flow. ............................................................................................................84
9 USB Reference circuit ...........................................................................................................................85
2
3
1 Document History
NT68400 series APN: Document History
Version Content Data

NT68400 Preliminary (First version)
V0.1 20171214
Modify from NT68390
4
2 System Layout Guide
2.1 Layout placement recommendations
NT68400
NT68400
NT68402
NT68402
5
NT68409
6
2.2 Power and Ground Guidelines
It’s the most important part of the PCB layout and should always be carefully considered in
the system design.
1. Maximize the ground plane area. The circuit board should have one large common
ground plane.
2. All ground pin should be directly connected to the ground layer through vias and as
short as possible of the length.
3. The component and solder side should be filled in with copper wherever possible.
4. Every power supply pin of the NT68400 series should connect to a ceramic bypass
capacitor. The capacitors should be position in the closest possible to the power pin and
double via should be used wherever possible.
5. To minimize plane-to-plane cross coupling noise and to maintain a low noise level,
power plane should be isolated with 25 mil-wide.
6. Each isolate power plane should be positioned close to their associated VDD pin and
ferrite beads should be positioned directly over the slits.
Bulk capacitors should be places near the power regulator, close to ferrite bead and
scattered in area of each VDD
7. One de-coupling capacitor should be used for each VDD/GND pin pair
8. The power group should be separated.(Please reference to NT68400 application
schematic)
9. The power trace width should be >= 40mil, can minimize the trace resistance and
minimize the power noise.
10. PLL power is more sensitive to noise. Please see section 2.4 to make sure the
schematic and placement can meet this rule.
2.3 ADC Signal Guidelines

1. ADC:
a. Move the NT68400 series as close as possible to VGA D-SUB connector
b. The length of each line (RIN+/-, GIN+/-, BIN+/- input to NT68400 series) should be
equal.
c. The analog RGB should be routed on the top layer with 8 ~10 mil-wide traces and
be connected directly from D-SUB to NT68400 series, not routing by any via.
d. Each signal pair should run parallel from the chip to near the connector to minimize
common mode noise.
2. Do not run any digital signal over analog area, ex HS, VS, SDA, SCL...
3. Aid out RIN+/- , GIN+/- , BIN+/- trace impedance as 75 Ohm.
4. RIN+/- , GIN+/- , BIN+/- avoid closed prevent signal Coupling.
5. Terminate 75 Ohm should be put at the input D-sub first.
6. Add bypass capacitor in the input Hs, Vs Signal First, can minimize the bounce effect
avoid bounce noise couple to input signal.
7
RED+ FB409 30 OHM R454 75R 1/16W 5% C440 47nF
RIN+ 5
R453
D404 Parallel Line
75 R 1/16 W 5%
R460 100R 1/16W 5% C444 47nF
RIN- 5
BAV99
1
C447
Keep space in ESD_5V 0.1uF 16V
Signal pair of
R/G/B
GREEN+ FB407 30 OHM R455 75R 1/16W 5% C441 47nF

GIN+ 5
3
R458
D405 Parallel Line
75 R 1/16 W 5%
R461 100R 1/16W 5% C445 47nF

GIN- 5
BAV99
2
C448
ESD_5V
0.1uF 16V
Figure 1 Recommended Input Signal schematic
VS
C VSIN PIN
100
ZD5V6 100PF
A
GND_A GND_A
HS
C HSIN PIN
100
ZD5V6 22PF
A
GND_A GND_A
Figure 2 Recommended Input Hs, Vs Signal schematic
8
2.4 DP/HDMI/DVI Interface Guidelines
1. Receiver Trace Routing
The receiver chip should be placed as close as possible to the input connector that caries
the TMDS signals. For a system using the industry-standard HDMI/DVI connector, the
differential lines should be routed as directly as possible from connector to receiver.
Differential pair length is not critical but ideally should be less than 10cm. The routing for the
PanelLink chips is relatively simple since no spiral skew compensation routing is needed.
However, a few small precautions are required to achieve the full performance and reliability
of PanelLink. The receiver trace routing care should be taken to route each differential signal
pair together. Via should be avoided, but if used they should be placed on both signal lines
of the differential pair in a way that gives both lines equivalent reflection characteristics and
minimize the number of via the signal lines are routed through.
Figure 3 Example of acceptable differential signal routing
Figure 4 From chip to DVI connector signal trace routing example

Do not split the pairs and minimize the number of vias. Vias are very inductive and can cause
phase delay
9
Figure 5 Pair separation and excessive or asymmetric via routing is not recommended
2. Impendence
As defined in the HDMI and DVI and MHL and DP Specification, the impedance of the traces
between the connector and the receiver should be 100 ohm differentially, The 100 ohm
requirement is to best match the differential impedance of the cable and connectors, to
prevent reflections. The common mode currents are very small on the TMDS interface, so
differential impedance is more important than single-ended.
Avoid any trace across DVI/HDMI/MHL input differential pair (top or bottom) just routing
AGND to reduce DVI EMI reflection.
10
4 Layer PCB Rule
PCB Layer Stacking
4-Layer Example:
 Layer 1 component + signal side (short traces)
 Layer 2 ground plane
 Layer 3 power plane
 Layer 4 component + signal side
PCB Stack up Example:
Layer Property Thickness (mil)
Top side solder mask 0.8
L1 Copper + plating 1.5
Prepreg 4
L2 copper 1.4
CORE 44.5
L3 copper 1.4
Prepreg 4
L4 Copper + plating 1.5
Bottom side solder mask 0.5
PCB Differential Pair Example:
 HDMI / DP / LVDS Differential Impedance 100 ohm;
 MHL Differential Impedance 100 ohm; Common mode Impedance 30 ohm
2.5 Vx1 / eDP / LVDS Interface Guidelines

 SCALER Display Output Part Trace Routing
11
1. The display (Vx1 / eDP / LVDS output on PCB), should be located as close to the
connector as possible to minimize the PCB overall trace length and thus skew as well.
Skew is generally proportional to length, thus a shorter interconnect nominally has less
skew associated with it.
2. In addition TTL/CMOS single-ended lines should be kept away from the differential lines
to minimize any coupling of noise onto the differential pair.
3. The distance between the two signal traces that compose the differential pair is also
controlled. This distance is critical to specify correctly as it is related to both the
differential-mode characteristic impedance of the trace pair and also related to the
differential noise margin of the system.
4. The spacing between the traces should be kept to a minimum to maximize the differential
noise rejection. This minimum distance between the traces of a pair assures that any
external noise coupled onto the pair will be seen as common mode, and rejected by the
receivers.
5. To adjust trace impedance set “S” to a minimum spacing between metal lines, and adjust
the width “W” of the trace to the desired impedance (typically 100 ohm). The distance
between adjacent differential pairs should be at least 2S or greater as shown in Figure 1.
Microstrip traces are usually employed for this inter-connects. It is also possible to design
the inter-connect without any via, thus a better signaling environment. It is recommended
that all impedances should be equal (typically 100 ohm) to minimize any reflections.
Figure 1
6. Differential pair features fast edge rates, therefore the inter-connect between transmitters
and receivers will act as a transmission line. The PCB traces that form this interconnect
must be de-signed with care. The following general guidelines should be adhered to:
 Traces should be designed for differential impedance control (space between traces
needs to be controlled).
 Minimize the distance between traces of a pair to maximize common mode rejection.
 Place adjacent differential trace pairs at least twice (>2S) as far away (as the distance
between the conductors of the pair).
 Place TTL/CMOS (large signals) far away from differential, at least three times (>3S)
away or on a different signal layer.
 Match electrical length of all differential lines.
 Avoid 90˚ bends (use two 45s).
 Minimize the number of via on differential traces.
 Match impedance of PCB trace to connector to media (cable) to termination to
12
minimize reflections (emissions) for cabled applications (typically 100 ohm
differential mode impedance).
2.6 Un-used and Reserved signals Guidelines
1. Unused Inputs:
Unused inputs of NT68400 series should be connected to ground. This is to avoid
unstable conditions when there is no on-chip, pull-up, and pull-down resister on this
input.
2. Unused Outputs:
Unused outputs of NT68400 series should be kept unconnected.
3. Reserved Signals (NC):
These signals are used for factory testing and debugging only. These pins shall be kept
unconnected.
2.7 DDR3 Interface Guidelines

1. The impedance of the single-end traces between the main-chip to DDR3 SDRAM should be 50 ohm, for
the differential traces should be 100 ohm.
2. The SDRAM should be closed to main-chip as possible.
3. The DQ / DQS trace should be routed on layer 1/4.
4. The CMD/ADDR should be routed on top layer 1 and layer 3 , the length after split point as short as
possible.
5. The layer 2/4 is whole ground plane.
6. Layer 4 must be isolated a DRR3 SDRAM power domain for reference plane.
Impedance:
1. All signal planes must be 50 ohm, single-ended, ±10%.
2. All signal planes must be 100 ohm, differential ±10%.
3. All unused via pads must be removed, because they cause unwanted capacitance.
Decoupling Parameter:
4. Use 0.1uF in 0402 size to minimize inductance.
5. Make DDR3_P1P5V voltage decoupling close to the DDR3 SDRAM components and pull-up resistors.
6. Connect decoupling caps between VDDQ and VDD using a 0.1uF cap for every other VDDQ and VDD
pin .
7. Use a 0.1uF cap and 0.01uF cap for every VDDQ pin.
General Routing:
1. Use 45° angles (not 90° corners).
2. Ground shielding of differential pair, ex. DQS/DQS#, CLK/CLK#. (GND/ Signal+ / Signal- / GND)
3. Route over appropriate VCC and GND planes.
4. Keep signal routing layers close to GND and power planes.
5. The signal traces (CMD/ADDR/CLK) are routing between the Scaler to SDRAM, as shown in figure 2.
(Trace length must be L1 = L2)
13
Figure 2
6. Such as CMD/ADDR/CLK, the signal to signal routing distances do not match for minimizing layout.
7. The clock routing is reserved he terminate resistance 100 ohm in which it is in front of T-branch
position, as shown in figure 3.
Figure 3
8. CMD signal does not fine turn trace match.

9. The net of CSn is installed two resistances 200 ohm, such as one pull-up (1.5V) and the other one
pull-down With SDRAM
10. CMD / DQ / DQS – do not install damping resistance in the circuit.
DQ/DM Rules :
DQ/DM Impedance Control Zo=50 ohm
DQ-to-DQ spacing > 10 mils
DQ-to-DM spacing > 10 mils
DQ-to-CMD/ADDR spacing > 10 mils
Group1 : DQ[7:0] + DM[0] + PKG+PCB Length Matching Tolerance +/- 20 mils
DQS0_P/N
Group2 : DQ[15:8] + DM[1] + PKG+PCB Length Matching Tolerance +/- 20 mils
DQS1_P/N
Group3 : DQ[23:16] + DM[2] PKG+PCB Length Matching Tolerance +/- 20 mils
+ DQS2_P/N
Group4 : DQ[31:24] + DM[3] PKG+PCB Length Matching Tolerance +/- 20 mils
14
+ DQS3_P/N
Note1 : It is unnecessary to match routing length among Group1 to Group4.
Note2 : It is unnecessary to match routing length among DQS0 to DQS3.
DQS Rules :
DQS Differential Impedance Control Zdiff=100 ohm
DQS-to-Others spacing > 12 mils
15
16
CMD/ADDR Rules :
CMD/ADDR Impedance Control Zo=50 ohm
CSN-to-Others spacing > 10 mils
In addition to CSN, other CMD/ADDR-to-CMD/ADDR spacing > 8 mils.
For CMD/ADDR T-branch topology, the trace length of L1 and L2 must be matching. (Toleranc
e +/- 10 mils)
L1
DRAM0
L0
CMD/ADDR
Output Buffer
L2
DRAM1
CLK Rules :
CLK Differential Impedance Control Zdiff=100 ohm
CLK-to-Others spacing > 12 mils
Note1 : matching rule between CLK and Others signals.
17
18
2.8 System Power Structure
3 Product ID
The system can read the chip product ID from the register of 0x4510. NT6840x is 0x16.
4 Register optimum setting
4.1 ADC Operating Setting:
 ADC OP Operate current select guide:
ADC OP Current Select guide table

0x8014[7:4] 0x8014[3:0] Maximum Input Resolution
4’b0101 4’b0101 1600x1200@75Hz
When you choice the maximum ADC OP current, the current is about 34mA
 SOG mode program procedure:

i. Set the SOG slicer threshold (0x8031[7:3])and enable the SOG slicer circuit
19
(0x8033[7]=1)
ii. Set 0x8033[6]=1, to enable SOG normal operating.
iii. Set 0x8034[5]=1, to enable SOG pull down
iv. To check Hsync and Vsync from Sync processor.
 ADC / HPLL optimum setting:

ADC
Scaler Reg. Function Must Recommend
Non-SOG mode: 0
0x1AB0[3] HSYNC_SEL
SOG mode: 1
0x8023 CMCTL[2:0] 0x20
0x8019 ADC_CMP_BIAS 0x60

PDOWNB
0x8033[4:2] PU_ALL 3b' 111
PDN_PPLNBIAS
Non-SOG mode EN_SOG_SLICER: 2b' 00
0x8033[7:6]
SOG mode EN_SOG_SLICER: 2b' 11
0x8035[7:5] Power up Power up RGB channel 3b' 111
ADC clamp mode
Normal: 3b' 111
0x8022[7:5] RGB+ input clamping
YPbPr input: 3b' 111
(VMID) enable setting
Normal: 0
0x8011[7] VMID_ON
YPbPr input: 1
Normal: 3b' 000
0x8012[7:5] CLAMP_MODE2[2:0]
YPbPr input: 3b' 101
Analog bandwidth select ( B-
0x8009[7:4] 4b' 0000 *5
input capacitor select )
Analog bandwidth select
0x800A[7:4] 4b' 0000 *5
( B+input capacitor select )
Analog bandwidth select ( G-
0x800B[7:4] 4b' 0000 *5
Analog bandwidth select ( G+
0x800C[7:4] 4b' 0000 *5
Analog bandwidth select ( R-
0x800D[7:4] 4b' 0000 *5
Analog bandwidth select ( R+
0x800E[7:4] 4b' 0000 *5
0x8033[5] SOG Input_SEL 1b' 0
SOG Pull up Clamp Current
0x8032[7:5] 3b' 000
Control
SOG discharge current biasing
0x8030[7:6] 2b' 11
setting
0x8033[7:6] EN_SOG_SLICER 2b' 11 SOG or Non-SOG
20
PU_SOG [6]:must set 1
0x8031[7:3] SOGTH[4:0] 5b' 11100
Enable trimming function
0x8020[7] 1b' 0
Internal 0.7V
0x8020[4] Internal 0.18V 1b' 0
0x4507 HS schmitt 0x37
0x4508 VS schmitt 0x37
0x4507[7] HS schmitt power 0
0x4507[3] HS schmitt mux 0
0x4508[7] VS schmitt power 0
0x4508[3] VS schmitt mux 0
capture clk invert
0x1A05[6] VGA mode 0 (reset value)
Main
0x1A16[4] Sample clk invert VGA mode 1 (reset value)
0x45AE[1] Sample clk invert 1
Non-SOG mode 0
0x8034[5] SOG pull down resister
SOG mode 1
0x8021[4] bandgap sel. 1 (bandgap)
0x8014 ADC current 0x55
Power down ADC LDO
0x8033[0] 1 : Power down 1b' 1 (External LDO) *3
0 : Power up
comparator
0x8014 0x55 current
(細調)
0x801E LDO 1V voltage adj 0x40 LDO1V=1.099V
0x801A LDO 1V ref voltage 0x20 LDO1V=1.099V
第一級的
0x8017 0x88 level-shifter 電
流(粗調)
ADC Normal to Low Power Mode

0x4507 HS schmitt 0x88
0x4508 VS schmitt 0x88
0x8033[6] PU_SOG 0
PDOWNB
0x8033[4:2] PU_ALL 3b' 000
PDN_PPLBIAS
0x8035[4] PDN_BG 1b' 0
0x8035[7:5] Power up ADC RGB channel 3b' 000
21
0x8033[0] PD_LDO 1b' 0
Note:
*3 : Not support External LDO, default using internal LDO
5: This setting is bandwidth selected, user can fine-tune by himself.
APLL
0x4904 PU_LDO_D[3:0] 0xFE
PU_RG20
0x4905 0xA1
BG_OP_EN
0x4906 0x83
0x4907 0x00
0x4908 0x05 MPLLx5
0x4909 0x71
0x490A 0xFF
0x490B 0x80
HPLL
0x490C 0x03
[1] HDDS_EN
0X4A00 0X33
[0] PU_HPLL
0X4A01 [1] PFD_PDB 0x02
phase lock filter
0x4A02 0x81
[0] hpll_plock_en
0x4A0E 0x50
0x4A08~
HPLL Div FW control
0x4A09
0x4A0F 0x0C
0x4A10 0x02
VGA separate sync refer to *1
0x4A01[5]
VGA composite/sog sync refer to *2
[7] HPLL_OP_LOOP
0x4A01[7:6] 2b' 00 (reset value)
[6]HS_QUICK_UNLOCK_CHK
DATA_SMP_INV
0x4A00[4] 1
data sample invert
HS≦25K , 0x0A
25K＜HS≦50K ,
OSC12M
0x0B
0x0DB HPLL line
0x4A11[3:0] count HS＞50K , 0x0C
*1 : HPLL counts auto load for Separate sync for 0x4A01[5] :

a. HS＞25K( OSC=12M) , always set “0”
b. HS≦25K( OSC=12M) , set “0” while f/w detect mode change and to set “1” to disable auto
load function after mode change .
*2 : HPLL counts auto load for Composite/SOG sync 0x4A01[5]:

22
Set “0” while f/w detect mode change and to set “1” to disable auto
load function after mode change .
4.2 DisplayPort Receiver

DP RX
Scaler Reg. Recommend
Function Must
Page Offset
0x450F[2:0] DP clock off 3b' 000
0x3C87[4:3] DP rclk select 2b'00
0x459D[7] DP rck gated 1b’0
0x10,0x15 0x00[4:0] Fix Hardware error 5b' 11111
0x10,0x15 0x01[3:0] BIST 4b' 0000
<300K 0x34
0x10,0x15 0x2A AUX_I2C
≥300K 0x37
0x10,0x15 0x2B[6] AUX_I2C 1b’1
0x10,0x15 0x2B[5:0] TX_PRE_CHG_NUM 6b’011001
0x10,0x15 0x2C[5:0] RX_PRE_CHG_NUM 6b’001111
0x10,0x15 0x2E[5] mask_aux_i2c_rw_sel 1b’1
0x10,0x15 0x2E[4] aux_i2c_rd_fix 1b’1
0x10,0x15 0x2E[0] iic_bus_free_fix 1b’1
0x10,0x15 0x2F DP reference clock OSC CLK(MHz)X4
0x10,0x15 0x32[1] GR_DK_SAMPLE_SEL 1b’1
0x10,0x15 0x32[0] GR_DQ_SAMPLE_SEL 1b’1
0x10,0x15 0x33[7] Error detection enable 1b’1
0x10,0x15 0x33[3:0] HPD_RE_PULSE_WAIT 4b’ 0111
0x10,0x15 0x34 CERR_RANGE 0x50
0x10,0x15 0x35 ALIGN_RANGE 0x80(reset value)
0x10,0x15 0x37 Error Detection 0x38
0x10,0x15 0x39[3] anti_stupid_m_ld 1b’1
0x10,0x15 0x3A[4:0] HPD_IRQ_WIDTH 4b’ 0111
0x10,0x15 0x3F MN control 0x20(reset value)
DP_FIFO_DE_OUT_METH
0x10,0x15 0x45[6] 1b’1
OD_SEL
0x10,0x15 0x46 DP Video mode control 0x13/0x17
0x10,0x15 0x50[7] audio fifo enable 1b’1
0x10,0x15 0x57 audio clock cycle 0x03
0x10,0x15 0xBC reg_m_lsb_cross_th 0xF0
0x10,0x15 0xC0[3] the_new_de_attrib 1b’0
0x10,0x15 0xC5[1] r_cdr_done_mask_dis 1b’0
DP PHY
5.4G=0x21
0x8206 CDR_EN_CDR 2.7G=0x27
1.62G=0x2F
0x8207 CDR_EN_PD 0x05
0x8208 CDR_SEL_ICP 0x08
0x820A CDR_EN_COMP 0x21
0x820B CDR_SEL_VL/VH 0x22
0x820C CDR_CP_EN 0x31
23
0x820D CDR_LF_R 0x09
5.4G=0x08
0x820E CDR_VCO_SPD 2.7G=0x03
1.62G=0x02
0x82FC AUX_PU 0x64
0x82FD AUX_IMP 0x64
0x82FE AUX_IMP 0x00
Low Power Control

operating mode to power down current
All port:
0x45FD = 0x80(Port sel)
0x45FE = 0x1F (Port sel)
All lane:
0x81D2 = 0x0F (dprm_lane0_hi_page05_en)
CDR:
0x8206 = 0x10
0x820D = 0x00
EQR:
0x8300 = 0x00
0x8302 = 0x00
0x8305 = 0x00
AUX:
0x82FD = 0x00 (REG_AUX_PU)
Bias:
DP RX 0x831C = 0x00 (pu_bias=0)
PS:
Belong HDMI/MHL Block need power down
FA:
0x8320 = 0x00
0x8324 = 0x00
eCBUS & CBUS:
82C0 = 0x00
82C9 = 0x00
82C1 = 0x00
82C4 = 0x00
82C6 = 0x00
82CB = 0x00
82CC = 0x00
82E1 = 0x00
82FA = 0x00
4.3 DisplayPort Transmitter

DP TX
Scaler Reg. Recommend
Function Must
Page Offset
MPLL Init
0x3C87[4:3] DP TX AUX Ref clock 2b’00
0x45AF[6] Daisy LS_CLK Source 1b’0:mpll input
24
0x45AF[7] eDP LS_CLK Source 1b’0:mpll input
0x00, 0x00, 0x2D HBR2
0x4AB1, 0x4AB2,
set DP TX Daisy MPLL 0x00, 0x80, 0x16 HBR
0x4AB3
0x00, 0x80, 0x0D RBR
0x00, 0x00, 0x2D HBR2
0x4AA1, 0x4AA2,
set DP TX eDP MPLL 0x00, 0x80, 0x16 HBR
0x4AA3
0x00, 0x80, 0x0D RBR
Daisy TX PHY Init
0x06 HBR2
0x631A Dclk_inv /dclk_apr_inv 0x00 HBR
0x00 RBR
0x631B En_com /en_ugb 0x06
0x0C HBR2
0x631C BAND 0x04 HBR
0x02 RBR
0x631D PU_LDO_P2S 0xAA
0x631E REG_LDO_P2S 0x48
0x631F EN_LPF/VCO_RESET 0xD2
0x0B HBR2
0x6320 EN_C 0x4B HBR
0xCB RBR
0x6321 VC_SEL 0x20
0x6323 Driving current 0x0D
0x6324 Driving current 0xB6
0x6325 BIAS SEL 0x0F
0x6326 PU_BGR 0xBF
0x6327 EN_ILDO 0xCF
0x6328 SP_EN 0x27
0x632B DrivingLane 0xF1
eDP TX PHY Init
0x6800 BIAS poweron 0x86
0x6833 TX LDO 0x1A
0x6846 Enable PLL 0x01
0x6846 Reset PLL 0x03
0x683D setAPLL 0x4F
HBR2 high speed mode 0x4D
0x6834
HBR/RBR 0x43
0x681F TXR50 0x0C
0x6840 EN P2S power (C port) 0x3C
0x6841 EN P2S power (D port) 0x0F
0x6849 Dis output pull-low 0x03
0x684A Dis output pull-low 0x30
0x6803 EN buf power (C port) 0x3C
0x6804 EN buf power (D port) 0x0F
0x6824 TX output (C port) 0x3C
0x6825 TX output (D port) 0x0F
0x6960 SEL eDP upper 4lane 0x00
[4:2]=100 4lane
0x690C Lane cunt [4:2]=010 2lane
[4:2]=001 1lane
0x690D Cunt_m_EN 0x80
25
0x6964 Done_com/fsm_com 0x07
[1:0]=01 train_pat_com
[2]=1 CDR seL done
CDR_sel_done [6:4]=001 D10.2
0x6963
pattern [6:4]=010 TPS2
[6:4]=101 PRBS7
[7]=1 buf_en_com
TX Link Init
0x62,0x64
0x02 LINK_BW_SET 6 or A or 14
0x65,0x66
0x62,0x64
0x03[4:0] LANE_COUNT_SET 1 or 2 or 4
0x65,0x66
0x62,0x64
0x18[0] reg_auto_non2x_fst 1b’1
0x65,0x66
0x62,0x64
0x18[4] reg_auto_non2x_snd 1b’1
0x65,0x66
0x62,0x64
0x6F[7] reg_dptx_input_port_no 1b’1:dual
0x65,0x66
0x62,0x64
0x71 V,H timing cal threshold 0xFE
0x65,0x66
0x62,0x64
0x76[2] reg_pkr_speed_up 1b’1
0x65,0x66
TX AUX Init
0x4CA1[2:0] Reg_dp_tx_aux_pow 3b’111
0x4CA2[4][0] Reg_dp_tx_aux_rterm_off 2b’00
0x4CA3[0] Reg_dp_tx_aux_rterm_off 1b’0
0x4CA9 Reg_dp_tx_ztm_tx_0 0xE0
0x4CAA Reg_dp_tx_ztm_tx_1 0xE0
0x4CAB Reg_dp_tx_ztm_tx_2 0xE0
0x62,0x64
0x31[0] reg_aux _tx_en 1b’1
0x65,0x66
TX HPD Init
0x62,0x64
0x07 reg_dp_rck_freq OSC CLK(MHz)X4
0x65,0x66
0x62,0x64
0x21[0] reg_hpd_proc_en 1b’1
0x65,0x66
0x62,0x64
0x23 reg_hpd_irq_lth 0x32
0x65,0x66
0x62,0x64
0x24 reg_hpd_irq_hth 0xC8
0x65,0x66
0x62,0x64
0x28[3] reg_hpd_plug_autorst 1b’0
0x65,0x66
Low Power Control

operating mode to power down current
0x631B[3] = 1
0x631D[7] = 0
0x631F[5] = 1, 0x631F[6] = 0
DP_TX
0x6320[1:0] = [00]
0x6326 = 0x00
0x6327[3:0] = 0x00
26
0x6328[5] = 0
0x632A[0] = 0
0x632B[7:4] = 0
0x6801[5:0] = 0
0x6802[5:0] = 0
0x6803[5:0] = 0
0x6804[5:0] = 0
0x6805[5:0] = 0
0x6806[5:0] = 0
0x6807[5:0] = 0
0x6808[5:0] = 0
0x6835[7:4] = 0
0x683E[5:0] = 0
0x683F[5:0] = 0
eDP 0x6840[5:0] = 0
0x6841[5:0] = 0
0x6842[5:0] = 0
0x6843[5:0] = 0
0x6844[5:0] = 0
0x6845[5:0] = 0
0x6846[0] = 0
0x6833[7:6] = 0, 0x6833[3:2] = 0
0x6833[1] = 0
0x6800[7] = 0
0x681F = 0
0x6847-0x684E=3F
4.3.1 DisplayPort Transmitter(Daisy) Route & Bypass Mode Setting

TX_LINK
Register 0x6278[0] 0x4C00[7] 0x4C00[5:0] 0x4C01
SST Route 0 0 0 0
SST Bypass 1 0 X(which loop fifo is used) 0
MST Route 1 1 0 X(which route fifo is used)
MST Bypass 1 0 X(which loop fifo is used) 0
TX_LS_CLOCK
Register 45AF[6] 45AE[2]
from MPLL input 0 X
from DPRX input 1 0 : RX4 phy, 1 : RX3 phy
4.4 TMDS/HDMI Receiver Operating Setting:

For NT68400 HDMI Rx, there are four PHYs and three LINKs. PHY3 output-path can go through to
HDMI Link2 or DP Link1, so RX3 input could be either HDMI or DP. Please refer to the following
figure for simplified diagram. The way of accessing PHY and LINK registers is different from previous
ICs.
27
TMDS-PHY registers are located at page 0x81/0x82/0x83, and 0x45FE is applied to access specific PHY.
The mapping is RX 0/1/2/3 corresponding to 0x45FE [0]/[1]/[2]/[3].
HDMI link0 registers are located at page 0/1/2/3.
HDMI link1 registers are located at page 4/5/6/7.
HDMI link2 registers are located at page 8/9/A/B.
0x45AF[0] is applied to select input-path of HDMI link2 coming from TMDS phy2 or phy3.
All possible TMDS paths are:
“TMDS PHY0 + HDMI LINK0” & “TMDS PHY1 + HDMI LINK1” &
“TMDS PHY2 + HDMI LINK2” & “TMDS PHY3 + HDMI LINK2” &
“TMDS PHY1+ TMDS PHY2 + HDMI LINK1”
4.4.1 HDMI RX – PHY

HDMI Rx – PHY registers
0x02 if access lane1 only

0x81D2 En CDR L1~L3
0x0E if simultaneously
access lane 1~3
0x8200 [6:5]EQR_VB[1:0] = 01 0x21

28
[0] EQR_EN_EQR =1
0x8202 [0] EQR_ZRX_EN 0x01

0x8203 [0]EQR_COMP_EN 1b1
[5]: CDR_RECLK_RSTB 1b1
[4]: CDR_VCO_RESET 1b0
Initial value: 3b000
0x8206
[3:1]CDR_ENC[2:0] Target value:
dependent on timing
[0]CDR_EN_CDR 1b1
[2]CDR phase detector
enable
0x8207 0x05
[0] En VCO IDAC low pass
filter
CDR charge pump current
0x8208 0x06
select
0x820A [0]CDR_EN_COMP 0x21
0x820B 0x14
[1] CDR_EN_4X = 0
0x820C 0x31
[0] CDR_CP_EN =1
0x0A: Low bit rate mode
(Data rate < 1.2GHz)
0x820D
0x08: High bit rate mode
(Data rate > 1.2GHz)
Initial value: 0x08
0x820E CDR_VCO_SPD Target value:
dependent on timing
HDMI 1.4: 0x01(DIV by 1)
0x820F CDR_DIV_SEL
HDMI 2.0:0x08(DIV by 4)
0x8211 En Auto EQ 0x12
0x33: DC_manual,
AC_manual
0x8242
31: DC-gain manual,
AC-gain auto
0x8249 EQ CC Gain By application
0x824A EQ AC Gain_LSB By application
0x824B EQ AC Gain_MSB By application

Channel 0~2 phase lock
0x8296 0x07 (Read only)
flag
Scramble:0x18
(Read only)
0x829B HDMI2.0 CH0~2 LN value
Non-Scramble:0x00
(Read only)
0x829A 0x20
29
[5:4] EQR current
control=11
HDMI 1.4: 0x06
0x8300 [2] Leak-back block
HDMI 2.0: 0x36
enable bar=1
[1] RCK_HDMI enable=1
[7:4]L0~L3 Impedance
0x8302 EN=1111 0xFE
[3:0]L0~3 EQ enable=1110
The setting should
[4:0]L0,2,3 impedance match the impedance
0x8303
control of PCB trace
The setting should
0x8304 [4:0]L1 impedance control match the impedance
of PCB trace
0x830D TMDS CKDT 0x10 (Read only)
0x831C 0xA0
0x831D VCO LDO voltage control 0x02 (1.0V)
[7]L3_N switch on
[6]L3_P switch on
[5]L2_N switch on Before B version
[4]L2_P switch on (included): 0x0F
0x831F
[3]L1_N switch on After C version (included):
[2]L1_P switch on 0xFF
[1]L0_N switch on
[0]L0_P switch on
RX0 HDMI Deep Color PLL COLOR_DEP_SELECT

0x45FE[0]=0x01, page 0/4/8,
Before C (ver.C 0x45[3:0]=4’b0100,
included) version
0x45FD[7]=1b1, set 0x8320 to 0x00,
After D (ver.D 0x8321 to 0x00,
included) 0x8322 to 0x00,
version 0x8323 to 0x00,
RX1
0x45FE[0]=0x02,
page 0/4/8,
RX2 0x45[3:0]=4’b0101 and
0x45FE[0]=0x04, TMDS_CLK<120MHz,
RX3 set 0x8320 to 0xC2,
0x45FE[0]=0x08, 0x8321 to 0x19,
0x8322 to 0x00,
0x8320~0x8323 & 0x8323 to 0x00,
0x3C89
的設定值
page 0/4/8,
0x45[3:0]=4’b0101 and
TMDS_CLK>=120MHz,
set 0x8320 to 0xC0,
0x8321 to 0x19,
0x8322 to 0x00,
0x8323 to 0x00,
30
page 0/4/8,
0x45[3:0]=4’b0110 and
TMDS_CLK<120MHz,
set 0x8320 to 0xC2,
0x8321 to 0x1E,
0x8322 to 0x00,
0x8323 to 0x00,
page 0/4/8,
0x45[3:0]=4’b0110 and
TMDS_CLK>=120MHz,
set 0x8320 to 0xC0,
0x8321 to 0x1E,
0x8322 to 0x00,
0x8323 to 0x00,
page 0/4/8,
0x45[3:0]=4’b0111 and
TMDS_CLK<120MHz,
set 0x8320 to 0xC6,
0x8321 to 0x14,
0x8322 to 0x00,
0x8323 to 0x00,
page 0/4/8,
0x45[3:0]=4’b0111 and
TMDS_CLK>=120MHz,
set 0x8320 to 0xC4,
0x8321 to 0x14,
0x8322 to 0x00,
0x8323 to 0x00,
PD option 開
CP=02
Only for DVI R=2k
case: VC=0.4
CAP_MULT OFF
Check 81D2=0E
1. ENC=111 (8206=2F)
Flow CDR CLK Training
2. CP=02 (8208=02)
3. CAP_MULT OFF (放大 CP mismatch, 因此可嘗試關閉) (820D=0B 關閉)
4. VC_L=0.3,VC_H=0.6V (820b=12)
5. VC=0.4 (820a=11)
6. LF RES: 2k (831B=30)
7. PD OPTION: ON (831B=B0)
31
HDMI Rx – LINK registers
page 0/4/8, HDMI lost sync auto reset 1b1: before sync ready
0x05[4] circuit 1b0: after sync ready
page 0/4/8, Interrupt mode selection 1
0x08[0]
page 0/4/8, HDMI output clk invert 0
0x08[1]
page 0/4/8, HDCP slave address 0x74 HDCP receiver slave
0x3F[7:0] address
page 0/4/8, For H/W HDCP key 1
0x40[3] decryption use
page 0/4/8, For HDMI key download 1 When down load key
0x41[7] use use
page 0/4/8, HDMI Input clk invert 0
0x41[6]
page 0/4/8, HDMI deep color mode 3b' 111 This control must to
0xB4[2:0] auto control set to 3’b111.
page 0/4/8, HDMI video mode auto 0
0xB5[2] control
RX0 YCbCr 4:2:0 If 0x144[7:5]=3’b011,
0x0048[5]的設定值 set 0x0048[5]=1b1
If 0x144[7:5]!=3’b011,
set 0x0048[5]=1b0
If 0x544[7:5]=3’b011,
RX1
0x0448[5]的設定值 set 0x0448[5]=1b1
If 0x544[7:5]!=3’b011,
set 0x0448[5]=1b0
If 0x944[7:5]=3’b011,
RX2 set 0x0848[5]=1b1
0x0848[5]的設定值
If 0x944[7:5]!=3’b011,
set 0x0848[5]=1b0
If 0x944[7:5]=3’b011,
RX3 set 0x0848[5]=1b1
0x0848[5]的設定值
If 0x944[7:5]!=3’b011,
set 0x0848[5]=1b0
page 0/4/8, repetition If page 1/5/9,
0x08 0x48[3:0]=4b0000 (x1),
32
 0x08[7:4]=4b0000
0x48[3:0]=4b0001 (x2),
 0x08[7:4]=4b0101
0x48[3:0]=4b0011 (x4),
 0x08[7:4]=4b1111
HDMI Rx – Global registers

0x4599[7] & DVI DUAL-LINK 0x4599[7]=1b1, If RX1 & RX2 input is
0x4599[3] 0x4599[3]=1b1 dual-link timing
0x3C89 HDMI LINK PLL Clk COLOR_DEP_SELECT
page 0/4/8,
0x45[3:0]=4’b0100,
 0x3C89[0]/[1]/[2]=1b1
 0x3C89[4]/[5]/[6]=1b1
page 0/4/8,
0x45[3:0]=4’b0101,
 0x3C89[4]/[5]/[6]=1b1
 0x3C89[0]/[1]/[2]=1b0
page 0/4/8,
0x45[3:0]=4’b0110,
 0x3C89[4]/[5]/[6]=1b1
 0x3C89[0]/[1]/[2]=1b0
page 0/4/8,
0x45[3:0]=4’b0111,
 0x3C89[4]/[5]/[6]=1b1
 0x3C89[0]/[1]/[2]=1b0
RX0 YCbCr 4:2:0 If 0x144[7:5]=3’b011,
0x4590[0]的設定值 set 0x4590[0]=1b1
If 0x144[7:5]!=3’b011,
set 0x4590[0]=1b0
RX1 If 0x544[7:5]=3’b011,
0x4590[1]的設定值
set 0x4590[1]=1b0
If 0x544[7:5]!=3’b011,
set 0x4590[1]=1b0
RX2 If 0x944[7:5]=3’b011,
0x4590[2]的設定值 set 0x4590[2]=1b0
If 0x944[7:5]!=3’b011,
set 0x4590[2]=1b0
33
RX3 If 0x944[7:5]=3’b011,
0x4590[0]的設定值 set 0x4590[3]=1b1
If 0x944[7:5]!=3’b011,
set 0x4590[3]=1b0
0x45D1[4:2] 0x45D1[2] 1b1, RX0 + HDMI link0
0x45D1[3] 1b0, RX1 + HDMI link1
HDMI RX Low Power Control
operating mode to power-saving/power down
對應的 PHY (經由 0x45FD or 0x45FE 控制)
作以下的控制
0x81D2 = 0x0F
0x8302 = 0xF0 (for power-saving) / 0x00 (for
power-down)
0x8300 = 0x06 (for power-saving “DPMS
mode”) / 0x04 (for power-down “DC off
mode” & TVCC3V3 is ON) / 0x00 (for
power-saving/power-down power-down “DC off mode” & TVCC3V3 is
(power-down means the OFF)
HDMI RX PHY is shut-down and 0x831C = 0x00
would not have response to 0x8305 = 0x00
input signal) 0x82C0 = 0x00
0x82C9 = 0x00
0x8206 = 0x10
0x820D = 0x00
0x8320 = 0x00
0x8324 = 0x00
0x82FD = 0x00
0x450E[2]=1b0 if all PHYs enter power

saving / power down
4.4.2 HDMI RX HDCP 1.4

HDCP (1.4)
0x005[7][3]
2b00 when load HDCP
0x405[7][3] HDCP RST
trim key to HDCP SRAM
0x805[7][3]
0x01E~0x01A
Store BKSV key of SINK
0x41E~0x41A BKSV[39:0]
device
0x81E~0x81A
0x03F HDCP receiver slave
0x43F HDCP slave address 0x74 address
0x83F
0x040[3] For H/W HDCP key
1b1
0x440[3] decryption use
34
0x840[3]
0x646 HDCP_CTRL3 0x60 For HDCP CTS

0x040[7:4]
0x440[7:4] 4’b0000 (reset value)
0x840[7:4]
0x043
0x443 RGB/DE Pipeline Delay 0x00 (reset value)
0x843
0x136
0x536 0x00 (reset value)
0x936
0x138
0x538 0x0C (reset value)
0x938
4.4.3 HDMI RX HDCP 2.2

HDCP (2.2)
0x031F[7]
HDCP22 DDC Channel
0x071F[7] 4’b1
Short read
0x0B1F[7]
0x4460[2] 0 : 1024 bit
RSA mode
0x4860[2] 1 : 512 bit
4.5 HDMI / TMDS Transmitter Operating Setting:

For NT68400 HDMI Tx, there are two PHYs and two LINKs. Please refer to the following figure for
simplified diagram. It supports single mode and dual mode. For single mode, each port is an independent
HDMI Tx port.
For dual mode, HDMI TX0s send out Odd/Even pixels of the field, and HDMI TX1 sends out Even/Odd
pixels of the field.
HDMI TX0 LINK registers are located at page 0x6A & 0x6B.
HDMI TX0 PHY registers are located at page 0x6C.
HDMI TX1 LINK registers are located at page 0x6D & 0x6E.
HDMI TX1 PHY registers are located at page 0x6F.
ICP Hx/Ht registers

0x209C[7] ICP_OVS_EN HDMI in recommend set
0x219C[7] 1b’1.
Analog in recommend
35
set 1b’0.
HDMI Tx – PHY registers

0x6C00 TTX_CLK_CFG 0x00  0x00 (default value)
0x6F00 ttx_itclk_vi_inv=0 (先不
反向)
Clock for Video In Path
from Link Layer to DPHY
1 : Inverse internal tclk
0 : Normal internal tclk
0x6C01[0] TTX_RST 0
0x6F01[0]
0x6C02 0x05 *1
0x6F02
0x6C05[0] PLL, P2S_DRV, BIAS_Trim 1’b=1
0x6F05[0] Power ON/OFF
1: Power On
0: Power Off
0x6C05[3:2] CLKIN/R (R=8, 4, 2, 1) PLL 2’b=01 *2(Deep color)
0x6F05[3:2] reference clock (8bit , no deep color)
00: R=8
01: R=4
10 :R=2
11: R=1
0x6C06[3:2] reg_dpcolor_ctl 2’b=00 *2(Deep color)
0x6F06[3:2] VCOCLK/R (R=4, 5, 6) PLL (8bit , no deep color)
feedback clock
00: R=4
01: R=5
10: R=6
11: R=6
0x6C09 TTX_LDO_CFG0 0xC3
0x6F09
0x6C0A TTX_LDO_CFG1 0x21
0x6F0A
0x6C0B[7:2] Reg_sw_ctl 6b’= 000111
0x6F0B[7:2] (default value)
0x6C0C TTX_RESTRIM_CFG0 0x10
0x6F0C
0x6C0E TTX_P2S_DRV_CFG0 0x5D *3 (Intra-Pair Skew)
0x6F0E
0x6C66 TTX_P2S_DRV_CFG1 *4
0x6C66
0x6C30 TTX_TG_CFG 0x00:HDMI 1.4 Scramble off *4
0x06:HDMI 2.0 Scramble ON
*5 (HDMI 串接 for Jitter
correction)
36
*6 (HDMI 串接 for PHY
to PHY)
*1:
0x02 TTX_SWAP_CFG R/W
Bits Name Description
7 ttx_chc_pn_swap P/N Swap - Channel Clock R/W

6 ttx_ch2_pn_swap P/N Swap - Channel 2 R/W
Swap the data channel
PAD{TXC,TX0,TX1,TX2}<=
4’b0000 : chC, ch2 , ch1 , ch0(default case)
4’b0001 : chC,ch1 , ch2 , ch0
4’b0010 : chC,ch2 , ch0 , ch1
4’b0011 : chC,ch0, ch2 , ch1
4’b0100 : chC,ch1 , ch0 , ch2
4’b0101 : chC,ch0 , ch1 , ch2 (no mirror case)
03:00 ttx_chd_swap_mode R/W
4’b1000 : ch2 , ch1 , ch0, chC (mirror case)
4’b1001 : ch1 , ch2 , ch0, chC
4’b1010 : ch2 , ch0 , ch1, chC
4’b1011 : ch0, ch2 , ch1, chC
4’b1100 : ch1 , ch0 , ch2, chC
4’b1101 : ch0 , ch1 , ch2, chC
3’b110 : Test Mode - 40Bit Pattern
3’b111 : Test Mode - Trigger Pattern for FT
0x02[7:0], Default: 8’h00
所以400 cut2 回來， no mirror case:fw 要將0x6C02=0x05

0x6F02=0x05
*2:
Clkmult:0x6C05[3:2]
Div:0x6C06[3:2]
pclk  5  div
tclk  div = 4(default), 5, 6
clkmult  5 clkmult = 8,4(default),2,1
pclk
tclk
PLL
pclk clkmult div tclk unit

8bit 4 594.00 MHz
10bit 5 742.50 MHz
4Kx2Kp60 594 4
12bit 6 891.00 MHz
16bit 8 1188.00 MHz
4Kx2Kp30 297 4 8bit 4 297.00 MHz
37
10bit 5 371.25 MHz
12bit 6 445.50 MHz
16bit 8 597.00 MHz
8bit 4 74.25 MHz
10bit 5 92.81 MHz
1080i 74.25 4
12bit 6 111.38 MHz
16bit 8 148.50 MHz
8bit 4 148.50 MHz
10bit 5 185.63 MHz
1080p 37.125 1
12bit 6 222.75 MHz
16bit 8 297.00 MHz
*3:
0x0E=0x1D，我們測 CTS HF1-4- Intra-Pair Skew 會 Fail
可 pass CTS 的設定值(0x5D, 0x9D, 0xDD)
*4:
480P60 – 27MHz / 720P60 – 74.25MHz
0x6C0e 0x01 REG_OE
REG_TERM_EN (Default)
REG_DE_EN (Default)
REG_CLK_DE_EN (Default)
0x6C66 0x20 REG_DYNAMIC_LEAK_EN
REG_DYNAMIC_LEAK=3’b000
0x6C30 0x00 HDMI 1.4
1080P60 – 148.5MHz
0x6C0e 0x01 REG_OE
REG_TERM_EN (Default)
REG_DE_EN (Default)
0x6C30 0x00 HDMI 1.4
4K2KP30 – 297MHz
0x6C0e 0x25 REG_OE
REG_TERM_EN (297MHz)
REG_DE_EN (297MHz)
0x6C66 0x2C REG_DYNAMIC_LEAK_EN
38
0x6C30 0x00 HDMI 1.4
4K2KP60 – 594MHz
0x6C0e 0x1d REG_OE
REG_TERM_EN (594MHz)
REG_DE_EN (594MHz)
0x6C30 0x06 HDMI 2.0
*5:
HDMI TX0
w B0 49A0 0 VPLL7 duty 50 OFF
[1]ttx_pclk_sel
w B0 6C00 2 1 : dbg_di[0]
0 : pclk
[0] REG_HDMI_TX0_TCLK_BYP
w B0 45EF 1
HDMI TX0 clkin bypass from MPLL filtered RX Tclk
[2:0]bypll_src_sel[2:0] 0x492F[2:0]=100, DP PHY0 的lsclk

0x492F[2:0]=101, DP PHY1 的lsclk
vpll7 for filtering input clock source selection 0x492F[2:0]=000, HDMI PHY0 的Pclk
[2] : 1 : dp rx bypass clock source(lsclk) 0x492F[2:0]=001, HDMI PHY1 的Pclk
w B0 492F 0
0 : hdmi rx bypass clock source (pclk) 0x492F[2:0]=010, HDMI PHY2 的Pclk
[1:0] : depends on bit2, dp/hdmi input phy source clock selection 0x492F[2:0]=011, HDMI PHY3 的lPclk
[0] clk_vbi_clr_sel
CLK_VBI_CLR manual clock path source selection (to combotx /
w B0 492B 1 hdmitx )
0 : original vbi_clr path (for post frc enable clock )
1 : hdmi fpll clock path
[7:6] clk_mode_sel_hdmitx[1:0] =10

hdmitx pll reference clock source selection (properly select
bypll_src_sel[2:0])
w B0 492C 81 0 : pclk clock bypass (properly select bypll_src_sel[2:0]) CLK mode 切換成FPLL
1 : m/n lock mode (maunal setting vpll7 mn, and
v7pll_syn_mode[0] = 1)
2 : vpll7 output on fpll mode (refer to fpll setting)
3 : hpll mode (properly config hpll)
w B0 5120 B0 reset fpll loop
w B0 5120 F0
w B0 5120 B0
HDMI TX1
w B0 49A0 0
w B0 6F00 2
w B0 45EF 2
w B0 492F 0
w B0 492B 1
w B0 492C 81
w B0 5120 B0
w B0 5120 F0
w B0 5120 B0
*6:
RX1 TXB
WRITE B0 8607 62 (RX1 8607[1]=1, 將 6502 關掉, 讀 860C 的值不變，表示有把 6502 關
掉)
WRITE B0 84D2 0E (同時將 RX1 的 ch0~2 寫入)
WRITE B0 85AF 01 (請看表 2)
WRITE B0 6F30 00
WRITE B0 45EA 2A (請看表 1 and 圖 1)
WRITE B0 6F30 03 (請看表 3)
RX1 TXA
WRITE B0 8607 62 (RX1 8607[1]=1, 將 6502 關掉, 讀 860C 的值不變，表示有把 6502 關
掉)
WRITE B0 84D2 0E (同時將 RX1 的 ch0~2 寫入)
39
WRITE B0 85AF 01 (請看表 2)
WRITE B0 6C30 00
WRITE B0 45EA 15 (請看表 1 and 圖 1)
WRITE B0 6C30 03 (請看表 3)
表1
表2
1 : 10b out from FIFO

0x84 0xAF 0 FIFO_LaneAlign_Sel 0 : 10b out from Lane Alignment
表3
0x6F 0x30 7-4 reg_dbg_sel
1 : hdmi mode for pattern gen
0x6F 0x30 3 hdmi_mode
0 : dvi mode for pattern gen
1 : Scramble On
0x6F 0x30 2 scramble_en
0 : Scramble Off
1 : HDMI 2.0 (1/40)
0x6F 0x30 1 hdmi_2p0
0 : HDMI 1.4 (1/10)
1 : bypass video data encoded function
0x6F 0x30 0 dvi_bypass_mode
0 : video data encoded
40
4.6 LVDS/DPLL Operating Setting:
DPLL Register Mapping Table
DPLL DPLL Ratio
FRC OFF GPLL0(FRC_m):
0x4A21, 0x4A22, 0x4A23
FRC ON GPLL4(DISP):
0x4A61, 0x4A62, 0x4A63
Register Function Must

0x4911[0] Frc_m enable 1’b1
0x4910[0] Disp Enable 1’b1
0x4914[0] Frc_m Rst 1’b0
0x4913[0] Disp Rst 1’b0
0x0F0[4] LVDS 1x clock duty 1’b0
0x6865 REG_VBSEL[1:0] 0x28
REG_VVX1SEL
REG_VBGRSEL
0x683D 0x8F
0x6834 0x52
0x6864 TX mode select pin, 0xFF 0:Vx1/eDP
1:LVDS
0x6849 REG_PULL_LOW_C[ 0x00
5:0]
0x684A REG_PULL_LOW_D[ 0x00
41
5:0]
0x6866 REG_VLDOSEL_TX 0x08
CD
0x3B56[6] DCLK polarity 1’b1 This bit always set to “1”
0x3B57[6:5] DCLK delay 2’b10
0x6801 REG_BUF_PDN_A 0x00 NT68400 only C D port, Power
down A port
NT68400 only C D port, Power
0x6802 REG_BUF_PDN_B 0x00
down B port
0x6803 REG_BUF_PDN_C 0x3F C port power on
0x6804 REG_BUF_PDN_D 0x3F D port power on
0x6805 REG_BUF_PDN_E 0x00
down E port
0x6806 REG_BUF_PDN_F 0x00
down F port
0x6807 REG_BUF_PDN_G 0x00
down G port
0x6808 REG_BUF_PDN_H 0x00
down H port
0x6835[7] REG_LP2S_PDN_G 1’b0
H
0x6835[6] REG_LP2S_PDN_E 1’b0
F
0x6835[5] REG_LP2S_PDN_C 1’b1 See Note1
D
0x6835[4] REG_LP2S_PDN_A 1’b0
B
REG_P2S_PDN_A[5:0 0x00
0x683E
]
REG_P2S_PDN_B[5:0 0x00
0x683F
]
REG_P2S_PDN_C[5:0 0x00
0x6840
]
REG_P2S_PDN_D[5:0 0x00
0x6841
]
REG_P2S_PDN_E[5:0 0x00
0x6842
]
0x6843 REG_P2S_PDN_F[5:0] 0x00
REG_P2S_PDN_G[5:0 0x00
0x6844
]
REG_P2S_PDN_H[5:0 0x00
0x6845
]
0x6846 PLL RSTN 0x03
PLL PDN
REG_LDO_PDN_TXG 1’b0
0x6833[7]
H
REG_LDO_PDN_TXE 1’b0
0x6833[6]
F
REG_LDO_PDN_TXC 1’b1 See Note1
0x6833[3]
D
REG_LDO_PDN_TXA 1’b0
0x6833[2]
B
42
0x6800 0x81
0x6833 REG_IREFSEL[1:0] 0x1A
REG_LDO_PDN_TX
CD
REG_LDO_PDN_PL
L
0x6824[5,4,21,0] LVDS C port data See below table of LVDS Swing
0x685B[4:0] swing control Reference Setting
0x6825[5,4,21,0] LVDS D port data
0x685C[4:0] swing control
0x6855 0x0F
0x6824[3]=1 LVDS C port CLK See below table of LVDS Swing

0x685B[4:0] swing control Reference Setting
0x6825[3]=1 LVDS D port CLK
0x685C[4:0] swing control
0x681C Pre-emphasis 0x33
0x6809 LVDS 1X CLK 0x00
inverted
0x6836 LVDS output inverted 0x00
0x6813[7:4] & LVDS C port Depend on application of Panel
0x6815[7:4] Data delay spec.
0x6817[7:4] & LVDS D port Depend on application of Panel
0x6819[7:4] Data delay spec.
0x680B[7:4] LVDS C port Depend on application of Panel
Clock delay spec.
0x680F[7:4] LVDS D port Depend on application of Panel
Clock delay spec.
0x3B50[4:3] Display color depth By

applica
tion
1’b11 4port offset mode
0x3B56[2:1] LVDS offset mode
1’b01 4port non offset mode
1’b1 4Port
0x3B56 [1] LVDS Port config
1’b0 2Port
0x3B79[7:6] LVDS 10bits Mode By
config applica
tion
1’b1 Select C/D port
0x3B79[5] LVDS 2Port select
1’b0 Select A/B port
By
0x3B79[4:2] LVDS port swap applica
tion
Note:
1. NT68400 only 2 port LVDS (C and D port)
LVDS Data Swing Reference Setting C port:T0

Table 0x6824[0]=1
43
Data Swing (mV) 0x685B[4:0]
80 00000
120 00001
160 00010
200 00011
240 00100
280 00101
320 00110
360 00111
400 01000
440 01001
480 01010
520 01011
560 01100
600 01101
640 01110
680 01111
720 10000
760 10001
800 10010
840 10011
880 10100
920 10101
960 10110
1000 10111
1040 11000
1080 11001
1120 11010
1160 11011
1200 11100
1240 11101
1280 11110
1320 11111
LVDSCLK Swing Reference Setting C port:CK

Table 0x6824[3]=1
CLK Swing (mV) 0x685B[4:0]
80 00000
120 00001
160 00010
200 00011
240 00100
280 00101
320 00110
360 00111
400 01000
440 01001
480 01010
44
520 01011
560 01100
600 01101
640 01110
680 01111
720 10000
760 10001
800 10010
840 10011
880 10100
920 10101
960 10110
1000 10111
1040 11000
1080 11001
1120 11010
1160 11011
1200 11100
1240 11101
1280 11110
1320 11111
4.7 MPLL Operating Setting:

MPLL
Power up Mau, lbm, rsa,
0x4910 0xFF
usb, dsy, edp, axi, vbi
0x4911 Power up audio, frc 0xFF
0x4912 Power video0~7 0xFF
Reset Mau, lbm, rsa, usb,
0x4913 0x00
dsy, edp, axi, vbi
0x4914 Rest audio, frc 0x00
0x4915 Reset video0~7 0x00
0x4A21~
FRC_m Div ratio FW control
0x4A23
0x4A31~
FRC_p1 Div ratio FW control
0x4A33
0x4A41~
0x4A43
0x4A51~
0x4A53
0x4A61~
DISP Div ratio FW control
0x4A63
0x4A71~
MAU Div ration FW control
0x4A73
0x4A91~
USB Div ration FW control
0x4A93
45
0x4AA1~
EDP Div ration FW control
0x4AA3
0x4AB1~
DSY Div ration FW control
0x4AB3
0x4AC1~
LBM Div ration FW control
0x4AC3
0x4AD1~
AXI Div ration FW control
0x4AD3
0x4AE1~
RSA Div ration FW control
0x4AE3
0x4934~
Video0 M/N ration FW control
0x493A
0x4944~
0x494A
0x4954~
0x495A
0x4964~
0x496A
0x4974~
0x497A
0x4984~
0x498A
0x4994~
0x499A
0x49A4~
0x49AA
0x49B4~
Audio0 DVI ration FW control
0x49B6
0x49C4~
0x49C6
0x49D4~
0x49D6
0x49E4~
0x49E6
*1 (only for DP
RXHDMI TX)
*1:
x2 clk 480MHz 以下: Duty mode off, option enable (0x512a)
VPLL setting in accordance with when DP using which PLL (VPLL0~VPLL7)
Duty mode off

0x4930[7]=0 video0 PLL
46
0x49A0[7]=0 video7 PLL
option enable (0x512a) +4930[4]

0x512a[0]=1 +4930[4]=1 video0 PLL
0x512a[1]=1+4940[4]=1 video1 PLL
0x512a[2]=1+4950[4]=1 video2 PLL
0x512a[3]=1+4960[4]=1 video3 PLL
0x512a[4]=1+4970[4]=1 video4 PLL
0x512a[5]=1+4980[4]=1 video5 PLL
0x512a[6]=1+4990[4]=1 video6 PLL
0x512a[7]=1+49A0[4]=1 video7 PLL
x2 clk 480MHz 以上: Duty mode on, option disable (0x490F[3]=0)

Duty mode on
0x49A0[7]=1 video7 PLL
Option disable (0x512a)

0x512a[7]=0
0x512a[6]=0
0x512a[5]=0
0x512a[4]=0
0x512a[3]=0
0x512a[2]=0
0x512a[1]=0
0x512a[0]=0
4.8 Other Operating Setting:

4.8.1 eFuse
Load eFuse
47
1: Before load trim key
0x4522[7] reg_efuse2sram_cpu_clk
0: After load trim key
4.8.2 MCU clock setting follow

Power Up -> Power down
[5]: MPLL_1V8N1_PD
0x31 (CPU Clk is 12M)
0x4929 [4]: MPLL_1V8N2_PD
(Step1)
[3:0]: MCU_CLK_SEL
0x10
0xF04C MCU_CLK_SEL
(Step2)
1’b0
0x490B[7] APLL_PU_SEL
(Step3)
4’b0000
0x4904[7:4] PU_LDO_D[3:0]
(Step4)
1’b0
0x4905[7] PU_RG20
(Step5)
Power Down -> Power Up

0x60
0xF04C MCU_CLK_SEL
(Step1)
[6]: EN_PLL_OVP
[5]: EN_LDO_VCO
[4]: EN_LDO_OVP
[3:0]: LDO_OVP_SEL[3:0] 0x61
0x4909
0001 :1.4v (Step2)
0010 :1.55v
0100 :1.7v
1000 :1.9v
[7]: PU_RG20
[6]: BG_OP_EN
[5:4]: BG_LEVEL[1:0]
[3:0]: PLL VCTL detect level
0xA1
0x4905 select
(Step3)
0001: 1.2v
0010: 1.3v
0100: 1.4v
1000: 1.7v
[7:4]: PU_LDO_D[3:0]
[3:2]: RG4_VADJ
[1]: PLL VCO cap Enable 0xFE
0x4904
[0]: Pre divider (Step4)
1: /8
0: /16
0x80
0x490B APLL_PU_SEL
(Step5)
0x05
0x4908 [4:0]: APLL_N16
(Step6)
0xFF
0x490A
(Step7)
48
[5]: VER_DOUB_BYPASS
0x30
0x490C [4]: Double buffer Load Data
(Step8)
at VSYNC Blanking
[5]: MPLL_1V8N1_PD
0x06 (CPU Clk is 96M)
0x4929 [4]: MPLL_1V8N2_PD
(Step9)
[3:0]: MCU_CLK_SEL
4.8.3 DDCCi
DDCCi
0xF06A[7] DP_I2C_DDC_ADY 1’b1
4.9 MAU Operating Setting:

MAU CLK Setting:
Register Function Recommend Comment
0x4AC1~0x4AC3 MAU CLK ratio AA/AA/36 depend on
application
requirement
0x4AD1~0x4AD3 AXI CLK ratio AA/AA/36 depend on
application
requirement
MAU Operating Setting:

DRAM Base address mapping
DRAM
Register Setting
Base
CH0 addr0 Main 0x4620 0
CH0 addr0 Frame1 0x4621 0
CH0 addr0 0x4622 12
CH0 addr0 0x4623 0
CH0 addr1 0x4626 24
CH0 addr1 0x4627 0
CH0 addr2 0x462A 36
CH0 addr2 0x462B 0
CH1 addr0 PIP 1 0x462C 0
CH1 addr0 Frame1 0x462D 0
CH1 addr0 0x462E 48
CH1 addr0 0x462F 0
CH1 addr1 PIP 1 0x4630 0
CH1 addr1 0x4632 51
49
CH1 addr1 0x4633 0
CH1 addr2 0x4636 5A
CH1 addr2 0x4637 0
CH2 addr0 0x463A 63
CH2 addr0 0x463B 0
CH2 addr1 0x463E 6C
CH2 addr1 0x463F 0
CH2 addr2 0x4642 75
CH2 addr2 0x4643 0
CH3 addr0 0x4646 7E
CH3 addr0 0x4647 0
CH3 addr1 0x464A 87
CH3 addr1 0x464B 0
CH3 addr2 0x464E 90
CH3 addr2 0x464F 0
CH4 addr0 Pre-FRC 0x4650 0
CH4 addr0 0x4652 99
CH4 addr0 0x4653 0
CH4 addr1 0x4656 A2
CH4 addr1 0x4657 0
50
CH4 addr2 0x465A AB
CH4 addr2 0x465B 0
CH5 addr0 OD 0x465C 0
CH5 addr0 0x465E B4
CH5 addr0 0x465F 0
CH5 addr1 0x4660 0
CH5 addr1 0x4661 0
CH5 addr1 0x4662 BD
CH5 addr1 0x4663 0
CH5 addr2 0x4664 0
CH5 addr2 0x4665 0
CH5 addr2 0x4666 BD
CH5 addr2 0x4667 0
3D NR 0x22B6 0
3D NR 0x22B7 0
3D NR 0x22B8 0
3D NR 0x22B9 0
AV Sync 0 Start 3D44 0
AV Sync 0 3D45 0
AV Sync 0 3D46 C6
AV Sync 0 3D47 0
AV Sync 0 End 3D48 0
AV Sync 0 3D49 0
AV Sync 0 3D4A C8
AV Sync 0 3D4B 0
AV Sync 1 Start 3D64 0
AV Sync 1 3D65 0
AV Sync 1 3D66 C8
AV Sync 1 3D67 0
AV Sync 1 End 3D68 FF
AV Sync 1 3D69 FF
AV Sync 1 3D6A C9
AV Sync 1 3D6B 0
3D DEI 3D DEI 0x56D0 0
3D DEI 3D DEI 0x56D1 0
3D DEI 3D DEI 0x56D2 0C
MAU Initial flow and setting :

4-byte mode
Setting
Register
51
3604 00008AAA
3608 045917A4 Note.2-a
360C 1CBC8B56
3610 4726E16C
3614 00100D78 Bottom
3618 218 Note.2-a Note1,2
361C AA4D04E9
3620 10C00000
3624 33000000
3740 9E3C78EE Note.2-a
3748 08411D0B
374C 003C01C0
3778 0x03e00042
37B8 78
37F0 00FF2400
392C 000C0000
3600 0
3640 1
37D4 1
3600 6
3600 0
3600 0000000E
3600 0
3600 0000000D
3600 0
3204 00008AAA
3208 045917A4 Note.2-a
320C 1CBC8B56
3210 4726E16C
3214 00100D78
3218 218 Note.2-a TOP
321C AA4D04E9 Note1,2
3220 10C00000
3224 33000000
3340 9E3C78EE Note.2-a
3348 08411D0B
334C 003C01C0
3378 0x03e00042
52
33B8 78
33F0 00FF2400
352C 000C0000
3200 0
3240 1
33D4 1
3200 6
3200 0
3200 0000000E
3200 0
3200 0000000D
3200 0
Note.1 MAU FIFO setting should depend on system requirement to do adjust.

Note.2 Memory mode control should depend on PCB condition to do adjust.
Note.2-a DDR3 Refresh setting mapping table :
DDR3
REFRESH PIVOT OFF PIVOT ON (pre-FRC 32bit mode) PIVOT ON (pre-FRC 64bit mode)
SETTING
Register Auto refresh Manual Refresh Auto refresh Manual Refresh Auto refresh Manual Refresh
0x3618 258 218 258 218 258 218
0x3218 258 218 258 218 258 218
0x3740 DE3C78EE 9E3C78EE DE0478EE 9E0478EE DE023CEE 9E023CEE
0x3340 DE3C78EE 9E3C78EE DE0478EE 9E0478EE DE023CEE 9E023CEE
044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G
0x3608 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G
046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G
044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G 044BF7A4 //1.3G
0x3208 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G 045917A4 //1.5G
046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G 046187A4 //1.6G
4.10 DDR3_PHY Operating Setting:

NT68400 Top phy REG
0x7220 0x09 REN D0 LB
0x7221 0x09 REN D0 HB
0x7222 0x09 REN D1 LB
0x7223 0x09 REN D1 HB
Driving/ODT control Note3
0x7238[4:0] 0x12 PLEG_CA
0x7239[4:0] 0x12 NLEG_CA
0x7240[4:0] 0x1a PLEG_MCLK
0x7241[4:0] 0x1a NLEG_ MCLK
53
0x7242[4:0] 0x16 PLEG_0_LB
0x7243[4:0] 0x16 NLEG_0_LB
0x7244[4:0] 0x16 PLEG_0_HB
0x7245[4:0] 0x16 NLEG_0_HB
0x7246[4:0] 0x1a PLEG_0_DQS
0x7247[4:0] 0x1a NLEG_0_DQS
0x7248[4:0] 0x16 PLEG_1_LB
[7]ODTEN_CA_MRST
0x7253 0xd2 [6]ODTEN_CA_MCS
[4:0]NLEG_CA_MRST
0x7254 0x12 NLEG_CA_MCS
0x7255 0x01 ODTMD_CA_MCS[4:0]
0x7256 0x01 ODTMD_CA_MRST[4:0]
0x7257[4:0] 0x12 PLEG_CA_MCS
0x7258[4:0] 0x12 PLEG_CA_MRST
0x7259[2:0] 0x01 ODT_MODE_WR_DQS0
0x7260[2:0] 0x01 ODT_MODE_WR_D0
0x7262[2:0] 0x01 ODT_MODE_WR_D1
0x7280[4:0] 0x16 NLEG_1_LB
0x7281[4:0] 0x16 PLEG_1_HB
0x7282[4:0] 0x16 NLEG_1_HB
0x7283[4:0] 0x1a PLEG_1_DQS
0x7284[4:0] 0x1a NLEG_1_DQS
[7] ODT_EN_CMD
[6:4] ODT_MODE_CMD
0x7285 0x99
[3] ODT_EN_CK
[2:0] CK ODT mode
DQ_ODT_EN_D0
DQ_ODT_MODE_D0
0x7286 0x99
DQS_ODT_EN_D0
DQS_ODT_MODE_D0
[7] DQ_ODT_EN_D1
[6:4] DQ_ODT_MODE_D1
0x7287 0x99
[3] DQS_ODT_EN_D1
[2:0] DQS_ODT_MODE_D1
[1] IEHB_Data1
IO Read enable 0x729e 0x03 Note3
[0] IEHB_Data0
0x729a 0x00 CMD_SEL[7:0]
Write CMD group selection 0x729b 0x00 CMD_SEL[15:8] Note3
0x729c 0x00 CMD_SEL[23:16]
54
0x729d 0x00 CMD_SEL[26:24]
0x7200[5:0] 0x00 CLK duty adjust
0x724a[5:0] 0x00 WDQS0 duty adjust
0x7207[5:0] 0x00 WDQS1 duty adjust
0x724b[5:0] 0x00 WDQS2 duty adjust
Signal duty adjustment 0x7207[5:0] 0x00 WDQS3 duty adjust Note3
0x724d 0x48 CMD/ADDRESS Int. VREF level setting
0x724e 0x48 Data0 Int. VREF level setting

0x724f 0x48 Data1 Int. VREF level setting
[5:4] LDO_VCCA_CLK level
0x7294 0xb9
[3:2] LDO_PLL_V10N level
[7:4] LDO_DD_0 level
0x721b 0x44
[3:0] LDO_AD_0 level
LDO level selection Note3
0x721c 0x44
0x72f1[3:0] 0x11 LDO_PAD_0 level
0x72b0[4:0] CMD phase
0x72b1[4:0] CLK phase
0x72b2[4:0] WDQ0 phase
0x72b3[4:0] WDQS0 phase
ADDRES phase if REG_0x9a~0x9d is
Phase selection 0x72b7[4:0] Note3
set to 1
0x72b8[7:0] RDQS0/RDQS1 phase
0x72ba[4:0] WDQ2 phase
0x72bb[4:0] WDQS2 phase
0x72bd[4:0] WDQ3 phase
0x72be[4:0] WDQS3 phase
0x7220 Data0 LB
0x7221 Data0 HB
Read enable delay selection Note3
0x7222 Data1 LB
0x7223 Data1 HB
NT68400 Bottom phy REG

0x7320 0x09 REN D0 LB
Driving/ODT control Note3
0x7321 0x09 REN D0 HB
55
0x7322 0x09 REN D1 LB
0x7323 0x09 REN D1 HB
0x7338[4:0] 0x12 PLEG_CA
0x7339[4:0] 0x12 NLEG_CA
0x7340[4:0] 0x1a PLEG_MCLK
0x7341[4:0] 0x1a NLEG_ MCLK
0x7342[4:0] 0x16 PLEG_0_LB
0x7343[4:0] 0x16 NLEG_0_LB
0x7344[4:0] 0x16 PLEG_0_HB
0x7345[4:0] 0x16 NLEG_0_HB
0x7346[4:0] 0x1a PLEG_0_DQS
0x7347[4:0] 0x1a NLEG_0_DQS
0x7348[4:0] 0x16 PLEG_1_LB
[7]ODTEN_CA_MRST
0x7353 0xd2 [6]ODTEN_CA_MCS
[4:0]NLEG_CA_MRST
0x7354 0x12 NLEG_CA_MCS
0x7355 0x01 ODTMD_CA_MCS[4:0]
0x7356 0x01 ODTMD_CA_MRST[4:0]
0x7357[4:0] 0x12 PLEG_CA_MCS
0x7358[4:0] 0x12 PLEG_CA_MRST
0x7360[2:0] 0x01 ODT_MODE_WR_D0
0x7362[2:0] 0x01 ODT_MODE_WR_D1
0x7380[4:0] 0x16 NLEG_1_LB
0x7381[4:0] 0x16 PLEG_1_HB
0x7382[4:0] 0x16 NLEG_1_HB
0x7383[4:0] 0x1a PLEG_1_DQS
0x7384[4:0] 0x1a NLEG_1_DQS
[7] ODT_EN_CMD
[6:4] ODT_MODE_CMD
0x7385 0x99
[3] ODT_EN_CK
[2:0] CK ODT mode
DQ_ODT_EN_D0
DQ_ODT_MODE_D0
0x7386 0x99
DQS_ODT_EN_D0
DQS_ODT_MODE_D0
56
[7] DQ_ODT_EN_D1
[6:4] DQ_ODT_MODE_D1
0x7387 0x99
[3] DQS_ODT_EN_D1
[2:0] DQS_ODT_MODE_D1
[1] IEHB_Data1
IO Read enable 0x739e 0x03 Note3
[0] IEHB_Data0
0x739a 0x00 CMD_SEL[7:0]
0x739b 0x00 CMD_SEL[15:8]
Write CMD group selection Note3
0x739c 0x00 CMD_SEL[23:16]
0x739d 0x00 CMD_SEL[26:24]
0x7300[5:0] 0x00 CLK duty adjust
0x734a[5:0] 0x00 WDQS0 duty adjust
0x7307[5:0] 0x00 WDQS1 duty adjust
0x734b[5:0] 0x00 WDQS2 duty adjust
Signal duty adjustment 0x7307[5:0] 0x00 WDQS3 duty adjust Note3
0x734d 0x48 CMD/ADDRESS Int. VREF level setting
0x734e 0x48 Data0 Int. VREF level setting

0x734f 0x48 Data1 Int. VREF level setting
[5:4] LDO_VCCA_CLK level
0x7394 0xb9
[3:2] LDO_PLL_V10N level
0x731b 0x44
LDO level selection Note3
0x731c 0x44
0x73b0[4:0] CMD phase
0x73b1[4:0] CLK phase
ADDRES phase if REG_0x9a~0x9d is
Phase selection 0x73b7[4:0] Note3
set to 1
0x73ba[4:0] WDQ2 phase
0x73bb[4:0] WDQS2 phase
0x73bd[4:0] WDQ3 phase
0x73be[4:0] WDQS3 phase
57
0x7320 Data0 LB
0x7321 Data0 HB
Read enable delay selection Note3
0x7322 Data1 LB
0x7323 Data1 HB
Note.3 DDR_PHY setting should depend on PCB condition to do adjust.
4.11 OD Operating Setting:

Register Function Recommend
0x4B80 OD Configuration 0x01
0x4B81~0x4B8 OD Window Horizontal Start Position 0x000
2
0x4B83~0x4B8 OD Window Horizontal Width 0x7FF
4
0x4B85~0x4B8 OD Window Vertical Start Position 0x000
6
0x4B87~0x4B8 OD Window Vertical Length 0x7FF
8
0x4B90 OD Compress Mode Configuration 0x71
0x4B98 OD Still Check Configuration 0x03
0x4B99 OD Still Check Threshold 0x0B
0x4B9B OD motion check enable 0x12(one chip)
0x16(two chip)
0x4BA0 OD DCC Configuration 0x01
0x4BC0 Motion detect Lo threshold0 0x40
0x4BC3 Motion detect Hi threshold0 0xff
0x4BC4 Motion detect Hi threshold1 0xff
0x4BC5 Motion detect Hi threshold2 0x1f
0x4BC6 Motion de-bounce frame count 0x0E
0x4BC7 Motion de-bounce threshold 0x01
0x4BC8 Motion de-bounce enable 0x01
NT68400 OD Recommend Setting

1. 0x4B80 = 01h
2. 0x4B81~0x4B82 = 000h (default)
3. 0x4B83~0x4B84 = 7FFh (default)
4. 0x4B85~0x4B86 = 000h (default)
5. 0x4B87~0x4B88 = 7FFh (default)
6. 0x4B90 = 71h
7. 0x4B98 = 03h
8. 0x4B99 = 0Bh
9. 0x4B9B = 12h 0x12(one chip) 0x16(two chip)
10. 0x4BA0 = 01h
11. 0x4BC2 / 0x4BC1 / 0x4BC0 = 00 / 00 / 40h
12. 0x4BC5 / 0x4BC4 / 0x4BC3 = 1F / FF / FFh
13. 0x4BC6 = 0Eh
14. 0x4BC7 = 01h
15 0x4BC8 = 01h
4.12 USB Type C BMC IO Operating Setting:

58
0x2260[7] reg_pd_data_role 1b' 0
0x2260[6:5] reg_pd_spec_ver 2b'01
0x2260[0] reg_usbc_cc_enable 1b' 1
SC_USBC_CC_RESET_CTR
0x2261 L
0x40
SC_USBC_CC_REF_CLK_S
0x2262[5:0] ET
0x0C@ 12M OSC
0x2262[7] reg_usbc_cc_filter_option 1b' 1
0x2263[6:4] CTS_FIX_ERROR 3b'011
0x2270 reg_cc_tx_bit_time[7:0] 0x28 @ 12M OSC
reg_cc_tx_preamble_nu
0x2271 0x40
m[7:0]
0x2273 reg_cc_tx_hold_time[7:0] 0x03
0x2276[7:4] reg_cc_tx_conflict_ofst 4b’0001
reg_rx_auto_bit_time_ma
0x2279[7:4] 4b’0111
rgin[3:0]
reg_cc_rx_bit_time_l_th[
0x227A 0x22
7:0]
reg_cc_rx_bit_time_h_th[
0x227B 0x40
7:0]
0x227E[6:4] CTS_FIX_ERROR 3b'111
0x227E[3:0] CC_RX Check 4b’1011
USB Type C CC BMC IO PHY control

0x2250 Power LDO setting 0x83
0x2251 CC IO Control 0x7D
0x2252 BIAS current 0x0F
0x2253 CC1 IO Pad control 0xFD
0x2254 CC2 IO Pad control 0xFD
0x2255 CC1&2 IO Pad control 0x00
0x2256 reg_cc_phy_reg_rsvd 0xC0
59
4.13 HDR Application Setting:
EOTF
General Setting
Register Function Must Recommand
E00E3F00[0] hdr double buffer 1
E00E3F00[1] bypass hdr control 1
EOTF
follow ST2084 curve

table format input- 2048 entry
output- maximum :2^18 (18 bits depth)
(1)enable RGB access:E00E3FD0[2:0]

recursive follow the sequence:
(2)write index in E00F3FD0[19:8]
write flow
(3)write LUT in E00E3FD8[17:0]
Finally,
(4)write Maximum index 2048 to E00E3FDC[17:0]
3x3
purpose Gamut Mapping
60
– Function:
Preout_0 = input_0 + PreOffset_0;
formula
TMO
purpose tmo mapping by different panel maximum luminance
input- 256 entry

table format output- maximum :2^12 (12 bits depth)
unity gain : 1024
if TMO update every V sync

• 1. write TMO LUT to buffer
write flow
• 2.toggle update bit E00E3F60[28],ready for update table from LUT to sram
• 3.After Vsync falling N lines (E00E3F60[7:1]), table from LUT to sram.
RGB out (Gain is after tone mapping)

R = R*gain;
TMO output
G = G*gain;
B = B*gain;
OETF
reverse of Panel Gamma
table format input- 256 entry
output- maximum :2^12(12 bits depth)
(1)enable RGB access:E00E3FE0[2:0]

recursive follow the sequence:
(2)write index in E00F3FE0[18:8]
write flow
(3)write LUT in E00E3FE8[11:0]
Finally,
(4)write Maximum index 2048 to E00E3FEC[11:0]
61
4.14 LDC (Local dimming control) Application Setting:
Local Dimming system blocks
Register Function Must Recommand

E0080000[15:8] segment row by Panel
E0080000[7:0] segment col by Panel
6,Num of block per row(2^
E0080000[23:16] block_X
BLOCK_NUM_X)
5,Num of block per col(2^
E0080000[31:24] block_Y
BLOCK_NUM_Y)
E0080004[31:16] Panel Height by Panel
E0080004[15:0] Panel Width by Panel
E0080134[31:16] MUTILFACTOR_FOR_DIV_00 0x0808
E0080134[15:0] MUTILFACTOR_FOR_DIV_01 0x0808
62
E0080138[20:16] BITS_FOR_DIV_00 0x17
E0080138[4:0] BITS_FOR_DIV_01 0x17
E008013C[31:16] MUTILFACTOR_FOR_DIV_10 0x0826
E008013C[15:0] MUTILFACTOR_FOR_DIV_11 0x0826
E0080140[20:16] BITS_FOR_DIV_10 0x17
E0080140[4:0] BITS_FOR_DIV_11 0x17
E00802C4[27:16] CHANGE_VALUE_DOWN_LIMINT 0xFFF
E00802C4[11:0] CHANGE_VALUE_UP_LIMINT 0xFFF
E00802C8[27:16] DIRECT_CHANGE_VALUE_THR 0x180
E00802C8[15:8] ALPHA_DOWN 0x40
E00802C8[7:0] ALPHA_UP 0x40
E0080370 SAMPLE_PIXEL_X 0x10
E0080900~
segment X boundary by Panel X Segment
E008093C
E0080940~
segment Y boundary by Panel Y Segment
E008097C
interrupt
0xE0080400[4] Gamma duty enable 1
Histogram
1: Ave, 2: MAX95, 3 :MAX,4 : blend
0xE008028C[6:4] histogram Mode
depends on application
0xE0080010[9:0] INITIAL_DUTY_TH0 0x0100
0xE0080018[9:0] INITIAL_DUTY_SLOPE_0 0x40
63
0xE0080018[25:16] INITIAL_DUTY_SLOPE_1 0x40
0xE008001C[9:0] INITIAL_DUTY_SLOPE_2 0x40
0xE008001C[25:16] INITIAL_DUTY_SLOPE_3 0x40
0xE0080020[9:0] INITIAL_DUTY_OFFSET_0 0
Panel_width / Sample_X
0xE0080040[15:8] LB_LEN
(0xE0080370)
0xE0080040[7:0] R_LB_STR_ADDR (LB_LEN/2)
Profile Setting
COMPENSATION_MASK_
0xE0080280[15:8] 3
X
COMPENSATION_MASK_
0xE0080280[7:0] 3
Y
mask per block
0xE0080164[31:16] profile size
= ((block_X) * (block_Y)+4)/5
Address Setting
MAU address: 0x7A000
0xE0080160[31:0] Profile Address
Profile address:0xF40000
MAU address: 0xF20000
0xE00802A4[31:0] Intensity Address
LDC reg address(0x2A4):0x79000
Gain Setting
0xE0080B40~0xE008
RGB Gain LUT gain range: 0~0xFF
0B7C
table format:
0xE0080C00~ Gain1(2byte),Gain1-Gain2(2byte),Gain
pixel intensity Gain LUT
0xE0080FFF 2(2byte),Gain2-Gain3(2byte),Gain3(2b
yte)
64
4.15 LDC GPIO Pins control Setting:
LDC pins PI7-0 and PJ7-0, port I/J setting tables as show below:
65
5 OD Application Guide
5.1 OD engine block diagram
Current frame
Video input
Compress Motion
DCC
codec Check
Previous frame
SRAM
MMU
5.2 OD control register mapping

0x4B80~0x4B88 : OD window control
0x4B90~0x4B9D : OD compress mode & threshold control
0x4BA0~0x4BAE : OD DCC type control & look up table for debugging
0x4BB0~0x4BBB : OD post-pattern for testing
0x4BC0~0x4BC8 : OD align NT68670 BTC frame motion check
5.3 OD frame definition

1. F1 : previous frame uncompressed video data
2. F2 : current frame uncompressed video data
3. F1_DC: previous frame decompressed video data
4. F2_DC: current frame decompressed video data
5. F2_OD: Over-drived current frame video data
OD
BTC DCC
F2
Pixel_in F2_DC
compress decompress Pixel_out
F1_DC
F1
MMUIF
MMU
DRAM
Figure.1
66
5.4 OD Window Control (Reg. 0x4B80~0x4B88)
OD window begin position
(OD_WIN_H_BEG,OD_WIN_V_BEG)
OD_WND_V_LEN OD_WND_H_WID
IWND
(support : F1/ F2/ F1_DC/ F2_OD) OWND
(support : F2/ F2_DC)
Figure.2
H begin position: 0x4B81, 0x4B82

Actually H width =(0x4B83,0x4B84) ，the setting value multiply by 4 window width.
V begin position: 0x4B85, 0x4B86

Actually V length =(0x4B87,0x4B87) ，the setting value multiply by 2 window length.
Example:
Output resolution is 1280x1024，assume full screen use OD function，how should I set the OD window
Solution 1:
Use default setting for all resolution OD
Solution 2:
0x4B81 = 0h , 0x4B82 = 0h ;
H active = 1280 / 4 = 320d = 140h
0x4B83 = 40h , 0x4B84 = 1h
0x4B85 = 0h , 0x4B86 = 0h ;
V active = 1024 / 2 = 512d = 100h
0x4B87 = 0h, 0x4B88 = 1h
5.5 OD compression mode

1. 0x4B90 = 71h
5.6 OD S/W setting sequence

1. Load OD table
2. Enable OD
3. Set OD window position and size
4. Set OD compress mode
5. Set still check threshold and enable
6. Set motion check threshold and enable
7. Enable DCC
5.7 OD Threshold Setting

Table 1.
67
OD_MC OD_SC OD_EN_ENB
(0x4B9B[4]) (0x4B98[0]) (0x4B98[4])
Reg. MC_FRM_LO MC_FRM_HI SC_THRLD OD_EN_THRLD
(0x4BC0~2) (0x4BC3~5) (0x4B99) (0x4B9A)
Mode
(0x4B90)
0x4B90 = Ex : 1920x1080 Ex : 1920x1080 Bh 0h
71h 0x4BC0 = 00h 0x4BC3 = FFh
0x4BC1 = 00h 0x4BC4 = FFh
0x4BC2 = 40h 0x4BC5 = 1Fh
5.8 OD Response Time Measurement Setting

1) During Normal display : 0x4B9B = 12h , 0x4BC8 = 01
2) Measure response time : 0x4B9B = 00h , 0x4BC8 = 00
68
6 Audio Application Guide
6.1 Audio Setup Block
Audio setup up Block:
Follow set-up flow to set audio.
6.2 Audio PLL Function
There are four set audio-PLL on 390 series.

PLL0 (49B0~49BF)
PLL1 (49C0~49CF)
PLL2 (49D0~49DF)
PLL3 (49E0~49EF)
There are four operation mode , example for DP /HDMI/I2SIN/free-run.
Example PLL0 (49B0~49BF)
DP mode:
49B2[2]=1 DP mode EN
49B2[1:0]=01 256FS
49B0[0]=1 FIFO lock
HDMI mode:
69
49B7[4]=1
49B2[1:0]=01 256FS
49B0[0]=0 FIFO lock
400&390 I2SIN mode:
49B2[1:0]=01 256FS
49B7[7]=1(I2S_En)
49B2[2]=1(DP_acr_sel)
49B8=0x00
49B9=0x04
49BA=0x00 4X
49BC=0x00
49BD=0x01
49BE=0x00
49B3[3]=1(mn_sel_aud)
49B2[5]=1(ld_man_sel_aud)
Toggle 49B2[6]=0 -1 -0 (ld_aud_man)
Freerun mode:
49B7[4]=0
49B2[2]=0
Toggle 4911[4]=1->0->1
49B4=E4(Ratio LSB)
49B5=17
49B6=04(Ratio MSB)
=>Mclk=12.28MHz
Manual load M N to AudioPLL flow:

Ref HDMI/DP source to program MPLL
(1)Read DP /HDMI M N or N CTS
(2)set 49B8~49BA (M) ;49BC~49BE (N)
(3)49B3[3]=1
(4)49B2[5]=1
(5)Toggle49B2[6]=0->1->0
(6)Toggle4914[4]=0->1->0
6.3 Setup Audio General Control

6.3.1 Audio Setup Examples:
HDMI RX link0/1/2 LPCM in, DAC Out + S/PDIF + I2S Out
(1)0x013E[6]/0x053E[6]/0x093E[6]=1(MCLK clk tree)
(2)0x4473/4474(set clock root path)
(3)0x4490/4491(only HDMI PLL src SEL)
(4) 0x0127/0x0128/0x0129=0x19/0xE4/0x64(HDMI link0 I2S)
0x0527/0x0528/0x0529=0x19/0xE4/0x64(HDMI link1 I2S)
0x0927/0x0928/0x0929=0x19/0xE4/0x64(HDMI link2 I2S)
(5)4470~4474[7:6][3:2] set PLL root location
(6)4470[1][0]=11(I2S0 /I2S1 mclk EN)
(7)4480/4483/4486[3:0] (DAC out src seL /I2S out SRC seL)
(8)4409=40(I/O I2Sout)
(9)0929[0]/0529[0]/0129[0]=1(SPDIF EN)
(10)45AC[3:2][1:0]=10(SPDIF1)/10(SPDIF0)
(11)0xF135=C0(PM6,7 push-pull)
400: (12)4483[7]=I2S0 data mute ;4486[7]=I2S1 data mute
70
390 HDMI TX
(1)6B14=F1(stream EN)
(2)6B2F=41(HDMI mode)
(3)6B1D=00(I2S format)
(4)6B24[3:0]=1011(24bit)
(5)6B02[2:0]=001(256FS) ,if DP in 1057=0x03
400 HDMI TX
(1)6B14=09(PCM stream EN)
(2)6B2F=A1(HDMI 2.0 mode)
(3)6B1D=40(I2S format)
(4)6B24[3:0]=1011(24bit)
(5)6B02[2:0]=001(256FS) ,if DP in 1057=0x03
(6)6B01=02(HW auto CTS)
(7)6B03~6B05(ref Rx N) HW auto 6B09~6B0B (CTS)
Only DP fix PLL location:

DP PLL fix 4480~4486 Domain Link Sample mode
[3:0]
Fix PLL0 0100 DP0 Link0 S0(R,L) SST/MST
Fix PLL1 0101 DP1 Link0 S1(R,L) SST/MST
Fix PLL2 0110 DP2 Link1 S0(R,L) SST
6.3.2 DP audio setup example

DPRX link0 I2Sout+S/PDIF:
0x1056=0x00//32bit word size
0x1057=0x03//256fs
0x1055/1058/1059/105A=0x00//Disable all FIFO sel
0x1055=0x80//I2S FIFO sel
0x1050=80//FIFO EN
>>4470~4474[7:6][3:2] set PLL root location
0x4470[1][0]=11(I2S0 /I2S1 mclk EN)
0x4480/4483/4486[3:0] (DAC out src seL /I2S out SRC seL)
0x4409=40(I/O I2Sout)
0x0929[0]/0529[0]/0129[0]=1(SPDIF EN)
0x45AC[3:2][1:0]=10(SPDIF1)/10(SPDIF0)
0xF135=C0(PM6,7 push-pull)
PS:SST mode=10C0=80; MST mode 10C0=81
MST FIFO:
1050[4]=1(MST FIFO EN)
1070&1071=0x1FF
Delaytime=(0x1FF)511*2(sample)/48K=21.29ms(EX:2ch;Fs=48K)
DPRX link0 DAC out
0x1057=0x03//256fs
0x1055/1058/1059/105A=0x00
0x105A=0x80//DAC FIFO sel
71
If MST mode:0x105A[4]=1 +[ 0x1070=0x01+0x1071=0xFF(Delay time=0x1FF*2/48K
=21.29ms]
0x1050=80//FIFO EN
4470~4474[7:6][3:2] set PLL root location
0x4480(DAC out src seL)
PS:SST mode=10C0=80; MST mode 10C0=81
DPTX
63A0=10 (DPTX EN)
4481=0x04 (source DP link0)(audioPLL0)
63AD~63AF (CTS pattern set)
63B0~63B2 (Channel status & audio Infoframe)
6.3.3 AV sync function

PS:DP MST not support Avsync
(1)Avsync0+HDMI link0:
4D05=FF (bottom MAU ch EN)
02A7=00 (HDMI Avsync EN)
4495=80 (DRAM_SCL_sel)
449A=88(Avsync DRAM path)
3D40=40
3D40=80
3D41=20
3D42=20
3D43=20
3D4C=80
3D4D=03
3D4E=00
3D4F=00
3D40=80
02A7=C0 (HDMI Avsync EN) ([6]=1;HDMI Avsync EN)
(2)Avsync0+DP link0:
105A=00
1050=00
4D05=FF (bottom MAU ch EN)
02A7=00 (HDMI Avsync EN)
4495=40(DRAM_SRC_SEL)
449A=88
3D40=40
3D40=80
3D41=20
3D42=20
3D43=20
3D4C=80
3D4D=03
3D4E=00
3D4F=00
3D40=80
105A=80
1050=88([3]=1,DP Avsync EN)
400:
add DP avsync passthr MPLL
1051[0]=0 bypass =1passthr MPLL
72
1054[6]:FIFO-over
1054[1];FIFO under
105C[0]=0 Avsync FIFO mode mask
105C[7]=1 Avsync FIFO mode main mask
6.3.4 DAC Power Up

390
(1)4404=FC (power)
(2)4402=20 (PCM path)
(3)4402=21 (PCM path+power EN)
(4)4403=00 (No mute)
(5)4401=CC(Driving current)
400
(1)delay 1ms
(2)4403=1E
(3)4400=A0
(4)4401=44
(5)452C[2]=1
(6)4400=A7
(7)4402=01
(8)4403=02
(9)452C[2]=0
(10)4400=A0
(11)4403=00
(12)4404=FC
6.3.5 Audio ADC Power Up

4430=E5
4435=30(128FS)
4436=18
4437=50
4438=FE
4439=18
4432=00
+ set AudioADC CLK(PLL free run mode)
49B6=04 49B5=17 49B4=E4
ADC->SPDIF
4437[0]=1
4440[7][6][5]=111(PUV)
443A~443F (C bit)
45AC[3:2]=10 SPDIF1
45AC[1:0]=10 SPDIF0
0xF135=C0 push-pull PM6,7
400:
ADC APHY power up
4430=F7
4431=04
4432=15
452D[7]=0 iso off
73
6.3.6 I2C IN
Ref Mclk:
F0D0[2]=1
453A=0x55 (I2S in GPIO )
4452=0x87(I2S in EN)
4470=0x10(root)
4450=0x03(clk cyc)
4451=0x08
4456=0x
Ref sck+PLL0
49B7[7]=1
49B2[2]=1
49B8=0x00
49B9=0x08
49BA=0x00
49BC=0x00
49BD=0x01
49BE=0x00
49B3[3]=1
49B2[5]=1
Toggle 49B2[6]=0 -1 -0
400:
Ref Mclk:
445D[7]=1(Mclk in from GPIO)
445D[3:0]=(I2S in internal path)
453A=0x55 (I2S in GPIO )
4452=0x87(I2S in EN)
4470=0x10(root)
4450=0x03(clk cyc)
4451=0x08
4456=0xFF
Ref sck+PLL0
49B7[7]=1
49B2[2]=1
49B8=0x00
49B9=0x04
49BA=0x00
49BC=0x00
49BD=0x01
49BE=0x00
49B3[3]=1
74
49B2[5]=1
Toggle 49B2[6]=0 -1 -0
75
6.3.7 Audio Control Flow chart
Initial HDMI Audio
Program Start
Check audio status
Setup Audio ACR,AAC..
Select Input Source

Check FIFO error? Reset FIFO
Select Output Type & Clear AAC done & AEC

Check AAC done?
format flags
Clear all mute & interrupt

& AEC flasg
76
6.3.8 Hardware reference application circuit
I2S output
Line Out and S/PDIF Out
10 ohm 100 uF
Line-out min. min. Line-out
NT68400 Earphone NT68400 Closely to AMP
m K
100ohm ho 1 AMP
cte K 1 uF
otr 01
p K
D F 7
S p
0 .4
2.2n . E
~ 12mW for 16~32 0
0
~
0
1 7
4
ohm earphone
Direct drive earphone Drive Audio -AMP
R601 C619 CN601

430 1uF 16V S/PDIF
1
5 SPDIF
R602
2
82
6.3.9 Audio Offset Compensation

Digital Audio Offset Control is use to canceling HDMI/Line In source switch
POP noise
0x02A5 Digital Audio Offset Control Right Channel R/W

7-0 D_R_OFFSET Digital Audio Offset Control Right Channel, 2’s complement
Min = 80h , B[7:0]
Zero Offset = 00h
Max = 7Fh
Default: 0000 0000B
0x02A6 Audio Auto Offset compensation control R/W
7 AUDIO_COMP_EN Digital audio auto offset comparator Enable.
6-2 Reserved
1 L_COMP_RESULT Digital audio auto offset comparator result for Left channel.
0 R_COMP_RESULT Digital audio auto offset comparator result for Right channel.
Default: 0xxx xx00
6.3.10 Mute Function
Audio auto mute
441C[1:0]=11 En
441D=0x80 (threshold Ex:Dacout=16mv)
441E=0x50 (detect period Ex:1ms)
441F=0xC6(target level)
77
Zero cross: Digital to DAC
Zero cross En(PGA gain)
4412[6:5]=11+4413=0xFF+4414=0x0F
Zero cross En( Dgain)
4420[5:4]=11+4421=0xFF+4422=0x0F
Analog gain smooth:

4405
One step = 1/osc*2048*audio_smooth_cnt*200
Digital gain smooth
4423
One step = 1/osc*audio_smooth_cnt
Mute:
DAC mute: 4403[1]=1 (A-mute)
Zero cross mute:
4406[3][2]=11+4420[5:4]=11(D-zero cross)+4421=0xFF+4422=0x0F
Fast mute:
4489=0xFF (fast mute en)
When source change ,
Fast mute tigger ,then clear 4487 / 4488 flag to remove mute status.
78
7 Vx1 TX Control
7.1 Control Registers
Vx1 control registers:
Page: 0x3A Comb TX Vx1/eDP/LVDS control
Page: 0x67 Vx1 TX phy control
Page: 0x68 Vx1 TX link control
Page: 0x3B56 offset mode control
7.2 Vx1 TX pin assignment

Vx1 TX pins are show as below.
7.3 Vx1 TX Data mapping and lane control

Vx1 TX is support P/N swap but no port and lane swap.
Support byte mode, data mapping and resolution are show as below.
RGB 18 bit 24 bit 30 bit 36 bit
5 byte mode X X X X
4 byte mode X Y Y X
3 byte mode X Y Y X
1 Section
Hactive= 3840
port 0 port 1 port 2 port 3
Lane
Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 7
FSBS FSBS FSBS FSBS FSBS FSBS FSBS FSBS
FSBP FSBP FSBP FSBP FSBP FSBP FSBP FSBP
V Blanking
… … … … … … … …
FSBE_
FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR SR
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8
Pixel
Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 16
Line 1
… … … … … … … …
… … … … … … … …
Pixel Pixel
3833 Pixel 3834 Pixel 3835 Pixel 3836 Pixel 3837 Pixel 3838 Pixel 3839 3840
Bla
nki
ng

H
79
… … … … … … … …
FSBE FSBE FSBE FSBE FSBE FSBE FSBE FSBE
Pixel
Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 16
Line 2
… … … … … … … …
… … … … … … … …
Pixel Pixel
3833 Pixel 3834 Pixel 3835 Pixel 3836 Pixel 3837 Pixel 3838 Pixel 3839 3840
2 Section
Hactive= 3840
Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7
V Blanking
… … … … … … … …
FSBE_S
FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR R FSBE_SR
Pixel
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 1921 Pixel 1922 1923 Pixel 1924
Pixel
Line 1
… … … … … … … …
… … … … … … … …
Pixel Pixel
1917 Pixel 1918 Pixel 1919 Pixel 1920 Pixel 3837 Pixel 3838 3839 Pixel 3840
H Blanking

… … … … … … … …
Pixel
Pixel
Line 2
… … … … … … … …
… … … … … … … …
Pixel Pixel
1917 Pixel 1918 Pixel 1919 Pixel 1920 Pixel 3837 Pixel 3838 3839 Pixel 3840
80
Lane count
4K2K/60 (3840x2160) 8
1920x1080/60 4 or 2
7.4 S/W control flow.

Please reference to Novatek S/W code.
81
8 Vx1 RX Control
8.1 Control Registers
Vx1 control registers:
Page: 0x74 RX link control
Page: 0x75 Vx1 global control
Page: 0x76/77 phy A/B control
8.2 Vx1 RX Data mapping and lane control
Vx1 RX is support P/N, lane and port swap.
Support byte mode and resolution are show as below.
RGB 18 bit 24 bit 30 bit 36 bit
5 byte mode X X X X
4 byte mode X Y Y X
3 byte mode X Y Y X
1 Section
Hactive= 3840
Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7
V Blanking

… … … … … … … …
FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR
Line 1
… … … … … … … …
… … … … … … … …
H Blanking

… … … … … … … …
Line 2
… … … … … … … …
… … … … … … … …
82
Lane count
4K2K/60 (3840x2160) 8
1920x1080/60 4 or 2
Lane control
No. Description Registers
1 VX1 RX total lane count (set 8/4/2) 0x7410[3:0]
2 A/B phy lane count 0x7503
3 p/n pair swap 0x7607[6] / 0x7707[6]
lane_swap_4 (For 4 lane)
4
L0~L3-->L3~L0 0x7607[7] / 0x7707[7]
lane_swap_2 (For 2 lane)
5
L0,L1-->L1,L0 L2 L3-> L3,L2 0x7608[6] / 0x7708[6]
6 port swap A~B -> B~A 7403[2]
VX1 RX input port mode (Valid for 2/4 lane)
7 1: Use Two port (1+1 or 2+2)
0: Use Single port (2+0 or 4+0) 0x7403[4]
8 Clock source select See *1
9 display timing 0x7440~744F
Lane 8 lane 4 lane 2 lane 1 lane

Lane 0 ● ● / ● ● /x x
Lane 1 ● ● / ● ● /x
Lane 2 ● ● /x
Vx1 Lane 3 ● ● /x
RX
Lane 4 ● x/ ● x/ ●
Lane 5 ● x/ ● x/ ●
Lane 6 ●
Lane7 ●
PS: ●: recommend ●: support but deference setting x: not support
8.3 Vx1 RX default setting

unsigned char vx1_rx_phy_Def[255]= { // VX1 phy page: 0x76~77
0x0A,0x00,0xF8,0x23,0x2C,0x23,0x09,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0xF1,0x02,0xFF,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x90,0x04,0x1E,0x5A,0x4A,0xF7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x14,0x00,
0x01,0x0F,0x01,0x0F,0x3F,0x00,0x4F,0x1F,0x2F,0x14,0x14,0x14,0x14,0x3F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0xC8,0x00,
0x87,0xA0,0x00,0xB4,0xE3,0x00,0x0E,0x01,0xFF,0xFF,0x00,0xF0,0xFF,0x17,0xFF,0x17,
0x3E,0x14,0x23,0x2F,0x00,0x00,0x00,0x0F,0x3E,0x14,0x23,0x2F,0x00,0x00,0x00,0x0F,
0x3E,0x14,0x23,0x2F,0x00,0x00,0x00,0x0F,0x3E,0x14,0x23,0x2F,0x00,0x00,0x00,0x0F,
83
0x73,0x37,0x30,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,
0x33,0x33,0x11,0x0F,0xFF,0x00,0x00,0x9F,0x00,0x1F,0x1F,0x00,0x20,0x00,0x00,0x01,
0x00,0x00,0xC0,0x00,0x08,0xFF,0xFF,0xFF,0x03,0x03,0x00,0xFF,0x01,0xFF,0x01,0x00,
0x00,0x04,0x08,0x80,0xF5,0x03,0xA0,0x05,0xA0,0x05,0xA0,0x05,0xEA,0x07,0xCC,0x0A,
0xFF,0xFD,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC6,0xC6,0xC6,0x04,
0x80,0xE0,0x80,0xE0,0x4E,0x1F,0xE6,0x5A,0xF3,0x05,0x73,0x10,0x01,0x73,0x05,
}
8.4 S/W control flow.

Please reference to Novatek S/W code.
Start
Set i/o for Htpdn and Lockn

0x45AD=0x50
I n i t i 1a Rl XV xp/l hi ny k
S/W R e s e t
0x7504= 0x0->0x1-> delay 10mS-
>0x0
END
Vx1 RX auto mode for

TX sync = Separate
0x7433[2:0]=000
0x7419[0]=0
0x7460[3:0]=0000
0x7464[0]=0
0x7460[3:2]=01
0x7430[2]=0 //auto
84
9 USB Reference circuit
NT68400 USB BLOCK
NT68402 USB BLOCK
85

Novatek MCU

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Novatek MCU

Hochgeladen von

Copyright:

Verfügbare Formate

NT68400 Series

NT68400 System Design Guidelines

Version Content Data

2.3 ADC Signal Guidelines

GREEN+ FB407 30 OHM R455 75R 1/16W 5% C441 47nF

R461 100R 1/16W 5% C445 47nF

Figure 1 Recommended Input Signal schematic

Figure 2 Recommended Input Hs, Vs Signal schematic

Figure 3 Example of acceptable differential signal routing

Figure 4 From chip to DVI connector signal trace routing example

 MHL Differential Impedance 100 ohm; Common mode Impedance 30 ohm

2.5 Vx1 / eDP / LVDS Interface Guidelines

2.7 DDR3 Interface Guidelines

8. CMD signal does not fine turn trace match.

ADC OP Current Select guide table

 SOG mode program procedure:

 ADC / HPLL optimum setting:

0x8023 CMCTL[2:0] 0x20

0x8019 ADC_CMP_BIAS 0x60

0x1A16[4] Sample clk invert VGA mode 1 (reset value)

0x45AE[1] Sample clk invert 1

ADC Normal to Low Power Mode

*3 : Not support External LDO, default using internal LDO

5: This setting is bandwidth selected, user can fine-tune by himself.

*1 : HPLL counts auto load for Separate sync for 0x4A01[5] :

*2 : HPLL counts auto load for Composite/SOG sync 0x4A01[5]:

4.2 DisplayPort Receiver

Low Power Control

4.3 DisplayPort Transmitter

Low Power Control

4.3.1 DisplayPort Transmitter(Daisy) Route & Bypass Mode Setting

4.4 TMDS/HDMI Receiver Operating Setting:

4.4.1 HDMI RX – PHY

0x04 if access lane2 only

0x8200 [6:5]EQR_VB[1:0] = 01 0x21

0x8202 [0] EQR_ZRX_EN 0x01

0x824A EQ AC Gain_LSB By application

0x824B EQ AC Gain_MSB By application

RX0 HDMI Deep Color PLL COLOR_DEP_SELECT

3. CAP_MULT OFF (放大 CP mismatch, 因此可嘗試關閉) (820D=0B 關閉)

HDMI Rx – Global registers

Scaler Reg. Function Must Recommend

0x450E[2]=1b0 if all PHYs enter power

4.4.2 HDMI RX HDCP 1.4

0x646 HDCP_CTRL3 0x60 For HDCP CTS

4.4.3 HDMI RX HDCP 2.2

4.5 HDMI / TMDS Transmitter Operating Setting:

ICP Hx/Ht registers

Scaler Reg. Function Must Recommend

HDMI Tx – PHY registers

Scaler Reg. Function Must Recommend

Bits Name Description

7 ttx_chc_pn_swap P/N Swap - Channel Clock R/W

所以400 cut2 回來， no mirror case:fw 要將0x6C02=0x05

pclk clkmult div tclk unit

可 pass CTS 的設定值(0x5D, 0x9D, 0xDD)

[2:0]bypll_src_sel[2:0] 0x492F[2:0]=100, DP PHY0 的lsclk

[7:6] clk_mode_sel_hdmitx[1:0] =10

1 : 10b out from FIFO

Register Function Must

0x6824[3]=1 LVDS C port CLK See below table of LVDS Swing

0x3B50[4:3] Display color depth By

LVDS Data Swing Reference Setting C port:T0