Computer Components

„ Computer components are made from both

combinational and sequential logic circuits

„ We will apply the knowledge of Boolean Algebra

Combinational Logic Circuits to realize these circuits

CIT 595 „ First we will look at Combinational Logic Circuit

Spring 2010

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Combinational Logic Circuits 1 Bit Addition Unit (Half Adder)

„ Always gives the same output for a given set of
inputs

„ Do not store any information (memoryless)

„ Examples: adder, decoder, multiplexer (mux),

shifter
■ These
Th are combined
bi d tto fform llarger units
it such
h This circuit is known as half adder
as ALU ■ Does half the job – does not account for carry-in input

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 1 Bit Addition Unit (Full Adder) 1 Bit Addition Unit (Full Adder) contd..
Sum =

NOTE:
Carry Out =

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1 Bit Full Adder N-bit Adder

„ Just as we combined half adders to make a full
adder, full adders can connected in series
„ The carryy bit “ripples”
pp from one full adder to the
Half Half next; hence, this configuration is called a ripple-
Adder Adder
carry adder

Two half adders make a full adder 16-bit Ripple Carry Adder

C0 is assumed to be 0
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 Multiplexer 2-to-1 MUX

„ A multiplexer sets its single „ Selects between two inputs

output to the same value as
one of its many inputs 0 1

x1 x1
„ Output is determined by the x1 x2
value of the multiplexer’s x2 x2
control lines (a.k.a selector)
This is a block
„ To be able to select among n diagram for a
„ What is the logic behind selection?
inputs, log2n control lines are multiplexer
needed

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2 to 1 MUX Subtraction

s x1 x2 F(s,x1,x2) „ The adder logic circuit seen before does only addition
0 0 0 0
„ Recall that X – Y = X + (-Y)
■ We find 1’s complement of Y and add 1 to get
0 0 1 0
negative
ti value
l off Y ii.e. –Y
Y
0 1 0 1 ■ Then we add X and -Y
0 1 1 1
1 0 0 0 01101000 (104) 11110110 (-10)
1 0 1 1 -00010000(16) -11110111 (-9)
1 1 0 0 s’x1
’ 1 + sx2
2
01101000 (104) 11110110 (-10)
1 1 1 1
+11110000(-16) +00001001 (9)
01011000 (88) 11111111 (-1)
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 Implementing Subtraction Logic in 1 Bit Adder Unit Modification to the 1 Bit Adder
(w/ Subtraction)
„ Let Y be the 2nd input
„ We need both the Y and Y complement (Y’) S

„ To choose between addition and subtraction we will use

y 0
a select signal “S” (we will learn later that S is actually
_
generated by the control unit) y 1
■ S = 0, then addition i.e. Y input is chosen
■ S = 1, then subtraction i.e. Y complement is chosen

„ If subtraction then we need to add 1 to Y complement

(Y’)) so as to get –Y
(Y Y
■ +1 can be achieved by making the first carry C0 into
the adder be 1
■ Hence, C0 = S (this will allow both operations i.e. add/sub)

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Detecting Arithmetic Overflow Detecting Overflow

„ Overflow is said to occur if result is too large to fit in the number of bits
„ Circuit outputs 1 when the
used in the representation Cout MCin Overflow
Carry into MSB (MCin) does not
equal carry out (Cout) 0 0 0
Carry 1
into 01000 ((8)) 11000 ( )
(-8)
MSB „ If you observe carefully, the 0 1 1
+01001 (9) + 10111 (-9) output is equivalent to XOR gate
Carry 0 10001 (-15) 1 01111 (+15) 1 0 1
Out
„Thus to detect overflow we
XOR the values of Cout and 1 1 0
„ We have overflow if MCin
■ Signs of both numbers are the same, and Sign of sum is different
■ If Positive number is subtracted from a Negative number
number, result is „ In general
general, for n
n-bit
bit adder
positive and vice versa Overflow = Cn + Cn-1

„ Another test (easy for hardware) Cout Cin into MSB

■ Carry into MSB does not equal carry out
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 Bit Shifter Creating Logic for 2-bit Shifter
„ Lets see the design of an unsigned 2-bit shifter O1 O0
D1D0
D1D0
S 00 01 11 10 S 00 01 11 10
„ To determine 1-bit shift to left or right 0 0 1 1 0 0 0 0 0 0
Inputs Outputs
S D1 D0 O1 O0 1 0 0 0 0 1 0 0 1 1
„ Assume th
A thatt this
thi ddecided
id d b
by control
t l
0 0 0 0 0 O1 = O0 = SD1
variable/signal input called S
0 0 1 1 0
■ If S = 0, then we do 1 bit left shift 0 1 0 0 0
■ Else, we do 1 bit right shift 0 1 1 1 0
1 0 0 0 0
„ Lets say the input is 2-bit value D(D1, D0) where 1 0 1 0 0
D1 is the most significant bit(MSB) 1 1 0 0 1
Logic
1 1 1 0 1 circuit
„ Lets call the output of the shift be O(O1, O0) diagram

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4-Bit Bit Shifter Decoder

„ Decoders are circuits used to decode encoded
„ Similarly, we can information
make 4-bit shifter „ A binary decoder converts binary information from n-bit
that moves the bits input code to a maximum of 2n unique outputs
of a nibble (half of ■ Decoder logic uses n-bit input value to chose exactly
a byte) one one of the 2n outputs (only a particular output is active)
position to the left ■ Example: Memory Address Decoding
or right

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 Address Decoder Example
n-bit Address
2-to-4 Decoder Logic
„ A binary number with 2 bits as its input
„ Selects exactly 1 of 4 outputs
„ At any time, only 1 output line is “ON'' or “1” and all others
Read/
Write are “OFF” or “0” (referred to as one-hot encoded)

2n Memory
locations Array
Decoder
(2n x m)

m bits (data)

Decoder will select only 1 memory location (row) based on address

1 – active/asserted/chosen
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Encoder Resolving Interrupts

„ Opposite of decoder

„ Given information is transformed into more

compact form

„ Example:
■ In Interrupt Driven I/O - need to determine higher
priority among devices who interrupted at the same
time
■ Priority encoder circuit determines which interrupt
request should be serviced by the processor
¾ In priority encoder each input has a priority level associated
with it
¾ The encoder outputs indicate active input that has the
highest priority
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 Example: 4:2 Priority Encoder Code Converters

„ x3 has highest priority „ In general encoders and decoders are known as

■ x2 the next highest…x0
code converters
has lowest priority Inputs Outputs
x3 x2 x1 x0 y1 y0 „ Convert from one type of coded information
„ y1y0 are outputs 1 x x x 1 1 (encoding) to another output encoding
determine the which 0 1 x x 1 0
request goes to processor „ Example: BCD to 7 segment display (calculators
for servicing 0 0 1 x 0 1 and digital number displays etc)
0 0 0 1 0 0 ■ Binary-Coded
Binary Coded Decimal (BCD) is an encoding for
0 0 0 0 x x decimal numbers in which each digit is represented
by its own binary sequence.
■ see “Handout” on code converters
X – don’t care

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Enabling/Gating Outputs 2-Bit ALU

„ Combinational logic circuits produce an „ f0 and f1 control lines
output based on certain inputs (generated by control unit)

„ We may not want to use its output all the „ The value of control lines
time determine
dete e which
c ope
operation:
at o
■ Same inputs are shared amongst different ■ 00 – A + B (Addition)
logic units
■ 01 – NOT A
■ Some how we only want to make one unit
active and disable all others ■ 10 – A OR B
■ 11 – A AND B
„ Hence we want some sort of control to
temporarily disable the circuit and only „ Similarly a N-Bit ALU can
enable it if the control is set Who decides value be made
of EN?
„ Basic gates allow us to achieve this: All sub units form their
■ AND gate - Figure a. EN = 1, F = X operation, but final output is
■ OR gate - Figure b. ~EN = 0, F = X chosen only if enabled (EN = 1).
Example on the next slide
Here EN is decided by the
decoder logic.
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 2-Bit ALU 8-bit ALU made from eight “bit slices”

Cin

„ Bit slices allow designers to build an ALU of any

desired bit capacity
„ Carry out of each bit slice connects to carry in of next
(more significant bit) slice
„ F0 and d F1 (d
(decoder
d iinputs)
t ) connectt simultaneously
i lt l tto
all slices so that the identical operation is selected in all
slices at a given time
„ There is a single input to the least significant slice i.e.
carry-in (Cin) input
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Propagation/Gate Delay Efficient Design E.g. Carry Look Ahead

„ The length of time starting from when the input „ Recap
to a logic gate becomes stable and valid, to the ■ Si = Ai ^ Bi ^ Ci

time that the output of that logic gate is stable ¾ Si = Pi ^ Ci where Pi = Ai ^ Bi

and valid. ■ Ci+1 = Ci (Ai ^ Bi) + AiBi
¾ Ci+1 = Ci Pi + Gi where Gi = AiBi
„ The levels of gate for digital can add to more
„ Gi is called carry generate and it produces a carry of 1
delay when both Ai and Bi are 1 regardless of the carry in Ci
■ E.g. in Ripple Carry adder, the carry bit has to
„ Pi is called carry propagate and is associated with
propagate through, end to end
propagation of Ci to Ci+1
¾ Assume one gate has a propagation delay of x units
■ The addition will carry whenever there is an input
¾ Carry passes through 2 gate levels per adder
¾ Total carry propagation time for n-bit adder = 2*n*x units carry, but will not carry if there is no input carry
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 Carry Look Ahead Programmable Logic Array (PLA)
„ A digit of addition will carry: „ A PLA is a prepackaged circuit
that can be tailored to suit
various needs
„Note that carry C1, C2, C3 are
calculated at the same time
„ Any truth table can be
represented by some AND gates
feeding into an OR gate
■ Sum Of Product form

„ # of AND gates determines how

many truth table rows can have
1’s in them over all the functions
implemented
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FPGAs FPGA logic block

„ Field Programmable Gate „ Typically has small
Arrays number of inputs and
„ Used to implement larger one output
circuit
i it
■ > 20K gates
„ Contains Look Up
„ Contains
■ I/O blocks
Table (LUT) which
■ Logic blocks for implementing
contains storage cells
required
q functions used to implement a
■ Interconnection (contain wires & small logic function
programmable switches so as
allow logic blocks to
interconnected in many ways)
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 Hardware Descriptive Languages E.g. Verilog code
„ Language to describe the circuit's operation, its „ 2-input (32-bit) mux „ ???
design and organization, and tests to verify its module circuit_1 (q, a, b)
operation by means of simulation module Mux_2_32(mux_out, data_1, output q;
data 0 select);
data_0, i
input t a, b
b;
always@(a or b)
„ A simulation program, designed to implement parameter word_size = 32 begin
output [word_size – 1: 0] mux_out; if(a == 1’b1)
the underlying semantics of the language
input [word_size – 1: 0] data_1, data_0; q = b;
statements, coupled with simulating the progress Input select; else
of time provides the hardware designer with the q=1 1’b0;
b0;
ability to model a piece of hardware before it is assign mux_out = select ? data_1: data_0; end
created physically endmodule
endmodule

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