EE 3610: Digital Systems 1

Lecture 9:

State Machine Charts

and
Microprogamming

EE 3610 Digital Systems Suketu Naik

 2

Part 1: State
Machine Charts

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 State Machine Diagram 3

 State Diagram or State Graph Examples

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 State Machine Chart 4

 Principle Components of State Machine Chart

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 State Machine Chart 5

 Resembles flow charts

 Also known as Algorithmic State Machine (ASM) Chart

State Box, Lists Moore Outputs

Condition

Conditional Output

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 State Machine Block 6

 SM Chart is constructed from SM Blocks

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 State Machine Block 7

When S1 state is entered

Z1Z2 are 1
When X1 =0,
Z3Z4 are 1

When X1 = X2 = 0,
machine goes
to next state
via exit path 1

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State Machine Block 8

In both blocks, Z2 =1
if X1 = 0; next state
is S2 if X2 = 0 and
S3 if X2 = 1 and

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 State Machine Chart Rules 9

 A state consists of 1 state box and all the other boxes coming
from it (until another state box is encountered)
 There must be exactly 1 exit path active for a state at any time,
no matter what the input
 No internal loops (feedbacks)
 All paths are traversed simultaneously
 Outputs on active paths or in the state box are asserted; all other
outputs are de-asserted

Feedbacks

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 State Machine Chart: Example 10

X/Z1
A
A 1
X B
X
X/Z1 0 1
B Z1 X Z1
0
X X
C/Z2
C/ Z2
1
0
X
X

State Box Condition Conditional Output

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 State Machine Chart 11

Advantage
Why use SM Charts?
A
 Some states in State
Diagram get very cluttered 1
 SM Charts allow busy states X B
to use more room for clear 0
depiction 1
Z1 X Z1
VHDL code can be written
0
directly from the SM Chart
C/Z2
1
0
X

State Box Condition Conditional Output

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 State Machine Chart: VHDL Code 12

process (PS, X)
begin A
--set all outputs to inactive state
1
Z1 <='0'; Z2 <= '0'; X B
case PS is 0
when A => ---conditionals 1
Z1 X Z1
if x= '1' then
NS <=B; 0
else C/Z2
Z1 <= '1'; ---encountered Z1
1
NS <= A;
0
end if; X
when B =>
if x='1' then Z1 <='1';
else NS <= C;
when C =>
Z2 <= '1';---moore output
if x= '1' then NS <=C;--conditionals
else NS <=B;
end if
end case;

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State Machine Chart: Example 13

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 State Machine Chart: Example 14

Add/Shift Multiplier

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 State Machine Chart: Example 15

SM Chart
State Diagram

Ref: http://www2.hawaii.edu/~lucam/EE260/S10/lectures_files/Lecture14.pdf

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 16

Part 2:
Microprogramming

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 Read Only Memory (ROM) 17

 Store the whole truth table in ROM

 ROM can implement any n-input, m-output
combinational problem
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 Usefulness of ROM 18

Example:Figure
Sort rods9.20
of varying length (+/-10%)
An 8-Word on conveyor
X 4-Bit ROM belt
 Inputs: Three sensors A,B,C (light sources and photodiodes)
 Outputs: Two arm control signals

A
spec
- 5%

Too Within Too spec

Long Spec Short + 5%

B
C

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 Usefulness of ROM 19

Example:Figure
Wifi enabled
9.20lighting control inX
An 8-Word a large
4-Bitroom
ROMor a house
 Inputs: Three switches in different positions
 Outputs: Three different modes of light = three different control
signals

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 Why use Microprogramming? 20

 State Machine (hence SM chart) can be stored into

ROM as a look-up table

 If the state machine (hence SM chart) has large number of

inputs, the size of ROM will be very large

 Solution: transform SM chart to Microprogramming

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 Microprogramming 21

 Hardwired Control
 Implemented using gates and flip-flops

 Faster, less flexible, limited complexity

 Microprogram Control
 Control Store

 Memory storing control signals and next state info

 Controller sequences through memory

 Slower, more flexible, greater complexity

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Microprogamming 22

22
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 Microcode 23

 Assign one word of memory per state (microcode)

 Limit states to 1 qualifier (input used for next_state
decision)
 Works only on Moore machines (output is a function of
state)
 State register provides address to microcode ROM
 ROM word decodes
1) outputs
2) which input to test
3) next_state if true
4) next_state if false

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 Implementing SM Charts 20

 Transformations for Microprogramming

1) Eliminate conditional outputs
 Transform to a Moore machine

2) Test only one input in each state

3) Eliminate redundant states

 Same output and same next states

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 Binary Multiplier Control 21

4-bit Binary Multiplier SM Chart for Multiplier Controller

State Machine for Multiplier Controller

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 Modified Multiplier Control 22

 Transformations for Microprogramming

 Eliminate conditional outputs
 Transform to a Moore machine
 Test only one input in each state
 Eliminate redundant states
 Same output and same next states

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 Two-Address Microcode 23

 Six states: 3 flip-flops required

 ROM will need
 six entries (for six states)
 each entry will contain 12 bits
 2 bits for TEST, 3 bits for NSF, 3 bits
for NST, 4 bits for Load, Ad, Sh and
Done
 ABC are the address bits
 Single qualifier per state (St, M, K)
 Each ROM location stores control word
for microinstruction

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 Two-Address Microprogram 24

4-bit Binary Multiplier SM Chart for the Multiplier

Controller

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 Putting It All Together 28

 Binary Add-and-Shift Multiplier

 Multiplier Control
 Counter
 SM Chart

 Two-Address Microcode
 Microprogram ROM

 VHDL Simulation

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 Add-and-Shift Multiplier 29

We are creating an efficient ROM table for this...

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Multiplier Control 30

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 Two-Address Microprogram 31

Schematic SM Chart

TEST Bits
TEST Inputs
00 St
01 M
10 K
11 1

St: if 0 (NSF) goto S0

if 1 (NST) goto S01

M: if 0 (NSF) goto S2
if 1 (NST) goto S11

K: if 0 (NSF) goto S1
if 1 (NST) goto S3

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 Multiplier VHDL Model: Two Address Microprogram 35

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mult4X4_micro is
port(Clk, St: in std_logic;
Mplier, Mcand: in std_logic_vector(3
downto 0);
Product: out std_logic_vector(7 downto 0);
Done: out std_logic);
end mult4X4_micro;

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 Multiplier VHDL Model: Two Address Microprogram 36

architecture microprogram of mult4X4_micro is

type ROM is array(0 to 5) of

std_logic_vector(11 downto 0);
constant control_store: ROM :=
(X"010", X"D28", X"630", X"E44", X"952",
X"C01");
12-bit binary number encoded in hexdecimal
(each number represents the row of controller ROM truth table)

signal ACC: std_logic_vector(8 downto 0);

alias M: std_logic is ACC(0);
signal Load, Ad, Sh, K: std_logic;
signal counter: std_logic_vector(1 downto 0) :=
"00";
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 Multiplier VHDL Model: Two Address Microprogram 37

signal TMUX: std_logic;

signal uAR: std_logic_vector(2 downto 0) :=
"000";--ROM index
signal uIR: std_logic_vector(11 downto 0) :=
X”000”;--store ROM output

alias TEST: std_logic_vector(1 downto 0) is

uIR(11 downto 10);
alias NSF: std_logic_vector(2 downto 0) is
uIR(9 downto 7);
alias NST: std_logic_vector(2 downto 0) is
uIR(6 downto 4);

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 Multiplier VHDL Model: Two Address Microprogram 38

begin --control signals load,ad,sh,done are the

last 4 bits of uIR
Load <= uIR(3);
Ad <= uIR(2);
Sh <= uIR(1);
Done <= uIR(0);
Product <= ACC(7 downto 0);
K <= '1' when counter = "11" else '0';
with TEST select
TMUX <= St when "00",
M when "01",
K when "10",
'1' when others;

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 Multiplier VHDL Model: Two Address Microprogram 39

controller: process(Clk)
begin
if falling_edge(Clk) then
uIR <= control_store(to_integer(uAR));
end if;
if rising_edge(Clk) then
if TMUX = '0' then
uAR <= NSF;--set the index to NSF
else
uAR <= NST;
end if;
if Sh = '1' then
counter <= counter + 1;
end if;
end if; end process;

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 Multiplier VHDL Model: Two Address Microprogram 40

datapath: process(Clk)
begin
if rising_edge(Clk) then
if Load = '1' then
ACC(8 downto 4) <= "00000";
ACC(3 downto 0) <= Mplier;
end if;
if Ad = '1' then
ACC(8 downto 4) <= '0' & ACC(7
downto 4) + Mcand;
end if;
if Sh = '1' then
ACC <= '0' & ACC(8 downto 1);
end if;
end if; end process; end microprogram;
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 Single-Address Microprogram 31

Schematic SM Chart

TEST Bits
TEST Inputs
00 St'
01 M
10 K'
11 1

St': if 0 (NST) goto S0

M: if 1 (NST) goto S11

K': if 0 (NST) goto S1

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