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Q-1 Explain why NAND and NOR gates are more common than AND and OR Gates.
Q-2 Build a 2-input XOR gate using minimum number of CMOS transistors.
a) Compare the performance. Assume a 100-ns clock for the microcontroller, and a 20-ns
clock for the custom processor. Assume the microcontroller uses two operand
instructions, and each instruction requires four clock cycles. Estimates for the
microcontroller are fine.
b) Estimate the number of gates for the custom design, and compare this to 10,000 gates for
a simple 8-bit microcontroller.
c) Compare the custom GCD with the GCD running on a 300-MHz processor with 2-
operand instructions and one clock cycle per instruction (advanced processors use
parallelism to meet or exceed one cycle per instruction).
d) Compare the estimated gates with 200,000 gates, a typical number of gates for a modern
32-bit processor.
Q-5 A subway has an embedded system controlling the turnstile, which releases when two
tokens are deposited.
Q-6 Illustrate how program and data memory fetches can be overlapped in Harvard architecture.
Q-7 Acquire data-sheet for PPC 403GCX, AT91SAM, 68HC16, C2000, TLCS-900 and ARM9. List the
features of the basic version of that microcontroller, including key characteristics of the
instruction set (number of instructions of each type, length per instruction, etc), memory
architecture and available memory, general purpose registers, special function registers, I/O
facilities, interrupt facilities, and other salient features and explicitly mention the applications
where they are mostly used. Create a table and mention all the features.
Q-8 Write the instruction set simulator for the given instruction set for some processor.