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DIGITAL SYSTEMS TCE1111
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DIGITAL SYSTEMS TCE1111
Counters
* Counters are important digital electronic circuits.
* They are Sequential logic circuits because timing
is obviously important and they need a memory
characteristic.
* Digital counters have the following important
characteristics,
1. Maximum number of count
2. Up-Down Count
3. Asynchronous or Synchronous Operation
4. Free-Running or Self-Stopping
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DIGITAL SYSTEMS TCE1111
Asynchronous/Ripple Counter
Only the first FF receive clock pulse from the source ( clock generator),
others FFs receive clock pulse from either Q or Q’ of prior FF
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Asynchronous/Ripple Counter
Four-bit asynchronous binary counter and its timing diagram.
CLK Q3 Q2 Q1 Q0
PLUSE
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
REPEAT
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CLK Q3 Q2 Q1 Q0
PLUSE
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
GLITCH
11 0 0 0 1
12 0 0 1 0
13 0 0 1 1
14 0 1 0 0
15 0 1 0 1
16 0 1 1 0
MOD 10 RIPPLE UP COUNTER – NGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE
FROM Q
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MOD 10 AS RESET / CLITCH AT 1010.
•The inputs the NAND gate are from the Q output from FF1 and FF3 ( from 1010 -- FF3FF2FF1FF0)
DIGITAL SYSTEMS TCE1111
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0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
(REPEAT
)
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0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
A 4-bit 9 1 0 0 1
synchronous 10 1 0 1 0
binary counter
11 1 0 1 1
and timing
12 1 1 0 0
diagram. Points
where the AND 13 1 1 0 1
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STEP -2
Use the state transition diagram to set up a table that lists all
PRESENT states and their NEXT states
Present state Next state
C B A C B A
1 0 0 0 0 0 1
2 0 0 1 0 1 0
3 0 1 0 0 1 1
4 0 1 1 1 0 0
5 1 0 0 0 0 0
6 1 0 1 0 0 0
7 1 1 0 0 0 0
8 1 1 1 0 0 0
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STEP -3
Add a column to this table for each J and K input. For each PRESENT state,
indicate the level required at each J and K input in order to produce the transition
to the NEXT state.
Present state A
C B A jA kA A A
1 X
0 0 0 1 X BC X 1
0 0 1 X 1 0 X
BC X 1
0 1 0 1 X
BC 0 X BC X X
0 1 1 X 1
1 0 0 0 X 1 X BC X 1
1 0 1 X 1
1 1 0 0 X jA= C kA = 1
1 1 1 X 1 21
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kB = A+C
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SETP -5
Finally to implement the final expressions.
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Objective:
To design a 3 bit counter (D FF) with the following count sequence 7,6,5,4,1. All unwanted stages go to 7.
000
010
111
011
110
101
001 100
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DIGITAL SYSTEMS TCE1111
CLK Q Qt Qt’
PRESET CLEAR D
1 1 0 ↓ 0 0 1
0 ↓ 1 0 1
1 ↓ 0 1 0
1 ↓ 1 1 0
PRESENT NEXT D
0 0 0
0 1 1
1 0 0
1 1 1
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OUTPUT INPUT
PRESENT STATE NEXT STATE C B A
C B A C B A D DB DA
C
0 0 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1
1 0 0 0 0 1 0 0 1
1 0 1 1 0 0 1 0 0
1 1 0 1 0 1 1 0 1
1 1 1 1 1 0 1 1 0
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K- Map
A A A A
A A
CB 1 1
CB 1 1
CB 1 1
CB 1 1
CB 1 1
CB 1 1 CB 1 1
0 1 CB 0 1
CB CB 1 0
CB 0 0
DC CB 1 0
=A+
DB = AB
C’ + B DA = A’ +
+ C’ C’
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DIGITAL SYSTEMS TCE1111
Objective:
To design a 3 bit counter (T FF) with the following count sequence 7,6,5,4,1. All unwanted stages go to 7.
SOLUTION
Output sequence 7,6,5,4,1
In 3 bits format: 111,110, 101, 100, 001
111
011
110
101
001 100
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1 1 0 ↓ 0 0 1 No change
0 ↓ 1 1 0 No change
1 ↓ 0 1 0 Toggle
1 ↓ 1 0 1 Toggle
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PRESENT NEXT T
0 0 0
0 1 1
1 0 1
1 1 0
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OUTPUT INPUT
PRESENT STATE NEXT STATE C B A
C B A C B A TC TB TA
0 0 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 0
0 1 0 1 1 1 1 0 1
0 1 1 1 1 1 1 0 0
1 0 0 0 0 1 1 0 1
1 0 1 1 0 0 0 0 1
1 1 0 1 0 1 0 1 1
1 1 1 1 1 0 0 0 1
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K- Map
A
A A A
A
A
1 1 1 1 1 0
CB CB CB
CB 1 1 CB 0 0 1 0
CB
CB 0 0 CB 1 0
CB 1 1
CB 1 0 CB 0 0
CB 1 1
TC =A’B’ TB =
+ C’ B’C’ + TA = A’
A’BC +C
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Objective:
To design a 3 bit counter (JK FF) with the following count sequence 4,7,3,0,2. All unwanted stages go to 4.
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