Beruflich Dokumente
Kultur Dokumente
Naseem Ullah
Master’s Thesis
Electrical Engineering
Embedded Systems
2014
Avdelningen för data- och elektroteknik
Department of Computer and Electrical Engineering
Master’s Thesis
This exam work has been carried out at the School of Engineering in Jönköping
in the subject area Electrical Engineering. The work is a part of the two-year of
Master of Science programme with a specialization in Embedded Systems. The
authors take full responsibility for opinions, conclusions and findings presented.
Supervisor:
JTH, Alf Johansson
Examiner:
JTH, Prof Shashi Kumar
Scope: 30 ECTS
Reg Nr: JTH-
Jönköping 2014
School of Engineering
Jönköping University
SE-551 11 Jönköping Sweden
Abstract
With advancement in automotive systems, it is not just the combination of me-
chanical devices like in old days. Almost all the systems of today’s modern car
are controlled electronically by a number of ECUs (Electronics Control Unit) with
the combination of sensor modules. To exchange information between the ECU
and sensor modules a number of communication standards are used. The most
commonly used standards are CAN, LIN, and PWM etc.
The data transmission between the ECU and sensor modules can be easily es-
tablished with a PWM (Pulse Width Modulation) techniques in comparison with
CAN or LIN. PWM provide a convenient solution in terms of cost and perfor-
mance when the data-rate is upto 10-bits. While for higher resolution data rates
its performance are not satisfied. Extra effort is needed to implement diagnostic
information for the integrity of data. Also, the accuracy of PWM signal is depen-
dent on the noise voltage and channel bandwidth. In 10-bit system a single bit
is represented by 4mV which face serious problem in automotive system due to
the noise voltage pulses which effect the resolution of the PWM. The alternative
solution for safe and high data rate which is more than 10-bit resolution is to used
CAN and LIN protocols.Both CAN and LIN have availability of diagnostic modes
for an ensured data transmission. Also, their capabilities for interconnecting a
number of nodes (sensors-modules) on the same network can significantly reduced
the wiring cost. But in automotive a number of systems need to communicate
through point-to-point link, and it seem to be too expensive to used CAN and
LIN for point-to-point communication because of its development complexity and
wiring cost for a standalone system. To overcome these issues and to provide
an alternative low cost solution the SAE (Society of Automotive Engineers) devel-
oped a 3-wire new digital point-to-point protocol called SENT. SENT (Single Edge
Nibble Transmission) Protocol is now an international standard (SAE J2716).
This thesis work focuses on the development of SENT protocol decoder and its
signal robustness analysis in comparison with the conventional PWM signal. Our
first goal is to developed SENT-Protocol decoder in software on the available
iii
iv
microcontrollers is to check how much memory foot print is used and how much
the processor overhead. Two platforms has been used for this purpose. First,
two implementation designs prototype were made with fixed-point and floating-
point development techniques on the 32 bit platform for SENT decoder. Secondly
SENT-decoder were developed with 8-bit platform and compared with the two
previous designs to check how much memory foot print is used and how much is
the processor overhead. Finally, the signal integrity analysis has been performed
for PWM and SENT signal using spice simulation. The purpose is to check the
maximum data rate limit that the PWM signal support with out creating any bit
error in the transmitted signal. The same data rate is then used for SENT signal
to be compared with PWM signal.
Keywords
SENT
CAN
LIN
PWM
PSI5
Nios II
DE 2 Board
GPIO
SOPC Builder
ADC
DAC
SPICE Simulation
v
Acknowledgments
First and foremost I want to thank my supervisor Alf Johansson for his continuous
supervision and suggestions throughout this thesis and during my complete Mas-
ter’s study. I appreciate all his contributions of time, ideas and his great patience
to make my M.Sc. I had a great opportunity of learning so many things from him
in the meetings during our discussions.
I would like to thank Professor Shashi Kumar for his continuous support and
motivation throughout my master study program. I really appreciate his invaluable
time and advises that he gave me during my complete study program.
I would also like to thank all my teachers for their full time support and providing
invaluable knowledge during my Master’s study. I had a good time while studying
in JTH. I want to thank to JTH and Sweden for providing a beautiful environment
and a realistic study atmosphere during my study.
Last but not least, I would like to pay a special thank you to my parents whose
moral support and prayers has always been with me.
vii
List of Figures
1.1 SENT senor and receiver communication interface . . . . . . . . . 2
List of Figures xi
Contents xv
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Automotive protocols challenges: . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Objectives and Tasks . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Delimitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Theoretical Background 7
2.1 Communication Protocols in Automotive . . . . . . . . . . . . . . . 7
2.1.1 Communication Requirements for Automotive System . . . 7
2.1.2 Local Interconnect Network . . . . . . . . . . . . . . . . . . 8
2.1.3 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . . 11
2.1.4 Controller Area Network . . . . . . . . . . . . . . . . . . . . 13
2.1.5 Single Edge Nibble Transmission Protocol . . . . . . . . . . 15
2.2 Hardware Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 Nios II Processor . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.2 DE2 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.3 Microchip-PIC Microcontroller . . . . . . . . . . . . . . . . 24
2.3 IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 ADS-Advanced Design System Tool . . . . . . . . . . . . . . . . . 27
2.5 Sensors in automotive . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.1 Position or Speed sensor . . . . . . . . . . . . . . . . . . . . 29
2.5.2 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . 30
2.5.3 Linear Hall Sensors TLE4998X . . . . . . . . . . . . . . . . 32
2.5.4 Mass air flow sensors - MAF . . . . . . . . . . . . . . . . . 33
2.5.5 Tire pressure sensors or TPMS . . . . . . . . . . . . . . . . 33
2.5.6 Throttle Position sensors - TPS . . . . . . . . . . . . . . . . 33
2.5.7 Manifold air pressure sensor - MAP . . . . . . . . . . . . . 33
2.5.8 Fuel pressure sensor - FPS . . . . . . . . . . . . . . . . . . . 33
xiii
xiv Contents
Bibliography 99
Introduction
This thesis focuses on the implementation and signal analysis of the Single Edge
Nibble Transmission protocol (SENT) described by SAE J2716 SENT [46]. SENT
is a point-to-point digital protocol used to interface high resolution sensors to
Electronic Control Unit (ECU) in modern automotive systems. In this chapter we
will focus on some features of SENT protocol and their applications in automotive
systems. The complete introduction of SENT protocol and its comparison with
the conventional PWM (Pulse Width Modulation) also with some other point to
point digital protocols will be described in details in up coming chapters. This
chapter also includes thesis objectives and layout of thesis report.
1.1 Background
Today modern vehicles are equipped with a large number of smart sensor modules
which are capable of accurate sensing, signal conditioning and produced digital
output that can be interface with microcontroller without any prior conversion
(ADC or DAC). In order to retrieve the high resolution information remotely
from these sensors the signal integrity and robustness should be ensured. Up to
the recent times the conventional Pulse Width Modulation (PWM) was the most
commonly use interface between sensors and ECU in automotive systems [5]. But
the high resolution output form sensors, real time, safety critical, electromagnetic
compatibility (EMC) requirements and low cost overhead demands for more robust
and standardized interface. To accommodate the previously mentioned require-
ments the Society of Automotive Engineer (SAE) has developed a low cost digital
point-to-point interface for unidirectional sensor data the interface is called Single
Edge Nibble Transmission (SENT) protocol [46].
SENT protocol was initially adopted for the powertrain [6] applications in automo-
tive but because of its low implementation cost and maintaining greater integrity
of high resolution sensor data, also due to its more robustness to noise make it more
appealing for other automotive and non-automotive applications. The situation
1
2 Introduction
Due to the long distance between the ECUs and off-sensor modules the wire length
plays a vital rule in the distortion of signal-(data). A pair of parallel wires acts
like a transmission line when high frequency, short period pulses are applied to
the channel for high resolution data transmission. The channel line behaves a
series of inductance and capacitance which can be model as a lumped circuit an
element of wire segment is shown in figure 1.1. A number of techniques are used to
achieve high data rate with less signal loss for designing automotive communication
standards such as PWM technique. There is a trade-off to achieve high resolution
1.3 Thesis Objectives and Tasks 3
data transmission and signal using the PWM technique. The development of
SENT protocol was intended to overcome these issues [46].
This thesis work focuses on the development of SENT protocol decoder and its
signal robustness analysis in comparison with the conventional PWM signal.The
first goal of this thesis work is to perform a comparative study of different automo-
tive communication protocols in order to understand the challenges that demand
for new communication standards. The comparison will be based on their fea-
tures and feasibility for specific applications. The second goal is to developed
SENT-Protocol in software on the available microcontrollers to check how much
memory foot print is used and how much the processor overhead. To achieve the
purpose of this goal two platforms has been used. The software implementation
is done with two different design algorithms fixed-point and floating-point. The
32 bit platform (Nios-II soft-core processor) has been used, which is provided by
Altera FPGA DE2 board for SENT decoder. To check for a low cost and high
performance solution, SENT-decoder are developed with 8-bit platform and are
compared with the two previous designs prototype to check how much memory
foot print is used and how much is the processor overhead. The last goal is to an-
alyze the signal integrity for PWM and SENT signal using spice simulation. This
can be achieved by developing the complete transceiver and channel SPICE model
in SPICE simulation tool. The purpose is to check the maximum data rate limit
that the PWM signal support with out creating any bit error in the transmitted
signal. The same data rate is then used for SENT signal to be compared with
PWM signal.
In order to achieve these goals first a details study has been performed on dif-
ferent point-to-point and network based protocols. The SENT-decoder prototype
is designed by first performing a details study of SENT protocol to specify the
requirements for implementation. The SENT decoder system has been design in
the SOPC builder a utility provided by the Quartus II IDE. The design system
is compiled and loaded to DE2 board to program the FPGA chip. To evaluate
the performance and resource usage analysis of SENT decoder two applications
are developed in NIOS II IDE (Integrated Development Environment) using C-
Programming language with fixed-point and floating point algorithms. The de-
4 Introduction
sign prototype is tested by connecting the SENT sensor module to DE2 board
and receiving the data messages from the sensor module in NIOS II IDE console.
Secondly to check for the alternative low cost solution another prototype has been
developed on 8-bit platform using PIC18 microcontroller together with MP-LAB
IDE which is provided by Microchip. The performance and resource usage of both
prototypes are also compared to check for a good design prototype. To analyse
the signal distortion over the channel for PWM and SENT. The SPICE simulation
model has been designed in the ADS-2008 (Advanced System Design) tool from
Agilent technology which is a very powerful tool for signal integrity analysis. The
channel is model as lumped circuit elements and IBIS model are used for both
input and output buffers models. To analyse the effect of the transmission line on
both SENT and PWM signals different frequencies range and data rate are set for
performing simulation.
1.4 Delimitation
In this thesis our focus is mainly on implementation of SENT protocol on two
different platforms to evaluate the performance and robustness of the SENT signal.
For verification and analysis of our implementation we will not use any off-the-
shelf sensor with the SENT-decoder module instead we will use a custom developed
SENT-transmitter (sensor) module which is described in chapter 2 section 4.2.4
for evaluation of the design SENT-decoder prototypes. In this thesis work the
analysis of SENT protocol is mainly based on prospective of its use in automotive
systems and no other application areas.
In chapter 3 a comparative study has been performed on the most common point-
to-point protocols with SENT protocol which are used nowadays in the automotive
industry. Also the features of network based protocols are described in comparison
with the point-to-point protocols.
Chapter 4 describes the details of SENT decoder prototype design. Also it de-
scribes how the design decisions are made to implement the SENT decoder in
software. The two different software algorithm are explain in details. The IDEs
1.5 Thesis Structure 5
The signal integrity analysis of SENT and PWM signal are performed in this
chapter. In Chapter 5 also a complete description are given about the SPICE-
simulation model of the SENT receiver module, transmitter module and the chan-
nel SPICE model. Each module of the SPICE simulation design is describe in this
chapter. Finally in this chapter the complete simulation design are presented.
The results are presented in chapter 6. The performance analysis of the design
prototypes are presented in this chapter. This chapter also describes evolution of
the resource usage of the design prototypes. Simulation results for signal integrity
analysis are evaluated for both SENT and PWM in this chapter.
Chapter 7 describes the contribution of our work and gave some ideas for further
research in this area. The appendixes consists some schematics and tables which
has been used in this thesis work.
Chapter 2
Theoretical Background
This chapter will described the background for this thesis. We will describe some
of the important protocols standards that are used nowadays in the automotive
system. These protocols standards are either serial (point-to-point) or network
based. The structure and applications of these protocols will be describe in this
chapter and their comparison will be presented in the next chapter. This chapter
will also describe the platforms that are used for the implementation of the design
prototypes. The description of Altera DE2 board and SOPC builder together with
the Nios II soft-core processor are given in this chapter. PIC18F67J50 development
board for 8-bit processor based prototype is also describe in this chapter. Some
of the the most commonly used sensors in the automotive system are describe.
ADS (Advanced Design System) SPICE simulator from Agilient technology which
is used for signal integrity analysis is also describe in this chapter.
Determinism:
In automotive system some of the system are time critical and their exact response
time should be known. For example in safety critical systems a protocol must ful-
filled the deterministic behavior of messages between two components in a vehicle
which are responsible for safety related functions.
7
8 Theoretical Background
Tolerance:
Its not necessary in vehicles that all systems should have fault tolerant functional-
ity but some systems should continue their proper operation even in the presence
of faults. A communication protocol in automotive system should be capable of re-
liable communication. The examples of the systems which requires highly reliable
communication are X-by-wire systems.
Bandwidth:
The communication bandwidth in vehicle is application as well as protocol depen-
dent. For example a bus protocol which connect several ECUs requires greater
bandwidth. Multimedia application require higher data rates and communication
channel bandwidth.The requirement for the higher bandwidth in point-to-point
protocol is less than bus protocol.
Flexibility:
The performance of a communication protocol should not be degraded with the
addition of system or sub-system functionality. Due to the rapid advancements in
addition of new features in automotive systems the communication protocol needs
to be more flexible and scalable.
Security:
In order to secure the data transmission in automotive systems the data encryption
mechanism should be described for communication standards [42]. The security
become more important when vehicle system are exposed to out side world such
as remote diagnosis and inter vehicle communication.
• Based on existing and highly available UART technology exclude the special
consideration for hardware
• No protocol license fee is required [9].
A typical LIN frame comprises of header and response. The header part of LIN
frame is always generated by the master node while response can be generated
by master or slave. As shown Figure 2.4 in the header consist of three fields
synch break, synch field and ident field. The synch break has fixed 13 bits length.
Synch break is issue by master node to inform the slaves that a message is ready.
Synch field set the clock for entire bus. Its value is HEX-55 including start and
stop bits plus 1 bit synch delimiter. A 15% clock drift is allowed between master
and slaves. The inclusion of this field in LIN frame eliminate the use of crystal
for precise clock synchronization. The third part of the LIN header is ident field
which specify what type of data will be on the bus which node should respond to it
and how long should be response. In ident field is further divided into three fields
4 bits (0-3) are used to address devices, 2 bits (4-5) indicate the message length to
follow and the last 2 bits (6-7) are parity bits. A slave can respond when master
commands it. the slave response can be 2, 4 or 8 byte long. The slave nodes
can transmit and receive data directly to each other without involving master if
commanded by the master.
• Ease of implementation
1 The signal timing diagram and the interface line are represented by a single line for figure
• Seats heating
shows the CAN data frames structures for standard frame and extended frame.
As described earlier the main difference between the two formats is the length of
identifier field. The first field of the CAN message is Start Of Frame(SOF) is 1
bit long, indicate the beginning of the message. SOF field is followed by Arbi-
tration field which comprises of 11 bits or 29 bits message identifier depends on
whether the frame is of standard or extended version and 1 bit Remote Transmis-
sion Request(RTR)fields which is used to request data from another CAN node. In
extended frame format arbitration field includes two extra 1 bit long fields: Substi-
tute Remote Request(SRR) used for arbitration between standard and extended
frames and Identifier Extension(IDE) which differentiate the two formats. Arbi-
tration field is followed by 6 bits control field which consists of two parts Reserved
bits(r0, r1) 2 bits in length and 4 bits Data Length Code(DLC) which specify the
numbers of bytes in the data field that will follow. Data field is 0 to 64 bits. A 15
bits Cyclic Redundancy Check(CRC) field and 1 bit CRC delimiter(DEL). CRC
field is followed by acknowledge(ACK) field which includes 1 bit ACK slot and
delimiter DEL. The last field in a CAN frame is End Of Frame(EOF) consisting
of 7 bits to indicate the end of message.
mechanism and shorter transmission time due to the utilization of the number
of nibbles for encoding data. The developed SENT/SPC driver has the support
for all Infineon Technologies programmable linear Hall sensors such as TLE4998C
[12] it is also compatible with TLE4998C supported SPC modes and SENT/SPC
frame formats. Another SENT decoder implementation is provide by Infineon
technologies called SENT decoder for XC2000 [47] which is a complete software
package. The receiver has the support for the following features:
• Reception and decoding of SENT frames
• Configurable number of data nibbles per frame
• Configurable SAE SENT or Infineon specific SENT protocol receiver
• Serial data decoding Error detection
surface. MLX90324 sensor IC has support to decode the rotary angular position
from 0 to 360 degrees. The application area is mostly in automotive industries.
MLX90324 produces an output signal which is proportional to the decoded angle.
The output is selectable between Analog, PWM and SENT (SAE-J2716) Proto-
col. The functional block diagram of MLX90324 is depicted in Figure 2.13 [15].
According to the functional description shown in Figure 2.13 it is clear that the
output can be selected among three different formats. The details explanation
about MLX90324 will be presented in section 4.5.
after the synchronization pulse is depicted in Figure 2.14. The pause pulse is op-
tional and it is defined in the new SAE J2716, JAN2010 standard. There are six
data nibbles the nibble value can be varied between (0-15). CRC nibble is use
for signal integrity purpose. Figure 2.14 describe the basic telegram of the SENT
protocol. The following are some features of the SENT protocol.
• Due to the large rise and fall time of the pulse, SENT signal is more robust
to noise
The transmitted SENT frame from the sensor module is represented by a sequence
of pulses. The complete message contains two 12 bits sensors information the
whole frame is divided into 8 nibbles after the synchronization pulse. The length
of Synchronization pulse is 56 clock ticks if there is no variation in the transmitter
clock frequency. SAE J2716 standard described a 20% variation in the transmitter
clock frequency according to this feature of SENT specification the synchronization
pulse time can be varied between (48.8 - 67.2) clock ticks. The basic unit of time is
called a clock tick and its value can be in the range (3usec to 10usec) according to
SAJ J2716 specification. Figure 2.15 describe the SENT frame format the second
pulse after the synchronization is called status or communication pulse which is
4 bits (one nibble) wide.The length of each nibble can be calculated as (12 + N)
where N is the nibble values which can be varied between (0 -15).
2.1 Communication Protocols in Automotive 19
The nibble value depends on the amount of data being encoded in the data nibble.
The 24 bits data are represented into two signals each 12 bits long. To understand
the complete SENT transmission sequence each pulse can be individually explain
as follows:
20 Theoretical Background
Status or Communication pulse: The status nibble is use for diagnostic pur-
pose. The first two bits are reserved for specific applications like part number and
error information. The 3 and 4 bit of the status nibble can be used to send a short
or enhanced serial message specified by SAE J2716. One bit of a serial message
can be send during each SENT complete frame transmission to send a 16 bit serial
message 16 consecutive transmissions are needed.
Data Pulse: The data nibble pulse is used to transmit the actual of the sensors
module to the ECU. A maximum of six data nibbles (24 Bits data) can be transmit
in one complete frame. The 24 bits data are divided into two signals each carries
three data nibbles is depicted in figure 4. The width of the data nibble pulse varied
with the nibble value and can be calculated according to the formula. Data nibble
pulse width = (12 + Nibble Value) where the nibble value change from 0 to 15.
CRC Pulse: For the data integrity the SAE J2716 Specification provide a 4
bit CRC checksum nibble. The CRC checksum is calculated using the polynomial
x4 + x3 + x2 + 1 with the seed value 5 (0101). The checksum is only calculated for
data nibbles and not for status nibble. The following error can be detected with
this crc checksum:
Pause Pulse: According to the new SENT specification SAE J2716 JAN2010 a
new pulse is defined in the frame this pulse is called a pause pulse which is use to
provide equidistant SENT transmission. The length of this pulse can be 12 to 768
clock ticks.
• Branch prediction
Nios II processor has three different types of cores: Nios II/f (Fast), Nios II/s
(Standard) and Nios II/e (Economy). These cores are shown in the Figure 2.18,
which is taken from the SOPC builder in quartus II design tool. The processor
that we use for the implementation of our design is Nios II/e (economy) type which
is highlighted in yellow in the Figure 2.18. The difference among these cores in
term of performance, area, and memory utilization is given in the Figure 2.18.
Nios II/f (Fast): This is the most powerful core of Nios II family with the 25
percent high performance then the standard core. This core has six-step instruc-
tion pipeline and can execute one instruction per clock cycle which is higher than
the both cores standard and economy type.
Nios II/s (Standard): Nios II/s "standard" processor core implements a small
processor core without a significant trade-off in software performance. The ALU
of standard and fast cores provides the same performance. The standard core has
the five instruction pipeline.
Nios II/e (Economy): The core size is smaller than standard and fast type.
There is no instruction pipe line in this core only fetches one instruction at the
time. It is good for those applications where the implementation cost is required
to be less.
All these devices which the DE2 board provides are connected through the cyclone
II FPGA so the user can configure the FPGA according to the requirement for
their system design. DE2 board is provided with the quartus II hardware design
tool and Nios II embedded processor a software design tool. The three tools DE2
board, Nios II and Quartus II provides complete platform for the hardware and
software co-design of any system design. There is a large amount of learning
material for students and researchers are available on Altera website and also with
the de2 board accessories. For the design and prototyping of our system design
we use the DE2 board along with Quartus II software and Nios II processor IDE.
The complete description of our implementation and how we used these tools will
be presented in the next chapter. Some of the devices that we used in our system
design are highlighted in yellow in Figure 2.19.
All PIC microcontrollers come in various size and functionality. The data process-
ing speed of PIC is 8-bit at a time the data larger then 8-bit should be divided
into 8-bit pieces to be processed. The PIC18 is an ideal choice for new system
designs because of its availability in different pins packages from 18 pins package
to 80 pins package also it is inexpensive and all the required hardware is available
on the one chip. We select the PIC18F67J50 member PIC18 family for the design
of our system due to its low power consumption and USB boot loader which is
really easy to reprogram the device. The PIC18F67J50 is available in the form of
small development board as shown in Figure 2.20 on the previous page from the
Robot-Electronics UK [1]. The details description about the implementation of
this board will be presented in the implementation part.
PIC18F67J50 Microcontroller
As shown in the Figure 2.21 there are multiple ports available with some of the
ports pins are multiplexed with an alternate function from the peripheral features
on the device. Some of the key features of PIC18F87J50 USB microcontroller are
• USB (Universal Serial Bus) V2.0 with low speed 1.5Mb/s and High speed
12Mb/s
• Peripheral Features:
such as IBIS input/output (I/O) Buffer Information Specification model are intro-
duced. IBIS became a standard later on for describing the analog behavior of the
buffers of digital devices. The IBIS model is use for signal integrity analysis such
as transmission line effect, crosstalk and ringing phenomenon on PCB (Printed
Circuit Board). The I/O buffer information is given in the form of voltage-current
(VI) and voltage-time (VT) tables together with a set of rise and fall times of the
drive output voltage and packages parasitic in an IBIS model. The IBIS model of
a digital (I/O) buffer is show in the Figure 2.23.
The V/I characteristics of upper and lower device as depicted in figure are given
in an IBIS model in two different tables each table consists of max and min values
of VI characteristics. The actual VI curve varies between these two set of VI
characteristics.
Applications
• MMIC Design: A Monolithic Microwave Integrated Circuit, or MMIC is a
type of integrated circuit (IC) device that operates at microwave frequencies
(300 MHz to 300 GHz)
• Signal Integrity Engineers
28 Theoretical Background
• RFIC Designers
Key Features
• Complete schematic capture and layout design in the same environment
• RFIC Designers
The list of most common type of sensors that are used in modern automotive are
given below. Some of the sensors are further described in details, such as position
senors and temperature sensor because they used SENT interface which is related
to the work of this thesis.
• Rotational motion sensors
• Temperature Sensors
• Positional/Speed Sensors
• Mass air flow sensors
• Throttle Position sensors
• Linear Hall Sensors TLE4998X
• Manifold air pressure sensor
• Fuel pressure sensor
• Crash sensors
• Airbag side impact sensor
• Exhaust gas Sensors
• Tire pressure sensors
Advantages
• Manufacturing cost is low
• High level EMC low static internal resistance no extra electronic circuitry
need for protection.
Disadvantages
• Due to the coil technology the size cannot be reduced.
• The output signal depends on the rpm unsuitable for quasi-static moments
Applications
These are some application areas in automotive where the position or speed sensor
can be used
• The sensor can be used as an engine speed sensor to measure the crank
shaft-rpm.
• Camshaft sensor
• Needle-motion sensor
The ECT sensor works on the same principle of thermistor. The change in temper-
ature produces a change in resistance that causes a voltage change on the junction.
The ECU sends a reference voltage to the sensor and received the change in volt-
age by a feedback line. ECU determines the temperature of engine using the Vref
and the feedback voltage this process is describe in the Figure 2.27.
A typical engine coolant sensor can measure temperature from -40 to +130Câ◦
degrees. Applications of temperature sensor beside the engine coolant sensor and
32 Theoretical Background
there measuring temperature ranges used in various parts of the automotive system
as follows
• Air-temperature sensor: it is installed in an intake air passage for calculating
the intake air mass the operating range is (-40 to +120Câ◦ ).
• Engine-oil temperature sensor: This sensor is use for calculating the service
interval operating range is (-40 to +170Câ◦ ).
• Fuel-temperature sensor: This sensor is use for calculating the precise in-
jected fuel quantity operating range is (-40 to +120Câ◦ ).
• Exhausted gas-temperature sensor: The measuring range is (-40 to +1000Câ◦ ).
The change in magnetic flux is detected by the hall-effect cell the output signal
from hall-effect cell is then converted from analog to digital in the ADC cell to
stabilize magnetic offset low pass filtering is done in the LPF cell and the output
signal send to DSP unit for signal processing the final output from the TLE4998S
module is a SENT signal based on SAJ2716 standard with the resolution of 16 bit.
2.5 Sensors in automotive 33
Comparison of Automotive
Communication Protocols
This chapter presents the comparative study of some of the communication pro-
tocols that were introduced in previous chapter. In the previous chapter the main
focus was on the protocol description and their features and applications in general
while in this chapter we will try to dig a little deeper to explore the challenges
that demands for a new communications protocols and their features comparison
that makes them feasible for certain applications.
3.1 Overview
Today’s modern cars are the wonderful combination of electronics and mechan-
ics. As computer systems are becoming more pervasive, they are also becoming
integral parts of objects all around us and cars are no exceptions. The vehicles
manufactures are competing for market edge and satisfy their costumers needs
by inserting more and more new sophisticated features and gadgets with lower
cost. They also have to fulfill regulation requirements related to safety, emission,
environment, etc. All these factors somehow contribute in more semiconductor
consumption in vehicles. The insertion of semiconductor eliminate some of the
bulky and complex mechanical and hydraulic system that results in reduction of
over-all system cost, weight and better performance. The inclusion of smart elec-
tronics control units makes modern vehicles a complex distributed system with the
capabilities of better control, monitoring, scalability, ease of configuration, safety
and communication. The intercommunication among these ECUs requires robust
and highly efficient communication interfaces with the ability to satisfy the strict
timing requirements from different subsystems.
Couple of decades ago in vehicles communication among ECUs was mostly done
through point to point interfaces. The side effects of dedicated point to point
interface was the size of wiring harness that ultimately results in increase in cost,
35
36 Comparison of Automotive Communication Protocols
cost per node. It is also one of the reason to have more than one communication
protocols in an automotive system.
Figure 3.2: Automotive protocols comparison based on their data rates [3]
SAE classify in-vehicle protocols into four classes: Class A, Class B, Class C
and Class D. Specific protocol standards exist for each class except Class D. Any
protocol with data rates higher than 1Mb/s comes under Class D.
Class A: The protocols with data rates lower than 10kb/s comes under the
Class A category. As in Figure 3.1 have been shown the automotive electronic
modules associated with the body domain are mostly implemented with low data
rates protocols. Low implementation cost is the most attractive feature of Class
A protocols. But there is lack of globally accepted Class A standard. There are
several Class A protocols but the widely adapted are LIN and Time Triggered
Protocol (TTP)/A [48]. CAN can also be implemented as Class A protocol.
Class B: Class B protocols have data rates between 10kb/s to 125kb/s. The
major uses of Class B protocols in vehicles are for general information sharing, di-
agnosis, instrumentation and body electronics. J1850 [21] adapted by SAE as Class
B standard and has wide acceptance among North American car manufactures.
38 Comparison of Automotive Communication Protocols
J1850 has two versions: 10.4kb/s single wire with Variable Plus Modulation(VPM)
encoding and 41.6kb/s two wires with PWM encoding. While its counter part and
widely accepted among European car manufactures is CAN.
Class C: The data rates ranges from 125kb/s to 1Mb/s. Class C protocols are
mainly used for real time control, powertrain control, engine management, etc. A
more comprehensive list of Class C protocols applications are shown in Figure 3.1.
CAN 2.0 is the most dominate Class C standard protocol. Other Class C protocol
standards are SAEJ1939 and SAEJ2284. These protocols adapt CAN as a base so
medium access and message formate is consistence with CAN. Another feature of
J1939 and J2284 is they target all layers of network model.
Class D: As stated earlier SAE does not specify any standard for the Class D
network. Class D protocol targeted area is multimedia applications. The widely
adapted protocol for such applications across Europe among car manufactures is
Media Oriented System Transport (MOST) [22]. MOST is de-facto standard for
multimedia networks in automotive industry. The alternatives to MOST are D2B
[43] and IEEE1394 [23].
Features Protocols
CAN[24] J1939[25] J2284[26] LIN[27] MOST[28] PSI5[29] PWM[30] SENT[46] TTP/A[31]
Medium Twisted Twisted Twisted Single Optical Single 3 to 4 Single Single
Pair Pair Pair Wire Fiber Wire Wires Wire wire/Twisted
Pair/Opti-
cal
Encoding NRZ NRZ NRZ NRZ Dual Manchester - Falling to NRZ
Phase Encoding Falling
Edge
Media Contention Contention Contention Master- CSMA Point-to- Point-to- Point-to- TDMA
Access Slave Point Point Point
Error De- CRC CRC CRC CRC CRC Parity Bit - CRC CRC
tection
Data 10kb/s- 250kb/s 500kb/s 20kb/s 24Mb/s 125kb/s - 24kb/s- >1Mb/s
Rate 1Mb/s 37kb/s
Data 0-8bytes 0-8bytes 0-8bytes 8bytes 60bytes 10bits - 24bits -
Length
Cost Medium Medium Medium Low High Low Low Low Low
Number 32 32 32 1-15 - 1 to many 1 1 -
of Nodes
Protocol Bus Bus Bus Bus Bus point-to- point-to- point-to- Bus
Type point point point
Function Control Control Control Sensors Multimedia Sensors Sensors sensors Sensors and
and and and and and Actu- and and Actuator
Diagnose Diagnose Diagnose Actuator ator Actuator Actuator
3.3 Features Comparison of Network and Point to Point Protocols 39
Chapter 4
SENT-Protocol
Implementation on two
different platforms
41
42 SENT-Protocol Implementation on two different platforms
Concept building
In this thesis research in the first phase we made a pre-study related to SENT,
PWM and some other commonly use automotive protocols. The aim of the thesis
was clear and understood from the mentioned research questions in chapter 1 of
this document.
4.2 Decisions and method 43
System building
According to the research questions a procedural approach was use for achieving of
our goals. The development of SENT protocol is performed on different platforms
for the better performance and a simulation based approach is use for SENT
signal integrity check. Some of the design decisions were made according to the
architectural design which was created for the system development.
System evaluation
The developed software on two different platforms was tested for better perfor-
mance and less resource utilization with respect to the research questions. The
robustness of the SENT and PWM signals was tested using Spice simulations. The
SENT protocol provides a better solution in term of performance as well as signal
integrity comparing to PWM according to our research questions.
The platforms that have been used for implementation will be described in the
following section.
SENT decoder prototype are depicted in figure 4.2. The system consists of SENT-
transmitter which is a custom developed sensor module on Xilinx Spartan III
FPGA board which is mentioned in section 4.2.4 of this chapter.
The above diagram gives the complete design overview of the system. The Xilinx
FPGA board is used for the prototype of the SENT-transmitter the data are sent
in a serial way. Two wires are used for communication one is common GND and
other is used for serial data transmission. DE2 board provides us the GPIO for
communication with the external devices we used GPIO pin to receive SENT-data
message. The received data are displayed in two ways the first it is displayed in
the Nios II console and another way is to display it on the DE2 board LCD. The
received data-message has been printed the data in both ways. Quartus II was
used to first designed the system in the SOPC builder and then to download it to
the DE2 board for prototyping of the system.
The module can be powered form the USB or in case of external power source
4.5 to 9V to pin 50 and 0V Ground to pin 25 of the board should be given. This
module is compatible to use with the microchip MP-Lab and the program can be
download through boot loader. A character LCD is being used with this board
for displaying results. The complete hardware interface for this implementation
design will be presented in the hardware setup section.
SENT data signal are defined using 10 usec clock tick according to the require-
ment of the thesis work. The encoding scheme and the frame structure of the
SENT data frame are the same as described in chapter 2 section 2.1.5. The out-
put signal of SENT-transmitter module is depicted in figure 4.5 it is measured
with digital oscilloscope.The encoded signal consists of two data messages and one
46 SENT-Protocol Implementation on two different platforms
serial message. The first three data nibbles which are marked by Data1,Data2
and Data3 represents the first message. The second message is represented by
Data4,Data5,and Data6. The details information about serial message are given
in section 4.3.5 of this chapter.
The first pulse is called the calibration or synchronization pulse which is 56 clock
ticks long but there is the possibility of 20 percent variation due to the crystal
oscillator frequency variation in the sensor. According to the requirements of the
thesis we implement one clock tick equal to 10µsec there fore the synchronization
pulse is 560µsec long. The clock frequency variation in the transmitter (Sensor)
can be corrected with this calibration pulse.
Synchronization pulse is followed by status pulse. This pulse is use for the error
code or information about the part number etc. Status pulse is four bits long. The
first two bits are reserved for specific applications the remaining two bits define a
serial message. A complete serial message is 16 bits long and can be completed
in 16 consecutive SENT-data message transmission. The 3rd bit is use for the
start of the serial message and the 4th bit consists of one bit data in one complete
transmission of the SENT-message. The status nibble is depicted in figure 4.7.
Status nibble is followed by six data nibbles which consist of 24 bits data. First
three nibbles of the data nibbles define message1 which consists of 12 bits data
and the second three nibbles define message2.
The checksum nibble is a four bit CRC which is use for diagnosing the error in
48 SENT-Protocol Implementation on two different platforms
the data messages of the data nibbles only. To calculate the CRC the following
polynomial shall be used x4 + x3 + x2 + 1 and the seed value is 5(0101) which is
mentioned in chapter 2 section 2.1.5.
Pause pulse can be used for the equidistant SENT- frames transmission, or con-
stant number of clock ticks. The minimum length will be 12 ticks and the max-
imum length will be 768 clock ticks in our case the length of the pause pulse is
730µsec by using 1 clock tick equal to 10µsec the details description is give in
chapter 2 section 2.1.5.
Sensor module continuously transmitting SENT data frames, it shall start a new
message immediately in case of reset. The length of the data nibble pulse width
can be defined by Data Nibble Pulse Width = (12 + N ibbleV alue) = 12 + M
where M is the nibble value and can have the value from 0 to 15. The minimum
and maximum value that data nibble pulse can have, are lies between this range
12 + 0 = 12 clocks (120µsec at 10µsec clock tick) or 12 + 15 = 27 clocks ticks (
270µsec at 10µsec CT). One complete SENT-transmitted frame and the value of
each nibble are shown in figure 4.6 that is mentioned before.
after calibration pulse its measured period shall be used for adjusting the succeed-
ing pulses period time. A delta factor is used for correction which is the ratio
between the calibration pulse period and the nominal 56 clock ticks in our case
560µsec period.
To calculate the nibble value of each data nibble pulse the SAE J2716 standard
defined the following algorithm.
By using this algorithm we can find the correct values of all the data nibbles pulses
and the CRC pulse. Table 4.1 show the duration of each nibble pulse period and
its binary equal values. These values are further used in table 4.2 in such an order
that we can construct and decode the real data messages that has been encoded
in the SENT-transmitted signal. As we discussed earlier our unit time is 10µsec
so all the data nibbles pulses will be decoded according to this unit.
Table 4.2 show the data message in the decimal notation and this is the real data
that has sent by the sensor-module in an encoded form of SENT-frame. We will
50 SENT-Protocol Implementation on two different platforms
MSB LSB
Data_1 Data_2 Data_3 Data_4 Data_5 Data_6
0011 1110 1000 0111 1101 0000
12 Bits Message 1 12 Bits Message 2
Decimal = 1000 Decimal = 2000
implement this algorithm to find the value of the data nibble and CRC will be
described in details in software design section.
CheckSum=5;
f o r i =1: l e n g t h ( data )
tempCS=data ( i )+CheckSum ∗ 1 6 ;
CheckSum=CRC4Table ( tempCS +1);
end
In one complete SENT transmission we sent 24 bits data in the data nibbles with 1
bit data of the serial message in the 3rd bit of the status nibble. After successfully
capturing 16 frames of SENT protocol we can send 32 bits data. According to SAE
J2716 [46] Standard there is also an enhanced serial message which can provide
larger bandwidth for data transmission but we mainly focused on short serial
message.
c-programs.
SRAM and JTAJ-UART setting is configured in the system library setting of the
project as shown in the figure 4.11. The SOPC system file called .ptf is selected
from the SOPC builder box. All the configuration is make in the Nios-II IDE.
Nios II soft-core is connected with JTAG, on-chip RAM and PIOs through Avalon
bus. SRAM is used to store the instructions of Nios II core during execution of
the program. Communication between the host PC and system are performed by
USB-Blaster cable. Sensor module is connected to Nios-II core through PIO. Nios
II core receive data from the sensor module using PIO pin.
How the system components are configured in the SOPC builder will be presented
as follow.
Nios II Processor: We used the economy core of Nios II (e). There are three
types of Nios II soft-core and they were described in detailed in section 2.2.1 of
54 SENT-Protocol Implementation on two different platforms
chapter 2. The detail about each core has been discussed in chapter 2. Our system
is based on the economy type of Nios II, it optimized for minimum logic usage. it
used 600-700 logic elements as shown in the figure 4.13.
Parallel input output (PIO): PIO is initialized to receive the data from the
sensor module. The parameter settings is change according to our requirement of
capturing the SENT-signal. The edge capture registered is set to falling edge. The
width register is set to 1 bit because the data is coming in serial form. Interrupt
is set to generate IRQ and it is set to edge captured mode so whenever a falling
edge occurred it should generate an interrupt. JTAG UART is initialized and its
width is set to 16 bytes.
Character LCD: To display the data message on the display the character LCD
is institutionalized in the SPOC Builder.
Timer-IP: Two timer-IPs (T imer0 andT imer1 ) are included and configured in
the SOPC builder T imer0 is used for the pulse period time calculation and T imer1
is used to measure time of functions such as printf(), calculation() and delta.
Performance Counter Core: Performance counter core has been added in the
design code profiling. It is a set of counters which keep track clock cycles timing
each section of the code. How it can be use to measure the time of the code section
it will be described in the code profiling section of the this chapter.
4.4 Nios-II Based Prototype 55
Fixed point and floating point numbers have its own advantages and disadvantages
in computer programming such as most of the low-cost embedded processors does
not provide Floating Point Unit (FPU) for representing fractional values in that
case fixed point integer are useful. In general Fixed point processor are cheaper
comparing to floating point but floating point processor provides better precision,
higher dynamic range, and a shorter development cycle.
decimal place in between two bit locations for a given length of data.
Timer: Timer-IP is included in the design from the SOPC builder for measuring
time. The timer-IP is import in the Nios IDE through the system header file
so it communicate through the system file that is generated automatically after
generation and compilation of the quartus design. The timer configuration is
shown in the listing.
#d e f i n e TIMER_START IOWR_32DIRECT(TIMER_0_BASE, 4 , 0 X80000000 )
#d e f i n e TIMER_STOP IOWR_32DIRECT(TIMER_0_BASE, 4 , 0 X00000000 )
#d e f i n e TIMER_RESET IOWR_32DIRECT(TIMER_0_BASE, 4 , 0 X40000000 )
#d e f i n e TIMER_READ IORD_32DIRECT(TIMER_0_BASE, 0 )
Timer 1 f o r time c a l c u l a t i o n
#d e f i n e TIMER1_START IOWR_32DIRECT(TIMER_1_BASE, 4 , 0 X80000000 )
#d e f i n e TIMER1_STOP IOWR_32DIRECT(TIMER_1_BASE, 4 , 0 X00000000 )
#d e f i n e TIMER1_RESET IOWR_32DIRECT(TIMER_1_BASE, 4 , 0 X40000000 )
#d e f i n e TIMER1_READ IORD_32DIRECT(TIMER_1_BASE, 0 )
Interrupt: To capture the falling edge the interrupt is set in the PIO configura-
tion in the SOPC builder design. Whenever a falling edge occur at the PIO an
IRQ is generated. The NIOS II architecture provides 32 non-vectored hardware
interrupts. The processor will jump to a single exception address that is used for
all interrupt and exception processing in the system [41].
In this implementation method we use floating point representation for the calcu-
lation of the data nibble value. Floating-point representations provides a wider
dynamic range programmers do not need to specify the number of digits after the
4.4 Nios-II Based Prototype 57
radix point. Nios II processor have the support for floating point operation. We
developed the algorithm described in section 4.4.3 using floating point representa-
tion to calculate the data nibble values.
Timer read value
− 120
Pulse time = Round
∆
(4.3)
10
The implemented algorithm is shown in the listing, here we defined a function for
the calculation of data nibble values. Delta time is a fraction of timer measured
value and calibration pulse time.
int calculation ( float a)
{
s t a t i c i n t data_value ;
data_value=round ( ( ( a / d e l t a _ t i m e ) − 0 . 0 0 0 1 2 0 ) / 0 . 0 0 0 0 1 0 ) ;
r e t u r n data_value ;
}
d e l t a _ t i m e =( t [ i ] [ 0 ] / 5 0 0 0 0 0 0 0 . 0 ) / . 0 0 0 5 6 0 ;
The delta time is declared as a float to have a support for wide range of memory
space for storing its value. The value that is store at the first element of the array
is use to find the first pulse width. We will explain the complete algorithm that
capture and decode the data messages using the floating point algorithm in section
4.4.7 here we will focus on detection of the synchronization pulse. PIO status are
monitored by an interrupt service routine when whenever a falling edge is detect
at PIO an IRQ request is send to processor the free running timer value is read
at that particular time and it is stored in a variable "T1" this process is shown
in the flowing figure 4.15 with the detection of another falling edge a new IRQ is
send and the timer is read and its value is store in a variable "T2". The difference
"T1" and "T2" gave us the synchronization pulse time, if the synch pulse time is
not equal the synch pulse (560 ∓20 percent) the process repeat for another synch
pulse. All the pulse periods after synchronization pulse is measured in the same
way and stored in array. The described algorithm is for the calculation of the data
nibble values with having tolerance of ∓20 percent clock variation. Which means
our synchronization pulse value shall lies between 448µSec and 672µSec.
floating point unit for calculation. Microprocessor that only support integer sig-
nificant overhead can be encounter to follow floating point both in ROM size and
execution time. To solve this problem fixed point calculation can be done by ex-
ecuting this with inter function. In our second implementation method we used
fixed point arithmetic for the calculation of the data nibble value. To developed
the program using fixed point another algorithm shall be implemented for finding
the data nibble values. To understand how we can implement in the fixed point
arithmetic we will use an example for demonstration. Suppose we have a value
.1234 we can represent this number 1234 in fixed point data type by a scaling
1
factor of 10000 similarly a huge number like 50000000 can be represented 50 by a
scaling factor of 1000000. In general we can scale any small or big number using
the scaling factor by performing two integers operations a multiplication followed
by division. 1.234 = 1234/1000 −→ M/D = 1234/1000 where "M" and "D" in-
tegers scaling factors. To calculate the synchronization pulse time in fixed point
implementation method. We ignored the six zeros of the 50000000 Hz frequency
component and multiplied the resultant value of the synchronization pulse with a
scaling factor of 10000 it is shown in the following code section.
sync_time=( t [ i ] [ 0 ] / 5 0 ) ∗ 1 0 0 0 0 ;
Now the next step is to calculate the delta time and data nibbles values. We
developed a new algorithm that is used to find the data nibbles values using fixed
point arithmetic calculation. The shortest period of pulse is 120µSec and the
longest is 270µSec depends on the nibble values from 0 → 15. To find the ranges
of all data nibbles values we take the mean of maximum and minimum data values
that is
M ean = 12+27
2 = 19.5
with ∓ 20Percent Variation
20
100 × 19.5 = 3.9
rounding this value give us 4
(4.5)
Now the rang of can be defined by subtracting and adding 4 with each data nibble
values as illustrated below in table 4.3. All the values are in µSec 12 + 0 = 12
using 10 µ Sec unit time will give 120 µ Sec and then adding and subtracting 4
respectively produces 124 and 116 the same for all 15 values.
We use these range to developed the calculation function for the fixed point arith-
metic operation instead of using the algorithm that is described in the floating
point section. This solution is more efficient and the memory footprint is low
60 SENT-Protocol Implementation on two different platforms
Data value = 0
Data value = 1
.........
.........
.........
Else IF (Data value ≥ 256 and ≤ 264)
Data value = 15
The hardware and software configuration for this implementation is the same
The process start when a falling edge is detected an IRQ signal is send from PIO
to the processor for execution of ISR routine. In ISR current value of the timer
is read with an IRQ request after reading the timer value the capture register is
reset for the upcoming IRQs if they are on waiting. The value of the timer is store
in a variable "T1". When another falling edge is detected a new IRQ request is
send to the processor and timer value is read at that particular time, the value of
timer is store in another variable "T2". at the occurrences of each falling edge an
IRQ signal is send to the processor. the process is shown in the figure 4.17.
The difference between "T1" and "T2" gave us the pulse time. P ulseT ime =
T 2 − T 1 if this time equal to calibration pulse duration 560µsec then "T2" is
become our "T1" for the measurement of the next pulse time. After getting the
right calibration pulse the difference between the next "T2" and "T1" is measured
4.4 Nios-II Based Prototype 61
and this time the pulse time is stored in an array. Every time we get a new falling
edge our previous time become current time T 2 −→ T 1. The process repeat for all
the nine pulses time measurement. After successfully measuring the time of nine
nibble pulses. The process repeat for sixteen frames as we mentioned in section
4.3 about the frame structure and serial message. The data values are the same
for all the frames. The difference is just in the serial message data so the data
nibbles values is overwrite in the arrays elements every time we measured it for the
sixteen frames. The serial message data is measured after successfully capturing
sixteen frames. After getting all the 16 frames we check the CRC for the data
messages if it matched then message1 and message2 are calculated by rearranging
and shifting of array elements it is shown in the code section below. This shifting
and rearranging is necessary to get the actual encoded data and serial message.
The serial message is calculated by rearranging all the 16 frames for the start bit
of serial message. CRC is calculated for the serial message after matching CRC
serial message value can be find. The complete step by step process is depicted in
figure 4.16.
Data messages, CRC, serial message and CRC of the serial message is display in
the Nios II console and also on the character LCD of the altera DE2 board it is
depicted in the figure 4.18.
taneously.
Sensor module is interface through serial link. Dev-PIC18 board is powered from
the USB cable that is connected to PC. LCD-Module is used for display the data
messages and serial message. LCD is interfaced with the microcontroller. The data
pins of the LCD are connected to board by PORTD of PIC18 microcontroller and
the control pins are connect to to RC2,RC3, and RC4 of PORTC of microcontroller
the schematics diagram is given in the appendix B. SENT-Sensor are connected
to I/O pin number 48 (RB0) of PIC18F67J50 microcontroller. RB0 is an external
interrupt 0 input (INTO). To test our developed software for 8-bit platforms we
design the complete SENT-transmitor (sensor) and SENT-decoder in the ISIS-
64 SENT-Protocol Implementation on two different platforms
Proteus VSM simulator for testing the functionality of the system before we burn
the program on the real chip.
An interrupt service routine is defined for the detection of the falling edge and
read the timer value whenever a falling edge occurred. Three timers are used for
performing different tasks in the program.
Timer0: Timer0 is used in the 16 bit mode for the pulse periods measurement.
The T0CON (Timer0 Control register) register controls all aspects of the mod-
uleÂs operation, including the prescale selection. Timer0 can be accessed in 8-bit
or 16-bit mode. In 16-bit mode it can be accessed as 8-bit TMR0L (lOW byte)
register and 8-bit TMR0H (high byte) register due to the fact of 8-bit architecture
of PIC18. Timer0 used timer flag for overflow condition.
4.5 Prototyping with PIC-Microcontroller 65
Timer1: Timer1 is used for the measurement of the complete program execu-
tion and the time taken by the calculation function to calculate the data value.
Timer3: Timer3 is to create specific delays for the LCD module to function
properly all the timers setting is done from the PIC18 data sheet [32].
Interrupt Service Routine (ISR): In our ISR the "TMR0L" low byte is read
and store it in the variable "time" and the timer0 high byte "TMR0H" is store in
varible "timer1" and irq − status is enable. The following initialization are made
before or main while loop.
Character LCD: L2032 2*20 Character LCD [33] is used to displaying data mes-
sages and CRCs. We modify the fixed point implementation program to include
LCD configuration. Timer3 used for creating the required delay for LCD.
SENT Transceiver simulation: After developing the code in the MPLAB IDE
we build the project and create the Hex (executable-file) for the microcontroller.
The developed algorithm is working in the same way as we described in section
4.4.7 except in this implementation we used the fixed point algorithm on the 8-bit
platform. The simulation of the whole system (SENT-Sensor and SENT-Decoder)
has been performed by using the ISIS-Proteus simulator. The purpose was to test
the functionality of our developed prototype before transferring the design to real
hardware. The screen shot of the ISIS IDE-simulator is depicted in figure 4.20.
66 SENT-Protocol Implementation on two different platforms
One of the task of the this thesis work is to investigate the SENT signal and
PWM signal that how robust is the SENT signal comparing to PWM signal. The
main purpose of this task is to find the highest frequency limit at which PWM
transmit 12-bit data correctly without creating any bit errors. First we will give
a short introduction to the importance of this signal analysis and simulation. At
low frequency data rate there is no need to consider the signal integrity issues, it
comes into action at high data rate or at high resolution data transferred. When
the digital high frequency signal passing through a (channel) wire, the wire ex-
hibits as a transmission line. Due to the transmission line phenomenon the input
signal is subjected to ringing, overshoot, cross talk, undershoot, and rise fall times
increase. These are the majors causes that produces bit errors (ISI-Inter Symbol
Interference) in the transmitted data over a communication channel. Our goal is to
see the effects of these factors which cause signal integrity issues on data integrity
by simulating both SENT and PWM signals with the same data rates. To achieve
this goal we developed a spice model of the whole system for analyzing the signal
integrity issues of both the signals. This chapter described how we modeled the
transmitter, receiver and channel to design the platform for signal analysis.
67
68 Signal Integrity Analysis of SENT and PWM with Simulation
7
Figure 5.2: An electrical equivalent model of an output buffer
5.2 Simulation Overview 69
To study the signal integrity issues of the system, we need to have a model of the
transmitter (Digital I/O Driver), the model of receiver (Digital Buffer) and channel
model. To model digital I/O driver we will used the IBIS model of Spartan-3
FPGA. The receiver will be model with the IBIS Model of M58BW32F [34] 32-bit
flash memory and the channel is model using lumped circuit elements. In figure
5.3 a general overview is given how our system will look.
We have the model of transmitter (Sensor), the model of the receiver and channel
model. We used ADS (Advanced Design System) tool from Agilent Technologies
for the simulation of our system, It is a powerful tool for signal integrity analysis
and it provides the facility for IBIS models simulation. ADS is described in section
2.4 of chapter 2.
Simulation were performed using ADS tool. IBIS models are used for spartan-3
FPGA and M58BW32F [34] 32-bit flash memory devices. Simulation frequency is
set to 200MHz. The purpose of selecting this frequency because it is high enough
to analyze the step edges of the PWM signal because these edges are really sensi-
tive to noise. The main difference between a PWM signal and SENT signal is its
rise and fall times. The SENT pulse have a large rise time (18.5 µ Sec) and fall
time is (6 µ Sec) due to this feature it is more robust to high voltage spikes which
is common in automotive system. We will study the effect of rise and fall time
on both signals. The next problem for the signal integrity is the transmission line
whenever a fast edge signal passed through a transmission line the output signal
will have a long rise-time. The rise time increase due to the losses in the transmis-
sion line. To study this increase in rise time will will model a transmission line,
The ADS components library provides transmission line component for modeling
the transmission line. We use the transient/convolution simulation mode for the
analysis. We use two memory chip as a buffer. The complete simulation setup for
the transmitter (Driver), receiver (Buffer) and channel is given in figure 5.4.
70 Signal Integrity Analysis of SENT and PWM with Simulation
5.3 Signal integrity analysis of SENT and PWM signals 71
As we see from our simulation setup in figure 5.4 there are different modules that
build the whole setup which are describe as follows:
Signal generator: The input PWM and SENT signal are generated by using the
”V tBitSeq” (Voltage Source, Pseudo Random Pulse Train Defined at Continuous
Time by Bit Sequence) which is available in ADS. VtBitSeq is used for transient
simulations. BitSeq allows you to vary the waveform of a pulse. The frequency is
set to 200MHz and the rise and fall time can be change according to the require-
ment for PWM and SENT signal in the VtBitSeq edit menu.
Spart-3 IBIS-Model: PIN 126 of spartan-3 FPGA is used for modeling the
driver. It is called SST L18 − I (Stub series terminated logic 1.8V) single ended
standard I/O. The pullup powerclamp network is connected to 1.8V VDD and the
pulldown and groundclamp network is connected to 0V Vdc. The input signal is
applied at terminal T of the IBIS-Model.
Channel Model: To model the transmission line we use lumped circuit elements.
The total length of the transmission line is set to approximately 5 inches from the
driver to the memory chip. Which is model with the Transmission line library
components in ADS
Buffer Model: To model the receiver we use the IBIS Model of M58BW32F
32-bit flash memory.
We run a number of simulation to see the affect of transmission line losses on the
rise and fall times, and how it can effect the signal waveform all these outcome of
the simulation will be presented in the next chapter.
Wire Model: The transmission line has been model using the lumped circuit
elements network. The value of the capacitance and inductance is set according to
the Twisted wire data sheet [35]. We used two branch of lumped network which
represents 2 meters long twisted pair cable.
frequency. Our goal is find the maximum data rate of the PWM signal, and to
check the maximum PWM data rate at which it performance is assured and there
is no ISI occurred. To performed this analysis we need to consider the effect of
wires which mainly contribute in the data lost if it is not terminated properly. A
complete SPICE-Model is design in the ADS as mentioned in section 5.2 of this
chapter for analyzing the effects of these parameters on the signal integrity. To
achieve our goal we made the complete transceiver SPICE-Model that is described
in section 5.2 of this chapter. As we described earlier that the transmission line
effects occurred at high frequency there fore we select different data rates to find
the critcal data rate at which PWM faced ISI problem which intern creates bit
errors. The choices that we made for selecting the simulation setup and the de-
tails explanation about how we got the results are presented in section 5.2. To
make our design simple three data nibbles of the SENT signal are considered for
data encoding which represents 12-bit data. The same 12-bit data will be used
for both signals. A number of simulations were performed to see the effects of
different parameters of the design system on both signals PWM and SENT. First
we will present the obtained simulation results for both SENT and PWM signals
and after presenting the results we will describe the conclusions from these results:
Figure 5.5 show the simulation result of SENT signal. The red graph with the
markers position represents the input SENT-signal which is a complete three data
nibbles message. In which the first data-nibble start time is 9.426nsec and the last
data-nibble stop time (marker 2) is 319.5nsec. While the output SENT signal is
shown in the blue graph which is slightly delayed the start time is 14.03nsec and
stop time is 325.0nsec. These values are also given in the table 5.1. Equations 5.1
and 5.2 is used for calculation in the table 5.1.
Pulse period = Stop time of the pulse - Start time of the pulse (5.1)
5.3 Signal integrity analysis of SENT and PWM signals 73
Error in pulse period = Pulse period of output pulse - Pulse period of input pulse
(5.2)
The rise-fall times increase occurred in the output signal due to the transmission
line losses which is shown in figure 5.6.
When rise-time is equal to the bit-period then the Inter Symbol Interfere (ISI)
occur which destroy the integrity of the data. ISI occurred in a long bits of stream
as (11111110111111) where after many 1s one 0 occurred and the actual voltage-
level of this 0 − bit depends on the previous bits voltage-levels, due to the rise-fall
times increase all bits voltage-levels overlapped which create bit-errors.
The effect of transmission line on rise time of the PWM pulse are depicted in figure
5.4 SENT and PWM signal simulations at frequency range ( 1KHz-
250MHz) with different data rate (10-Bits-100-Bits) 75
5.8.
The representation of PWM signal at frequency 1KHz and the data rate is 100
bits is depicted in figure 5.11. The output signal is the same as input with no bit
76 Signal Integrity Analysis of SENT and PWM with Simulation
error.
Figure 5.11: Frequency is 1KHz and data bits are 100 bits
The representation of PWM signal at frequency 10KHz and the data rate is 100
bits is depicted in figure 5.12. The output signal is still the same and there is no
bit error occurred yet.
Figure 5.12: Frequency is 10KHz and data bits are 100 bits
The representation of PWM signal at frequency 50KHz and the data rate is 10
bits is depicted in figure 5.13. There is slightly ringing effect occurred at 50KHz
but the signal can be decode correctly with the right information.
5.4 SENT and PWM signal simulations at frequency range ( 1KHz-
250MHz) with different data rate (10-Bits-100-Bits) 77
The representation of PWM signal at frequency 1MHz and the data rate is 10 bits
is depicted in figure 5.14. The effect of ringing start at 1MHz frequency. Which
creates overshoot and undershoot at the edge of the pulse transition as depicted
in figure 5.14.
The representation of PWM signal at frequency 10MHz and the data rate is 10 bits
is depicted in figure 5.15. At 10MHz the ringing is high also the ISI occurred which
creates bits errors and there is some information lost occurred at this frequency.
The input signal is not matching with the output signal due to the change in the
pulse period time.
78 Signal Integrity Analysis of SENT and PWM with Simulation
The representation of PWM signal at frequency 50MHz and the data rate is 20
bits is depicted in figure 5.16. At 50MHz the output signal is changed due to the
ringing and ISI effects, the original data which is encoded in the input signal is
completely lost now since the periods of the pulse changed.
The representation of PWM signal at frequency 100MHz and the data rate is 20
bits is depicted in figure 5.17. At 100MHz the output signal completely changed
due to the ringing and ISI effects, the original data which is encoded in the input
signal is completely lost now since the periods of the pulse changed.
5.4 SENT and PWM signal simulations at frequency range ( 1KHz-
250MHz) with different data rate (10-Bits-100-Bits) 79
The representation of PWM signal at frequency 150MHz and the data rate is 50
bits is depicted in figure 5.18. At 150MHz the signal is distorted due to ringing
and transmission line effects. Also the shape of the signal is changed.
The representation of PWM signal at frequency 200MHz and the data rate is 50
bits is depicted in figure 5.19. At 200MHz the signal is completely distorted due
to ringing, ISI and transmission line effects.
The representation of PWM signal at frequency 250MHz and the data rate is
10 bits is depicted in figure 5.20. At 200MHz the signal is completely distorted
due to ringing, ISI and transmission line effects. The markers position is used to
measured the period of the input and output signal. It is clear from the following
figure that PWM is not suitable for high data rates.
The representation of SENT signal at frequency 1KHz and the data rate is 100
bits is depicted in figure 5.21.
Figure 5.21: Frequency is 1KHz and data bits are 100 bits
The representation of SENT signal at frequency 100KHz and the data rate is 100
bits is depicted in figure 5.22.
5.4 SENT and PWM signal simulations at frequency range ( 1KHz-
250MHz) with different data rate (10-Bits-100-Bits) 81
Figure 5.22: Frequency is 100KHz and data bits are 100 bits
The representation of SENT signal at frequency 50MHz and the data rate is 100
bits is depicted in figure 5.23.
Figure 5.23: Frequency is 50MHz and data bits are 100 bits
The representation of SENT signal at frequency 150MHz and the data rate is 100
bits is depicted in figure 5.24.
Figure 5.24: Frequency is 150MHz and data bits are 100 bits
The representation of SENT signal at frequency 250MHz and the data rate is
100 bits is depicted in figure 5.25. According to SENT protocol data encoding
scheme even at such a high frequency the data are still secured, since we are only
82 Signal Integrity Analysis of SENT and PWM with Simulation
interested in measuring the data nibble period between the two consecutive falling
edges of the SENT signal. It does not matter if the signal is distorted due ringing
or transmission line effects as long as the period between the two falling edges is
the same.
Figure 5.25: Frequency is 250MHz and data bits are 100 bits
The following table described the outcome of simulation for both PWM and SENT
signals:
SENT PWM
When the data are decoded in the SENT PWM is a three wires digital system, where
approach then the existing noise voltage the spark type noises are inductively cou-
pulses do not have any effect on the sig- pled to the data line and produces edges at
nal integrity since it is time critical sys- the wrong places which produces ISI prob-
tem. Also SENT protocol has ∓20 percent lem and destroy the signal integrity.
transmitter clock compensation.
The rise-fall times has been increased The main cause of this degradation in rise-
as mentioned before. This rise-fall time fall times is the high frequencies compo-
degradation is due to the losses in the nents (step-edges of PWM) of the signal,
transmission line. Which produces inter- which is more attenuated more then the
symbol interference (ISI) which cause sig- lower frequency components
nal integrity issues.
5.5 Conclusion of the simulations 83
While in case of SENT the integrity of data In a typical 10-bit system one bit is a single
is dependent on time not on the voltage bit is represented by 4mV, which in 12-bit
levels. Also the availability of transmit- system a single bit is represented by 1mV,
ter clock variation compensation which en- due to the noise voltage pulses in auto-
sured the integrity of data. motive system the 4mV presents a severe
problem. So to use PWM for 12-bit data
transmission 1 bit is equal 1mV which can
easily be corrupted due to the noise volt-
ages.
According to the difference in time due While this 1.2 nsec delay can cause the
to the rise-fall time increase which cause PWM data pulse edges at the wrong
1.2nsec difference in the pulse width it does placed which intern produce bit error.
not affect the SENT data because of the
compensation feature of the SENT signal.
While SENT provides a high resolution The resolution of the PWM depends on
comparing to PWM. According to the the Fclock and Fpwm Resolution =
specification of the SENT 24-bits data can Log2 (Tpwm /Tclock . The PWM works fine
be transmitted by data nibbles while 8 bit upto 10-bit resolution but for the data
can be transmitted in each serial message rates higher then 10-bit its resolution de-
of the SENT frame. So a total of 32-bits grades.
can be transmit in less than 1 msec.
Higher resolution more then 16-bits can be If 32-bits are transmit with PWM a either
transmitted with TLE4998 which is a linear a very long pulse period will be need or
hall sensor described in the first chapter. a very high resolution which is impractical
with today high speed MCU.
From the depicted figures we saw that the Every transmitter has a source impedance
rise-fall times (at high frequencies com- Zs also an inductance Lthat could lead to
ponents) ringing occurred. It effects the ringing and intersymbol interference ISI
PWM signal due to the encoding mecha- as we saw in the figure at the high frequen-
nism of the PWM where each bit is rep- cies components of both signals. Ring-
resented by some voltage level as 4mV in ing can be reduced by the rise-time of the
case of 10-bit system and 1mV in case of input signal wave-form. By reducing the
12-bit system. The signal become stable high frequency components of the input
after some time whenever the signal level less energy is coupled into the tank circuit
changed which may cause bit error to cause the ringing. Which is problem in
PWM case
SENT used two wires one is common GND In case of PWM we use three wires power,
and other wire is use for data as well as GND and data in case of three wires system
power. we need an extra power supply. So the
power consumption is more and also the
wiring cost.
In digital system jitter are produce when The deviation in the clock frequency due to
rising and falling edges are occur at time the bad crystal oscillator cause these prob-
that is different than ideal time . Or jitter lem (jitter and rise-fall time increase) fre-
produced due to the misalignment of rising quently so we need a more precise crystal
and falling edges. Due to jitter the problem and it is also expensive but SENT can have
the signal integrity are effected. But in ∓20 percent tolerance rate that can solved
case of SENT protocols we measured data this problem.
between the two falling edges which solved
this problem
84 Signal Integrity Analysis of SENT and PWM with Simulation
Cross talk also occurs in the lossy transmis- In the case of the capacitive coupling ef-
sion line.Cross talk happens between the fect, the moving edge on the aggressor
signal and return paths of one wire and net induces positive-going current pulses
the signal and return paths of another wire. on the victim net in both the forward and
Cross talk produces due to the capacitive reverse directions. while inductive coupling
or inductive coupling. is opposite to capacitive coupling.
Inductive coupling produces switching As we designed the transmission line with
noise and ground bounce, Inductive cou- the lumped elements all these elements
pling is more dominated then the capaci- make some contribution in the SI problems
tive coupling. which are more effective at high frequency.
In SENT case two signals share the same To ensured a secure high data rate with
wire. Low susceptibilty is required for PWM we need to have more then one
SENT protocol against EM I so we do not channel (parallel-wires) should be used
need shield or twisted pair cable reduce which increase the cost as well as more
cost for wiring. EM I problems.
From this discussion and simulation results we conclude that SENT provide a best
solution in either case comparing to the conventional PWM. The goal is achieved
in this task by simulation and analyzing the physical layer comparison of both
PWM and SENT signals.
Chapter 6
This chapter will describe all the experiences and performance analysis that has
been made during the implementation and simulation as we mentioned in the pre-
vious chapters. The aim of this thesis work was to compare SENT-Protocol with
other serial communication protocols for an alternative best solution in terms of
cost, performance, execution power and robustness for an automotive high data-
rate communication. We will describe the comparison among all the implemen-
tation designs and simulations; also we will perform the functional testing of our
design prototypes. We divide our thesis work into tasks as describe in chapter 1
section 1.3. We will discuss the experience gained during completion of these tasks
for achieving our thesis goals.
Another feature of SENT is studied which is its ability for high resolution data
transmission which can replace the lower-resolution methods using 10-bit ADC
85
86 Results and Discussion
and PWM techniques and can provides a low cost alternatives to CAN and LIN
protocols in some specific applications of the automotive system. It is seen that if
we use PWM or ADC for high resolution data transmission, how the data integrity
can be affected this topic will be describe in detail in section 6.5 of this chapter.
By using SENT we can also reduce the wiring cost because SENT interface uses
two wires one is common GND and another wire is used for Power as well as data
transmission.
The aim of this task was do a comparative study of the communication protocols
that are used in the automotive industry nowadays. We explore the challenges that
demands for new communications protocols and their features comparison that
makes them feasible for certain applications. The embedded systems in vehicles
are divided into different domains: according to their functionality, architecture
and the constraints: powertrain domain, chassis domain, body domain, telematics
domain and safety domain which are described in section 3.1 of chapter 3. The
communication among the ECUs of these domains interconnect with different sen-
sor modules require a robust and highly efficient communication interfaces with
the ability to satisfy the strict timing constrains from the different subsystems,
also having the mechanism for data integrity. To fulfill these requirements a num-
ber of communication protocols were developed by different vendors according to
their needs for specific task, these standards are divided into two main categories
namely point-to-point and network protocols.
Networks protocols are further subdivided into classes described by SAE (Soci-
ety of automotive engineer) according to their data rates versus cost which are
depicted in figure 3.2 as mentioned earlier in detail in section 3.2 of chapter 3.
Why different types protocols exist? To answer this question we made a complete
features comparison and the feasibility for specific applications of networks and
point-to-point protocols which is described in table 3.1 section 3.3 of chapter 3.
Networks protocols effectively reduce the amount of cabling which reduce cost and
easy to do the maintenance of the system. But for a standalone system or when
one sided data traffic is require the use of network protocols is waste of band-
width and resources so point-to-point protocol is the best solution for this kind of
scenarios. Due to these different requirements and the aim for reducing cost the
manufactures of automotive industry are keep looking for new protocols they are
base on network and point-to-point protocols.
6.3 Design prototypes comparison implemented with fixed-point and
floating-point 87
To get more accurate results a performance counter core has been added to design
in the SOPC builder. Performance counter core is a set of counters which keep
track of the clock cycles timing different section of the code.There are three default
counters unit in the performance counter core for profiling purpose and can be can
be increase according to the requirements if more sections of the code need to be
examined for optimization purposes. The details explanation about code profiling
and performance counter is given in section 4.4.6 of chapter 4. The performance
counter measured the number clock cycles each section of the code takes. To
measured the time in seconds we used the formula T = n F1 which give us the time
in seconds ”n” represents the number of clock cycles each code section takes to
execute.
To measured the CPU utilization in percentage we need to find the CPU idle
88 Results and Discussion
time when it is waiting for the interrupt and doing no operation. To do so our
software design algorithm consists two idle loops in both fixed and floating point
implementation designs one for synchronization pulse capturing and another to
captured all the nine nibbles of the SENT frame. it is explain in detailed in
section 4.4.6 of chapter 4. The formula used for finding CPU utilization is given
as:
Idle Time
Percentage Idle Time = × 100(6.2)
Total Program Execution Time
By using values from table 6.2 and table 6.1 into these equation we measured the
CPU utilization in percentage of both designs which is given in table 6.2. It is clear
that the floating point design utilize more CPU then the fixed point design due to
the fact that floating point arithmetic need more processor overhead because of its
internal complex algorithms. Most of the modern processor consist of a separate
unit called co-processor for floating point operation. So designing with floating
arithmetic processor overhead significantly increased.
The resource usage of both designs is depicted in figure 6.2 and the description is
also given in table 6.3. It is the program linking memory footprint with reduce
device driver option and without reduce device option that can be selected in the
project properties of Nios II IDE for optimized C-code generation. The memory
foot print play an important role in the system design. The designers should
always focus to make sure that the design is optimized for less memory usage
because high memory foot print increase the system cost, While fabricating the
system will need more CMOS logic gates which means more silicon and it can
significantly increase the cost of the system due to the price of the silicon. It is
obvious from the results that the fixed-point design is more efficient in execution
power with less memory footprint comparing to floating point implementation
6.4 Design prototypes comparison implemented on an 8-bit and a 32-bit
platforms 89
design. The goal of implementing with the fixed point arithmetic is to make the
design prototype more efficient and reduce the resource utilization which was our
goal that is achieve in this task.
CompleteCalculation
Idle Time Total Idle
Implementation Idle Time % CPU
Design 2nd Program Function Utilization
1st Time
Execution Time
PIC18 with
0.68msec 1.7msec 2.38msec 64msec 80usec 96.28%
Fixed Point
The source code is compiled in MPLAB IDE and executable Hex-file is generated
by building the project,to be burned on the targeted board. The size of the
Hex-file is the actual memory footprint of the source code. PIC18F67J50 provide
128KBytes of flash program memory that can be reprogrammed. The execution
time taken by the complete program and calculation function are measured the
help of time1. It is obvious from the results that the best solution for the design
of SENT-decoder is Fixed-Point implementation design on the 32-bit platform
among all the designs prototypes. But if we consider interms of cost then the
6.4 Design prototypes comparison implemented on an 8-bit and a 32-bit
platforms 91
8-bit platform provide a convenient and efficient design. Table 6.4 only describes
the execution power of the 8-bit platform based design, the other two designs were
described in table 6.3. The comparison resource utilization of the design prototypes
are depicted in figure 6.3. Also table 6.5 describe the resource utilization for PIC-
Based design.
The aim of our compassion among these three different implementation designs
was to find an optimal solution for designing SENT-decoder prototype. As we
see the FPGA base design will be more effective because of the 32-bit NiosII
architecture but the cost is high comparing to the PIC prototype. One of the
most important aim was also to reduced the memory footprint and we try to
optimize the code using the fixed point algorithm technique. It was due the fact
that memory footprint represents the actual physical IC chip size it means high
footprint will required more logic elements (LEs) or memory elements which will
required more silicon and it will significantly increase the cost. By comparing
the design prototypes of an 8-bit platform and a 32-bit platform interms of cost,
resource utilization, execution power and power consumption we reached to the
92 Results and Discussion
conclusion that the 8-bit platform provide a more convenient and best solution for
the design of SENT-Decoder. The aim was to compare an 8-bit platform prototype
with a 32-bit platform as described earlier which was our goal that is achieved in
this task.
95
96 Conclusions and Future Work
links are more immune to noise. There fore more and more sensors are going to
convert to digital interfaces. Many sensors can be pack together in a single module
which communicate with the ECU through digital channel this sensor fusion can
reduced the wiring cost and improve the data integrity. SENT is digital interfaces
and having the capability of high resolution so a sensor fusion prototype can be
designed using two or three sensor to share the same signal wire. SENT two signals
share the same wire this can help for future sensor fusion.
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SENT-Decoder CRC
Implementation
The CRC checksum can also be implemented by using 16 element array [46]. This
103
104 SENT-Decoder CRC Implementation
For Checksum with an extra zero "0" value the following MATLAB algorithm shall
be implemented.
CheckSum16=5;
f o r i =1: numNibbles
CheckSum16 = b i t x o r ( u i n t 8 ( 0 ) , u i n t 8 ( c r c 4 _ t a b l e ( CheckSum16 + 1 ) ) ) ;
end
Appendix B
Schematics Diagrams
In this section we present the schematic diagram B.1of the SENT-Transmitter and
SENT-Receiver modules. The system is design for testing purpose. ISIS-Proteus
7.10 simulator has been used for testing before transferring the design to real
hardware (PIC18 Microcontroller).
105
106 Schematics Diagrams