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Analog Integrated Circuits & Systems

Phase Locked Loop (PLL)

ELC401A – Fall 2017
Dr. Ahmed Nader

Department of Electronics and Communications Engineering

Faculty of Engineering – Cairo University

 PLL Dynamics
 PLL Linear Model
 Stability
 Settling behavior
 Phase error
 Disadvantages of Type-I PLL

 Charge Pump PLL (Type-II)

Phase Detector Linear Model
Φin + Φe VPD


• VPD=KPDΦe=KPD(Φin – Φout)
• KPD: gain of phase detector (V/rad)
VCO Linear Model

• ωout = ω0 + KVCO .VCONT VCONT Фout

• ωo is the free running frequency
• KVCO: gain of VCO [rad/(sec.V)]

Without loss of generality, we can

assume initial phase=0

The quantity of interest for the linear model is the small

variation around steady state solution.
PLL Linear Model
φ𝑜𝑢𝑡 𝐾𝑉𝐶𝑂
𝑠 =
𝑉𝑐𝑜𝑛𝑡 𝑠

𝑠 = 𝐾𝑉𝐶𝑂

= =

 Type-I PLL (open loop TF has one pole at the origin)

 First order LPF results in 2nd-order PLL
 Vcont(s) represents the closed loop response
𝜔𝑜𝑢𝑡 𝑉𝑐𝑜𝑛𝑡 𝑉𝑐𝑜𝑛𝑡
𝐻 𝑠 = 𝑠 . 𝑠 = 𝐾𝑉𝐶𝑂 𝑠
𝑉𝑐𝑜𝑛𝑡 𝜔𝑖𝑛 𝜔𝑖𝑛
Settling Phase Error Behavior



Example: Calculate the change in phase error if a

Type-I PLL experiences a phase step Δφ and a frequency step Δω.
Is The PLL Stable?

• PLL is 2nd-order system

• PLL may be stable or unstable (oscillatory)
depending on phase margin
• Phase margin is determined from linear model
of PLL in frequency-domain
• Stability affects phase error, settling, jitter
• Find damping (phase margin) using system
simulations (for example SIMULINK).
PLL Stability

Bode Plot
Type-I PLL Poles

 Trade-offs
Phase error
• ωLPF is reduced to minimize ripples on control
voltage (quality of the VCO output signal)
• KPD.KVCO is increased to reduce phase error
• If ζ (damping factor) < 1 (underdamped and poles
are imaginary), step response is given by:
Step Response of a 2nd Order System

Decay Time Constant = 1/(ζωn)

For ζ < 0.5, there

are large overshoots
Example: Settling Vs. Noise Filtering

Assume ζ=0.7
Effect of VCO Jitter (Phase Noise)

• Attenuation at low frequencies

• PLL acts as a high-pass filter for VCO phase noise

What Does PLL Bandwidth Mean?
• PLL acts as a low-pass filter with respect to the
reference (input frequency)
• Low-frequency reference jitter (phase noise) is
passed to the VCO clock.
• High-frequency reference jitter is rejected.
• Bandwidth affects settling and jitter.
• Optimum loop BW depends on the application.
• What happens if a divider is used in the feedback?
Lock Acquisition
 Acquisition (capture) range of type-I PLL is ~ ωLPF
 The loop locks if the difference between ωout and ωin is less
than ωLPF (trade-off between reference jitter and acquisition range)
 A wide acquisition range is needed to cover the expected PVT
variations of the VCO (can be achieved using Frequency
Detector FD).
Disadvantages of Type-I PLL

 Suffers from tough trade-offs between phase error

and stability.

 Suffers from tough trade-offs between settling

speed and ripple on the control voltage.

 At frequency offsets compared to ωLPF, the PLL

begins to lose lock with the reference.
Thus, acquisition range may not be adequate with
tough trade-off with input jitter.