Performance Enhancement in Al0.3Ga0.

7N/GaN
HEMT based inverter using MOSHEMT
Soumya Prava Nayak, Pradipta Dutta, S K Mohapatra
School of Electronics Engineering
KIIT University
Bhubaneswar, India-751024
nayak.soumya5@gmail.com, pduttafet@kiit.ac.in, sushanta.mohapatrafet@kiit.ac.in

Abstract— In this work, a 2D structure of AlGaN/GaN HEMT In this paper, we have given the description of the devices in
is designed and an inverter is implemented to investigate the section II, the analysis of the obtained results is presented in
switching characteristics of the device. The issues of high on- section III and the logic circuit implementation using
resistance of HEMT due to the occurrence of current collapse MOSHEMT in section IV.
causing poor charging and discharging of the device, making it
undesirable for switching circuit operations are justified through
the voltage transfer characteristics (VTC) of the inverter circuit. II. DEVICE DESCRIPTION AND SIMULATION METHODOLOGY
Among the methods of reducing the on-resistance of the device, the
recessed-gate structure is analysed. Further in order to prevail
over the gate leakage current and high on-resistance the inverter
based on metal oxide semiconductor high electron mobility
transistor (MOSHEMT) is compared with the inverters designed
with the conventional structure and the recessed-gate structure of
HEMT. An efficient inverter with better on-off switching is
obtained on improvising the HEMT to MOSHEMT. The Power
Delay Product of the inverter is also calculated and its value
obtained is 8.287fJ/mm. In addition to the inverter, functionality
of some more logic circuits is also presented through proper dc and
transient analysis.

Keywords— MOSHEMT; on-resistance; VTC; Power delay Fig. 1. Basic AlGaN/GaN HEMT Structure
product; HEMT.

Fig. 1 shows the basic AlGaN/GaN HEMT followed by the

structural depiction of MOSHEMT[5] as shown in Fig. 2. The
I. INTRODUCTION
structural blocks common to both the structures are SiN
Recently III-V material based HEMT device is gaining wide passivation layer, AlGaN layer and GaN layer. The only
attention among its counterparts because of some of its highly difference comes here is from the inclusion of HfO2 oxide layer
desirable properties. Due to the involvement of wide bandgap of thickness 20nm. Both in Fig. 1 and Fig. 2, the height of
materials, these devices exhibit good temperature stability, AlGaN is taken as 25nm, height of GaN is taken as 300nm, the
higher breakdown potential and low switching losses [1]. source and drain lengths are confined to 1μm, and the gate length
In the area of CMOS technology, tremendous amount of scaling of 100nm is taken.
has been considered leading to some drawbacks to the device
performance and in order to follow an alternate approach to the
conventional Si devices, III-V HEMTs are chosen for the very
purpose [2]. Several material combinations providing higher
electron mobility in the channel has already been used like InP,
which is having almost twice the electron mobility as GaN [3].
But it is still behind GaN in the race because of the better
thermal and breakdown properties of the latter.
In other words, GaN HEMTs are more suitable for high voltage
operations as a switching device. In our work we have used the
enhancement type GaN HEMT device to implement an inverter, Fig. 2. MOSHEMT Structure with HfO2 oxide.
and the issue of high on-resistance has been solved taking
appropriate methods [4].

978-1-5386-1703-8/17/$31.00 ©2017 IEEE

 The schematic configuration of AlGaN/GaN HEMT based
inverter is shown in Fig. 3. In the circuit of inverter, the supply
voltage Vdd is taken as 1.5V, the drain node of HEMT transistor
hemt2 and source node of hemt1 are connected together to the
output. The gate and drain nodes of hemt1 are connected
together to Vdd. The gate of hemt2 is connected to the input
voltage. The load capacitance of 3fF is taken as the load
capacitor. After analyzing the inverter using the conventional
HEMT in Fig. 1, the device is modified to improve some
important functional characteristics of the inverter circuit.
Fig. 3. Schematic of HEMT based inverter.
All the simulated results are obtained using simulation
software TCAD Sentaurus. The tool used is Sentaurus Device to
simulate the electrical behavior of the device by solving the set
of diffusion and transport equations in accordance with
boundary conditions and other physical parameters. The
physical models included are Drift Diffusion Model,
Thermodynamic Transport Model, Non Local Tunneling Model
and Thermionic Emission Model. In our work, because of
HEMT being the provider of electrons (the majority carriers),
two similar physical devices are used to carry out a DC and
transient mixed-mode simulation of the inverter, shown in Fig.
3 through Sentaurus Device [6].
III. RESULTS AND ANALYSIS
After examining the individual characteristics of the
conventional HEMT, the DC Voltage Transfer Characteristics
(VTC) of the inverter using the device in Fig. 1 is obtained as
shown in Fig. 4.
Fig. 4. Voltage Transfer Characteristics of conventional HEMT at Vdd =1.5V.
From the Fig. 4, the dynamic range of output voltage is found
to be very small, suggesting undesirable functioning of the
inverter. At VIN = 0V, the discontinuity in VTC curve is
occurring because of the current collapse phenomenon in
HEMT, which is one of the major issues in HEMT devices. The
sudden degradation in drain current at higher voltage causes
current collapse [7]. Because of the accelerated charges in
2DEG channel the current collapse phenomenon occurs leading
to trapping of charges at the interface of passivation, resulting
in depletion of the 2DEG channel, even when the device is in
on-state[8].
The smaller output swing in Fig. 4 is due to the improper
discharging of the output capacitor through the HEMT device,
highlighting the high on resistance of the device.
Fig. 5. Voltage Transfer Characteristics Comparison for different HEMT
structures. Vdd = 5V
Our work has focused on the implementation of inverter using
MOSHEMT by reducing the on-resistance. Some other features
such as noise margin has also got improved with MOSHEMT.
Noise margin (NM) is the noise tolerances for digital circuits
specifying the allowable variation in signal levels while getting
transmitted from the output of one logic gate to another. More
the noise margin, better the noise immunity of the circuit [10].
NML = VIL Ȃ ܸOL (1)
NML = VOH Ȃ ܸIH (2)
Using (1) and (2), NM of the circuit has been analyzed.
Fig. 5 shows the effect of back-barrier on VTC curves of
inverter, and comparison with MOSHEMT based inverter [9].
The inclusion of In0.1Ga0.9N back-barrier reduces the parasitic
resistance of the device and the improved transfer characteristic
in Fig. 5 is justifying the same. But on using MOSHEMT based
inverter, the suppression of current collapse effect along with
the improvement in the device characteristics is obtained. Thus
from the figure we derived the improved noise margin through
MOSHEMT based inverter.
From the previously published works, there has been validation
to the high on-resistance and current collapse phenomenon in
HEMT devices.
 Where ‫ڴ‬PHL is the time delay between half of the voltage level
of the rising input and the half of the voltage level of the falling
output. ‫ڴ‬PLH is the time delay between the half of the voltage
level of falling input and the half of the voltage level of the
rising output[11].
The value obtained for ‫ڴ‬P is 50 picoseconds. Following the
calculation of time delay, average power dissipation including
both static and dynamic power, has been calculated. The static
power dissipation came out to be negligible because of very
small value of steady state current or the leakage current. As the
input and output are periodic, the dynamic power dissipation
has been found using:

೅
‫׬‬బ ሼᖮ௏ሺ௧ሻǤூሺ௧ሻሽ
Fig. 6. Analysis of output voltage with input voltage for MOSHEMT based Pavg = (4)
inverter adopting gate recessed structure. Vdd = 5V. ்

Among the techniques of reducing the parasitic resistance of the Here, v (t) is the output voltage waveform and
device, gate recessed structure furnishes higher current density ௗ௩ሺ௧ሻ
with reduced on-resistance [10]. The MOSHEMT is then I (t) = ‫ܥ‬ (5)
ௗ௧
modified through recessed gate electrode, that is, keeping gate
to channel separation as 12nm and the corresponding inverter
Using the above expressions (4), (5) from [11] and adding the
VTC is compared with that of the MOSHEMT inverter as
value with the static power dissipation, the total power
shown in Fig. 6.
dissipation came out as 165.75nanoWatt/mm. With the
From the transition slope of the curves shown in Fig. 6, it is
obtained values of delay time and power dissipation, the power
seen that gate recessing to MOSHEMT is providing better
delay product is calculated as 8.287fJ/mm.
transition characteristics but improved noise margin is obtained
with MOSHEMT and higher noise immunity is one of the IV. LOGIC CIRCUIT IMPLEMENTATION
desired conditions for RF applications [11]. Thus, MOSHEMT
inverter is having moderate transition slope with better noise
margin as compared to the inverter using gate recessed
structure.

Fig. 8. Schematic of (a) AND logic circuit and (b) OR logic circuit.

In Fig. 8 the schematic of AND and OR logic circuits are

Fig. 7. Transient Analysis of MOSHEMT based Inverter.
shown, which we have simulated using Mixed Mode simulation
After examining the dc characteristics of the inverter circuit, we of Sentaurus TCAD [5]. As shown in (a) and (b), we have taken
have shown the transient analysis result in Fig. 7. In this figure, the load resistance of 1MŸ across which we have obtained the
we have observed that at the falling edge of the input, outputs.
the output is rising, showing the basic inverter operation.
Further, from Fig. 7 the average propagation delay, ‫ڴ‬P, is
calculated using:

ሺᎄ୔ୌ୐ାᎄ୔୐ୌሻ
‫ڴ‬P = (3)
ଶ

Fig. 9. AND logic circuit implementation using MOSHEMT. Red colour, Green
colour and Blue colour waveforms are input1, input2 and output respectively.
As per the basic operation of AND logic, whenever both the
inputs are logic high the output will come as high. In Fig. 9, at
time 0-0.1 nsec, both inputs are high and after simulation the
output is showing a logic high, representing the AND logic
functionality.
Fig. 10. OR logic circuit implementation using MOSHEMT. Red colour,
Green colour and Blue colour waveforms are input1, input2 and output
respectively.
Similarly in Fig. 10 the simulation result of OR logic
functionality is shown. At time 0.23-0.25 nsec, when both
inputs are low the output is showing a logic low and in all other
cases, that is, when any one of the input is high or both inputs
are high the output is showing a logic high.
CONCLUSION
In our work, we have studied the switching functionality of
HEMT, through inverter. Further we solved the issues of high
on-resistance and current collapse, affecting the functionality of
the inverter. On analyzing the MOSHEMT inverter, we found
significant improvement in dc characteristics. With proper
simulations and calculations we obtained the power delay
product as 8.287 fJ/mm. Along with that functionality of some
other logic circuits using HEMT device are also justified and
presented.
ACKNOWLEDGMENT
We would like to acknowledge the VLSI Design laboratory in
the School of Electronics Engineering at Kalinga Institute of
Industrial Technology Bhubaneswar, India for providing us
the proper platform to carry out the research work.
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