JVC LT 32da9bj LT 32da9bu SM

Preliminary
SCHEMATIC DIAGRAMS
INTEGRATED DIGITAL TERRESTRIAL/SATELLITE LCD TELEVISION
LT-32DA9BJ, LT-32DA9BU
DVD-ROM No.SML2008Q1
COPYRIGHT © 2008 Victor Company of Japan, Limited. No.YA607<Rev.001>

2008/6
LT-32DA9BJ, LT-32DA9BU
STANDARD CIRCUIT DIAGRAM
NOTE ON USING CIRCUIT DIAGRAMS
1.SAFETY Type
The components identified by the symbol and shading are No indication : Ceramic capacitor
critical for safety. For continued safety replace safety ciritical MM : Metalized mylar capacitor
components only with manufactures recommended parts. PP : Polypropylene capacitor
MPP : Metalized polypropylene capacitor
MF : Metalized film capacitor
2.SPECIFIED VOLTAGE AND WAVEFORM VALUES
TF : Thin film capacitor
The voltage and waveform values have been measured under the BP : Bipolar electrolytic capacitor
following conditions. TAN : Tantalum capacitor
(1)Input signal : Colour bar signal (3)Coils
(2)Setting positions of No unit : [µH]
each knob/button and Others : As specified
variable resistor : Original setting position
(4)Power Supply
when shipped
(3)Internal resistance of tester : DC 20kΩ/V : B1 : B2 (12V)
(4)Oscilloscope sweeping time :H 20µs / div
: 9V : 5V
:V 5ms / div
Respective voltage values are indicated
: Othters Sweeping time is
specified (5)Test point
(5)Voltage values : All DC voltage values : Test point : Only test point display
Since the voltage values of signal circuit vary to some extent
according to adjustments, use them as reference values. (6)Connecting method
: Connector : Wrapping or soldering

3.INDICATION OF PARTS SYMBOL [EXAMPLE]
In the PW board : R1209 R209 : Receptacle
(7)Ground symbol
4.INDICATIONS ON THE CIRCUIT DIAGRAM
(1)Resistors : LIVE side ground
Resistance value : ISOLATED(NEUTRAL) side ground
No unit : [Ω] : EARTH ground
K : [kΩ] : DIGITAL ground
M : [MΩ]
5.NOTE FOR REPAIRING SERVICE
Rated allowable power
This model's power circuit is partly different in the GND. The
No indication : 1/16 [W]
difference of the GND is shown by the LIVE : ( ) side GND and the
Others : As specified ISOLATED(NEUTRAL) : ( ) side GND. Therefore, care must be
Type taken for the following points.
No indication : Carbon resistor (1)Do not touch the LIVE side GND or the LIVE side GND and the
OMR : Oxide metal film resistor ISOLATED(NEUTRAL) side GND simultaneously. if the above
MFR : Metal film resistor caution is not respected, an electric shock may be caused.
Therefore, make sure that the power cord is surely removed from
MPR : Metal plate resistor the receptacle when, for example, the chassis is pulled out.
UNFR : Uninflammable resistor
(2)Do not short between the LIVE side GND and ISOLATED(NEUTRAL)
FR : Fusible resistor side GND or never measure with a measuring apparatus measure
Composition resistor 1/2 [W] is specified as 1/2S or Comp. with a measuring apparatus ( oscilloscope, etc.) the LIVE side GND
(2)Capacitors and ISOLATED(NEUTRAL) side GND at the same time.
If the above precaution is not respected, a fuse or any parts will be broken.
Capacitance value
1 or higher : [pF] Since the circuit diagram is a standard one, the circuit and
circuit constants may be subject to change for improvement
less than 1 : [µF] without any notice.
Withstand voltage
No indication : DC50[V] NOTE
Due improvement in performance, some part numbers show
Others : DC withstand voltage [V]
in the circuit diagram may not agree with those indicated in
AC indicated : AC withstand voltage [V] the part list.
Electrolytic Capacitors When ordering parts, please use the numbers that appear
47/50[Example]: Capacitance value [µF]/withstand voltage[V] in the Parts List.
(No.YA607<Rev.001>)2-1
CONTENTS
SEMICONDUCTOR SHAPES ......................................................................2-2
WIRING DIAGRAM .......................................................................................2-3
BLOCK DIAGRAM........................................................................................2-5
CIRCUIT DIAGRAMS ...................................................................................2-7
MAIN PWB CIRCUIT DIAGRAM ................................................................................................................. 2-7
MPEG PWB CIRCUIT DIAGRAM ............................................................................................................. 2-51
IR PWB CIRCUIT DIAGRAM .................................................................................................................... 2-87
KEY PWB CIRCUIT DIAGRAM ................................................................................................................. 2-89
LED PWB CIRCUIT DIAGRAM ................................................................................................................. 2-91
PATTERN DIAGRAMS .............................................................................. 2-93
MAIN PWB PATTERN .............................................................................................................................. 2-93
MPEG PWB PATTERN ............................................................................................................................. 2-97
IR PWB PATTERN .................................................................................................................................. 2-101
KEY PWB PATTERN .............................................................................................................................. 2-101
LED PWB PATTERN .............................................................................................................................. 2-102
USING P.W. BOARD

P.W.B ASS㵭Y name LT-32DA9BJ LT-32DA9BU
MAIN P.W. BOARD HU-71200010 φ
MPEG P.W. BOARD HU-71200005 φ
IR P.W. BOARD HU-72200004 φ
KEY P.W. BOARD HU-72200003 φ

LED P.W. BOARD HU-72200017 φ
SEMICONDUCTOR SHAPES
TRANSISTOR
BOTTOM VIEW FRONT VIEW TOP VIEW
CHIP TR
C
E
C
B B C E
E C B E C B B E
(G) (D) (S) E C B
IC
BOTTOM VIEW FRONT VIEW TOP VIEW
1 N
OUT
E
IN 1 N
IN E OUT 1 N
CHIP IC
TOP VIEW
1
N
N
1
2-2(No.YA607<Rev.001>)
WIRING DIAGRAM
TOP
LCD PANEL UNIT LCD PANEL UNIT
[INVERTER PWB] [LCD CONTROL PWB]
TOP DIGITAL TUNER

14 1
CN3
15
CN1
KEY PWB
1
JP900
1 40 MPEG PWB
TOP
40 1
JP710
15
TOP
31
JP680
JP630
5
JP2
1
1
1
5
JP681
F1
1
250V/6.3A
6
CN2
JP682
L N
POWER UNIT
1
ANALOG TUNER
JP581
TOP AC INLET
JP683
4 1
MAIN PWB
4 1
FRONT
IR PWB
1
JP1 5 1
6
LED PWB JP3

SPEAKER(L) SPEAKER(R)
(No.YA607<Rev.001>)2-3 2-4(No.YA607<Rev.001>)
BLOCK DIAGRAM
DTT_AUD_R/L DTT_RESET
MPEG_B_Pb
MPEG_G_Y MPEG_GPIO
RS232_SW
MPEG_R_Pr MPEG PWB
SERVICE PORT MPEG_CVBS SBTV
MPEG_R_Pr/G_Y/B_Pb
SPDIF_OUT
U660
COM_RXD/TXD
MPEG_CVBS
MPEG_RXD/TXD MPEG_RXD/TXD IR_SCART_TV
TXD_PC/RXD_PC RS232C TA1/RA1 L/S TA2/RA2
U661 COMU_RX/TX
DRIVER EEPROM
COMU_RX/TX
DIGITAL AUDIO
ROM_WP
TA1/RA1_Sub MICOM
COM_RXD/TXD
U800
83/84Pin
91/92Pin
RESETn VOLTAGE +5VST
VCTP_SCL/SDA_3V3 L/S SCL/SDA_STB
179Pin
181,180,
190Pin
SDPIF_OUT
105Pin
DET
X-TAL
14.318 TA1/RA1_Sub MICOM
SCL/SDA
P3.3
P2.5/TMS
P2.4/TDI
VIN2
VIN11/12/13
MHz
FRONT_LED_B
115,116Pin
P2.6
MSP_ENABLE U801
VCTP_SCL/SDA_3V3 P2.7
IR_SCART_TV MICOM
LED_R LED&KEY PWB
208Pin
HDMI_RESET P4.7 KEY_ADC1
VCTP_INT
OSDR/ 110Pin
KEY_ADC2
1Pin P3.0 VCTP_Fail
HPD1 P4.6 IR_IN
OSDFW
HDMI1_PWR(HDMI1_DET) EEPROM 159Pin
HPD2 P1.7 Y800
HPD1
EXT-4 CEC_A HPD3
160Pin
P1.6
X-TAL
16.0MHz
HDMI D1SDA/D1SCL R,C
2Pin P4.5 98Pin
HDMI1_DET OSDFW
TMDS1 filter
HDMI2_DET 100Pin P3.7
109Pin STBY_EN
HDMI3_DET P3.1 +24V
HDMI2_PWR(HDMI2_DET) +5VST
EEPROM
+5V
HPD2
VCTP_SCL/SDA_3V3 +7V
CEC_A
HDMI D2SDA/D2SCL
+12V
TMDS2 BRT_ADJ
Not use U470 BLT_EN
RGB(24Bits) 106Pin
50 ~ 73 Pin P3.2 SECAM-L POWER UNIT
HDMI3_PWR(HDMI3_DET) P3.4 102Pin
EEPROM ANT_PWR_EN
HPD3
HDMI RECEIVER DIGITAL VIDEO INPUT PORT
CEC_A
HDMI D3SDA/D3SCL P2.1 88Pin DEBUG
P2.0 87Pin RS232_SW
TMDS3
89Pin
HDMI_INT P2.2
AC_DETECT
CEC_A 117Pin
171,47Pin P4.1 VCTP_Fail
HSYNC/VSYNC VIN22/DVS
48Pin U1
IN0DE DEN
49Pin
IN0CLK DCLK SCALER
167Pin
P1.1 ANT_PWR_CTRL
Y470
X-TAL U560 11/12Pin 162Pin
HDMI_I2S HDMI_AUD_R/L AIN2R/L P1.4 SBTV
14.318MHz AUDIO DAC+OP +12V or +5V
AMP 161Pin
P1.5 DTT_RESET
166Pin
P1.2 VCTP_INT
187/184/182Pin
COM_Pr/Y/Pb (MUX_RO/GO/BO) VIN6/7/9
90Pin
P2.3 PANEL_PWR U2 POWER
101Pin P4.3 119Pin LCD
MPEG_GPIO P3.5 BRT_ADJ
EXT-2 P4.2 120Pin
BLT_EN
PANEL
13,14Pin
UNIT
MUX_AUD_R/L AIN3R/L LVDS_OUT
COMP_RI/LI 3Pin
U120 SELECTION1 P4.4
99Pin
Analog MUX P3.6 HEADPHONE_ID
AL/AR_CVBS 191Pin
CVBS_TIN VIN1
31Pin 173/174Pin
ANT_SIF SIFIN+ VIN19/20 SV_C/Y
SCART1_ID
SCART1_R/G/B/CVBS SCART_R/G/B/CVBS
178/177/176/189Pin
VIN15/16/17/3 VIN21
172Pin CVBS EXT-3
175Pin
SCART1_FB SCART_FB VIN18
AL/AR_CVBS
EXT-1 SCART1_RI/LI SCART_RI/LI
9/10Pin
AIN1R/L AIN4L/R
15,16Pin
DTT_AUD_R/L
23/24Pin
SCART1_RO/LO SCART1_RO/LO AOUT1R/L
195Pin
SCART1_CVBSO SCART1_CVBSO SCART1_CVBS_OUT VOUT1
U200 U580 194Pin
SCART2_CVBSO SCART2_CVBS_OUT VOUT2 25/26Pin
(OP AMP) HEADPHONEL/R
SWITCH HP_L/R OP AMP HPO_L/R
SCART2_ID
SCART2_R/G/B/CVBS
SCART2_FB AMP_R-
27Pin SPEAKER(R)
VCTP_SCL/SDA_3V3
Not use SCART2_RI/LI SPEAKERR
28Pin
R_SPK
U580
AMP_R+
21/22Pin SPEAKERL L_SPK
SCART2_RO/LO SCART2_RO/LO AOUT2R/L
118Pin (AUDIO AMP)
SCART2_CVBSO P4.0 MUTE_CTRL
SCART2 RESETQ Y60

XTAL X-TAL AMP_L-
8Pin 20.25MHz SPEAKER(L)
AMP_L+
U770 VSUP5.0SIF,
/RESET
AC_DETECT
MSP_ENABLE U630
VSUP8.0AU
ANT_SIF JTAG
VCTP_SCL/SDA_3V3 Debeg
(AT_SCL/SDA) MCP100T
CVBS_TIN +7V +8V , +5V
U771
+5V_ANT ANT_PWR_EN
REG
VSUP3.3COM
Analog Tuner
(No.YA607<Rev.001>)2-5 2-6(No.YA607<Rev.001>)
CIRCUIT DIAGRAMS
MAIN PWB CIRCUIT DIAGRAM (1/22) [Analog Tuner]
5 4 3 2 1
U770
TAUT-S711D
Input - IEC type

I2C AS : 0xC0 24
GND1
23
GND2
D 22 D
TP_+33V
ANT (5V)
GND3
BB(CTR)
RF_AGC
L/T outpur -
+B(+5V)
21
AUDIO
GND4
CVBS
Phono type
GND
SDA
SCL
AFT
SIF
NC
NC
NC
NC
NC
NC
NC
AS
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
R770 000/1005
ANT_SIF
AGC
+5V_ANT
MAIN PWB(4/22)
C780 R779 000/1005
CVBS_TIN
2.2uF/50V/MVK/S
R773
472/1005
AGC
R780
750/F/1005
+5V_Analog_Tuner R790 OPEN-000/1005
C771
OPEN_2.2uF/50V/MVK/S R776 330/1005 R791 000/1005
VCTP_SCL_3V3
R785
152/1005 R777 330/1005 R792 000/1005 MAIN PWB(3/22),(6/22),(13/22),(21/22)
VCTP_SDA_3V3
C C
+5V_Analog_Tuner
3
C781 C782 C783 C784 R793 OPEN-000/1005

MAIN PWB SECAM-L
1 Q773 330p 330p OPEN-330p OPEN-330p
(3/22) KST4401 C770 C772
R784 104p/1005 470uF/16V/MVK/S
101/1005
2
+3V3D
U771
LD29150PT/P-PAK 5P +5.29V
+7V
VOUT
MAX 1.5A
GND
GND
/INH
ADJ
VIN
+5V_ANT_A
R781 +5V_ANT_A
103/1005 U772
POWER SW MIC2544-1YMM
3
6
5
1 8 +5V_ANT
ANT_PWR_EN EN OUT
MAIN PWB(3/22) ANT_PWR_CTRL 2 7
FLG IN C777 C778
B 3 6 B
GND OUT
2
4 5 106p/2012 104p/1005 C775
NC ILIM C779
IF ANT_PWR_CTRL is L --> ANT_PWR_EN L R786
101p/1005
106p/2012 C776 D770
C773 C774 333/F/1005 104p OPEN-ZMMC5V6
R778 106p/2012 104p/1005
OPEN_103/1005 R789
152/1005
1
R787
103/F/1005
ANT_PWR_EN +5V_ANT
HIGH ON
LOW OFF
MAIN PWB ASS'Y (1/22)
A
[Analog Tuner] A
HU-71200010
All location are from 770 to 799

5 4 3 2 1
lt-32da9bj_scaler-20_0602_20/23_0.0
(No.YA607<Rev.001>)2-7 2-8(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (2/22) [VCTP Power]
1 2 3 4 5 6
VCT-P POWER
+3V3_VCTP L2 VSUP3.3DIG +3V3_VCTP L3 VSUP3.3IO1 +3V3_VCTP L4 VSUP3.3FE
BLM18PG300SN1D BLM18PG300SN1D BLM18PG300SN1D +12V
VSUP8.0AU
R1 471/1005
D R2 471/1005 D
C3 C4 C5 C6 C7 C8 C9 R3 471/1005
106p/2012 104p/1005 106p/2012 104p/1005 104p/1005 106p/2012 104p/1005 R4 471/1005
2
C11 C12 C10
D1 104p/1005 101p/1005 106p/3216
ZMM5237B
+3V3_VCTP L5 VSUP3.3FL +3V3_VCTP L6 VSUP3.3DRI +3V3_VCTP L7 VSUP3.3VO
BLM18PG300SN1D BLM18PG300SN1D BLM18PG300SN1D
1
C13 C14 C15 C16 C17 C18
106p/2012 104p/1005 106p/2012 104p/1005 106p/2012 104p/1005
+1V8_VCTP_A VSUP1.8DIG
+3V3_VCTP L8 VSUP3.3COM +3V3_VCTP L9 VSUP3.3RAM +3V3_VCTP L10 VSUP3.3IO3
BLM18PG300SN1D BLM18PG300SN1D BLM18PG300SN1D
C19 C20
C21 C22 C23 C24 C25 C26 106p/2012 104p/1005
106p/2012 104p/1005 106p/2012 104p/1005 106p/2012 104p/1005
C C
+3V3_VCTP L11 VSUP3.3LVDS +1V8_VCTP L12 VSUP1.8LVDS +3V3_VCTP L13 VSUP3.3DAC +1V8_VCTP L14 VSUP1.8FE
BLM18PG300SN1D C30 C32 BLM18PG300SN1D BLM18PG300SN1D HH-1M3216-501JT
102p/1005 104p/1005
C27 C28 C29 C34 C35 C36 C37 C38 C39 C40 C41
104p/1005 106p/2012 106p/2012 104p/1005 106p/2012 104p/1005 106p/2012 104p/1005 106p/2012 104p/1005 104p/1005
C31 C33
102p/1005 104p/1005
VSUP5.0SIF VSUP8.0AU_A
VSUP3.3LVDS
VSUP3.3IO3
VSUP1.8LVDS
VSUP3.3VO VSUP3.3DRI
VSUP1.8FE VSUP1.8DIG VSUP3.3RAM
VSUP3.3IO1 VSUP3.3DIG
VSUP3.3FE VSUP3.3FL C46 C47 VSUP8.0AU
5
B VSUP5.0SIF 106p/3216 106p/3216 B
VSUP3.3DAC VSUP3.3COM VSUP8.0AU_A
D1
D1
D2
D2
+5V
C43 C42 L15

197
192
185
169
170
164
156
150
139
133
127
142
124
114
104p/1005 106p/2012 BLM31PG121SN1L

96
86
77
75
45
36
33
18
17
G1
G2
S1
S2
U2
L16 SI4925DY
VSUP3.3IO3
VSUP3.3VO
VSUP1.8FE
VSUP1.8FE
VSUP3.3FE
VSUP3.3DAC
VSUP3.3LVDS
VSUP3.3LVDS
VSUP3.3LVDS
VSUP3.3LVDS
VSUP3.3LVDS
VSUP1.8LVDS
VSUP1.8DIG
VSUP3.3IO1
VSUP3.3IO1
VSUP3.3FL
VSUP3.3COM
VSUP3.3DRI
VSUP3.3RAM
VSUP3.3DIG
VSUP5.0SIF
VSUP8.0AU
VREFAU
BLM31PG121SN1L
4
Sequence : STBY_EN --> +3V3_VCTP --> MSP_ENABLE
C44 C45 R6
106p/3216 104p 104/1005 MSP_ENABLE H ON
GND3.3LVDS
GND3.3LVDS
GND3.3LVDS
GND3.3LVDS
GND3.3LVDS
GND3.3COM
GND3.3RAM
GND3.3DAC
GND1.8DIG
GND3.3DIG
GND3.3DRI
GND3.3IO3
GND3.3IO1
GND3.3IO1
L OFF
GND3.3FL
IC_GND
GNDA
SGND
GNDA
GNDA
REXT
Q1
3
U1D KST4401
VCT7993P-FA-A1-H-500 1 R7 472/1005
MSP_ENABLE MAIN PWB(21/22)
209
196
163
153
147
144
136
130
123
113
186
143
95
85
76
74
46
35
34
20
19
2
A R5 A
622/F/1005

[VCTP Power]
HU-71200010
All location are from 1 to 59.
1 2 3 4 5 6
lt-32da9bj_scaler-01_0602_1/23_0.0
(No.YA607<Rev.001>)2-9 2-10(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (3/22) [VCTP Reset & GPIO]
5 4 3 2 1
+3V3_VCTP +3V3_VCTP +3V3_VCTP

VSUP3.3COM VSUP3.3COM +3V3_VCTP
U60
ASM811REUSF-T R84 R85 R61
472/1005 472/1005 103/1005 R62 R63
4 1 R97 103/1005 103/1005
VCC GND OPEN-103/1005
D D
WP
3 2 /RESET R64
MR RESET
3
VCTP_SCL_3V3 VCTP_SDA_3V3 103/1005 DEBUG
C60 Q61 1 ROM_WP HEADPHONE_ID
104p/1005 S61 KST4401
OPEN-DHT-1105TABF R96
1
104/1005 Normal W/P
2
2
ROM_WP H L JP61
OPEN-HEADER 2P
MAIN PWB(11/22) HPD2 159

P1_7(CADC4)/TDO R100 000/1005
MAIN PWB(12/22) HPD3 160 120 BLT_EN MAIN PWB(16/22),(21/22)
R66 330/1005 P1_6(CADC3)/TCLR PCS0(VSO)/P4_2
DTT_RESET 161 119 BRT_ADJ MAIN PWB(16/22)
MAIN PWB(19/22) R99 101/1005 P1_5(CADC2) PCS1(HSO)/P4_3 R101 000/1005
SBTV 162 118 MUTE_CTRL MAIN PWB(15/22),(21/22)
P1_4(CADC1) PCS2(DEC1)/P4_0
MAIN PWB(13/22) HDMI_RESET 165 117 VCTP_FAIL MAIN PWB(21/22)
R68 101/1005 P1_3 PCS3(DEC2)/P4_1 VCTP_SCL_3V3
MAIN PWB(21/22) VCTP_INT 166 116 VCTP_SCL_3V3
P1_2 PCS4/P2_6 VCTP_SDA_3V3 MAIN PWB(1/22),(6/22),(13/22),(21/22)
MAIN PWB(1/22) ANT_PWR_CTRL 167 115 VCTP_SDA_3V3
P1_1 PCS5/P2_7
168 112
MAIN PWB(4/22),(9/22) SELECTION2 P1_0 OSDR0
111
OSDR1 OSDFSW C62 C63
110
R70 102/1005 OSDR2/P3_0 OPEN-150p/1005 OPEN-150p/1005
198
R71 102/1005 656I0
199
R72 102/1005 656I1
200
R73 102/1005 656I2
201
R75 102/1005 656I3
C 202 C
R76 102/1005 656I4 MAIN PWB
203 109 HDMI3_DET
656I5 OSDR3/P3_1
R77 102/1005 204
656I6 OSDG0
108 (12/22)
+3V3_VCTP R80 102/1005 205 107
R81 102/1005 656I7 OSDG1
206 106 SECAM-L
JP60 R82 102/1005 656CLKI OSDG2/P3_2 ROM_WP U61 +3V3_VCTP
207 105
OPEN-2110-DS12-G 656CLKO OSDG3/P3_3 AT24C64CN
104 MAIN PWB(1/22)
TMS OSDB0
103
TDO 1 2 OSDB1
102 ANT_PWR_EN 1 8
RESETO 3 4 OSDB2/P3_4 A0 VCC WP
101 MPEG_GPIO MAIN PWB(19/22) 2 7
TDI 5 6 DBRESET TMS OSDB2/P3_5 A1 WP VCTP_SCL_3V3
7 100 3 6
7 8 TDI 6
656O0/P4_0/TMS OSDHCS0/P3_7
99 HEADPHONE_ID
HDMI2_DET MAIN PWB(11/22) 4
A2 SCL
5 VCTP_SDA_3V3
TCLK 9 10 TDO 5
656O1/P4_1/TDI OSDHCS1/P3_6 HEADPHONE_ID MAIN PWB(15/22) VSS SDA
11 12 TCLK 656O2/P4_2/TDO C64
4
656O3/P4_3/TCLK 104p/1005
MAIN PWB(4/22),(10/22) SELECTION1 3
656O4/P4_4/TMSFW
HDMI1_DET 2
656O5/P4_5/TDIFW +3V3_VCTP
MAIN PWB(11/22) HPD1 1
656O6/P4_6/TDOFW
208 98 R93 OPEN-222/1005 OSDFSW
656O7/P4_7/TCLKFW OSDFW C68
97
OSDCLK OPEN-224p
R91 R92
92 COM_RXD MAIN PWB +3V3_VCTP 472/1005 472/1005
P2_5/TMS COM_RXD
91 COM_TXD
/RESET P2_4/TDI COM_TXD (17/22)
8 90 PANEL_PWR
RESETQ P2_3
89 HDMI_INT
P2_2 DEBUG
B 88 B
+3V3_VCTP P2_1(CADC6) R86 R87 COM_RXD
87 RS232_SW
R88 102/1005 P2_0(CADS5)
80
R89 102/1005 81
CLKOUT MAIN PWB(17/22) 472/1005 472/1005 COM_TXD
R90 102/1005 VSO MAIN PWB(13/22)
82
R69 HSO
MAIN PWB(16/22)
OPEN-472/1005 84 SDA_3V3
SDA SCL_3V3 +3V3_VCTP
83
SCL
RESETO
R95
R74 79 000/1005 JP62 C65
3
OPEN-473/1005 XTALOUT OPEN-53014-0410 OPEN-104p/1005

/RESET 1 Q62
R78 OPEN-KST4401 1 SCL_3V3
3
2mm
OPEN-102/1005 78 SDA_3V3
DBRESET 1 Q63 XTALIN 3
2
OPEN-KST4401 Y60 4
U1A 20.25MHZ/13pF
VCT7993P-FA-A1-H-500
2
C66 C67
140p 140p
A A

[VCTP Reset & GPIO]
HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-02_0602_2/23_0.0
(No.YA607<Rev.001>)2-11 2-12(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (4/22) [VCTP A/V Input]
5 4 3 2 1
U1C VCT7993P-FA-A1-H-500
U1B VCT7993P-FA-A1-H-500
MAIN PWB GB[7..0]

171 73 GB0 141 RN121 2 3
(9/22),(13/22) HSYNC
C120 105p VIN22 DBI0 GB1 LVDSA_0N 330*2
TXA0-
CVBS 172 72 140 1 4 TXA0+
MAIN PWB C121 105p VIN21 DBI1 GB2 LVDSA_0P RN122
SV_Y 173 71 138 2 3 TXA1-
VIN20 DBI2 LVDSA_1N
(22/22) SV_C
C122 105p 174
VIN19 DBI3
70 GB3
LVDSA_1P
137 330*2 1 4 TXA1+
175 69 GB4 135 RN123 2 3
SCART_FB VIN18 DBI4 LVDSA_2N TXA2-
C123 104p 176 68 GB5 134 330*2 1 4
MAIN PWB SCART_B
C124 104p VIN17 DBI5 GB6 LVDSA_2P RN124
TXA2+
177 67 132 2 3
(6/22) SCART_G
C125 104p 178
VIN16 DBI6
66 GB7 LVDSA_CLKN
131 330*2 1 4
TXACLK-
SCART_R/C VIN15 DBI7 GG[7..0] MAIN PWB(13/22) LVDSA_CLKP TXACLK+
D C126 105p 179 65 GG0 129 RN125 2 3 D
MPEG_B_Pb VIN13 DGI0 LVDSA_3N TXA3-
MAIN PWB C127 105p 180 64 GG1 128 330*2 1 4
MPEG_G_Y VIN12 DGI1 LVDSA_3P TXA3+
(19/22) MPEG_R_Pr
C128 105p 181
VIN11 DGI2
63 GG2
LVDSA_4N
126 1 TP120
MAIN PWB(16/22)
C129 104p R154 750/1005 182 62 GG3 125 1 TP121
MUX_BO VIN9 DGI3 LVDSA_4P
C130 105p 183 61 GG4 158 RN126 2 3
MAIN PWB C131 104p R155 750/1005 VIN8 DGI4 GG5 LVDSB_0N OPEN_330*2
TXB0-
184 60 157 1 4
(10/22) MUX_GO
C132 104p R156 750/1005 187
VIN7 DGI5
59 GG6 LVDSB_0P
155 RN127 2 3
TXB0+
MUX_RO VIN6 DGI6 LVDSB_1N TXB1-
58 GG7 154 OPEN_330*2 1 4
DGI7 GR[7..0] LVDSB_1P TXB1+
57 GR0 152 RN128 2 3
DRI0 LVDSB_2N TXB2-
MAIN PWB(6/22) C133 105p 188 56 GR1 151 OPEN_330*2 1 4
VIN5 DRI1 LVDSB_2P TXB2+
C134 105p 189 55 GR2 149 RN129 2 3
SCART_CVBS/Y VIN3 DRI2 LVDSB_CLKN TXBCLK-
C135 105p 190 54 GR3 148 OPEN_330*2 1 4
MPEG_CVBS VIN2 DRI3 LVDSB_CLKP TXBCLK+
C136 105p 191 53 GR4 146 RN130 2 3
CVBS_TIN VIN1 DRI4 LVDSB_3N TXB3-
52 GR5 145 OPEN_330*2 1 4
MAIN PWB(1/22) DRI5 LVDSB_3P TXB3+
51 GR6
MAIN PWB(19/22) DRI6 GR7
193 50
VOUT3 DRI7
SCART2_CVBS_OUT 194 122
VOUT2 PCLK1
SCART1_CVBS_OUT 195 121
VOUT1 PCLK2
MAIN PWB(5/22) DCLK
49 IN0CLK
48 IN0DE
MAIN PWB(13/22) +12V
C137 105p DEN
MAIN PWB SCART_RI 9
AIN1R DVS
47 VSYNC MAIN PWB(9/22),(13/22)
(6/22) C138 105p 10
SCART_LI AIN1L
11 R141
MAIN PWB HDMI_AUD_R
12
AIN2R
37 103/1005
(14/22) HDMI_AUD_L AIN2L SPDIF_OUT
MUX_AUD_R 13
MUX_AUD_L AIN3R
14
AIN3L
C MAIN PWB DTT_AUD_R 15 C
AIN4R Q120
(19/22) DTT_AUD_L 16
AIN4L R143 KST4401
38
I2S_DA_IN
3
39 103/1005
SC2_R I2S_CL 1
MAIN PWB SCART2_RO 21
AOUT2R/AIN5R I2S_WS
40
MAIN PWB(3/22),(10/22) SELECTION1
(8/22) SC2_L 22
SCART2_LO AOUT2L/AIN5L
SC1_R 23
MAIN PWB SCART1_RO
SC1_L AOUT1R +12V
2
24
(7/22) SCART1_LO AOUT1L
41
I2S_DEL_OUT R144 102/1005
42
HP_RO I2S_DEL_IN R145
HP_R 25 43
HP_LO HP_R I2S_DEL_CL OPEN_103/1005
MAIN PWB HP_L 26 44
SP_RO HP_L I2S_DEL_WS
R_SPK 27
(15/22) SP_LO 28
SPEA_R
L_SPK SPEA_L
31 C145 C146
ANT_SIF
MAIN PWB Q121
SIFN+
29 32 560p/1005 100p/1005 (1/22) R148 OPEN_KST4401
3
SUBWOOFER SIFN- OPEN_103/1005
MAIN PWB 1
(3/22),(9/22) SELECTION2
R147
472/1005 +12V
R120 102/1005 94 R142
2
30
OSDH VREFSIF 000/1005
R149 102/1005 93
OSDV C149 C150
106p/2012 104p
C147
B 104p/1005 B
16
10
9
C148
560p/1005
VDD
A1
A0
C151 102p/1005 SC2_R C152 105p R160 000/1005 1 C155
C153 102p/1005 SC2_L MAIN PWB(22/22) AR_CVBS
C154 105p R161 000/1005 5
Y0B
3 MUX_AUD_R
C156 102p/1005 SC1_R
MAIN PWB(10/22) COMP_RI
C157 OPEN_105pR162 OPEN-000/1005 YIB ZB
MAIN PWB(9/22) PC_RI 2
C158 102p/1005 SC1_L Y2B
4
C159 102p/1005 HP_RO Y3B 106p/3216
C160 102p/1005 HP_LO C161 105p R163 000/1005 12
C162 102p/1005 SP_RO
MAIN PWB(22/22) AL_CVBS
C163 105p R164 000/1005 Y0A C166
14
C164 102p/1005 SP_LO MAIN PWB(10/22) COMP_LI
C165 OPEN_105pR165 OPEN-000/1005 15 Y1A
13 MUX_AUD_L
MAIN PWB(9/22) PC_LI
11
Y2A ZA
VSS
VEE
Y3A
E#
106p/3216
U120
8
7
6
CD4052BM96
MAIN PWB ASS'Y (4/22) CVBS COMPONENT PC
A
[VCTP A/V Input] SELECTION 1 H L H A
SELECTION 2 H H L
HU-71200010

5 4 3 2 1
lt-32da9bj_scaler-03_0602_3/23_0.0
(No.YA607<Rev.001>)2-13 2-14(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (5/22) [Scart Video AMP]
1 2 3 4 5 6
+12V M_+12VA1
L180
D BLM18PG300SN1D D
C181
C180 104p
100uF/25V/BXE/S
M_+12VA1 M_+12VA1
R181 C182
C OPEN-103/1005 U180A 104p C
R180 TSH72CD
8
000/1005 C183
3 470uF/16V/MVK/S
SCART2_CVBS_OUT + 1
2 SCART2_CVBSO MAIN PWB(8/22)
R182 471/F
-
R183
OPEN-103/1005
4
C184 R184
OPEN-103p/1005 471/F
MAIN PWB(4/22) C185

OPEN-220p/1005
M_+12VA1
B B
M_+12VA1
R185
OPEN-103/1005
R186 U180B
C186
8
000/1005 TSH72CD
5 470uF/16V/MVK/S
SCART1_CVBS_OUT + 7
R187 471/F
-
R188
OPEN-103/1005
4
C187 R189
OPEN-103p/1005 471/F
C188
A
OPEN-220p/1005 MAIN PWB ASS'Y (5/22) A
[Scart Video AMP]

HU-71200010
1 2 3 4 5 6
lt-32da9bj_scaler-04_0602_4/23_0.0
(No.YA607<Rev.001>)2-15 2-16(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (6/22) [Scart Switch]
1 2 3 4 5 6
+5V +12V
L200 L201
BLM18PG300SN1D BLM18PG300SN1D
A A
C200 C202 C203 C204 C201

106p/2012 103p/1005 104p/1005 104p 106p/3216
C205 C206 C207

106p/2012 474p 104p/1005
14
24
36
20
V_AUD
V_VID
V_VID
Vcc12
C208 104p/1005 42 33 R201 750/F/1005
SCART2_B BIN_VCR BOUT_TV SCART_B
C209 104p/1005 41 32 R202 750/F/1005
MAIN PWB(8/22) SCART2_G GIN_VCR GOUT_TV SCART_G
C210 104p/1005 40 31 R203 750/F/1005
SCART2_R/C R/CIN_VCR R/COUT_TV SCART_R/C
C211 104p/1005 39 30 R204 750/F/1005
SCART2_CVBS/Y Y/CVBSIN_VCR Y/CVBS_TV SCART_CVBS/Y
37
R/CIN_TV R205 R206 R207 R208
35
R/COUT_VCR
B 38
Y/CVBSIN_TV Y/CVBS_VCR
34 750/F/1005 750/F/1005 750/F/1005 750/F/1005 MAIN PWB(4/22) B
C212 104p/1005 43 18
SCART1_CVBS Y/CVBSIN_ENC TV_OUTL
C213 104p/1005 44 19
SCART1_R R/CIN_ENC TV_OUTR
MAIN PWB(7/22) SCART1_G
C214 104p/1005 45
GIN_ENC
C215 104p/1005 46
SCART1_B BIN_ENC
47 16
YIN_ENC VCR_OUTL SCART_LI
48 15
CIN_ENC VCR_OUTR SCART_RI
R200 203/F/1005 C216 105p 11

SCART1_LI TV_INL
MAIN PWB(7/22) SCART1_RI
R209 203/F/1005 C217 105p 10 17
TV_INR AMO_RF
29
R210 203/F/1005 C218 105p CVBS_RF
SCART2_LI 9
MAIN PWB(8/22) R211 203/F/1005 C219 105p VCR_INL
SCART2_RI 8
VCR_INR
4
R212 R213 R214 R215 ENC_INL+
5 25 SCART2_FB MAIN PWB(8/22)
103/F/1005 103/F/1005 103/F/1005 103/F/1005 ENC_INL- VCRIN_FS
6 21 R216 101/1005
7
ENC_INR+ TV_SS
22 R217 101/1005
ID1 MAIN PWB(7/22)
ENC_INR- VCR_SS
27 R218 750/F/1005
ID2 MAIN PWB(8/22)
TVOUT_FS SCART_FB MAIN PWB(4/22)
MAIN PWB SCART1_FB 26 23 R219 104/1005
ENCIN_FS SET
(7/22) R220
C 750/F/1005 C
3
R221 101/1005 DEV_ADDR
VCTP_SCL_3V3 2
MAIN PWB(1/22),(3/22),(13/22),(21/22) R222 101/1005 SCL
VCTP_SDA_3V3 1 13
SDA AUD_BIAS
GND_AUD
GND_VID
C221
104p C220
47uF/25V/BLA/S
EP
28
49
12
U200
MAX4397DCTM
I2C_ADDR
0x94/95
D D

[Scart Switch]
HU-71200010
1 2 3 4 5 6
lt-32da9bj_scaler-05_602_5/23_0.0
(No.YA607<Rev.001>)2-17 2-18(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (7/22) [Scart 1]
5 4 3 2 1
SC1_RED
SCART1_R
RV231 R231
SV060305E101N 750/F/1005
D D
SC1_GREEN MAIN PWB(6/22)

SCART1_G
RV232
SV060305E101N R232
750/F/1005
SC1_BLUE
R230 SCART1_B
220/1005
SCART1_CVBS MAIN PWB(6/22) RV233
SV060305E101N R233
R234 750/F/1005
RV230 750/F/1005
SV060305E101N
JP230
C C
21
GND
20
CVBSI R235 750/F/1005
C/LUMA
18
GND(R)
17
GND(V)
16
RGBC
15 SC1_RED
SCART1_FB MAIN PWB(6/22)
R/CHROMA L230
14 CIL21J1R8KNE
GND(D) R238 R237
13 SC1_LI
GND(R) RV234 750/F/1005 OPEN-103/1005 SCART1_LI
12
DATA1 SC1_GREEN SV060305E101N
11
GREEN
10 RV235
DATA2
9 SV060314B431N C233 R240
GND(G)
8 ID1 102p/1005 224/1005
FNS
7 SC1_BLUE MAIN PWB(6/22) MAIN PWB(6/22)
BLUE SC1_LI
6
AIL RV236
5
GND(B) SV060314B431N
4 L234
GND(A) SC1_LO
3 CIL21J1R8KNE
AOL SC1_RI
2 SC1_RI
AIR SC1_RO SCART1_RI
1
AOR
TSSM-0740-21(STRAIGHT) RV237
SV060314B431N C234 R244
102p/1005 224/1005
B B
L235 C235 R245

CIL21J1R8KNE 106p/3216 101/1005
SC1_LO
SCART1_LO
RV238
SV060314B431N C236 R247
102p/1005 OPEN-224/1005
MAIN PWB(4/22)
L236 C237 R246

CIL21J1R8KNE 106p/3216 101/1005
SC1_RO
SCART1_RO
RV239
SV060314B431N C238 R248
102p/1005 OPEN-224/1005
A
MAIN PWB ASS'Y (7/22) A
[Scart 1]
HU-71200010

5 4 3 2 1
lt-32da9bj_scaler-06_0602_6/23_0.0
(No.YA607<Rev.001>)2-19 2-20(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (8/22) [Scart 2]
5 4 3 2 1
SC2_RED
SCART2_R/C
RV240 R261
SV060305E101N 750/F/1005
D D
SC2_GREEN MAIN PWB(6/22)

SCART2_G
RV241 R262
SV060305E101N 750/F/1005
SC2_BLUE
SCART2_B
R260 220/1005
SCART2_CVBS/Y MAIN PWB(6/22) RV242 R263
SV060305E101N 750/F/1005
RV243 R264
SV060305E101N 750/F/1005
JP260
C C
21
GND
20
CVBSI R265 750/F/1005
C/LUMA
18
GND(R)
17
GND(V)
16
RGBC
15 SC2_RED
SCART2_FB MAIN PWB(6/22) L260
R/CHROMA CIL21J1R8KNE
14
GND(D) R268 R267 SC2_LI
13 SCART2_LI
GND(R) RV244 750/F/1005 OPEN-103/1005
12
DATA1 SC2_GREEN SV060305E101N
11
GREEN RV245
10
DATA2 SV060314B431N C263 R270
9
GND(G) 102p/1005 224/1005
8 ID2 MAIN PWB(6/22)
FNS SC2_BLUE MAIN PWB(6/22)
7
BLUE SC2_LI
6
AIL
5
GND(B) RV246 L264
4
GND(A) SC2_LO SV060314B431N CIL21J1R8KNE
3
AOL SC2_RI SC2_RI
2 SCART2_RI
AIR SC2_RO
1
AOR
TSSM-0740-21(STRAIGHT) RV247
SV060314B431N C264 R274
102p/1005 224/1005
B B
L265 C265 R275

CIL21J1R8KNE 106p/3216 101/1005
SC2_LO
SCART2_LO
RV248
SV060314B431N C266 R277
102p/1005 OPEN-224/1005
MAIN PWB(4/22)
L266 C267 R276

CIL21J1R8KNE 106p/3216 101/1005
SC2_RO
SCART2_RO
RV249
SV060314B431N C268 R278
102p/1005 OPEN-224/1005

A A
[Scart 2]
HU-71200010

5 4 3 2 1
lt-32da9bj_scaler-07_0602_7/23_0.0
(No.YA607<Rev.001>)2-21 2-22(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (9/22) [VGA Input & SPDIF]
5 4 3 2 1
+5VSTB +5VSTB +5VSTB
R290 OPEN_000/1005
PC_B
3
JP290 U290A U290B
14
14
OPEN_HD-SF1511G-0 R291 OPEN_74HC14 OPEN_74HC14
8 1 2 OPEN_750/F/1005
8 DDC_SCL1 VSYNC1 R292 OPEN_000/1005 1 2 3 4 PC_VSYNC
15
15 7
7 VSYNC1 D290
14
OPEN_KDS226 R293
D 14 6 OPEN_472/1005 D
6 HSYNC1 R294 OPEN_000/1005 C291
7
13 PC_G
135 5 MAIN PWB(10/22) OPEN-102p/1005
3
12 DDC_SDA1
124 4 R295
11 1 2 OPEN_750/F/1005 RV291
113 3
10 OPEN_SV060305E101N
10 2 D291 +5VSTB +5VSTB
2 OPEN_KDS226
9
9 1 R296 OPEN_000/1005
1 PC_R
U290C U290D
14
14
17
16
3
OPEN_74HC14 OPEN_74HC14
R297
17
16
1 2 OPEN_750/F/1005 HSYNC1 R298 000/1005 5 6 9 8 PC_HSYNC
D292
OPEN_KDS226 R299
7
C292
OPEN_472/1005 OPEN-102p/1005
RV292
OPEN_SV060305E101N
+5VSTB +5VSTB +5VSTB
C C
R303 OPEN_000/1005
U290E
14
14
OPEN_74HC14 U290F
C290 OPEN_74HC14 C293
OPEN_104p/1005 11 10 13 12 OPEN_104p/1005
1
D293 +5VSTB
OPEN_DAN202K
3
7
+5VSTB R304
C294 OPEN_103/1005
OPEN_106p/2012 C295 R305 R306
OPEN_104p/1005
2
OPEN_472/1005 OPEN_472/1005 R307

OPEN_103/1005
3
Q290
1 8 1 OPEN_KST4401
A0 VCC MAIN PWB(3/22),(4/22) SELECTION2
2 7 +5VSTB
A1 WP R308 OPEN_000/1005 DDC_SCL1
3 6
A2 SCL R309 OPEN_000/1005 DDC_SDA1
2
4 5
VSS SDA
U292
OPEN_AT24C08A RV293 RV294 C296
OPEN_SV060314B431N OPEN_SV060314B431N OPEN_104p/1005
16
10
9
B B
R310
VDD
A1
A0
1 3 IN0VS 1
Y0B
OPEN_100/1005
PC_VSYNC 5 3
YIB ZB VSYNC
2 MAIN PWB(13/22) 2
Y2B
4
Y3B C297
12 R311 OPEN-220p/1005
MAIN PWB(4/22),(13/22)
JP291 R L L290
IN0HS
PC_HSYNC 14
Y0A OPEN_100/1005
OPEN_CIL10J1R8KNC Y1A
1 15 13 HSYNC
R 3 Y2A ZA
PC_RI 11
VSS
VEE
Y3A
5
E#
4 RV295 C298
L 2 OPEN_SV060314B431N R312 OPEN-220p/1005
OPEN_224/1005 U291
8
7
6
OPEN_THSE-0734T MAIN PWB(4/22) OPEN_CD4052BM96
L291
OPEN_CIL10J1R8KNC
PC_LI
+5V
RV296 R315 PC/HDMI SYNC SEL PC HDMI
2 R313 4R7 OPEN_SV060314B431N OPEN_224/1005
Vcc
Vin
1 R314 000/1005
SPDIF_OUT SELECTION 2 L H
A 3 A
GND C299
104p/1005
SH1
SH2
4
5
MAIN PWB(19/22)
JP292
RFT6112 [VGA Input & SPDIF]
HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-08_0602_8/23_0.0
(No.YA607<Rev.001>)2-23 2-24(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (10/22) [Component In & Signal Switch]
5 4 3 2 1
D D
Component_A/V Input +5V

L330
OPEN-BLM18PG121SN1D
Z330 Z331 +5V
ZMMC5V6 ZMMC5V6
2 1 1 2 C331 C332
OPEN-10uF/16V/MVK/S OPEN-104p/1005
COMP_Pb_0
R331
OPEN-104/1005 COMP_Y_0
COMP_Pr C330 OPEN_105p COMP_Pr_0 COMP_Pr_0
COMP_Y COMP_Y_0
R355 000/1005
R333 COMP_Pb_0
OPEN-104/1005
JP330 R330
TPSS-0738-3(STRAIGHT) 750/F/1005
R334 R335 R336
1 000/1005 000/1005 000/1005
2
Y 3
16
4 COMP_Pb
C 5 +5V C
VCC
Pb 6 2
RV330 S1A
3 4
OPEN-SV060305E101N R338 S2A DA
7
8 750/F/1005 R340 OPEN-330/1005 5
PC_R S1B
Pr 9 R339 R341 OPEN-330/1005 6 7 COMP_Pr_1
S2B DB MUX_RO
OPEN-104/1005
R342 OPEN-330/1005 11
PC_G S1C
COMP_Y C333 OPEN_105p R343 OPEN-330/1005 10 9 COMP_Y_1 MAIN PWB
S2C DC MUX_GO
COMP_Pr R346 OPEN-330/1005 14
(4/22)
PC_B S1D
R356 000/1005 R347 OPEN-330/1005 13 12 COMP_Pb_1
S2D DD MUX_BO
R345
RV331 OPEN-104/1005
OPEN-SV060305E101N R348 15
750/F/1005 EN
8 1
GND IN
MAIN PWB(9/22)
III
U330
OPEN-PI5V330WE
L331
JP331 BLM11B470SB +5V
1 COMP_RI
2 +5V
RED(R)
3
4 RV332 R351 MAIN PWB(6/22)
SV060314B431N 224/1005 R350
White(L)
B 5 OPEN-104/1005 R354 B
OPEN_103/1005
TPSE-0604-2 COMP_Pb C334 OPEN_105p
L332
BLM11B470SB R352
R357 000/1005 R349
COMP_LI OPEN-104/1005
OPEN_103/1005
3
Q330
1 OPEN_KST4401
RV333 R353 MAIN PWB(3/22),(4/22) SELECTION1
SV060314B431N 224/1005
2
PC/HDMI SYNC SEL PC COMPONENT
SELECTION 1 H L
A A

[Component In & Signal Switch]
HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-09_0602_9/23_0.0
(No.YA607<Rev.001>)2-25 2-26(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (11/22) [HDMI Input1,2]
5 4 3 2 1
HDMI1_INPUT HDMI2_INPUT
JP371
JP370
D D
19 D2+
1 2D2+
19 1 1D2+ 18 2
D2+ D2_SHIELD
18 2 17 3 2D2-
D2_SHIELD D2-
17 D2-
3 1D2- 16 D1+
4 2D1+
16 4 1D1+ 15 5
D1+ D1_SHIELD
15 D1_SHIELD
5 14 D1-
6 2D1- MAIN PWB(13/22)
14 6 13 7
D1-
7
1D1- MAIN PWB(13/22) D0+
8
2D0+
13 D0+ 1D0+ 12 D0_SHIELD
12 D0_SHIELD
8 11 D0-
9 2D0-
11 9 1D0- 22 10 10 2CK+
D0- SH1 CK+
22
SH1 10 CK+
10 1CK+ 23
SH2 9 CK_SHIELD
11
23 9 11 24 8 12 2CK-
SH2 CK_SHIELD SH3 CK-
24 8 12 25 7 13
SH3 CK- 1CK- SH4 CE_REMOTE CEC_A MAIN PWB(12/22),(13/22),(21/22)
25
SH4 7 CE_REMOTE
13 CEC_A MAIN PWB(12/22),(13/22),(21/22) 26
SH5 6 NC
14
26 6 14 5 15
SH5 NC DDC_CLK
5 DDC_CLK
15 4 DDC_DATA
16
4 16 3 17
DDC_DATA GND HDMI2_PWR
3 17 2 18
GND HDMI1_PWR +5V HP2_DET
2 +5V
18
HP1_DET
1 HP_DET
19
1 19 20
HP_DET Dummy1
20 21
Dummy1 Dummy2 RV376 L378
21
Dummy2 SV060314B431N CIL10J1R8KNC
RV377 L379 D2SDA
SV060314B431N CIL10J1R8KNC FW05050-21
FW05050-21 D1SDA
C D2SCL C
D1SCL L380
L381 CIL10J1R8KNC
CIL10J1R8KNC
RV371 RV372
RV373 RV374 OPEN_SV060305E101N OPEN_SV060305E101N
OPEN_SV060305E101N OPEN_SV060305E101N
HP1_DET HP2_DET
3
3
RV375
R370 1 R372 103/1005 R374 SV060314B431N 1 R375 103/1005
102/1005 RV370 Q374
HPD1 MAIN PWB(3/22) 102/1005 Q375
HPD2 MAIN PWB(3/22)
SV060314B431N KST4401 KST4401
2
2
HDMI1_PWR R373 103/1005 HDMI2_PWR R371 103/1005 MAIN PWB
HDMI1_DET MAIN PWB(3/22) HDMI2_DET
(3/22)
HDMI1_PWR D370 R376 HDMI2_PWR R377
DAN202K 183/1005 D371 183/1005
1
C370 DAN202K
1
104p/1005 L382 C371
BLM18PG121SN1D 104p/1005 L383
3 BLM18PG121SN1D
3
+5VSTB C372 C373 +5VSTB C374

B B
104p/1005 C375
R400 R401 104p/1005
2
106p/2012 106p/2012
220 220
2
+5VSTB
+5VSTB
U371 R378 R379

AT24C08A 473/1005 473/1005
U370 R382 R383 1 8
AT24C08A 473/1005 473/1005 A0 VCC
2 7
A1 WP R386 101/1005 D2SCL
1 8 3 6 D2SCL
A0 VCC A2 SCL R387 101/1005 D2SDA MAIN PWB(13/22)
2 7 4 5 D2SDA
A1 WP R388 101/1005 D1SCL VSS SDA
3 6 D1SCL
A2 SCL R389 101/1005 D1SDA MAIN PWB(13/22)
4 5 D1SDA
VSS SDA
A A

[HDMI Input1,2]
HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-10_0602_10/23_0.0
(No.YA607<Rev.001>)2-27 2-28(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (12/22) [HDMI Input 3_SIDE]
5 4 3 2 1
RV420 RV421
SV060314B431N SV060314B431N
R421
3
103/1005
1
HPD3 MAIN PWB(3/22)
D
Q421 D
KST4401
2
JP420
DC1R019JBA
19
HP_DET HDMI3_PWR R422
18
+5V 102/1005
23 17
SHIELD4 GND DDC3_SDA HDMI3_PWR R432 103/1005
16 HDMI3_DET MAIN PWB(3/22)
DDC_DATA DDC3_SCL
15
DDC_CLK
22 14
SHIELD3 NC R433
13 CEC_A
CE_REMOTE
12 HD0_RXC- MAIN PWB(11/22),(13/22),(21/22) 183/1005
CK-
11
CK_SHIELD HD0_RXC+
10
CK+ HD0_RX0- HD0_RXC-
9 3CK-
D0-
8
D0_SHIELD HD0_RX0+ HD0_RXC+
7 3CK+
D0+ HD0_RX1-
6
D1-
5
D1_SHIELD HD0_RX1+ HD0_RX0-
21 4 3D0-
SHIELD2 D1+ HD0_RX2-
3
D2- HD0_RX0+
2 3D0+
D2_SHIELD HD0_RX2+
20 1
SHIELD1 D2+
MAIN PWB(13/22)
HD0_RX1-
3D1-
C
HDMI3 HD0_RX1+
3D1+ C
HD0_RX2-
3D2-
HD0_RX2+
3D2+
HDMI3_PWR D420
DAN202K
1
C421
104p/1005 L424
BLM18PG121SN1D
3
C420
+5VSTB C422
106p/2012 104p/1005
R435
2
220
B B
+5VSTB
U420 R424 R425

AT24C08A 473/1005 473/1005
1 8
A0 VCC
2 7
A1 WP R428 101/1005
3 6 D3SCL
A2 SCL R429 101/1005
4 5 D3SDA MAIN PWB(13/22)
VSS SDA
L425
CIL10J1R8KNC
DDC3_SDA
DDC3_SCL
L426
CIL10J1R8KNC
A A
RV422 RV423
OPEN-SV060314B431N OPEN-SV060314B431N

[HDMI Input 3_SIDE]
HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-11_0602_11/23_0.0
(No.YA607<Rev.001>)2-29 2-30(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (13/22) [HDMI DECODE]
5 4 3 2 1
+3V3D L473 VDDP +3V3D L472 AVDD33 +3V3D L470 VMPLL +1V8D L471 AVDD18 +1V8D L474 VDDC
BLM18PG300SN1D C491 C497 C490 BLM18PG300SN1D C473 C477 BLM18PG300SN1D BLM18PG300SN1D BLM18PG300SN1D C474
104p/1005 105p 104p/1005 102p/1005 103p/1005 102p/1005
C499 C489 C498 C488 C502 C492 C501 C494 C500 C495
106p/2012 104p/1005 106p/2012 104p/1005 106p/2012 104p/1005 106p/2012 104p/1005 106p/2012 104p/1005
C472 C496 C470 C471 C475 C493 C476

102p/1005 104p/1005 102p/1005 102p/1005 103p/1005 104p/1005 103p/1005
D D
VMPLL VDDC
AVDD33 VDDP
AVDD18
118
128
142
105
110
25
35
45
52
61
68
78
85
90
27
54
70
92
6
[HDMI DECODE]
AVDD_33
AVDD_33
AVDD_33
AVDD_33
AVDD_33
AVDD_18
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
AVDD_MPLL
VDDC
VDDC
VDDC
HU-71200010 82
GB[7..0]
GB[7..0]
DATA0 PR470 101*4/1005
81
DATA1 RD4 GB0
80 1 8
DATA2 RD5 GB1
79 2 7
DATA3 RD6 GB2
77 3 6
DATA4 RD7 GB3
76 4 5
R475 100/1005 DATA5 RD8 GB4
1CK- 111 75 1 8
R496 100/1005 RXACKN DATA6 RD9 GB5
1CK+ 112 74 2 7
R474 100/1005 RXACKP DATA7 RD10 GB6
1D0- 113 73 3 6
R489 100/1005 RXA0N DATA8 RD11 GB7
1D0+ 114 72 4 5
R477 100/1005 RXA0P DATA9
C 1D1- 116 C
R485 100/1005 RXA1N PR471 101*4/1005
1D1+ 117
R473 100/1005 RXA1P
1D2- 119
R494 100/1005 RXA2N
1D2+ 120 65
RXA2P DATA10 PR472 101*4/1005 GG[7..0]
64 GG[7..0]
DATA11 GG0 MAIN PWB(4/22)
D1SCL 108 63 1 8
DDCDA_SCL DATA12 GG1
D1SDA 107 62 2 7
DDCDA_SDA DATA13 GG2
60 3 6
DATA14 GG3
59 4 5
DATA15 RD20 GG4
58 1 8
MAIN PWB(11/22) DATA16 RD21 GG5
57 2 7
DATA17 RD22 GG6
56 3 6
DATA18 RD23 GG7
55 4 5
R470 100/1005 DATA19
2CK- 121 U470
R487 100/1005 RXBCKN PR473 101*4/1005
2CK+ 122
R471 100/1005 RXBCKP
2D0- 123
R486 100/1005 124
RXB0N MST3380CLK 49
2D0+ RXB0P DATA20
R472 100/1005 126 48 PR474 101*4/1005 GR[7..0]
2D1- RXB1N DATA21 GR[7..0]
R493 100/1005 127 47 RD28 1 8 GR0
2D1+ RXB1P DATA22
R476 100/1005 129 46 RD29 2 7 GR1
2D2- RXB2N DATA23
R490 100/1005 130 44 RD30 3 6 GR2
2D2+ RXB2P DATA24
43 RD31 4 5 GR3
DATA25 RD32 GR4
D2SCL 144 42 1 8
DDCDB_SCL DATA26 RD33 GR5
D2SDA 1 41 2 7
DDCDB_SDA DATA27 RD34 GR6
40 3 6
DATA28 RD35 GR7
39 4 5
DATA29
B PR475 101*4/1005 B
R503 330/1005
HSYNC
R504 330/1005
VSYNC
MAIN PWB(4/22),(13/22)
R478 100/1005 132
3CK- RXCCKN
R495 100/1005 133 86 R499 101/1005 L475 BLM15BA750SN1D
3CK+ RXCCKP DATACK IN0CLK MAIN PWB(4/22)
R481 100/1005 134 87 R500 330/1005
3D0-
R483 100/1005 135
RXC0N DE
88 R501 OPEN-330/1005
IN0DE MAIN PWB(4/22)
3D0+ RXC0P HSOUT IN0HS MAIN PWB
R479 100/1005 137 89 R502 OPEN-330/1005 C506
3D1- RXC1N VSOUT IN0VS (9/22)
R488 100/1005 138 71 220p/1005
3D1+ RXC1P FIELD/CEC
MAIN PWB(12/22) 3D2-
R480 100/1005 140
R482 100/1005 RXC2N R492 OPEN_000/1005 MAIN PWB
3D2+ 141 93 CEC_A
RXC2P GPIO/CEC (11/22),(12/22),(21/22)
D3SCL 103
DDCDC_SCL HDMI_DOUT
D3SDA 104 97 SD
DDCDC_SDA AUSD HDMI_CLK
98 SCK
AUSCK HDMI_WS
99 WS MAIN PWB(14/22)
AUWS
VCTP_SCL_3V3 32 100
MAIN PWB(1/22),(3/22),(6/22),(21/22) 33
SCL AUMUTE
101 C505
VCTP_SDA_3V3 SDA MCKO MCLK
30 020p
MAIN PWB(3/22) HDMI_RESET HWRESET
HDMI_INT 36
INT
102
SPDIFO/CEC Y470 C503
R484 103/1005 31 14.31818MHZ/18pF 240p/1005
A0 XIN
29
XIN R498
OPEN-105/1005
R497
A 28 XOUT 000/1005 A
XOUT
AVDD33 C504
143 R491 391/F/1005 240p/1005
REXT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
106
109
115
125
131
136
139
26
34
53
69
91
7

5 4 3 2 1
lt-32da9bj_scaler-12_0602_12/23_0.0
(No.YA607<Rev.001>)2-31 2-32(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (14/22) [HDMI Audio DAC]
5 4 3 2 1
D D
U560
WM8521HC R561
PR560 330*4/1005 471/1005
1 8 3 10 C561 106p/3216
MCLK DIN VOUTL HDMI_AUD_L
WS 2 7 2
MAIN PWB(13/22) LRCLK MAIN PWB(4/22)
SD 3 6 4
+3V3D BCLK C562 106p/3216
SCK 4 5 13 6 HDMI_AUD_R
MCLK VOUTR +12V
R562
R560 472/1005 12 471/1005
R563 FORMAT
11 9
000/1005 DEEMPH AVDD
5
MUTE
C 7 C
AGND
14
L560 DVDD
BLM18PG300SN1D C563 1 8
C560 104p/1005 DGND CAP
106p/2012 C566 C567
104p/1005 C564 104p/1005 C565
106p/3216 106p/3216
* MODE SETTING *
MODE SETTING
SAMPLING 256FS
FORMAT I2S
B B
* MUTE CONTROL *
MUTE FUNCTION
LOW MUTE OFF
HIGH MUTE ON
A MAIN PWB ASS'Y (14/22) A
[HDMI Audio DAC]

HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-13_0602_13/23_0.0
(No.YA607<Rev.001>)2-33 2-34(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (15/22) [Audio AMP & HP AMP]
1 2 3 4 5 6
C581 C583 C584 C585

105p 105p 105p 470uF/25V/LXZ
+12V
C582
470uF/25V/LXZ
C587
102p/1005
C586
105p +12V [Audio AMP & HP AMP]
D
HU-71200010 D
R580
1212/F/1005
48
47
35
34
33
32
31
30
29
28
27
26
R_SPK
AVCC
AVCC
PVCCR
PVCCR
PGNDR
PGNDR
VCLAMPL
VCLAMPL
PGNDL
PGNDL
VCCLP
PVCCL
R581 C580
JP581
473/F/1005 102p/1005 43 C588 224p L581 OPEN-DBF-1015A C589 224p
BSRP SMW200-04
MAIN PWB(4/22)
C590 105p 2 AMP_R-
R582 RINN L582 DBF-1015S AMP_R+ 1
42
ROUTP 2 SPEAKER
2mm
1212/F/1005 C591 105p 3 41 AMP_L-
RINP ROUTP C592 AMP_L+ 3
L_SPK 4
474p
R583 C594 C593 105p 5 40
473/F/1005 102p/1005 LINP ROUTN L583 DBF-1015S
39
C595 105p ROUTN
6
LINN U580
38 C596 224p L584 OPEN-DBF-1015A C597 224p
BSRN
7 23 C598 224p L585 OPEN-DBF-1015A C599 224p
GAND0 TPA3100D2PHPR BSLN
8
GAND0
9 22 L586 DBF-1015S
+5VSTB GAIN1 LOUTN
21
LOUTN
10 C600
VREF_AMP MSTR/SLV
20 474p
R584 LOUTP L587 DBF-1015S
C 19 C
R592 473/1005 LOUTP
11
472/1005 R594 SYNC
000/1005 18 C601 224p L588 OPEN-DBF-1015A C602 224p
MUTE BSLP
45
R595 MUTE
3
472/1005 46 FAULT
1 Q581
MAIN PWB(3/22),(21/22) MUTE_CTRL
KST4401 C607
SHUTDOWN
44
GND_PAD
104p/1005
MUTE_CTRL H Mute off R585 L580
AGND
ROSC
AGND
VREG
2
VBYP
GND
GND
GND
GND
GND
GND
GND
220/1005 CIL10J1R8KNC
MUTE_CTRL L Mute On HPO_L
49
12
13
24
25
36
37
14
VREF_AMP 15
16
17
R587
4
1
9 6 000/1005
C603 8 5
223p/1005 7 4
2 HEADPHONE_ID
R590 L589 10
220/1005 CIL10J1R8KNC 11
R591 HPO_R 3
104/1005 1
MAIN PWB(18/22),(21/22) AMP_SHUTDOWN JP580 MAIN PWB(3/22)
AC_DETECT
C606 IJA03
C604 C605 223p/1005
R589 103p/1005 105p
B OPEN-123/1005 B
R597 R598
203/F/1005 163/F/1005
C608 105p
HP_L U581
TPA6110A2DGN
C609 1 8
2 BYPASS IN1- 7
AC_DETECT H Amp On , Headphone On OPEN-102p/1005
3 GND Vo1 6
C610 HPO_L
47uF/16V/MVK/S
Shutdown VDD
GND
AC_DETECT L Amp off , Headphone off MAIN PWB(4/22) C612 4 5 C611 HPO_R
+5V 105p IN2- Vo2 47uF/16V/MVK/S
9
R601 R602 R599 R600
203/F/1005 163/F/1005 103/1005 103/1005
R603 C613 105p
HP_R
103/1005
2
Q582
IRLML6402TRPBF C614
OPEN-102p/1005
1
R604
3
473/1005
3
1 Q583
MAIN PWB(18/22),(21/22) AC_DETECT
KST4401
A A
2
C615 C616
106p/2012 105p

1 2 3 4 5 6
lt-32da9bj_scaler-14_0602_14/23_0.0
(No.YA607<Rev.001>)2-35 2-36(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (16/22) [LVDS Connector]
1 2 3 4 5 6
+3V3D
+3V3D +3V3D +3V3D
R631
R632 202/1005 R637
472/1005 R634 472/1005
102/1005
BL_ADJ_O R640 R638
R635
BL_ADJ_O MAIN PWB(18/22) 472/1005 000/1005 BL_EN_O
BL_EN_O MAIN PWB(18/22)
3
D 103/F/1005 D
3
1 Q631 C630
MAIN PWB(3/22) BRT_ADJ
KST4401 105p 1 Q632
MAIN PWB(3/22),(21/22) BLT_EN C631
BRT_ADJ Min --> Bri. MAX R641 KST4401
104p/1005
103/F/1005
2
BRT_ADJ Max --> Bri. MIN BLT_EN L On
2
BLT_EN H off
For 32inch CMO 50/60Hz switching

H 60Hz
L 50Hz
+3V3D
R643 PANEL CONTROL

OPEN-103/1005
Module Power Samsung LPL&CPT MODULE_POWER

C C
R644 JP630
000/1005 FW12501-31A L630 OPEN SHORT
1
TP880 1 TP10 2 C636
TXA0-
TP881 1 TP10 3
TXA0+
TXA1-
TP882 1 TP10 4 L631 SHORT OPEN 106p/3216
TP883 1 TP10 5
TXA1+
TP884 1 TP10 6
TXA2-
5
TP885 1 TP10 7
TXA2+ +12V
8 +5V U630
D1
D1
D2
D2
TP886 1 TP10 9
TXACLK- SI4925BDY
TP887 1 TP10 10
TXACLK+
TP888 1 TP10 11
TXA3-
TP889 1 TP10 12
MAIN PWB(4/22) TXA3+ L631
TP890 1 TP10 13
G1
G2
S1
S2
TXB0- OPEN_BLM31PG121SN1L
TP891 1 TP10 14 L630
TXB0+
15 BLM31PG121SN1L
TP892 TP10
4
TXB1- 1 16
TP893 1 TP10 17
TXB1+
18
TXB2-
TP894 1 TP10 19 LCD PANEL UNIT
TXB2+
TP895
TP896
1
1
TP10
TP10
20
21
[LCD CONTROL PWB]
TXBCLK-
TP897 1 TP10 22 C632 C633 R645
TXBCLK+
TP898 1 TP10 23 104p 472/1005
TXB3-
TP899 1 TP10 24 106p/3216
TXB3+
B 25 B
26
27
28
MODULE_POWER TP15 29
TP900 30 32 R648
1 31 33 000/1005
PANEL_PWR H On
Q634
PANEL_PWR L off
3
FDV301N_NL
1 R647 474/1005
PANEL_PWR MAIN PWB(3/22)
2
C637 R646
105p/1005 472/1005

A
[LVDS Connector] A
HU-71200010

1 2 3 4 5 6
lt-32da9bj_scaler-15_0602_15/23_0.0
(No.YA607<Rev.001>)2-37 2-38(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (17/22) [RS232]
1 2 3 4 5 6
A
JP660 A
U660 THSE-0734T
ILX232 1
TA1 11 14 R660 101/1005 TXD_PC 3 R
TA1 T1IN T1O
MAIN PWB(21/22) 10 7 5
RA1 T2IN T2O R662 101/1005 RXD_PC
RA1 12 13 4
R1O R1IN
9 8 2 L +3V3D
R2O R2IN +5VSTB
1 16
C1+ VCC
C660 3 15 C661 C664 R669
104p/1005 C1- GND 104p/1005 106p/2012 103/1005
4
C2+
2
V+
5 6
C2- V- RV660 RV661
C662 SV060314B431N SV060314B431N 1
104p/1005 C663 2
104p/1005 JP662
OPEN-HEADER 2P
+5VSTB +3V3D
B B
R661 R663
472/1005 472/1005 R667 R668
472/1005 472/1005
1
TA1 3 2 TA2
Q662
FDV301N_NL
COM_RXD
1
STI5518_UART
VCTP_UART
MAIN PWB(3/22)
RA1 3 2 RA2
MPEG_RXD
Q661
FDV301N_NL
2 18 TA2
MPEG_TXD 1A1 1Y1
RA2 4 16
1A2 1Y2
COMU_TX 6 14
1A3 1Y3
8 12 COMU_RX MAIN PWB(19/22)
1A4 1Y4
COM_TXD 11 9
2A1 2Y1
13 7
2A2 2Y2
MAIN PWB(3/22) 15 5
2A3 2Y3 +3V3D
17 3
2A4 2Y4 C665 +3V3D
1 20 104p/1005
C 1G VCC C
19 10
MAIN PWB(19/22) 2G DGND
U661 R664 R665
SN74LVC244APWR 103/1005 472/1005
NORAML DISPALY DTT SW DOWN VCTP SW DOWN
R666 RS232_SW L L H
3
103/1005
1
RS232_SW MAIN PWB(3/22)
Q660
KST4401
2
D D
MAIN PWB ASS'Y (17/22) [RS232]

HU-71200010
1 2 3 4 5 6
lt-32da9bj_scaler-16_0602_16/23_0.0
(No.YA607<Rev.001>)2-39 2-40(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (18/22) [Power & Interface Connectors]
5 4 3 2 1
L681 BLM41PG600SN1L
MAX. 1A
+7V
JP680 C681 C682

+12V_MPEG
D SMW250-15 470uF/16V/BXJ/S 104p/1005 D
+5VSTB +5VSTB
L682 BLM41PG600SN1L
1 MAX.3.5A +12V
2
3 C683 C684 R681 R682
4 +5V_MPEG 472/1005 102/1005
470uF/16V/BXJ/S 104p
5 L683 BLM41PG600SN1L
POWER UNIT 6 MAX.5.5A
7 SMPS_ON
CN1 8
+5V
L684 BLM41PG600SN1L
2.5mm
MAX.1A
3
9 +5VSTB
C685 C686
10 C687 1 Q681
11
SMPS_ON MAIN PWB 106p/2012
470uF/16V/BXJ/S 104p/1005 MAIN PWB(21/22) STBY_EN
KST4401 C689
(15/22),(21/22) C688
12 AC_DETECT R685 OPEN-104p/1005
104p/1005
13 BL_ADJ_O 103/1005
2
14 BL_EN_O MAIN PWB(16/22) STBY_EN H off
15
STBY_EN L On
JP681
SMW250-05
KEY PWB 5 KEY_ADC2

2.5mm
C C
4 MAIN PWB(21/22) JP684 +5VSTB
JP2 3 KEY_ADC1 OPEN-SMW200-13
2
2mm
1 13
12
11 SPI_RST R691
+5VSTB
10 SPI_CS 471/1005
9 SPI_SCL IR
8 SPI_SDA MAIN PWB(21/22) MAIN PWB(21/22) IR_IN
OPEN 7 SPI_DAT0
JP682 C680 6 SPI_DAT1
SMW250-06 L687 104p/1005 5 SPI_DAT2
BLM18PG300SN1D IR R702 OPEN-000/1005 R692
4 SPI_DAT3 OPEN-332/1005
R703 OPEN-000/1005 FRONT_BLUE
6 3 R704 OPEN-000/1005 LEDR
2.5mm
5 2
IR 1
4
IR PWB 3 R694 OPEN_000/1005 FRONT_BLUE
JP1 2 LEDR
1
B B
JP683 +5VSTB +5VSTB
53014-0410
1
LED PWB FRONT_BLUE
2mm
2
JP3 3 LEDR
4
R701 R680 R697
2
OPEN-000/1005 103/1005 103/1005
1 Q680 1 Q686
MAIN PWB(21/22) FRONT_LED_B
KST4403
MAIN PWB(21/22) LED_R
KST4403
3
R695
Display Stand-by R693 Display Stand-by 301/3216
301/3216
FRONT_LED_B H L FRONT_BLUE LED_R L H LEDR

A A
[Power & Interface Connectors]

HU-71200010
DGND GND_A GND_D

5 4 3 2 1
lt-32da9bj_scaler-17_0602_17/23_0.0
(No.YA607<Rev.001>)2-41 2-42(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (19/22) [Tuner Docking Connectors]
1 2 3 4 5 6
+12V_MPEG
A A
MPEG PWB(18/18)
JP900
JP710
SMAW200-40D
DTT_AUD_R 1 21
DTT_AUD_L 2 22
3 23
MPEG_B_Pb 4 24 SBTV MAIN PWB(3/22)
MAIN PWB(4/22) 5 25 IR_SCART_TV MAIN PWB(21/22)
MPEG_G_Y 6 26
7 27
MPEG_R_Pr 8 28
9 29
B MPEG_CVBS 10 30 B
SPDIF_OUT MAIN PWB(9/22)

11 31
MPEG_TXD 12 32
MPEG_RXD 13 33 +7V
MAIN PWB(17/22) 14 34
COMU_TX 15 35 MPEG_GPIO MAIN PWB(3/22)
DTV_SDA
COMU_RX 16 36 DTV_SCL
17 37
MAIN PWB(3/22) DTT_RESET 18 38
19 39
+5V_MPEG 20 40 +5V_MPEG
750/F/1005
750/F/1005
750/F/1005
750/F/1005
C C
R710
R711
R712
R713

D
[Tuner Docking Connectors] D
HU-71200010

1 2 3 4 5 6
lt-32da9bj_scaler-18_0602_18/23_0.0
(No.YA607<Rev.001>)2-43 2-44(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (20/22) [Regulators]
1 2 3 4 5 6
NORMAL
POWER +3V3D +3V3_VCTP
+3V3_VCTP +1V8_VCTP
U721
L724 LD1117AL-ADJ
HH-1M3216-501JT L723 3 2
HH-1M3216-501JT VIN VO 4
TAP
ADJ
+5V
C726
D C734 +3.36V, C724 C731 R721 106p/2012 D
103p/1005 100uF/16V/MVK/S 104p/1005 121/F/1005
1
Max.2.5A
L721
SPC7040-100M
C733 C729 R729 C730 C728 C732
226p/2012 226p/2012 104/1005 100uF/16V/MVK/S R723
226p/2012 226p/2012 560/F/1005
1
R724
243/F/1005 R1
BS
IN
7 3
EN SW
8 5
GND_P
C727 SS FB
OPEN-106p/2012 4 6 C754 332p/1005
C753 GND COMP R722
U720 R2 912/F/1005
104p/1005 MP2307 C755 R731
9
OPEN-561p/1005 562/1005
VOUT = 0.925V * (1 + R1/R2)
C C
+3V3_VCTP
Vo=1.833V +1V8_VCTP_A
U723 I(Loadmax)=700mA
LD1117AL-ADJ
3 2
VIN VO 4
TAP
ADJ
R727 C737
121/F/1005 106p/2012
1
C738
104p/1005
+5V_Analog_Tuner R728
+7V 560/F/1005
U726
BA50BC0WFP
2 4
VIN VOUT
GND
NC
NC
B 1 B
C748 CTL C752 C751
104p/1005 C747 106p/2012 104p/1005 +3V3D +1V8D
100uF/16V/MVK/S U725
3
LD1117AL-ADJ
3 2
VIN VO 4
ADJ
TAP
C745
C743 C746 R730 106p/2012
100uF/16V/MVK/S 104p/1005 121/F/1005
1
R732
560/F/1005

A
[Regulators] A
HU-71200010

1 2 3 4 5 6
lt-32da9bj_scaler-19_0602_19/23_0.0
(No.YA607<Rev.001>)2-45 2-46(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (21/22) [MICRO CTRL(ATmega324)]
5 4 3 2 1
U800
+5VSTB KIA7042AF +5VSTB
GND
GND
VCC
OUT
D +5VSTB D
R801
103/1005 +5VSTB
1
2
4
3
JP800
RESETn
System Reset C802 C803 C804 C805 MISO
1 2
106p/2012 104p/1005 104p/1005 104p/1005 SCK_0 MOSI
RESETn 3 4
5 6
C801 S800
105p/1005 OPEN-DHT-1105TABF HPH-DS06-02
C800
104p/1005
+5VSTB
+5VSTB +5VSTB
5 27 +5VSTB
R803 VCC1 AVCC +3V3D
17 37 KEY_ADC2
OPEN_103/1005 VCC2 (ADC0) PA0
38 36 KEY_ADC1
VSUB5, VSUB8 DELAY PORT VCC3 (ADC1) PA1
35 FRONT_LED_B
(ADC2) PA2 MAIN
C 40 34 LED_R C
PB0 (XCK/T0) (ADC3) PA3 PWB R805 R806
41 33 1 8 SPI_DAT0
PB1 (T1) (ADC4) PA4
MAIN PWB(11/22),(12/22,(13/22)) CEC_A R807 OPEN_000/1005 42
PB2 (AIN0/INT2) (ADC5) PA5
32 2 7 SPI_DAT1 (18/22) 472/1005 472/1005
MAIN PWB(2/22) MSP_ENABLE 43 31 3 6 SPI_DAT2
PB3 (AIN1/OC0) (ADC6) PA6 PR800
44 30 4 5
MAIN PWB(18/22) STBY_EN SPI_DAT3
1
MOSI PB4 (SS) (ADC7) PA7 OPEN_101*4/1005 Q802
1 29
MISO PB5 (MOSI) AREF FDV301N_NL
2
SCK_0 PB6 (MISO) SCL_STB 3 2
3 19 VCTP_SCL_3V3 MAIN PWB
PB7 (SCK) (SCL) PC0 SDA_STB 3 2
20
uCOM_UARXD R821 000/1005 9
(SDA) PC1
21 VCTP_INT
VCTP_SDA_3V3 (1/22),(3/22),(6/22),(13/22)
RA1
uCOM_UATXD R822 000/1005 PD0 (RXD) (TCK) PC2 VCTP_INT MAIN PWB(3/22) Q800
MAIN PWB(18/22) 10 22
TA1 VCTP_FAIL_IN PD1 (TXD) (TMS) PC3 R802 OPEN_101/1005
SPI_RST MAIN PWB(18/22) FDV301N_NL
11 23
R818 OPEN_101/1005 PD2 (INT0) (TDO) PC4 MUTE_0 R809 OPEN_000/1005
1
12 24 MUTE_CTRL MAIN PWB(3/22),(15/22)
MAIN PWB(18/22) SPI_SCL R827 000/1005 13
PD3 (INT1) (TDI) PC5
25 BLT R810 OPEN_000/1005
MAIN PWB(19/22) IR_SCART_TV
R804 OPEN_101/1005 PD4 (OC1B) (TOSC1) PC6 R811 101/1005
BLT_EN MAIN PWB(3/22),(16/22)
14 26 AC_DETECT MAIN PWB(15/22),(18/22)
SPI_CS R820 000/1005 PD5 (OC1A) (TOSC2) PC7
IR_IN 15
MAIN PWB(18/22) R819 OPEN_101/1005 PD6 (ICP)
SPI_SDA 16
PD7 (OC2) RESETn
4
RESETn
6
GND1 +5VSTB
18
GND2 R814 101/1005
28 7
GND3 XTAL2 R815 162/1005 KEY_ADC2
39 8
GND4 XTAL1 Y800
16MHZ/20pF/SMD R817 162/1005 KEY_ADC1
U801 2 1
ATMEGA324P-20AU
C809 C810 C807 C808
B 180p/1005 180p/1005 104p/1005 104p/1005 B
+5VSTB
R812
R813 103/1005
OPEN-103/1005
VCTP_FAIL_IN
R816
3
103/1005
1 Q803
MAIN PWB(3/22) VCTP_FAIL
KST4401
2
A
MAIN PWB ASS'Y (21/22) A
[MICRO CTRL(ATmega324)]
HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-21_0602_21/23_0.0
(No.YA607<Rev.001>)2-47 2-48(No.YA607<Rev.001>)
MAIN PWB CIRCUIT DIAGRAM (22/22) [Side jack]
5 4 3 2 1
R840
D 220/1005 D
SV_C
SV_C
RV840 R841
SV060305E101N 750/F/1005
MAIN PWB(4/22)
JP840
DUAE-9619 R842
4 220/1005
C SV_Y
5 3 SV_Y
SGND Y
6
SGND
7 1
SGND GND RV841 R843
8 2
SGND GND SV060305E101N 750/F/1005
C C
R844
220/1005
CVBS
CVBS
JP841 RV842 R845

IJBH3-SYNPH SV060305E101N 750/F/1005
1
2
CVBS 3 L840 R846
CIL21J1R8KNE 102/1005
4 AL_CVBS MAIN PWB(4/22)
AL_CVBS
B
5 B
AL 6
7 C840
8 RV843 102p/1005 R847
AR 9 SV060314B431N 224/1005
L841 R848
CIL21J1R8KNE 102/1005
AR_CVBS
AR_CVBS
C841
RV844 102p/1005 R849
SV060314B431N 224/1005
A A
MAIN PWB ASS'Y (22/22) [Side jack]

HU-71200010
5 4 3 2 1
lt-32da9bj_scaler-22_0602_22/23_0.0
(No.YA607<Rev.001>)2-49 2-50(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (1/18) [Terrestrial Tuner]
1 2 3 4 5 6
R130
104/1005 C131
U130 RF_AGC0 104p/1005
A A
DTT73200 IIC AS : Tuner : 0xC2
+5VT0 +5VT0
17 R131
GND1 16 OPEN-272/1005
GND2 15 R132
IF_AGC Ext
GND3
ANT_PWR
14 472/1005
GND4
RF_AGC
8
VCC1
VCC2
VCC3
SDA
IF1+
SCL
IF1-
R133 3
NC
AS
VT
+
104/1005 C132 1
104p/1005 2
COMP_OUT0 MPEG PWB(6/18)
MPEG PWB(6/18) RF_AGC_PWM0 -
10
11
12
13
U131A
9
LM393MX
4
OPEN-472/1005
R134
OPEN-272/1005
L130 BLM18PG300SN1D
+5VT
C130 C133 C134

220uF/16V/MVK/S IF0_NARROW-
104p/1005 102p/1005
MPEG PWB(6/18)
IF0_NARROW+
R135
B
*NET SWAP B
RF_AGC0
1
R136 OPEN-000/1005
TUNER0_AGC MPEG PWB(6/18)
L131 BLM18PG300SN1D TP130
+5VT
+5VT0 +5VT0
C135 C136 C137

220uF/16V/MVK/S 104p/1005 102p/1005
8
5 +
7 C138
6 - 104p/1005
U131B
R137 OPEN-330/1005 LM393MX
MPEG PWB TUNER0_SCL
4
(6/18) TUNER0_SDA
R138 OPEN-330/1005
C139 C140
C OPEN-330p/1005 OPEN-330p/1005 C
L132 BLM18PG300SN1D
+5VT
C141 C142 C143

220uF/16V/MVK/S 104p/1005 102p/1005
MPEG PWB ASS'Y (1/18)

[Terrestrial Tuner]
D
HU-71200005 D
All locations are from 130 to 179 in this page

1 2 3 4 5 6
lt-19db9bd_mpeg-05_0520_5/21_0.0
(No.YA607<Rev.001>)2-51 2-52(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (2/18) [DIGITAL SATELLITE TUNER]
5 4 3 2 1
JP230
DK-504-039(F-CON)
Input - F type
D D
U230
TDQY-P101F I2C AS : 0xC2
1 GND
2 GND
3 GND
4 GND 30
GND 29
ERROR/FEL
GND 28
STROUT
L/T out GND 27
RESET
GND
+3.3V
+3.3V
+3.3V
(Not used)
LNBB
LNBA
BCLK
SDA
SCL
F22
+3V3S
D/P
NC
NC
NC
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
R231
472/1005
nCHANNEL1_RST MPEG PWB(9/18)

R230 000/2012
L230
BLM18PG300SN1D
MPEG PWB LNB-A C231
LNB_OUT
(7/18) R232 R233 472/1005 105p
+3V3S
C OPEN-RXE065 C
2
IRQ_QPSK
C230 D230
105p LNBTVS6-221S
1 MPEG PWB(9/18)
R234 470/1005
+3V3S TS1_STR
R235 470/1005
C233 TS1_VLD
L231 R236 470/1005
104p/1005 TS1_CLK
BLM18PG300SN1D MPEG PWB(5/18)
TS1_DATA[7..0]
C232 C234 PR230 470*4/1005
470uF/16V/MVK/S 101p/1005 Demod_DATA4 1 8 TS1_DATA4
Demod_DATA5 2 7 TS1_DATA5
L232 Demod_DATA7 4 5 TS1_DATA7
BLM18PG300SN1D
PR231 470*4/1005
C235 C236 +3V3S Demod_DATA3 4 5 TS1_DATA3
100uF/16V/MVK/S 104p/1005
B LNB_22K MPEG PWB(7/18) B
R238 L233
R237 OPEN-472/1005 BLM18PG300SN1D
OPEN-472/1005
+3V3S
R239 101/1005
DTV_SDA
MPEG PWB(6/18),(7/18),(9/18),(11/18) R240 101/1005
DTV_SCL
C237
C238 100uF/16V/MVK/S
104p/1005
A MPEG PWB ASS'Y (2/18) A
[DIGITAL SATELLITE TUNER]

HU-71200005

5 4 3 2 1
lt-19db9bd_mpeg-07_0520_7/21_0.0
(No.YA607<Rev.001>)2-53 2-54(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (3/18) [CI2000/CI2002]
5 4 3 2 1
MPEG PWB
PR2 470*4
(5/18) PR3 470*4
CI1_A11 CI1_A[11..0] CI1_TDI0 CI1_MDI0 CI1_MDI[7..0]
PR1 OPEN-000*4 1 8
PR4 OPEN-000*4 CI1_A10 CI1_TDI1 2 7 CI1_MDI1
TS_DATA[7..0] TS_DATA0 CAD0 +5V +3V3 CI1_A9 CI1_TDI2 CI1_MDI2
1 8 3 6
TS_DATA1 2 7 CAD1 CI1_A8 CI1_TDI3 4 5 CI1_MDI3
TS_DATA2 3 6 CAD2 CI1_A7 CI1_TDI4 1 8 CI1_MDI4
TS_DATA3 4 5 CAD3 CI1_A6 CI1_TDI5 2 7 CI1_MDI5 MPEG
TS_DATA4 CAD4 R2 CI1_A5 MPEG CI1_TDI6 CI1_MDI6 PWB
1 8 3 6
TS_DATA5 2 7 CAD5 R1 OPEN-000 CI1_A4 PWB CI1_TDI7 4 5 CI1_MDI7 (4/18)
D
TS_DATA6 3 6 CAD6 000 CI1_A3 (4/18) D
TS_DATA7 4 5 CAD7 CI1_A2 CI1_TSTRI R3 470/1005 CI1_STRI
CI1_A1 CI1_TVLDI CI1_VLDI CI1_STRI
C1 R4 470/1005
TS_STR OPEN-000/1005 CASTR CI1_A0 CI1_TCLKI CI1_CLKI CI1_VLDI
R5 104p/1005 R6 470/1005
TS_STR TS_VLD OPEN-000/1005 CAVLD CI1_CLKI
R7
TS_VLD TS_CLK CACLK CI1_D7 CI1_D[7..0]
R8 OPEN-000/1005
CI1_TSTRI
CI1_MDO2
CI1_MDO1
CI1_MDO0
CI1_TVLDI
CI1_TCLKI
CI1_CLKO
TS_CLK CI1_D6
CI1_TDI0
CI1_TDI1
CI1_TDI2
CI1_TDI3
CI1_TDI4
CI1_TDI5
CI1_TDI6
CI1_TDI7
Option for Free to Air CI1_D5
CI1_D4 L1
CI1_D3 BLM18AG601SN1D
CI1_D2
CI1_D1
CI1_D0
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
CI1_MDO[7..0] CI1_MDO0
TDO3_B
TDO4_B
TDO5_B
TDO6_B
TDO7_B
TDO0_B
TDO1_B
TDO2_B
TDO2_A
TDO1_A
TDO0_A
TOA_CLK
TOB_CLK
TIA_STR
TIB_STR
TDI0_B
TDI1_B
TDI2_B
TDI3_B
TDI0_A
TDI1_A
TDI2_A
TDI3_A
TDI4_A
TDI5_A
TDI6_A
TDI7_A
TDI4_B
TDI5_B
TDI6_B
TDI7_B
test
TIB_VLD
TIA_VLD
TOB_VLD
TOB_STR
+5V
GND
TIB_CLK
TIA_CLK
CI1_MDO1
CI1_MDO2
CI1_MDO3
CI1_MDO4 CI1_MDO3 1 120 CI1_STRO
CI1_MDO5 CI1_MDO4 TDO3_A TOA_STR CI1_VLDO
2 TDO4_A TOA_VLD 119
CI1_MDO6 CI1_MDO5 3 118
CI1_MDO7 CI1_MDO6 TDO5_A GND TS_CLK PR5 470*4
4 TDO6_A TI_CLK 117
MPEG PWB(4/18) CI1_STRO CI1_MDO7 5 116 TS_STR PR6 470*4
CI1_STRO CI1_VLDO TDO7_A TI_STR TS_VLD TO_D0 CAD0 CAD[7..0]
CI1_VLDO 6 GND TI_VLD 115 1 8
CI1_CLKO 7 114 TS_DATA0 TO_D1 2 7 CAD1
CI1_CLKO ADDR10_B TI_D0 TS_DATA1 TO_D2 CAD2
8 /OE_B TI_D1 113 3 6
C
CI1_CD1 9 112 TS_DATA2 TO_D3 4 5 CAD3 C
CI1_CD1 CI1_CD2 /CE_B TI_D2 TS_DATA3 TO_D4 CAD4
CI1_CD2 10 D7_B TI_D3 111 1 8
11 110 TS_DATA4 TO_D5 2 7 CAD5 MPEG PWB(9/18)
CI1_WAIT D6_B TI_D4 TS_DATA5 TO_D6 CAD6
CI1_WAIT 12 D5_B TI_D5 109 3 6
CI1_IRQ 13 108 TS_DATA6 TO_D7 4 5 CAD7
CI1_IRQ D4_B TI_D6 TS_DATA7
14 D3_B TI_D7 107
15 106 TO_STR R9 470/1005 CASTR
+3V3 CI1_D3 3.3V D0_B TO_VLD CAVLD CASTR
16 105 R12 R10 470/1005
CI1_D4 D3_A D1_B TO_CLK CACLK CAVLD
17 104 103/1005 R11 470/1005
CI1_D5 D4_A D2_B CACLK
18 D5_A /WAIT_A 103 +5V
CI1_D6 19 102 CI1_WAIT
CI1_D7 D6_A /WAIT_B
20 101 CI1_D0
CI1_CE 21
D7_A
/CE_A
CI2000PB D0_A
D1_A 100 CI1_D1
CI1_A10 22 99 CI1_D2 Option for CI
CI1_OE ADDR10_A D2_A
23 /OE_A RESET_B 98
24 GND +3.3V 97 +3V3
CLK27M_CI 25 96
nRST 27CLK ADDR7_B
26 RESET ADDR6_B 95
ADDR16 27 94
+3V3 ADDR15 SEL1 ADDR5_B
28 93
ADDR3 29
SEL0 ADDR4_B
92
MPEG PWB(9/18),(11/18),(12/18),(15/18)
R13 ADDR2 HA2 ADDR3_B
30 HA1 ADDR2_B 91
472/1005 ADDR1 31 90 CI1_CE
nCI2002_CS HA0 ADDR1_B CI1_OE CI1_CE DATA[7..0] DATA0
R14 32 /HCE ADDR0_B 89 CI1_OE
HWE 33 88 CI1_WE DATA1
OPEN-472/1005 HOE /HWE GND CI1_A0 CI1_IOWR CI1_WE DATA2
R15 34 87
CI_IRQ /HOE ADDR0_A CI1_A1 CI1_IORD CI1_IOWR MPEG PWB(4/18) DATA3
OPEN-000/1005 35 86
CPU_WAIT ACK /HIRQ ADDR1_A CI1_A2 CI1_IORD DATA4
B 36 ACK ADDR2_A 85 B
DTACK 37 84 CI1_A3 CAS1RST DATA5
DTACK ADDR3_A CAS1RST
nDTACK DATA0 38 83 CI1_A4 CAS1PWR DATA6
HD0 ADDR4_A CAS1PWR
DATA1 39 82 CI1_A5 DATA7
HD1 ADDR5_A
DATA2 40 81 CI1_A6
ADDR6_A
ADDR11_B
ADDR11_A
R16 HD2
ADDR9_B
ADDR8_B
ADDR9_A
ADDR8_A
ADDR7_A
RESET_A
/IOWR_B
/IOWR_A
/IORD_B
/IORD_A
TO_STR
TO_CLK
TO_VLD
472/1005
PWR_B
PWR_A
/IRQ_B
/IRQ_A
CD1_B
CD2_B
CD1_A
CD2_A
TO_D7
TO_D6
TO_D5
TO_D4
TO_D3
TO_D2
TO_D1
TO_D0
/WE_B
/WE_A
ADDR16
GND
HD3
HD4
HD5
HD6
HD7
ADDR16
+5V
ADDR15
ADDR15 ADDR3
MPEG PWB(9/18),(11/18),(12/18),(15/18) ADDR3 ADDR2
+3V3
ADDR2
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ADDR1
CAS1PWR ADDR1
CI1_IOWR
CI1_IORD
CAS1RST
CI1_CD1
CI1_CD2
TO_STR
CI1_A11
TO_CLK
TO_VLD
CI1_IRQ
CI1_WE
CI1_A9
CI1_A8
CI1_A7
TO_D7
TO_D6
TO_D5
TO_D4
TO_D3
TO_D2
TO_D1
TO_D0
DATA3
DATA4
DATA5
DATA6
DATA7
Control signal for host interfacing
nCI2002_CS R17 OPEN-000/1005

MPEG PWB(9/18) nCI2002_CS
+3V3
HOE from CPU_OE
MPEG PWB(9/18),(11/18) F_OE C2
A
MPEG PWB(9/18),(10/18) nRST
nRST
CI_IRQ
from Reset
to CPU_PIO
nDTACK 4
Y
GND
3 104p/1005
R18
000
R19
OPEN-000 C3
C4
104p/1005
MPEG PWB ASS'Y (3/18) A
MPEG PWB(9/18) CI_IRQ
[CI2000/CI2002]
2 DTACK 104p/1005
CLK27M_CI A
MPEG PWB(10/18) CLK27M_CI from CPU CLOCK
5
CPU_WAIT +3V3 VCC
MPEG PWB(9/18) to CPU_WAIT 1 +5V +3V3
MPEG PWB
CPU_WAIT
F_WE/DQM0
HWE from CPU_BE0 C5 U2
NC
HU-71200005
(9/18),(11/18),(12/18) 104p/1005 ELM7S04B

5 4 3 2 1
lt-19db9bd_mpeg-02_0520_2/21_0.0
(No.YA607<Rev.001>)2-55 2-56(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (4/18) [CI SLOT1]
5 4 3 2 1
+12V +5V
D R40 JP40 D
472 A03G6B10ACE0F00
CI1_D[7..0]
3
1 A1 A35 35
CI1_D3 2 A2 A36 36
CI1_MDO[7..0] MPEG PWB(3/18)
Q40 CI1_D4 CI1_CD1 MPEG PWB(3/18) CI1_MDO3
3 A3 A37 37
1 IRLML2502 MPEG PWB(3/18) CI1_D5 4 A4 A38 38 CI1_MDO4
+5V CI1_D6 5 A5 A39 39 CI1_MDO5
C41 CI1_D7 6 A6 A40 40 CI1_MDO6
104p/1005 MPEG PWB(3/18) CI1_MDO7
2
CI1_A[11..0] CI1_CE 7 A7 A41 41
CI1_A10 8 A8 A42 42 R41 103
R42 +5V
MPEG PWB(3/18) CI1_OE 9 A9 A43 43
472/1005 C40 R43 CI1_A11 10 A10 A44 44
682p/1005 121/5025 C42
MPEG PWB(3/18) CI1_A9 CI1_IORD MPEG PWB
11 A11 A45 45 CI1_IOWR CI1_MDI[7..0]
3
104p/1005 CI1_A8 12 A12 A46 46 CI1_STRI
(3/18)
1 Q41 13 A13 A47 47 CI1_MDI0
CAS1PWR CI1_MDI1 MPEG PWB
R45 KST4401 14 A14 A48 48
472/1005 15 A15 A49 49 CI1_MDI2 (3/18)
CI1_WE CI1_MDI3
2
CI1_IRQ 16 A16 A50 50

17 A17 A51 51
MPEG PWB 18 A18 A52 52
(3/18) 19 A19 A53 53 CI1_MDI4
CI1_VLDI CI1_MDI5
MPEG PWB(3/18) CI1_CLKI 20 A20 A54 54
21 A21 A55 55 CI1_MDI6
CI1_A7 22 A22 A56 56 CI1_MDI7
CI1_A6 23 A23 A57 57
CI1_A5 24 A24 A58 58
CLKO_CI1 (A)
CI1_A4 CAS1RST
25 A25 A59 59 CI1_WAIT
C
CI1_A3 26 A26 A60 60 C
CI1_A2 27 A27 A61 61 MPEG PWB(3/18)
CI1_A1 28 A28 A62 62
CI1_A0 CI1_VLDO
29 A29 A63 63 CI1_STRO
CI1_D0 30 A30 A64 64 CI1_MDO0
CI1_D1 31 A31 A65 65 CI1_MDO1
CI1_D2 32 A32 A66 66 CI1_MDO2
R46 103 33 A33 A67 67
+5V
34 A34 A68 68
CI1_CD2 MPEG PWB(3/18)
69 GND N.C 71
70 GND N.C 72
+5V
+5V CI1_WAIT R47 103/1005

+5V
B B
PR40 CI1_CE R48 103/1005
103*4
CI1_MDO3 1 8 CI1_STRO R49 103/1005
R50 R51 +5V CI1_MDO2 2 7
L40 472/1005 472/1005 CI1_MDO1 3 6 CI1_VLDO R52 103/1005
BLM18AG601SN1D CI1_MDO0 4 5
CLKO_CI1 CI1_CLKO MPEG PWB CI1_MDO4 4 5 CLKO_CI1 R53 103/1005
CI1_CLKO
(3/18) CI1_CD1 C43 CI1_MDO5 (A) CLKO_CI1
3 6
CI1_CD2 104p/1005 CI1_MDO6 2 7 CI1_IRQ R54 103/1005
CI1_MDO7 1 8
C44 CI1_OE R55 103/1005
680p/1005 C45 C46 PR41
104p/1005 104p/1005 103*4 CI1_WE R56 103/1005
CI1_IORD R57 103/1005
CI1_IOWR R58 472/1005
# Pull-up of R67 is 472.
A
[CI SLOT1]
HU-71200005

5 4 3 2 1
lt-19db9bd_mpeg-03_0520_3/21_0.0
(No.YA607<Rev.001>)2-57 2-58(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (5/18) [TS Switch]
1 2 3 4 5 6
A A
MPEG PWB(6/18) TS0_DATA[7..0] TS_DATA[7..0] MPEG PWB(3/18)

TS0_DATA from TERRESTRIAL U80
SN74LVC244APWR
TS0_DATA0 2 18 R80 101/1005 TS_DATA0 TS0_DATA0 R105 OPEN-000/1005 TS_DATA0
TS0_DATA1 4 1A1 1Y1 16 R82 101/1005 TS_DATA1 TS0_DATA1 R106 OPEN-000/1005 TS_DATA1
2A4 2Y4
SEL_TS0 1 20 TS0_CLK R113 OPEN-000/1005 TS_CLK
1G +5V +3V3 TS0_STR
19 10 R114 OPEN-000/1005 TS_STR
2G DGND TS0_VLD R115 OPEN-000/1005 TS_VLD
C80
104p/1005
MPEG PWB(2/18) TS1_DATA[7..0]
TS1_DATA from SATELLITE
U81
SN74LVC244APWR
TS1_DATA0 2 18
TS1_DATA1 4 1A1 1Y1 16
TS1_DATA2 6 1A2 1Y2 14
B 1A3 1Y3 B
TS1_DATA3 8 12
TS1_DATA7 11 1A4 1Y4 9
TS1_DATA6 13 2A1 2Y1 7
TS1_DATA5 15 2A2 2Y2 5
TS1_DATA4 17 2A3 2Y3 3
2A4 2Y4
SEL_TS1 1 20
1G +5V +3V3
19 10
2G DGND
C81
104p/1005
U82
SN74LVC244APWR
2 18 R99 101/1005 TS_CLK
TS0_CLK 1A1 1Y1 TS_STR TS_CLK
MPEG PWB(6/18) 4 16 R100 101/1005
TS0_STR
6 1A2 1Y2 14 R101 101/1005 TS_VLD TS_STR MPEG PWB(3/18)
TS0_VLD 1A3 1Y3 TS_VLD
8 12
11 1A4 1Y4 9
TS1_STR 2A1 2Y1
MPEG PWB(2/18) 13 7
TS1_VLD 2A2 2Y2 +3V3 +3V3
15 5
TS1_CLK 2A3 2Y3
17 3
2A4 2Y4
C C
SEL_TS0 1 20
SEL_TS1 19 1G +5V 10
2G DGND
C82
104p/1005 R102 R103
103/1005 472/1005
R104
3
103/1005
1 MPEG PWB(9/18)
TS_SEL
Q80
KST4401
2
D
MPEG PWB ASS'Y (5/18) D
[TS Switch]
HU-71200005
1 2 3 4 5 6
lt-19db9bd_mpeg-04_0520_4/21_0.0
(No.YA607<Rev.001>)2-59 2-60(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (6/18) [DEMOD]
1 2 3 4 5 6

MPEG PWB ASS'Y (6/18) +3V3
+5VT0
[DEMOD]
+3V3DT
HU-71200005 R191
OPEN-473/1005
R192
OPEN-473/1005
R180 R181
A OPEN-103/1005 473/1005 A
R182
102/1005
MPEG PWB IF_AGC0 d_SCL
TUNER0_AGC IF_AGC0 DTV_SCL MPEG PWB
(1/18) nCHANNEL0_RST MPEG PWB(9/18) R189 OPEN-103/1005
(2/18),(7/18),
C180 d_SDA (9/18),(11/18)
104p/1005 MPEG PWB(1/18) RF_AGC_PWM0
C181
DTV_SDA
R190 OPEN-103/1005
104p/1005
Near By Tuner VDDD_3V3
C196 C197
VDDD_1V2 VDDDC_1V2 OPEN-104p/1005 OPEN-104p/1005
JP180
OPEN-53014-0410
+5VT0 DTV_SCL 1
49
48
47
46
45
44
43
42
41
40
39
38
37
DTV_SDA 2
2mm
3
GND
VDDD_1V2
VSSD
VDDD_3V3
VDDDC_1V2
VSSDC
AGC_TUN
AGC_IF
CLR_N
TDO
TCK
TDI
TMS
R183 C182 4
OPEN-104 OPEN-100p VDDA_3V3
*NET SWAP
1 36
C183 105p VDDA_3V3 TRST_N
B IF0_NARROW- B
2 35 d_SCL
VIM SCL
MPEG PWB(1/18) 3 34 d_SDA
C184 105p VIP SDA
IF0_NARROW+ VDDD_3V3 R184 103/1005
4 33
VSSA_3V3 SADDR +3V3DT
5 32 R185 OPEN-000/1005
VDDD_3V3 GPIO0 COMP_OUT0 MPEG PWB(1/18)
R186 C185 VDDA_1V2 6 U180 31
VSSA_3V3 VDDDC_1V2 VDDDC_1V2
OPEN-104 OPEN-100p
7 TDA10048HN 30
XIN VSSDC
8 29
XOUT VSSD MPEG PWB(5/18)
9 28
VDDA_1V2 VDDD_3V3 VDDD_3V3
10 27 T0_DO7
C186 300p/1005 VSSA_1V2 DO7 TS0_DATA[7..0]
PR180
11 26 T0_DO6 470*4/1005
VDDA_1V2 DO6
PSYNC/S_PSYNC
VDDDC_1V2 T0_DO7 1 8 TS0_DATA7
T0_DO5 T0_DO6 TS0_DATA6
OCLK/S_OCLK
Y180 12 25 2 7
DO0/S_UCOR
16MHZ/20pF/SMD VDDDC_1V2 DO5 T0_DO5 3 6 TS0_DATA5
DEN/S_DEN
DO2/GPIO1
DO3/GPIO2
DO4/GPIO3
DO1/S_DO
T0_DO4 4 5 TS0_DATA4
SDA_TUN
SCL_TUN
VSSDC
VSSD
C187 300p/1005 T0_DO2 2 7 TS0_DATA2
C 13 T0_DO0 4 5 TS0_DATA0 C
14
15
16
17
18
19
20
21
22
23
24
SMD Type(Sunny,30pF) PR181
470*4/1005
T0_DO4 T0_OCLK 5 4
T0_DO3 TS0_CLK
6 3 MPEG PWB
T0_DO2 T0_DEN 7 2
T0_DO1 T0_PSYNC 8 1
TS0_VLD (5/18)
T0_DO0 TS0_STR
T0_OCLK PR182
SDAT0 T0_DEN 470*4/1005
SCLT0 T0_PSYNC
+5VT0
R187 R188 +1V2DT VDDA_1V2 VDDD_1V2 VDDDC_1V2

272/1005 272/1005 +3V3DT VDDA_3V3 VDDD_3V3
L181
L180 BLM18PG121SN1D
BLM18PG121SN1D
SCLT0 PIN1
TUNER0_SCL PIN9
L182
MPEG PWB L183 BLM18PG121SN1D
(1/18) SDAT0 BLM18PG121SN1D
TUNER0_SDA
D D
L184
PIN5 PIN28 PIN46 BLM18PG121SN1D PIN48
C191
C188 104p/1005
104p/1005 PIN31 PIN12
C192 C193
104p/1005 104p/1005
C189 C190 C194 C195
104p/1005 104p/1005 104p/1005 104p/1005
1 2 3 4 5 6
lt-19db9bd_mpeg-06_0520_6/21_0.0
(No.YA607<Rev.001>)2-61 2-62(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (7/18) [LNB POWER]
5 4 3 2 1
If PIN3=GND,Iout=<450mA
D D
If PIN3=HIGH or Floating,Iout=<750mA
L281
D280 C282 BLM18PG300SN1D
1 2 OPEN-1N5819 224p/2012
+12V
1 2 L280 C281
BLM18PG300SN1D 220uF/50V/KMG
D281 L282
S1G/SMA SPC12080-220M
C280
R280 I2C address : 0x10 OPEN-224p/2012
OPEN-103 ( at. Addr = 0 V)
C283 C284
U280 224p/2012 220uF/50V/KMG
1 20
2 GND GND 19
C VO_RX V_UP
3 18 C
4 ISEL VCC 17
MPEG PWB(2/18) LNB_OUT VO_TX GATE
5 16 L283
EXTM SENSE ATS3550L
6 15
7 GND DSQOUT 14 1 8
ADDR DSQIN A C
8 13 2 7
9 BYP SCL 12 3 A C 6
DETIN SDA S D C285
10 11 4 5
GND GND G D 220uF/50V/KMG
LNBH21PD-TR U281
STS4DNFS30L Routing shortly!!
C286
224p/2012 HEAT-SINK R282 Need a low ESR
0R1/F/6432
R281
0R1/F/6432
R283 330/1005
DTV_SCL
B MPEG PWB(2/18),(6/18),(9/18),(11/18) B
R284 330/1005
DTV_SDA
C287
104p/2012 R285 472
LNB_22K MPEG PWB(2/18)
R286 R287 C288

472 103 103p/2012
A MPEG PWB ASS'Y (7/18) A
[LNB POWER]
HU-71200005

5 4 3 2 1
lt-19db9bd_mpeg-08_0520_8/21_0.0
(No.YA607<Rev.001>)2-63 2-64(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (8/18) [STI5518 Decoupling cap]
1 2 3 4 5 6
D D
# Vcc Cap is to be located in the vicinity of STi5518
+3V3 C331 C333 C335 C337

104p/1005 104p/1005 104p/1005 104p/1005
C338 C339
C330 106p/2012 106p/2012
106p/2012
C C
C332 C334 C336

104p/1005 104p/1005 104p/1005
+2V5_1V8 C341 C343 C345 C347

104p/1005 104p/1005 104p/1005 104p/1005
B B
C340
106p/2012
C342 C344 C346

104p/1005 104p/1005 104p/1005

A
[STI5518 Decoupling cap] A
HU-71200005

1 2 3 4 5 6
lt-19db9bd_mpeg-09_0520_9/21_0.0
(No.YA607<Rev.001>)2-65 2-66(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (9/18) [STI5518BQC]
1 2 3 4 5 6
R398 CPU_CE0 nCI2002_CS MPEG PWB(3/18) PWM1 R380 103/1005

MPEG PWB SYS_nRAS
220/1005 CPU_CAS0 nFLASHCS RSTn MPEG PWB(15/18) PWM2 R381 103/1005 +3V3
(3/18),(11/18), DATA[15..0] MPEG PWB(12/18) SYS_nCAS nROMCS CLK27M nRST MPEG PWB(3/18),(10/18) IRQ1
CPU_CAS1 R382 103/1005
(12/18),(15/18) DATA0 SYS_nCS0 CPU_WAIT MPEG PWB(3/18) PWM0 CLK27M IRQ2
1 8 MPEG PWB(10/18) R383 103/1005
DATA1 RD/nW PWM0
2 7 PR380
DQM1 MPEG PWB(12/18) SC_IRQ0 SC_IRQ0 MPEG PWB(14/18)
DATA2 3 6 330*4/1005
DATA3 4 5 F_WE/DQM0 MPEG PWB(3/18),(11/18),(12/18)
DATA4 1 8 FOE R384
DATA5 2 7 PR381 F_OE MPEG PWB L381 000 510/1005 330 --> 510
DATA6 3 6 330*4/1005 (3/18),(11/18) CPUCLK
DATA7 CPU_CLK
CPU_CAS1
CPU_CAS0
4 5
nCPU_CE1
TCK near PIN #118
CPU_CE0
VDD_PLL
DATA8
SC_IRQ0
VSS_PLL
1 8
CPUCLK
CLK27M
DATA9 TDI
2 7 PR382 R385
PWM0
PWM1
PWM2
D MPEG PWB(15/18) D
RSTn
TDO
IRQ1
IRQ2
DATA10
FOE
3 6 330*4/1005 OPEN-102/F/1005 MPEG PWB
DATA11 TMS
4 5 (12/18)
DATA12 nTRST
1 8
DATA13 2 7 PR383 +3V3 L382 000
DATA14 3 6 330*4/1005 +2V5_1V8 SMI_CLKOUT
SW_RST MPEG PWB MemClkIn
L380 DATA15 4 5
BLM18PG300SN1D
(10/18) near PIN #95
+2V5_1V8 R386
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDD_PLL 510/1005 101 --> 510
R387
C380 C381 OPEN-102/F/1005
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
VSS
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
CPU_CAS1
CPU_CAS0
CPU_RAS1
VSS
CPU_RAS0
CPU_CE1
CPU_CE2
CPU_CE3
CPU_WAIT
CPU_RW
CPU_BE1
CPU_BE0
IRQ0
IRQ1
IRQ2
RESET
CPU_SDRAMCLK
CPU_OE
VDD_2V5
VDD_3V3
VSS_PLL
VDD_PLL
VSS
PIXCLK
TCK
TDI
TDO
TRST
VSS
ADC _PCMCLK
VDD_2V5
PWM0
PWM1
PWM2
ADC_DATA
TMS
VDD_3V3
L383 104p/1005 106p/2012
BLM18PG300SN1D
VSS_PLL
157 DATA14 ADC_LRCLK 104 nCHANNEL0_RST
158 103 MPEG PWB(6/18)
MPEG PWB DATA15 ADC_SCLK SMI_D15 nCHANNEL1_RST MPEG PWB(2/18)
ADDR[21..1] +3V3 159 VDD_3V3 SMI_D15 102 MemDQ[15..0]
(3/18),(11/18),(12/18),(15/18) 160 101 SMI_D14
ADDR1 VSS SMI_D14 SMI_D13 SMI_D15 1 8 MemDQ15
161 ADDR1 SMI_D13 100
ADDR2 162 99 SMI_D12 SMI_D14 2 7 PR384 MemDQ14
L384 ADDR3 ADDR2 SMI_D12 SMI_D11 SMI_D13 3 6 330*4/1005 MemDQ13
163 ADDR3 SMI_D11 98
OPEN-BLM18PG300SN1D C382 ADDR4 164 97 SMI_D10 SMI_D12 4 5 MemDQ12
102p/1005 ADDR5 165
ADDR4 SMI_D10
96 SMI_D11 1 8 MemDQ11 MPEG PWB
+3V3 ADDR6 ADDR5 VSS SMI_CLKOUT MemDQ10 (12/18)
166 95 SMI_D10 2 7 PR385
ADDR7 ADDR6 SMI_CLKOUT SMI_D9 3 6 330*4/1005 MemDQ9
167 ADDR7 VDD_2V5 94
VDD_RGB ADDR8 168 93 SMI_D9 SMI_D8 4 5 MemDQ8
+2V5_1V8 ADDR9 ADDR8 SMI_D9 SMI_D8 SMI_D7 MemDQ7
L385 169 92 1 8
BLM18PG300SN1D ADDR10 ADDR9 SMI_D8 SMI_D7 SMI_D6 2 7 PR386 MemDQ6
C 170 ADDR10 SMI_D7 91 C
C384 171 90 SMI_D6 SMI_D5 3 6 330*4/1005 MemDQ5
106p/2012 +2V5_1V8 VDD_2V5 SMI_D6 SMI_D5 SMI_D4 4 5 MemDQ4
172 VSS SMI_D5 89
C383 ADDR11 173 88 SMI_D4 SMI_D3 1 8 MemDQ3
104p/1005 ADDR12 ADDR11 SMI_D4 SMI_D3 SMI_D2 2 7 PR387 MemDQ2
VSS_RGB ADDR13 175 86 SMI_D2 SMI_D1 3 6 330*4/1005 MemDQ1
L386 ADDR14 ADDR13 SMI_D2 SMI_D1 SMI_D0 4 5 MemDQ0
BLM18PG300SN1D ADDR15 177 84 SMI_D0
ADDR16 ADDR15 SMI_D0
178 ADDR16 VSS 83
ADDR17 179 82 MemClkIn
ADDR18 ADDR17 SMI_CLKIN
180 81
ADDR19
ADDR20
181
182
ADDR18
ADDR19 U380 VDD_3V3
SMI_DQMU 80
79
+3V3
DQMU
ADDR21 ADDR20 SMI_DQML DQML
183 ADDR21 SMI_WE 78 nSDWE
+3V3
MPEG PWB
184
185
VDD_3V3
VSS
STI5518BQCL SMI_CAS
SMI_RAS
77
76
nSDCAS
nSDRAS
MPEG PWB(12/18)
SC_IO 186 PIO0B0 SMI_CS1 75
(14/18) TP380 1 187 PIO0B1 SMI_CS0 74 nSD_CS0
1 188 73 SMI_A13 MemAD13
TP381 PIO0B2 SMI_A13
MPEG PWB 189 72 SMI_A12 MemAD12
SC_CLK PIO0B3 SMI_A12 SMI_A11
(2/18),(6/18), R388 R389 MPEG SC_RESET 190 PIO0B4 SMI_A11 71
472/1005 472/1005 191 70 SMI_A10 MemAD13
(7/18),(11/18) PWB SC_VCCN PIO0B5 SMI_A10 SMI_A0 MemAD12
192 69
L387 000 (14/18) 193
PIO0B6 SMI_A0
68 SMI_A1
SC_DET PIO0B7 SMI_A1 SMI_A2 SMI_A11 MemAD11
DTV_SDA 194 PIO1B0 SMI_A2 67
195 66 SMI_A3 SMI_A10 MemAD10
PIO1B1 SMI_A3 SMI_A9 MemAD9
196 PIO1B2 VSS 65 +2V5_1V8
B L388 000 197 64 SMI_A8 MemAD8 B
MPEG_TXD PIO1B3 VDD_2V5 SMI_A9 SMI_A7 MemAD7
DTV_SCL 198 VDD_2V5 SMI_A9 63
199 62 SMI_A8 SMI_A6 MemAD6
VSS SMI_A8 SMI_A7 SMI_A5 MemAD5
200 61
MPEG PWB MPEG_RXD
201
PIO1B4 SMI_A7
60 SMI_A6 SMI_A4 MemAD4
COMU_TXD PIO1B5 SMI_A6
(18/18) 202 59 SMI_A5 SMI_A3 MemAD3
MPEG PWB
TRIGGER_IN SMI_A5 SMI_A4 SMI_A2 MemAD2
203 TRIGGER_OUT SMI_A4 58 (12/18)
L389 204 57 SMI_A1 MemAD1
PIO2B0 SPDIF SPDIF SMI_A0
OPEN-BLM18PG300SN1D 205 56 MemAD0
COMU_RXD PIO2B1 LRCLK
C385 206 55
DAC_PCMOUT0
+3V3 PIO2B2 PCMCLK MemAD[13..0]
102p/1005 207 54
PIO2B3 PCMDATA2
208 53 MPEG PWB(18/18)
NRSS_OUT
NRSS_CLK
DAC_SCLK
PIO2B4 PCMDATA1
VDD_PCM
VDD_RGB
VDD_YCC
VSS_PCM
VDD_YCC
VSS_RGB
VREF_RG
VSS_YCC
VREF_YC
VDD_3V3
VDD_2V5
VDD_2V5
VDD_3V3
IREF_RG
NRSS_IN
IREF_YC
S_VALID
+2V5_1V8
S_SYNC
S_DATA
S_BCLK
L390
PIO2B5
PIO2B6
PIO2B7
PIO3B0
PIO3B1
PIO3B2
PIO3B3
PIO3B4
PIO3B5
PIO3B6
PIO3B7
PIO4B0
PIO4B1
PIO4B2
PIO4B3
PIO4B4
PIO4B5
PIO4B6
PIO4B7
CVBS
BLM18PG300SN1D C387 PCM_CLKIN
VSS
VSS
VSS
VSS
PCM_CLKIN
106p/2012
G
R
C
C386
B
Y
104p/1005 VSS_YCC MPEG PWB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
L391
1
2
3
4
5
6
7
8
9
BLM18PG300SN1D LR_CLK (16/18)
C388 PCM_DATA
L392 102p/1005 PCM_CLKOUT
BLM18PG300SN1D CAD0
VDD_RGB
VDD_YCC
VSS_RGB
VREF_RG
VSS_YCC
VREF_YC
IREF_RG
IREF_YC
VDD_PCM CAD1 VSS_PCM

+2V5_1V8
GREEN
CAD2 VDD_PCM

BLUE
1
RED
C390 CAD3
L393 106p/2012 CAD4
A
C389 CAD5 +3V3
MPEG PWB(2/18) A
BLM18PG300SN1D
TP382
TP383
104p/1005 VSS_PCM CAD6 R392 000/1005
R394 R395
CAD7
MPEG PWB CACLK

R390
470/1005
+3V3
R391
472/1005 +2V5_1V8
R393 000/1005
IRQ_QPSK
TS_SEL
MPEG_GPIO
[STI5518BQC]
CAVLD CI_IRQ
203/F/1005
VREF_YC
IREF_YC
203/F/1005
VREF_RG
IREF_RG MPEG PWB(3/18) CAD[7..0]
(3/18) CASTR
R396
R397
472/1005
472/1005
+3V3
HU-71200005
GREEN MPEG PWB(3/18)
MPEG PWB GREEN BLUE MPEG PWB LUMA
BLUE CHROMA MPEG PWB(18/18)
All locations are from 380 to 429 in this page (13/18) RED
RED (13/18) CVBS MPEG PWB(5/18)
1 2 3 4 5 6
lt-19db9bd_mpeg-10_0525_10/21_0.0
(No.YA607<Rev.001>)2-67 2-68(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (10/18) [STI5518 RESET & CLOCK]
1 2 3 4 5 6
+3V3
R431 R432
+3V3 U430 +3V3 472/1005 472/1005
D KIA7027AF D
GND
GND
VCC
OUT
R430 MPEG PWB(11/18) FLASH_nRST
Q430 Q431 R434
3
103/1005 KST4401 R433 KST4401 223/1005
1 102/1005 1
1
2
4
3
nRST MPEG PWB(3/18),(9/18)
nRST MPEG PWB(3/18),(9/18)
2
C430
104p/1005 C432
R435 105p/2012
OPEN-101/1005 C431
4.7uF/35V/MVK/S
+3V3
S430
OPEN-DHT-1105TABF R436 R437 R438
472/1005 472/1005 103/1005
R439
561/F/1005
MPEG PWB(3/18),(9/18) nRST
Q432 Q433
SW_RST MPEG PWB(9/18)
3
C KST4401 KST4401 C
3
R449 1 1
1 Q434 R440
MPEG PWB(18/18) DTT_RESET
C433 OPEN-561/F/1005
103/1005 KST4401 104p/1005 JTAG_RST
2
JTAG_RST MPEG PWB(15/18)
2
+3V3
R441
103/1005 +3V3
R442 U431 L430

472/1005 OPEN-BSCH319V9CD-27.000M-PB 000
1 3
MPEG PWB(9/18) PWM0 VI CLK CLK27M MPEG PWB(9/18)
4 2 R443
R444 C434 VCC GND 101/1005 R445
OPEN-103/1005 104p/1005 681/1005
C435 C436
102p/1005 106p/2012
B B
L431 R446
000 101/1005
CLK27M_CI MPEG PWB(3/18)
Tunning Value R447

U432 681/1005
ICS7150GLF
1 5
XTB QO
C437 +3V3
3R3p/1005
8 6
Y430 XT VDD
27MHz/13.5pF/SMD
3
VSS
STB
VC
NC
R448 C438
103 103p
2
7
4
A A
[STI5518 RESET & CLOCK]

HU-71200005

1 2 3 4 5 6
lt-19db9bd_mpeg-11_0520_11/21_0.0
(No.YA607<Rev.001>)2-69 2-70(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (11/18) [FLASH & EEPROM]
1 2 3 4 5 6
+3V3
D D
C480 C481 C482

104p/1005 104p/1005 106p/2012
13
37
U480
VPP
VCC
MPEG PWB
(3/18),(9/18),(12/18),(15/18) ADDR[21..1] ADDR1 DATA0 DATA[15..0] MPEG PWB(3/18),(9/18),(12/18),(15/18)
25 29
ADDR2 A0 D0 DATA1
24 31
ADDR3 23 A1 D1 33 DATA2
ADDR4 A2 D2 DATA3
22 35
ADDR5 21 A3 D3 38 DATA4
ADDR6 A4 D4 DATA5
20 40
ADDR7 A5 D5 DATA6
19 42
ADDR8 18 A6 D6 44 DATA7 U481 +3V3
ADDR9 A7 D7 DATA8 AT24C64CN
8 30
ADDR10 7 A8 D8 32 DATA9 1 8
ADDR11 A9 D9 DATA10 A0 VCC
6 34 2 7
JS28F320C3TD70
ADDR12 A10 D10 DATA11 A1 WP
5 36 3 6
ADDR13 A11 D11 DATA12 A2 SCL DTV_SCL MPEG PWB
C 4 39 4 5 C
ADDR14 A12 D12 DATA13 VSS SDA DTV_SDA (2/18),(6/18),(7/18),(9/18)
3 41
ADDR15 2 A13 D13 43 DATA14 C483
ADDR16 A14 D14 DATA15 104p/1005
1 45
ADDR17 A15 D15
48
ADDR18 17 A16 +3V3
ADDR19 A17
16
ADDR20 15 A18 47
ADDR21 A19 VCCQ
10 14
A20 WP
9 12
A21 RP FLASH_nRST MPEG PWB(10/18)
R480
000/1005 C484
104p/1005
MPEG PWB(3/18),(9/18),(12/18) 11
F_WE/DQM0 WE
MPEG PWB(15/18) 26
nFLASH_CS1 CE
MPEG PWB(3/18),(9/18) 28
F_OE OE
GND
GND
27
46
B B
A
[FLASH & EEPROM]

HU-71200005
1 2 3 4 5 6
lt-19db9bd_mpeg-12_0525_12/21_0.0
(No.YA607<Rev.001>)2-71 2-72(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (12/18) [SDRAM (EMI & SMI)]
1 2 3 4 5 6
L530 +3V3_0 L531 +3V3_1

BLM18PG300SN1D BLM18PG300SN1D
+3V3 +3V3
C530 C531 C532 C533 C534 C535 C536 C537 C538 C539 C540 C541
D 104p/1005 104p/1005 104p/1005 104p/1005 104p/1005 106p/2012 104p/1005 104p/1005 104p/1005 104p/1005 104p/1005 106p/2012 D
# Shared Memory
(MPEG & System)
+3V3_0
U530 U531
MPEG PWB(9/18) MemDQ[15..0] +3V3_1
MPEG PWB DATA[15..0]
(3/18),(9/18),(11/18),(15/18) DATA0 2 37 MemDQ0 2 37
DATA1 4 DQ0 CKE MemDQ1 4 DQ0 CKE
DATA2 5 DQ1 1 MemDQ2 5 DQ1 1
DATA3 7 DQ2 VCC 14 MemDQ3 7 DQ2 VCC 14
DATA6 11 DQ5 VCCQ 9 MemDQ6 11 DQ5 VCCQ 9
DATA9 44 DQ8 VCCQ MemDQ9 44 DQ8 VCCQ
DATA10 45 DQ9 36 MemDQ10 45 DQ9 36
C DQ10 NC DQ10 NC C
DATA11
K4S281632I-UC75
47 40 MemDQ11 47 40
DATA12 48 DQ11 NC MemDQ12 48 DQ11 NC
K4S641632K-UC60
DATA13 50 DQ12 MemDQ13 50 DQ12
DATA14 51 DQ13 28 MemDQ14 51 DQ13 28
DATA15 53 DQ14 VSS 41 MemDQ15 53 DQ14 VSS 41
MPEG PWB DQ15 VSS 54 MPEG PWB(9/18) MemAD[13..0] DQ15 VSS 54
ADDR[21..1] VSS VSS
(3/18),(9/18),(11/18),(15/18) VSSQ
6
VSSQ
6
ADDR1 23 12 MemAD0 23 12
ADDR2 24 A0 VSSQ 46 MemAD1 24 A0 VSSQ 46
ADDR3 25 A1 VSSQ 52 MemAD2 25 A1 VSSQ 52
ADDR4 26 A2 VSSQ MemAD3 26 A2 VSSQ
ADDR5 29 A3 MemAD4 29 A3
ADDR12 35 A10 MemAD11 35 A10
ADDR15 21 A11 MemAD12 21 A11
ADDR16 20 A12 MemAD13 20 A12
A13 A13
15 15
MPEG PWB(3/18),(9/18),(11/18) F_WE/DQM0
39 DQML DQML
39 DQML
DQM1 DQMU DQMU DQMU
18 18
SYS_nRAS /RAS nSDRAS /RAS
17 17
MPEG PWB(9/18) SYS_nCAS
19 /CAS MPEG PWB(9/18) nSDCAS
19 /CAS
B SYS_nCS0 /CS nSD_CS0 /CS B
16 16
RD/nW CPU_CLK_IN /WE nSDWE /WE
38 38
CLK MemClkIn CLK
A12 = BA1, A13 = BA0

R530
000/1005
U532
1 6 CPU_CLK_IN
MPEG PWB(9/18) CPU_CLK 1A 1Y
2 5
GND VCC +5V
3 4
2A 2Y
OPEN-74LVC2GU04GV
A
if two sdram is in bank 0 MPEG PWB ASS'Y (12/18) A
CS 0
Sub Bank 0
notCPU_CAS[1] CS 1
Sub Bank 1
notCPU_RAS[1] [SDRAM (EMI & SMI)]
CAS 0 notCPU_CAS[0] CAS 1 notCPU_CAS[0] HU-71200005
RAS 0 notCPU_CE[0] RAS 1 notCPU_CE[0]

1 2 3 4 5 6
lt-19db9bd_mpeg-13_0520_13/21_0.0
(No.YA607<Rev.001>)2-73 2-74(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (13/18) [VIDEO AMP]
5 4 3 2 1
L580
BLM18PG300SN1D
+5V +5VA
C580 C582
D 104p/1005 C581 104p/1005 D
100uF/16V/MVK/S
+5VA
U580A C583
TSH74CD 104p/1005
4
R581
3 750/F/1005
CVBS +
1
MPEG_CVBS
R582 471/F 2
-
R580
331/1005
11
R583
R584 OPEN-750/F/1005
C584 471/F
OPEN-103p/1005
U580B
C C585 TSH74CD C
4
220p/1005 R585
5 750/F/1005
RED +
7
MPEG_R
R586 471/F 6
-
R587
331/1005
11
R588
R589 OPEN-750/F/1005
C586 471/F
OPEN-103p/1005
MPEG PWB(18/18)
C587
U580C 220p/1005
TSH74CD
4
R590
10 750/F/1005
MPEG PWB(9/18) GREEN +
8
MPEG_G
R591 471/F 9
-
R592
331/1005
11
R593
OPEN-750/F/1005
C588 R594
B OPEN-103p/1005 471/F B
U580D
C589 TSH74CD
4
220p/1005 R595
12 750/F/1005
BLUE +
14
MPEG_B
R597 R596 471/F 13
-
331/1005
11
R598
R599 OPEN-750/F/1005
C590 471/F
OPEN-103p/1005
MPEG PWB(9/18)
C591
220p/1005
LUMA CHROMA
R601
R600 331/1005
331/1005
A
[VIDEO AMP]
HU-71200005
5 4 3 2 1
lt-19db9bd_mpeg-14_0520_14/21_0.0
(No.YA607<Rev.001>)2-75 2-76(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (14/18) [SMART CARD VCC DETECTOR, Smart Card Connector]
1 2 3 4 5 6
+3V3 U630 +3V3

OPEN-KIA7029AF
U631
GND
GND
VCC
OUT
OPEN-ELM7S04B
D D
+3V3
R630 1
103 NC
1
2
4
3
5
VCC
2
A
4 MPEG PWB(9/18)
Y SC_IRQ0
3
GND C632 To STi5518 IRQ0
C630 C631 OPEN-104p
OPEN-104p OPEN-104p
C L660 C
OPEN-BLM18PG300SN1D
+3V3
R631
000
C660 C661
OPEN-104p/1005 OPEN-104p/1005
L661
OPEN-BLM18PG300SN1D C664
OPEN-100uF/16V/MVK/S
+5V
C662
OPEN-104p/1005
B B
MPEG PWB ASS'Y (14/18) C663

OPEN-104p/1005
[SMART CARD VCC DETECTOR, Smart Card Connector]
HU-71200005
1. +3.3V
L662
OPEN-BLM18PG300SN1D 1 2. +5V
2 3. GND
L663 OPEN-000 3
SC_DET 4 4. DETECT
L664 OPEN-BLM18AG601SN1D
SC_IO 5 5. IO
MPEG PWB(9/18)
L665 OPEN-000
SC_RESET 6
SC_VCCN
L666 OPEN-000
7
6. RESET
2mm
SC_CLK 8 7. VCC_EN
L667 9
A
OPEN-BLM18AG601SN1D L668 8. CLOCK A
OPEN-BLM18PG300SN1D 9. GND
contact to JP660
OPEN-53014-0910
connector side

1 2 3 4 5 6
lt-19db9bd_mpeg-15_16_0520_15/21_0.0
(No.YA607<Rev.001>)2-77 2-78(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (15/18) [ROM & JTAG Connector]
1 2 3 4 5 6
TP700 TP701 TP702 TP703 TP704 TP705 TP706 TP707 TP708 TP709 TP710 TP711 TP712 TP713 TP714 TP715 TP716 TP717 TP718 TP719
TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 MPEG PWB
MPEG PWB JP700
D DATA[15..0] (3/18),(9/18), D
(3/18),(9/18), ADDR[21..1]
42 (11/18),(12/18)
(11/18),(12/18)
1
ADDR1 20 40 DATA0
ADDR2 19 39 DATA1
ADDR3 18 38 DATA2
ADDR4 17 37 DATA3
ADDR5 16 36 DATA4
ADDR6 15 35 DATA5
ADDR7 14 34 DATA6
ADDR8 13 33 DATA7
ADDR9 12 32 DATA8
ADDR10 11 31 DATA9
ADDR11 10 30 DATA10
ADDR12 9 29 DATA11
ADDR13 8 28 DATA12
ADDR14 7 27 DATA13
ADDR15 6 26 DATA14
ADDR16 5 25 DATA15
ADDR17 4 24 nFLASH_CS1
ADDR18 23 PE nFLASH_CS1 MPEG PWB(11/18)
3
ADDR19 2 22
ADDR20 1 21
41 43
1
1
+5V
C C
C700
TP720 TP721 TP722 TP723 TP724 TP725 TP726 TP727 TP728 TP729 104p/1005 TP730 TP731 TP732 TP733 TP734 TP735 TP736 TP737
TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10 OPEN-15921440 TP10 TP10 TP10 TP10 TP10 TP10 TP10 TP10
C701
100uF/16V/MVK/S
+3V3
# Located on the Bottom Layer #
TP738 TP739 TP740 TP741

TP15 TP15 TP15 TP15
R701 R702 R703
103/1005 103/1005 103/1005
+5V +3V3
1
1
B JP701 B
2 1 TMS
4 3 TCK
6 5 TDI MPEG PWB(9/18)
R700 R704
8 7 TDO
222/1005 222/1005
10 9 JTAG_RST MPEG PWB(10/18)
12 11 nTRST MPEG PWB(9/18)
nFLASH_CS1 TP742 TP743 TP744 OPEN-2110-DS12-G
TP10 TP10 TP10
3
PE 1 Q700
KST4401 R705
103/1005
1
1
2
MPEG PWB(9/18) nROMCS

ADDR21 1
MPEG PWB(9/18),(11/18) ADDR21 2
MPEG PWB(9/18) nFLASHCS 3
4 2mm
JP702
OPEN-79107-7001
A
[ROM & JTAG Connector]

HU-71200005

1 2 3 4 5 6
lt-19db9bd_mpeg-17_0520_17/21_0.0
(No.YA607<Rev.001>)2-79 2-80(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (16/18) [Audio DAC]
1 2 3 4 5 6
A A
U750
PR750 WM8521HC C750 R751
330*4 10uF/25V/BXE/S 471/1005
1 8 3 10
PCM_CLKIN DIN VOUTL MPEG_AUD_L
2 7 2
LR_CLK LRCLK MPEG PWB(18/18)
MPEG PWB(9/18) 3 6 4
+3V3 PCM_DATA BCLK
4 5 13 6
PCM_CLKOUT MCLK VOUTR MPEG_AUD_R
+12V
C751 R752
R750 472/1005 12 10uF/25V/BXE/S 471/1005
R753 FORMAT
11 9
000/1005 5 DEEMPH AVDD
MUTE
7
AGND
14
L750 DVDD
B BLM18PG300SN1D C753 1 8 B
C752 104p/1005 DGND CAP
106p/2012 C756 C757 C755
104p/1005 104p/1005 10uF/25V/BXE/S
C754
10uF/25V/BXE/S
* MODE SETTING *
MODE SETTING
SAMPLING 256FS
FORMAT I2S
* MUTE CONTROL *
C C
MUTE FUNCTION
LOW MUTE OFF
HIGH MUTE ON

D
[Audio DAC] D
HU-71200005

1 2 3 4 5 6
lt-19db9bd_mpeg-18_0520_18/21_0.0
(No.YA607<Rev.001>)2-81 2-82(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (17/18) [Regulators]
1 2 3 4 5 6
TDA10048_+3.3V TDA10048_+1.2V
+5V +3V3DT +1V2DT
D U801 U802 D
LD1117AL-ADJ LD1117AL-ADJ
3 2 3 2
VIN VO 4 VIN VO 4
ADJ
ADJ
TAP TAP
R800
C802 121/F/1005
1
+5V MAX 3A 106p/2012 C806 C804 C807
+3V3 106p/2012 100uF/16V/MVK/S 106p/2012
U800
C813 C814 LD29300P2M R802 C815
104p/1005 104p/1005 122/F/1005 101p/1005 C803
2 VI VO 4
R801 100uF/16V/MVK/S
GND
GND
GND
GND
GND
SD
5 201/F/1005
SEN C817
104p/1005
C812
1
3
6
7
8
9
100uF/16V/MVK/S
C816
100uF/16V/MVK/S
+5V
R803
681/F/1005
R804
C 102/1005 C
+7V U803 +5VT +5VT0
BA50BC0WFP
2 4
VIN VOUT L805 BLM18PG121SN1D
GND
NC
NC
C818 1
CTL
OPEN-4.7uF/35V/MVK/S
C810 C811
106p/2012 106p/2012 C809
5
100uF/16V/MVK/S
Using forming type

+3V3 +2V5_1V8
D800
1N5402-U
1 2 TDQY-P101F_+3.3V
B +5V +3V3S B
U804
LD1117AL-ADJ C819
C823 C822 C824 100uF/16V/MVK/S
104p/1005 470uF/16V/MVK/S 104p/1005 3 2
VIN VO 4
ADJ
TAP
R806 C820
C821 121/F/1005 106p/2012
1
106p/2012
R807
201/F/1005
A A
MPEG PWB ASS'Y (17/18) [Regulators]

HU-71200005

1 2 3 4 5 6
lt-19db9bd_mpeg-19_0520_19/21_0.0
(No.YA607<Rev.001>)2-83 2-84(No.YA607<Rev.001>)
MPEG PWB CIRCUIT DIAGRAM (18/18) [Interface Connector]
5 4 3 2 1
+5V
C901
104p/1005
D D
JP901
R909 OPEN-53014-0410
000/1005
MPEG_TXD 1
MPEG_RXD 2
2mm
3
R910 4
222/1005
R911
332/1005
+12V
MAIN PWB(19/22)
C904
JP710
100uF/25V/BXE/S
JP900
C
SMH200-40NND C
MPEG_AUD_R 20 40
MPEG PWB(16/18) C905
MPEG_AUD_L 19 39 104p/1005
R900 000/1005 18 38
MPEG_B 17 37
R901 000/1005 16 36 L902 HH-1M3216-501JT
MPEG_G 15 35
MPEG PWB(13/18) 14 34
R902 000/1005
MPEG_R 13 33
R903 000/1005 12 32
MPEG_CVBS 11 31
10 30 SPDIF MPEG PWB(9/18)
R904 000/1005
MPEG_TXD 9 29 L900 BLM18PG300SN1D
R905 000/1005
MPEG_RXD 8 28 +7V
MPEG PWB(9/18) 7 27
R907 000/1005 R906 000/1005
COMU_TXD 6 26
R908 000/1005
COMU_RXD 5 25 C906
4 24 100uF/25V/BXE/S
MPEG PWB(10/18) DTT_RESET 3 23
L901 HH-1M3216-501JT 2 22 C900
+5V 1 21 104p/1005
B B
MPEG_GPIO MPEG PWB(9/18)
C902 C903
104p/1005 100uF/25V/BXE/S

A [Interface Connector] A
DGND GND_A GND_D HU-71200005

5 4 3 2 1
lt-19db9bd_mpeg-20_0520_20/21_0.0
(No.YA607<Rev.001>)2-85 2-86(No.YA607<Rev.001>)
IR PWB CIRCUIT DIAGRAM
1 2 3 4 5 6
A A
U1
GND
SIG
Vcc
S
S
+5VSTB
1
2
3
4
5
ROM-L0138SH14
MAIN PWB(18/22)
B JP682 B
JP1
TP1 1 TP10 L1 OPEN-000 +5VSTB
7 6
8 5
1.25mm
TP2 1 TP10 L2 OPEN-000 IR_OUT

4 TP4 1 TP10
3 R1
2 TP3 1 TP10 L3 OPEN-000 RED IR_OUT
1
12505WR-06A
000/2012
RV1
1
SV060305E101N C1 C2
105p 105p
RV2 D1 SLR124-WOS
SV060305E101N
2
C C
D
IR PWB ASS'Y D
HU-72200004
1 2 3 4 5 6
lt-32_42dx9_sub-02_0602_2/5_0.0
(No.YA607<Rev.001>)2-87 2-88(No.YA607<Rev.001>)
KEY PWB CIRCUIT DIAGRAM
1 2 3 4 5 6
MAIN PWB(18/22)
JP681
JP2
TP5 1 TP10 KEY2
6 5
1.25mm
7 4 TP6 1 TP10 KEY1
3
2 TP7 1 TP10
A 1 A
12505WR-05P
RV3 RV4
KEY1 SV060305E101N KEY2 SV060305E101N
R3 R4
OPEN-302/1005 OPEN-302/1005
R5 R6
271/F/1005 271/F/1005
S1 TV/AV S2 CH+
B 2 3 2 3 B
1 4 1 4
DHT-1106T DHT-1106T
R7 R8
471/1005 471/1005
S3 MENU S4 CH-
2 3 2 3
1 4 1 4
DHT-1106T DHT-1106T
R9
102/1005 R12
102/1005
S5 VOL-
2 3
1 4
DHT-1106T
R13
C R11 272/1005 C
272/1005
S7 VOL+ S6 STANDBY
2 3 2 3
1 4 1 4
DHT-1106T DHT-1106T
ADC1 SW Setting Point Center Voltage Min Voltage Max Voltage

TV/AV TV/AV/OK 0V~1.15V 0.750802139 0.654329977 0.85828112
MENU/OK Menu 1.16V~2.15V 1.644444444 1.457331095 1.846939486
VOL- VOL - 2.16V~3.25V 2.708982036 2.449990999 2.980406334
VOL+ VOL + 3.26V 4.5V 3.822516556 3.532878942 4.117521838
ADC2 SW Setting Point Center Voltage Min Voltage Max Voltage
D CH+ CH + 0V~1.15V 0.750802139 0.654329977 0.85828112 D
CH- CH - 1.16V~2.15V 1.644444444 1.457331095 1.846939486 KEY PWB ASS'Y

Not Used 2.16V~3.25V 2.708982036 2.449990999 2.980406334
STANDBY Power 3.26V 4.5V 3.822516556 3.532878942 4.117521838 HU-72200003
1 2 3 4 5 6
lt-32_42dx9_sub-03_0602_3/5_0.0
(No.YA607<Rev.001>)2-89 2-90(No.YA607<Rev.001>)
LED PWB CIRCUIT DIAGRAM
1 2 3 4 5 6
A A
LED1
BLUE LB580A
MAIN PWB(18/22)
JP683
B JP3 B
6 5 R2
1
1.25mm
7 4 FRONT_BLUE
3 TP8 1 TP10 FRONT_BLUE
2 TP9 1 TP10 000/2012
1
12505WR-05P
RV5
SV060305E101N
C C
D D
LED PWB ASS'Y

HU-72200017
1 2 3 4 5 6
lt-32_42dx9_sub-04_0602_3/5_0.0
(No.YA607<Rev.001>)2-91 2-92(No.YA607<Rev.001>)
PATTERN DIAGRAMS
MAIN PWB PATTERN [SOLDER SIDE]
TOP
(No.YA607<Rev.001>)2-93 2-94(No.YA607<Rev.001>)
MAIN PWB PATTERN [PARTS SIDE]
TOP
(No.YA607<Rev.001>)2-95 2-96(No.YA607<Rev.001>)
MPEG PWB PATTERN [SOLDER SIDE]
TOP
(No.YA607<Rev.001>)2-97 2-98(No.YA607<Rev.001>)
MPEG PWB PATTERN [PARTS SIDE]
TOP
(No.YA607<Rev.001>)2-99 2-100(No.YA607<Rev.001>)
IR PWB PATTERN [SOLDER SIDE] LED PWB PATTERN [SOLDER SIDE]
TOP FRONT
IR PWB PATTERN [PARTS SIDE] LED PWB PATTERN [PARTS SIDE]
TOP FRONT
KEY PWB PATTERN [SOLDER SIDE]
TOP
KEY PWB PATTERN [PARTS SIDE]
TOP
(No.YA607<Rev.001>)2-101 2-102(No.YA607<Rev.001>)
Victor Company of Japan, Limited
Display category 12, 3-chome, Moriya-cho, Kanagawa-ku, Yokohama-city, Kanagawa-prefecture, 221-8528, Japan
(No.YA607<Rev.001>)
Printed in Japan
VPT

JVC LT 32da9bj LT 32da9bu SM

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

JVC LT 32da9bj LT 32da9bu SM

Hochgeladen von

Copyright:

Verfügbare Formate

Preliminary

COPYRIGHT © 2008 Victor Company of Japan, Limited. No.YA607<Rev.001>

: Connector : Wrapping or soldering

USING P.W. BOARD

MAIN P.W. BOARD HU-71200010 φ

MPEG P.W. BOARD HU-71200005 φ

IR P.W. BOARD HU-72200004 φ

KEY P.W. BOARD HU-72200003 φ

TOP DIGITAL TUNER

LED PWB JP3

SCART2 RESETQ Y60

Input - IEC type

C781 C782 C783 C784 R793 OPEN-000/1005

All location are from 770 to 799

C43 C42 L15

104p/1005 106p/2012 BLM31PG121SN1L

MAIN PWB ASS'Y (2/22)

+3V3_VCTP +3V3_VCTP +3V3_VCTP

MAIN PWB(11/22) HPD2 159

OPEN-473/1005 XTALOUT OPEN-53014-0410 OPEN-104p/1005

MAIN PWB ASS'Y (3/22)

MAIN PWB GB[7..0]

MAIN PWB ASS'Y (4/22) CVBS COMPONENT PC

All location are from 120 to 179

MAIN PWB(4/22) C185

[Scart Video AMP]

C200 C202 C203 C204 C201

C205 C206 C207

R200 203/F/1005 C216 105p 11

MAIN PWB ASS'Y (6/22)

SC1_GREEN MAIN PWB(6/22)

L235 C235 R245

L236 C237 R246

All location are from 230 to 259

SC2_GREEN MAIN PWB(6/22)

L265 C265 R275

L266 C267 R276

MAIN PWB ASS'Y (8/22)

All location are from 260 to 289

+5VSTB +5VSTB +5VSTB

1 2 OPEN_750/F/1005 HSYNC1 R298 000/1005 5 6 9 8 PC_HSYNC

OPEN_472/1005 OPEN_472/1005 R307

Component_A/V Input +5V

COMP_Pr C330 OPEN_105p COMP_Pr_0 COMP_Pr_0

MAIN PWB ASS'Y (10/22)

+5VSTB C372 C373 +5VSTB C374

U371 R378 R379

MAIN PWB ASS'Y (11/22)

U420 R424 R425

MAIN PWB ASS'Y (12/22)

C472 C496 C470 C471 C475 C493 C476

MAIN PWB ASS'Y (13/22)

All location are from 470 to 509

A MAIN PWB ASS'Y (14/22) A

[HDMI Audio DAC]

C581 C583 C584 C585

All location are from 580 to 629

For 32inch CMO 50/60Hz switching

R643 PANEL CONTROL

Module Power Samsung LPL&CPT MODULE_POWER

MAIN PWB ASS'Y (16/22)

All location are from 630 to 659

MAIN PWB ASS'Y (17/22) [RS232]