BASIC ELECTRONICS SHOBHA A S

COURSE NAME WITH CODE: BASIC ELECTRONICS COURSE OUTCOMES:

CO25.1:
FACULTY NAME: SHOBHA A S Understand the characteristics operations of
DATE: different electronic components.
LECTURE HOUR:
OBJECTIVES OF THE LECTURE:
 Understand the construction and basic operation of bipolar junction transistor.
 Understand the active region, the saturation region and cut-off region of the BJT operation

BJT physical structure and operation

A transistor is a sandwich of one type of semiconductor (P-type or n-type) between two
layers of other types.
Physical structure of a transistor:
Transistors are classified into two types;
1. pnp transistor: pnp transistor is obtained when a n-type layer of silicon is
sandwiched between two p type silicon material.
2. npn transisitor: npn transistor is obtained when a p-type layer of silicon is
sandwiched between two n- type silicon materials.
Figure1.1 shows the symbolic representations of a transistor which is equivalent of two diodes
connected back to back.
JE JC JE JC

E C

n p n

A B

Fig 1: Symbolic representation

pnp npn
Fig 2: Sche matic representation
The three portions of transistors are named as emitter, base and collector. The junction between emitter
and base is called emitter-base junction while the junction between the collector and base is called
collector-base junction.
The base is thin and tightly doped, the emitter is heavily doped and it is wider when compared to base,
the width of the collector is more when compared to both base and emitter.

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 In order to distinguish the emitter and collector an arrow is included in the emitter. The direction of the
arrow depends on the conventional flow of current when emitter base junction is forward biased.

Ope rating regions of a transistor

Unbiased Transistor
 When the three terminal of the transistor kept open it is called unbiased transistor.
 Since transistor is like two p-n junction diodes connected back to back, there are
depletion region at both the junctions- Emitter junction and Collector junction.
 During diffusion process, depletion region penetrates more deeply into the lightly doped
side in order to include an equal number of impurity atoms in the each side of the
junction.
 As shown in the figure, depletion region at emitter junction penetrates less in the heavily
doped emitter and extends more in the base region.
 Similarly, depletion region at collector junction penetrates less in the heavily doped
collector and extends more in to base region.
 As collector is slightly less doped than the emitter, the depletion layer width at the
collector junction is more than the depletion layer width at the emitter junction.

Figure 3: Unbiased npn and pnp transistor

Biased transistor
A transistor can be operated in three different regions as
 Active region
 Saturation region
 Cut-off region

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Active region

Fig 4: pnp transistor operated in active region

 The transistor is said to be operated in active region when the emitter-base junction is forward
biased and collector–base junction is reverse biased.
The collector current is said to have two current components one is due to the forward biasing of
EB junction and the other is due to reverse biasing of CB junction.

Saturation region

Fig 5: pnp transistor operated in Saturation region

Transistor is said to be operated in saturation region when both EB junction and CB junction are
forward biased as shown in Fig 1.4.
When transistor is operated in saturation region IC increases rapidly for a very small change in VC. 

Cut-off region

Fig 6: pnp transistor operated in Cut-off region

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When both EB junction and CB junction are reverse biased, the transistor is said to be operated in cut-
off region.
The current in the transistor is very small and thus when a transistor in this region it is assumed to be
in off state.

Working of pnp transistor

Fig 7: Biased pnp transister

Consider a pnp transistor operated in active region as shown in Figure 7
Since the EB junction is forward biased large number of holes present in the emitter as majority
carriers are repelled by the +ve potential of the supply voltage VEB and they move towards the base
region causing emitter current IE.
Since the base is thin and lightly doped very few of the holes coming from the emitter recombine
with the electrons causing base current IB and the entire remaining holes move towards the collector.
 Since the CB junction is reverse biased all the holes are immediately attracted by the –ve potential of
the supply VCB. Thereby giving rise to collector current IC. 
 Thus, IE = IB + IC -----------------(1) (By KVL)
Since the CB junction is reverse biased a small minority carrier current ICO flows from base to
collector.

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Working of npn transistor

Fig 8: Biased npn transister

The base emitter (BE) junction is forward biased and the collector base (CB) junction is reverse
biased.
The forward bias at the BE junction reduces the barrier voltage and causes electrons to flow from
the n type emitter to the p type base.
The electrons are emitted into the base region.
Holes also flow from the p type base to the n type emitter, but because the base is much more
lightly doped than the collector, almost all of the current flowing across the BE junction consists
of electrons entering the base from the emitter. Thus electrons are the majority charge carriers in
an npn devices.
The reverse bias at the CB junction causes the CB depletion region to penetrate deeper into the
base.
The electron crossing from the emitter to the base arrives quite close to the large negative
positive electric field at the CB depletion region.
Because the electrons have a negative charge, they are drawn across the CB junction by this bias
voltage.
Some of the charge carriers entering the base from the emitter do not reach the collector, but
flow out through the base connection, because base region is lightly doped.













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 BASIC ELECTRONICS SHOBHA A S


Relation between Alpha (α) and Beta (Β)

Curre nt Gain Alpha(α):

It is the ratio of collector current variations to the emitter current variations on no load and constant
voltages.

alpha = Ic/Ie
Where,
Ic = Collector current variations
Ie = Emitter current variations
Beta(Β):
It is the ratio of collector current variations to the base current variations on no load and constant
voltages.
Β = Ic/Ib
Where,
Ib = Base Current variations
Β = α/(1-α)
OR
α = Β /(1 + Β)

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 BASIC ELECTRONICS SHOBHA A S

IMPORTANT POINTS TO REMEMBER:

 Physical structure of transistor.
 Difference between npn and pnp operation.
 Three regions in a transistor: Active region, saturation region and cut-off region.
 Operation of transistor.
 Equation for and
 Relation between and

BLOOMS LEVEL-1 ASSIGNMENT QUESTIONS:

1. Draw the block diagram of an unbiased NPN transistor. Identify each part of the device
and show depletion region and barrier voltages. Explain briefly.
2.Define αdc and βdc. Establish the relationship between α and β.
BLOOMS LEVEL-2
. ASSIGNMENT QUESTIONS:

1. Explain the working of NPN transistor. Clearly show the biasing arrangement of a PNP
and NPN transistor for conduction.

REFERENCES:
1. David A.Bell,”Electronic Devices and Circuits”, Oxford University Press ,4th Edition,Page no:
100-109
2. https://www.youtube.com/watch?v=hOT72IdQBbw
3. http://nptel.ac.in/video.php?subjectId=117103063

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BASIC ELECTRONICS SHOBHA A S

COURSE NAME WITH CODE: BASIC ELECTRONICS COURSE OUTCOMES:

CO25.1:
FACULTY NAME: SHOBHA A S Understand the characteristics operations of
DATE: different electronic components.
LECTURE HOUR:
OBJECTIVES OF THE LECTURE:
 Understand different BJT configurations namely CE and CB configurations.
NOTES: CB, CE and CC characteristics

Common Base (CB) configuration

Fig 1: CB configuration
Base is used as common to both input and output.
Input is applied between emitter and base and output is taken from the collector and base.
In CB configuration, IE is input current and IC is output current. 
Input characteristics

Fig 2: Input characte ristics

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 BASIC ELECTRONICS SHOBHA A S

I/p characteristics is a curve between IE and emitter base voltage VEB keeping VCB
constant.
IE is taken along y-axis and VEB is taken along x-axis. 
For a given input voltage (VEB ), more input current flows when higher levels of
collector base voltage (VCB ) are used.
This is because large collector base (reverse bias) voltage cause the depletion region
at the collector-base junction to penetrate more into the base of the transistor, thus
shortening the distance and reducing the resistance between the emitter-base and
collector base depletion region.
From the graph following points can be noted.
For small changes of VEB there will be a large change in IE. Therefore input resistance is very
small.
IE is almost independent of VCB
 I/P resistance , Ri = ΔVEB / Δ IE =constant 
Output characte ristics

Fig 3: Output characteristics

An output characteristic is the curve between IC and VCB at constant IE.
The collector current IC is taken along y-axis and VCB is taken along x-axis. 
A very large change in VCB produces a small change in IC. Therefore, output resistance is
very high.
 O/p resistance Ro = ΔVEB / Δ IC IE = constant 
Region below the curve IE =0 is known as cut-off region where IC is nearly zero.
The region to the left of VCB =0 is known as saturationregion.
To the right of VCB =0 is known as active region.
Active Region: For each fixed level of IE, IC is almost equal to IE, and IC appears to remains
constant when VCB is increased.
There is very small increase in IC with increasing VCB.

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Because the increase in collector to base bias voltage (V CB) expands the collector base
depletion region and thus shortens the distance between the two depletion regions.
With IE held constant, the increase in IC is so small that it is noticeable only for large
variation in VCB.
 Saturation region: When VCB is reduced to zero, IC still flows. The charge carriers which
constitute IC are minority carriers as they cross the collector base junction (Reverse current).
To stop the flow of charge carriers, the collector base junction has to be forward biased.
 Cut-off: In this region only reverse saturation current ICO flows in the circuit. When the
transistor is operated in this region, the diode act as an open switch that is in off condition.

Common Emitter Configuration

Fig 4: CE configuration
The input is connected between the base and emitter.
The output is taken between collector and emitter.
IB is input current and IC is the output current. 
I/p characteristics

Fig 5: I/p characteristics

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Input characteristics is a curve between EB voltage (VEB ) and base current (IB ) at constant VCE.
For a given level of VBE, IB is reduced when higher VCE levels are employed. Because the higher VCE
produces greater depletion region penetrates more into the base, reducing the distance between the
collector-base and emitter-base depletion regions. Resulting more of the charge carriers from the
emitter flow across the collector base junction and fewer flow out through the base terminal.
From the graph following can be noted.

 For small changes of VEB there will be a large change in base current IB. i.e., input resistance
is very small.
 For a fixed value of VBE, IB decreases as VCE is increased.
 Input resistance , Ri = ΔVEB / Δ IB V CE = constant
Output characte ristics

Fig 6: Output characteristics

It is the curve between VCE and IC at constant IB. 
From the graph we can see that,
 Very large changes of V CE produces a small change in IC i.e output resistance is very high.
 Output resistance Ro = ΔVCE / ΔIC │IB = constant
 Region between the curve I B =0 is called cut-off region where IB is nearly zero.
 For the operation in the active region, the emitter base junction is forward biased while
collector base junction is reverse biased.
 The saturation value of VCE usually ranges between 0.1V to 0.3V
Active Region: With increase in VCE, the base width decreases due to increase in the depletion region
width of collector base junction. Therefore more charge carriers are drawn from the emitter to the
collector. Thus IE increases to same extent with increase in VCE although IB is held constant.
Saturation Region: At the knee of the characteristics, VCE is small. Applying KVL to the transistor
shown below, we get

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VCE-VBE-VCB=0
VCB=V CE-VBE
When VCE=VBE, VCB=0. That is no reverse bias on collector base junction. With decrease in VCE,
VCB decreases and hence IC decreases. Further reduction in VC causes the collector base junction
to be forward biased. The forward bias repels the charge carriers injected from the emitter, thus
reducing IC to 0.
Cut-off Region: The base current IB=0 and collector current IC is equal to reverse leakage
current ICEO. The region below the characteristics for IB=0 is cut-off region.

IMPORTANT POINTS TO REMEMBER:

 Input and output characteristics of CB and CE configuration.

BLOOMS LEVEL-1 ASSIGNMENT QUESTIONS:

1. With a neat diagram explain the input and output characteristics of transistor in CE
mode. Explain active region, cut-off region and saturation region by indicating them on the
characteristic curve.
2. With a neat diagram explain the input and output characteristics of transistor in CB
mode. Explain active region, cut-off region and saturation region by indicating them on the
characteristic curve.
REFERENCES:
1. David A.Bell,”Electronic Devices and Circuits”, Oxford University Press ,4th Edition, Page
no:109-116
2. https://www.youtube.com/watch?v=z8awtkGoQLg
3. http://nptel.ac.in/courses/122106025/10

DEPARTMENT OF ELECTRONICS AND COMMUNICATION, DSCE Page | 52

 BASIC ELECTRONICS SHOBHA A S

COURSE NAME WITH CODE: BASIC ELECTRONICS- COURSE OUTCOMES:

18EC1ICBEE CO25.1:
FACULTY NAME: SHOBHA A S Understand the characteristics operations of
DATE: different electronic components.
LECTURE HOUR: 11
OBJECTIVES OF THE LECTURE:
 Compare performances of different BJT configurations namely CE, CB and CC configurations.

NOTES: Common collector configuration, DC load line and bias point

Common Collector Configuration

Fig 1: CC configuration
The input is connected between the base and collector while the output is taken between emitter and
collector.
Here IB is the input current and IE is the output current. 
Input characteristics

Fig 2: Input characte ristics

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BASIC ELECTRONICS SHOBHA A S

It is curve between VCB and IB at constant VCE.

IB is taken along x-axis and VCB is taken along y axis.
The CC input characteristics are different from other configuration. This is due to increasing the
level of VBC with VEC held constant, reduces the base emitter voltage (VEB) and thus reduces IB. This
explains the slope of the CC input characteristics.
VEC=VEB+VBC
VEB=VEC-VBC
Output characteristics

Fig 3: Output characteristics

It is the curve between IE and VCE at constant base current IB.
IE is taken along Y-axis and VCE along X-axis
Since IC is approximately equal to IE, the CC output characteristics practically similar to those
of the common emitter output characteristics.
Current gain of CC Configuration is given by,

+
= =
Divide both numerator and denominator by
+
= = + = +
−

∴ =
−

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BASIC ELECTRONICS SHOBHA A S

Comparison between CB, CC and CE configuration

Characteristics CB CE CC

1) Input resistance (Ri ) low low high

2) Output resistance
high high low
(Ro )

β α 1
3) Current
α = --------- β = -------- γ = --------
amplification factor
l+ β l- α l- α

4) Total output current IC= αIE + ICBO IC = βIB+(l + β) I CBO IE = γIB + γICBO

5) Input current IE IB IB

6) Output current IC IC IE

7) Input voltage applied

Emitter and Base Base and Emitter Base and Collector
between

8) Output voltage Emitter and

Collector and Base Collector and Emitter
applied between Collector

For high frequency

applications( As a input For audio frequency For impedance
9) Applications
stage of multistage applications matching
amplifier)

10) Current gain Less than unity Greater than unity Very high

11) Voltage gain Very high Greater than unity Less than unity

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IMPORTANT POINTS TO REMEMBER:

 Input and output characteristics of CB and CE configuration.
 Comparison of CB,CE and CC configuration.

BLOOMS LEVEL-2 ASSIGNMENT QUESTIONS:

1. Compare CB, CE and CC transistor configurations.
REFERENCES:
1. David A. Bell, ”Electronic Devices and Circuits”, Oxford University Press ,4th Edition, Page
no: 124-128
2. http://www.nptelvideos.in/2012/12/basic-electronics-drchitralekha-mahanta.html
3. www.vtuelearning.com

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COURSE NAME WITH CODE: BASIC ELECTRONICS - COURSE OUTCOMES:
18EC1ICBEE
CO1 :
FACULTY NAME:SHOBHA A S Understand the characteristics, operations of different
electronic components.
DATE:

LECTURE HOUR: 01

OBJECTIVES OF THE LECTURE:

To study and understand the construction, operation and characteristics of Field Effect Transistors.

2.1 Field Effect Transistor (FET)

A field effect transistor (FET) is a semiconductor device. While a BJT is a current-controlled device, a FET is
a voltage-controlled device. A FET requires very little current, hence its input resistance is very high, which
is its most important advantage over a BJT. There are two types of FET: the Junction FET and the Metal
Oxide Field Effect Transistor (MOSFET). However, we shall discuss only the Junction Field Effect
Transistors (JFET), which are further subdivided into N-channel and P-channel devices.

2.1.1 Junction Field Effect Transistors (JFET)

Field Effect Transistors (FET) , JFET’s are of two types, namely

 N-channel JFETs and

 P-channel JFETs.

Generally N-channel JFETs are more preferred than P-channel. N-channel and P-channel JFETs are shown in
the figures below.

Basic Construction:

 In an N-channel JFET an N-type silicon bar, referred to as the channel, has two smaller pieces of P-type
silicon material diffused on the opposite sides of its middle part, forming P-N junctions, as illustrated in
figure.
 The two P-N junctions forming diodes or gates are connected internally and a common terminal, called
the gate terminal, is brought out. Ohmic contacts (direct electrical connections) are made at the two ends
of the channel—one lead is called the Source terminal S and the other Drain terminal D.
 The silicon bar behaves like a resistor between its two terminals D and S. The gate terminal is analogous
 to the base of an ordinary transistor (BJT). It is used to control the flow of current from source to drain.
Thus, source and drain terminals are analogous to emitter and collector terminals respectively of a BJT.
 In the figure below, the gate is P-region, while the source and the drain are N-regions. Because of this, a
JFET is similar to two diodes.
 The gate and the source form one of the diodes, and the drain form the other diode. These two diodes are
usually referred as the gate-source diode and the gate-drain diode. Since JFET is a silicon device, it takes
only 0.7 volts for forward bias to get significant current in either diode.

Fig.2.1.Construction of JFET - Junction Field Effect Transistors (p-channel & n-channel)

 With the gate terminal not connected, and a potential applied (+ ve at the drain and – ve at the source), a
current called the drain current, ID flows through the channel located between the two P-regions. This
current consists of only majority carriers-electrons in this case.
  P-channel JFET is similar in construction to N-channel JFET except that P-type semiconductor material
is sandwiched between two N-type junctions, as shown in figure. In this case majority carriers are holes.

Schematic Symbols:

The schematic symbols for N-type and P-type JFETs are shown in the figure below.

 The vertical line in the symbol may be thought as channel and source S and drain D connected to the
line.
 Note that the direction of the arrow at the gate indicates the direction in which the gate current flows
when the gate junction is forward biased. Thus for the N-channel JFET, the arrow at the gate junction
points into the device and in P-channel JFET, it is away from the device.

Fig.2.2. Schematic Symbols of JFET

Source – The terminal through which the majority carriers enter the channel, is called the source terminal S and
the conventional current entering the channel at S is designated as Ig.

Drain – The terminal, througih which the majority carriers leave the channel, is called the drain terminal D and
the conventional current leaving the channel at D is designated as I D. The drain- to-source voltage is called VDS,
and is positive if D is more positive than source S

Gate – There are two internally connected heavily doped impurity regions formed by alloying, by diffus ion, or
by any other method available to create two P-N junctions. These impurity regions are called the gate G. A
voltage V GS is applied between the gate and source in the direction to reverse-bias the P-N junction.
Conventional current entering the channel at G is designated as I G.

Channel – The region between the source and drain, sandwiched between the two gates is called the channel
and the majority carriers move from source to drain through this channel.

Ope ration:

Let us consider an N-channel JFET for discussing its operation.

Fig.2.3. Operation of N-channel JFET

 When neither any bias is applied to the gate (i.e. when V GS = 0) nor any voltage to the drain w.r.t. source
(i.e. when VDS = 0), the depletion regions around the P-N junctions , are of equal thickness and
symmetrical.
 When positive voltage is applied to the drain terminal D w.r.t. source terminal S without connecting
gate terminal G to supply, as illustrated in fig. 9.4, the electrons (which are the majority carriers) flow
from terminal S to terminal D whereas conventional drain current I D flows through the channel from D
to S.
 Due to flow of this current, there is uniform voltage drop across the channel resistance as we move from
terminal D to terminal S. This voltage drop reverse biases the diode.
 The gate is more “negative” with respect to those points in the channel which are nearer to D than to S.
Hence, depletion layers penetrate more deeply into the channel at points lying closer to D than to S. Thus
wedge-shaped depletion regions are formed, as shown in figure. when Vd s is applied.
 The size of the depletion layer formed determines – the width of the channel and hence the magnitude of
current ID flowing through the channel.
Characteristics of JFET:
The circuit of Fig. 4.23 is used to experimentally obtain the various values for plotting the transfer characteristic
of a given JFET. The drain source voltage is held constant, VGS is adjusted in steps using the variable resistor
R, and the corresponding levels of VGS and ID are recorded.

Transfer Characteristics Drain Characteristics

Fig.2.4 Characteristic of JFET

Curved Region
At point A, the channel resistance begins to be affected by the depletion regions. Further increases in VDS now
produce smaller ID increases, as shown by the curved part of the characteristic. The increased ID levels, in
turn, result in more depletion region penetration and greater channel resistance. Eventually, a saturation level
of ID is reached, where further VDS increase has no effect on ID’ At the point B on the characteristic where ID
levels off, the drain current is known as the drain- source saturation current (IDSS). The shape of the
characteristic in the depletion regions in the channel at the I DSS level is such that they look as if they are
ready to pinch off the channel. Hence the drain-source voltage at this point is known as the pinch-off voltage
(V) (5.2 V in Fig. 4.24). Part AB is the curved region of the p characteristic.

Pinch-off Region Be

It is also known as saturation region or amplifier region. Here, the JFET operates as a constant current
device because ID is relatively independent of VDS’ This is due to the fact that as VDS increases,
channel resistance also increases proportionately, thereby keeping ID practically constant at I DSS’ This
is the normal operating region of the JFET when used as an amplifier.

Breakdown Region
If VDS is continuously increased (in the pinch-off region) a voltage is reached at which the reverse-
biased gate channel junctions experience avalanche breakdown (at point C on the characteristic in Fig.
4.24), where ID increases to an excessively high value and the device may be destroyed.

IMPORTANT POINTS TO REMEMBER:

 Junction Field Effect Transistor
 Construction of JFET
 Different regions of Characteristics of JFET
BLOOMS LEVEL-1 ASSIGNMENT QUESTIONS: (VTU/GATE/IES QUESTIONS)
1. Explain the working of FET with neat circuit diagram and relevant characteristics. Indicate each region
of the characteristics.(June-12 …10Marks)
REFERENCES:
1. David A. Bell, “Electronic Devices and Circuits”, Oxford University Press, 5th Edition, 2008. Page No.345

to 356.
2. https://www.youtube.com/watch?v=SjeK1nkiFvI
3. http://www.learnabout-electronics.org/fet_01.php
COURSE NAME WITH CODE: BASIC ELECTRONICS - COURSE OUTCOMES:
18EC1ICBEE
CO1 :
FACULTY NAME:SHOBHA A S Understand the characteristics, operations of different
electronic components.
DATE:

LECTURE HOUR: 02

OBJECTIVES OF THE LECTURE:

 To study and understand the construction, operation and characteristics of Metal Oxide Semiconductor Field
Effect Transistors (MOSFET).
 To study and understand the types of MOSFET (a) Enhancement mode MOSFET (b) Depletion Mode MOSFET

2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor
available whose Gate input is electrically insulated from the main current carrying channel and is therefore
called an Insulated Gate Field Effect Transistor or IGFET. The most common type of insulated gate FET
which is used in many different types of electronic circuits is called the Metal Oxide Semiconductor Field
Effect Transistor or MOSFET for short.

MOSFET is a voltage controlled field effect transistor that differs from a JFET in that it has a “Metal
Oxide” Gate electrode which is electrically insulated from the main semiconductor n-channel or p-channel
by a very thin layer of insulating material usually silicon dioxide, commonly known as glass.

This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor. The isolation of
the controlling Gate makes the input resistance of the MOSFET extremely high way up in the Mega-ohms (
MΩ ) region thereby making it almost infinite.

As the Gate terminal is isolated from the main current carrying channel “NO current flows into the gate”
and just like the JFET, the MOSFET also acts like a voltage controlled resistor were the current flowing
through the main channel between the Drain and Source is proportional to the input voltage. Also like the
JFET, the MOSFETs very high input resistance can easily accumulate large amounts of static charge
resulting in the MOSFET becoming easily damaged unless carefully handled or protected.
Symbolic representation of N-channel and P-channel MOSFET is shown in figure below.

Fig.2.5. Symbol of MOSFET

2.2.1 Construction of MOSFET

A MOSFET can be of two types;

(i) Depletion MOSFET
(ii) Enhancement MOSFET

Fig.2.6.Construction of DEMOSFET

 Figure shows the construction of an N-channel depletion MOSFET.

 It consists of a highly doped P-type substrate into which two blocks of heavily doped N-type
material are diffused forming the source and drain.
 An N-channel is formed by diffusion between the source and drain. The type of impurity for the
channel is the same as for the source and drain.
  Now a thin layer of SiO 2 dielectric is grown over the entire surface and holes are cut through the
SiO2 (silicon-dioxide) layer to make contact with the N-type blocks (Source and Drain).
 Metal is deposited through the holes to provide drain and source terminals, and on the surface area
between drain and source, a metal plate is deposited. This layer constitutes the gate.
 Si02 layer results in an extremely high input impedance of the order of 1010 to 1015 Q for this area.
 The chip area of a MOSFET is typically 0.003 um2 or less which is about only 5% of the area
required by a BJT.
 A P-channel DE-MOSFET is constructed like an N-channel DE-MOSFET, starting with an N-type
substrate and diffusing P-type drain and source blocks and connecting them internally by a P-doped
channel region.

2.2.2 Ope ration of MOSFET

Depletion Mode:

 DE-MOSFET can be operated with either a positive or a negative gate. When gate is positive with
respect to the source it operates in the enhancement—or E- mode and when the gate is negative with
respect to the source, as illustrated in figure, it operates in depletion- mode.
 When the drain is made positive with respect to source, a drain current will flow, even with zero gate
potential and the MOSFET is said to be operating in E-mode.
 In this mode of operation gate attracts the negative charge carriers from the P-substrate to the N-
channel and thus reduces the channel resistance and increases the drain-current. The more positive
the gate is made, the more drain current flows.

Fig.2.7.Depletion Mode Operation of MOSFET

 On the other hand when the gate is made negative with respect to the substrate, the gate repels some
 of the negative charge carriers out of the N-channel. This creates a depletion region in the channel,
as illustrated in figure, and, therefore, increases the channel resistance and reduces the drain current.
The more negative the gate, the less the drain current.
 In this mode of operation the device is referred to as a depletion-mode MOSFET. Here too much
negative gate voltage can pinch-off the channel. Thus operation is similar to that of JFET.

Enhance ment Mode:

 For the n-channel enhancement MOS transistor a drain current will only flow when a gate voltage (
VGS ) is applied to the gate terminal greater than the threshold voltage ( VT H ) level in which
conductance takes place making it a transconductance device.
 The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts more electrons
towards the oxide layer around the gate thereby increasing or enhancing (hence its name) the
thickness of the channel allowing more current to flow.
 This is why this kind of transistor is called an enhancement mode device as the application of a gate
voltage enhances the channel.

Fig.2.8.Depletion Mode Operation of MOSFET

 Increasing this positive gate voltage will cause the channel resistance to decrease further causing an
increase in the drain current, ID through the channel. In other words, for an n-channel enhancement
mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGS turns the transistor “OFF”.
Then, the enhancement- mode MOSFET is equivalent to a “normally-open” switch.

2.2.3 MOSFET Characteristics

We have seen above that we can construct a graph of the MOSFETs forward DC characteristics by keeping
the supply voltage, VDD constant and increasing the gate voltage, V G. But in order to get a complete picture
of the operation of the n-type enhancement MOS transistor to use within a MOSFET amplifier circuit, we
need to display the output characteristics for different values of both VDD and VGS

As with the NPN Bipolar Junction Transistor, we can construct a set of output characteristics curves
showing the drain current, ID for increasing positive values of VG for an n-channel enhancement- mode MOS
transistor as shown.

Fig.2.9. N-channel MOSFET characteristics

Note that a p-channel eMOSFET device would have a very similar set of drain current characteristics curves
but the polarity of the gate voltage would be reversed.
IMPORTANT POINTS TO REMEMBER:
 MOSFET’s are unipolar conduction devices
 Depletion MOSFET and Enhancement MOSFET
 Different regions of Characteristics of MOSFET

BLOOMS LEVEL-1 ASSIGNMENT QUESTIONS: (VTU/GATE/IES QUESTIONS)

1. Explain the construction and working of MOSFET and list the types of MOSFET.
2. Explain Enhancement mode and Depletion Mode operation of MOSFET with neat sketches.

REFERENCES:
1. David A Bell ,“Electronic Devices and Circuits”, Oxford University Press, 5th Edition, 2008. Page
No.367 to 371.
2. http://www.nptel.ac.in/courses/Webcourse-contents/IIT%20Kharagpur/Power%20Electronics/PDF/L-
6%28DK%29%28PE%29%20%28%28EE%29NPTEL%29.pdf
3. http://npteldownloads.iitm.ac.in/softlinks_3gp/117103063/mod03lec01.3gp