A B C D E F G H J K

0 U1 VCC
0
7805

1 3
VI VO

GND
1
B1 1
12V

2 2

VCC VCC
U4 U3
3 U2 7 13 7 13 R6 3
RV1
8

A QA A QA
1 12 1 12 1k
B QB B QB
4 3 2 11 2 11
VCC

R Q C QC C QC
6 10 6 10
D QD D QD
7 4 9 4 9
DC BI/RBO QE BI/RBO QE
5 15 5 15
RBI QF RBI QF
10k 5 3 14 3 14
4
CV LT QG LT QG Q3 4
74LS47 74LS47 BC547
GND

2 6
TR TH

R2
1

10k NE555
5 5
U5 U6
14 12 14 12
CKA Q0 CKA Q0
1 9 1 9
CKB Q1 CKB Q1
8 8
Q2 Q2
11 11
Q3 Q3
2 2
6 R0(1) R0(1) 6
3 3
R0(2) R0(2)
6 6
R9(1) R9(1)
C1 C2 7
R9(2)
7
R9(2) BUZ1
47uF 0.01uF
R5 74LS90 74LS90 D1
LED
1k
7 BUZZER 7
R3
1k

RESET VCC
SET MANUAL VCC

8 8
SW1 SW2
Q1 Q2 FILE NAME: Counter Up.pdsprj DATE:
BC547 BC547
DESIGN TITLE: Counter Up IC 7490 1/18/2018
R4 R1
9 PAGE: 9
1k 1k
PATH: E:\Counter Up.pdsprj 1 of 1
BY: Kadek Agus Denny Fratista REV: @REV TIME: 11:36:19 PM
A B C D E F G H J K