A PROCESS-INDEPENDENT THRESHOLD VOLTAGE INVERTER-
COMPARATOR FOR PULSE WIDTH MODULATION APPLICATIONS
Meng-Tong Tan, Joseph S. Chang and Yit-Chow Tong
School of Electrical and Electronic Engineering
Nanyang Technological University
Singapore 639798, Singapore
Email: p6917985a@ntu.edu.sg (Meng-Tong Tan)
ABSTRACT
This paper presents a novel self-tuning inverter-
comparator for a pulse width modulator. The inherent
threshold voltage of the inverter-comparator is made
independent of temperature and process variations by
means of a self-tuning mechanism. The measured duty
cycle error of the PWM at zero-input is typically 0.5%;
an error 5 2% is typically specified. This is achieved
without any post-fabrication trimming. The PWM is
realized by a very simple circuit and can be readily
fabricated in a low-cost digital CMOS process. The
prototype IC inet all design specifications and is suitable
for micropower low-voltage applications including
hearing instruments.
1. INTRODUCTION
In portable micropower low-voltage electro-
acoustical instruments including auditoryprostheses and
hearing instruments (hearing aids) [l-81, the critical
parameters include low voltage and micropower
operation, and a small IC area realization. To meet the
micropower requirements of hearing aids, the Class D
amplifier is often used [2-81 as the final power amplifier.
This is because Class D amplifiers feature high
efficiency (typically >80% over a large range of
modulation indices (equivalent to signal swing)) [2] and
is well suited for low voltage operations.
A block diagram of a typical Class D amplifier is
depicted in Figure 1. It consists of a .Pulse Width
Modulator (PWM) and an output stage. Due to the low
supply voltage (1.3V), the output stage is usually
configured as bridge output to increase the power (by
four times over a single-ended output).
Pulse Width MOdulalor
cL,L,,= LC filter
cis,* D 0 Y t p " t stag.
R b = Load ResinLance
Figure 1 Block diagram of a full-bridge output Class D
power amplifier.
0-7803-5682-9/99/$10.000 1 999 I E EE.
We derive the output voltage V Racross
~ load RLas:
VR,.= 2 ( 2 k - l ) + 2 0 ~ 0 ~ ~ 0 , t - (1)
where k is the duty cycle of the PWM signal at zero-
input, D is the modulation index and a.\ is the frequency
of the input signal.
From equation (I), we note that one of the major
drawbacks of such a configuration is the need for the
duty cycle k of the PWM at zero-input to be as close to
50% as possible. This requirement is essential because
the duty cycle error is translated into an output DC static
current (or voltage) flowing into the load, and the power
efficiency of the amplifier will subsequently be
substantially reduced if this DC current is large.
The simplified schematic of a simple PWM design
[3] is shown in Figure 2. In this circuit, a triangular-like
carrier is generated by integrating a 50% duty cycle
square wave Q with a simple RC integrator (R4 and Cm).
The input modulating signalV, is added to the carrier via
resistor R3. The comparator used in this design is a
simple CMOS digital inverter (MN2 and MP2) with an
inherent threshold voltage, V T H which , is dependent on
process and temperature variations. When the sum of
the input signal and carrier is higher than VTHc, the
output of the inverter will transit from high to low, and
vice-versa. The resultant output signal from the
comparator is a Pulse Width Modulated signal (PWM
signal).
I V
s
Figure 2 A current-art Pulse Width Modulator.
To reduce the output DC static current, a laser is
used to trim one of the two bias resistors, R I or Rz, to
adjust the DC bias of the carrier to VTHc. This post-
fabrication laser trimming process is, however,
expensive and labor intensive.
Other methods reported to reduce the output static
current include a complex and slower (switching speed)
I201
differential-input comparator in BiCMOS process [4] Table 1 Inherent VTHCdeviations and the resultant
and a complex differential approach [ 5 ] . output static current due to threshold voltages
To eliminate this post-fabrication trimming variations of the nMOS and PMOS transistors.
process, we had also proposed two methodologies- Threshold Voltage, O/P Static
namely, a self-error correction method by digital means Case V T H (VI % “ ~ x Current
Deviations
[6] and a self-tuning PWM based on Master-Slave nMOs MOS (PA)*
architecture 171 to reduce the output static current. In 1 0.751 0.756 0 0
both designs, the inherent threshold of the inverter- 2 0.68 0.65 -0.5 -20.8
comparator (similar to the one used in Figure 2) is 3 0.88 0.65 -8.7 -362.5
dependent on process variations (see Section 2 later), 4 0.68 0.85 7.4 308.3
and a self-tuning mechanism is used to adjust the DC 5 0.88 0.85 -0.7 -30
bias of the carrier to V T ~ ~ .
A better approach to reduce the output DC static
current is to design an inverter-comparator with stable
inherent threshold V T Hset ~ to a pre-determined voltage.
In this application, V T ~should
, be set to half of the
supply voltage ( W D o ) because at ? h V D D , the leading and
trailing edge of the carrier will be symmetrical. A
programmable threshold voltage inverter for CMOS ,
-

programmable logic circuits was recently proposed [9].

However, the maximum inherent threshold deviation of
the inverter from the mean threshold is 8.5% (or
equivalent to an unacceptable output static current of
8.5% full load current), too large for high efficiency
Class D amplifier applications. The IC area overhead of
the digital circuits will also be large if a large number of
bits are used to program the inherent threshold voltage.
In this paper, we proposed a novel self-tuning
inverter-comparator for the PWM to realize the above
approach. The inverter-comparator based on Master-
Slave architecture is capable of self-tuning its own
inherent threshold voltage VTHCto %VDD- independent
of process and temperature variations. Post-fabrication
adjustment or calibration is therefore unnecessary. This
circuit design methodology employs very simple tuning
circuitry and can be readily fabricated in a low cost
digital CMOS process.
2. AN INVERTER AS A VOLTAGE
COMPARATOR
In a micropower low voltage Pulse Width
Modulation design, the simple digital inverter is one of
the best approaches to realize the voltage comparator for
two reasons [lo]. First, the slew rate of the comparator
is not limited by the biasing current. Second, it offers
the maximum possible charging and discharging current
for a given supply voltage. However, one of the major
drawbacks of this inverter-comparator is that the
inherent threshold voltage VTHCis dependent on the
threshold voltage variations of the nMOS transistor
(nMOST) and the PMOS transistor (pMOST).
The VTHcdeviations of the inverter due to the
nMOS and PMOS transistors threshold voltage
variations in a typical CMOS process are tabulated in
Table 1. The resultant output static current at the load of
the Class D amplifier is also tabulated in Table 1. For a
better graphical illustration of the V T H C variations, we
have also plotted the corresponding DC Input/Output
transfer characteristics of the comparator in Figure 2.
5
Figure 3 DC transfer characteristics of the inverter-
comparator due to process variations.
From Table 1 and Figure 2, we note that the
inherent threshold voltage varies from -8.7% to 7.4%
(with respect to the typical value in Case 1) due to the
threshold variations of the nMOS and PMOS transistors.
In the worst case, an unacceptably large DC static
current of 362.5pA flows into the load, thereby
substantially reducing the power efficiency of the Class
D amplifier.
3. A PROPOSED SELF-TUNING INVERTER-
COMPARATOR FOR THE PWM
The schematic of the proposed self-tuning inverter-
comparator for the PWM is depicted in Figure 4. The
Master circuit comprises a simple bias circuit (?I,,, and
R2& and a self-tuning inverter-comparator which is
capable of self-tuning its own inherent threshold to the
voltage applied at its input (node DC-M). The self-
tuning inverter-comparator consists of an inverter
(MPlm and MNlm), and an nMOS and a PMOS
transistor (MPlam and MNlam) at the supply rails. The
inverter performs the logic switching whereas the two
transistors at the supply rails are used as variable
resistors to compensate for the inherent threshold
voltage variations of the inverter. The two transistors at
the supply rails are biased in the triode region, and their
output resistances is varied by the output voltage of the
inverter-comparator. The transistors of the Slave
inverter-comparator (comprising MPlas, MPls, MNls
and MNlas) are designed with the same dimensions as

I202
the Master to obtain the same inherent threshold as the
Master.
V""
r - - - - - -T-- -,
I
I
m via the two bias resistors (RI,,, and Rz,) which have a
,U
+
I'WM Output
, - - - - - -=- - ..-I
- - Slave
The inverter-comparator self-tunes its own inherent
for the
threshold in a DC feedback loop manner and operates as
follows. The desired inherent threshold voltages of the
Master and the Slave inverter-comparator at node
DC-Car and DC-M respectively, are set by biasing
node DC-M with a resistive divider comprisingRI, and
Rz,. In this design, the inherent threshold of the inverter
comparator is set to %VD, as discussed in Section 1.
With its input set to % V ~ Dthe , Master inverter-
comparator will generate the required output voltage to
tune the resistance of the two transistors at the supply
rails. Through this negative feedback mechanism, the
inherent threshold of the Master and Slave inverter-
comparator will be tuned to 1/2VoD, independent of
temperature and process variations.
Consider a case when the inherent threshold of the
Master inverter-comparator is below '/Voo. The output
voltage of the Master comparator will be lower than
?4VD,, resulting in an increase in the drain-to-source
resistance of the nMOST (MNlam) and a decrease in
the drain-to-source resistance of the pMOST (MPlam).
Due to the changes in resistance at its rails, the inherent
threshold of the comparator will rise towards '/zVDD.
This negative feedback action will continue (i.e. the
output voltage of the Master comparator will increase)
until the inherent threshold is approximately ' ~ " D D .
Similarly, when the inherent threshold is above 'NOD,
the inverter-comparator will tune its inherent threshold
to % VDo through the negative feedback mechanisms.
For stability, a Miller capacitor C,. is introduced
between the input and output of the Master inverter-
comparator to create a dominant pole at node DC-M.
This dominant pole will provide a large DC gain for the
inverter-comparator to minimize the tuning error and a
small AC gain (with good phase margin) to prevent
undesired oscillation.
The self-tuning inverter-comparator can also be
used for other applications which requires a stable
inherent threshold voltage. The inherent threshold can
be easily changed by changing the bias at nodeDC-M
matching accuracy better than 0.2%.
The schematic diagram of the proposed self-tuning
PWM is depicted in Figure 6. The 3 succeeding inverter
stages connected to the output of the Slave inverter-
comparator are used to increase the voltage gain of the
inverter-comparator and also to provide sufficient drive
to drive the Class D output stage.
!
U
I
I
._-
Figure 6 The proposed self-tuning PWM.
At the input of the comparator, there is a possibility
that any unwanted noise present would result in chatter
or high frequency oscillation at the output PWM signal.
To eliminate this chatter, two capacitors, C, and C,b, are
added to improve the noise immunity at the input of the
inverter-comparator (node DC-Car) [3]. The positive
feedback action of capacitor C , also has an added
advantage of improving the rise and fall times of the
PWM signal at the output of the inverter-comparator.
4. SIMULATION AND EXPERIMEMTAL
RESULTS
The proposed self-tuning PWM is simulated and
fabricated using a 1.2 pm CMOS process. For the
comparator inherent threshold deviations given earlier in
Table 1, the PWM embodying the proposed inverter-
comparator as depicted in Figure 6 was simulated. The
percentage deviation of VTHCfrom the nominal %VDo
and the resultant output bias current at the load of the
Class D amplifier are tabulated in Table 2. The
corresponding DC transfer characteristics of the self-
tuning inverter-comparator are plotted in Figure 5 for
comparison with Figure 2.
I 203
 Measurements show that by means of the self-
tuning mechanism, the 50% duty cycle error at zero-
input is typically 0.5% (or equivalent to -1lpL.A output
Case Threshold Voltage, % VTHc O/P Static bias current at 1.3V operation). This compares well
VTH(VI Deviations Current with the design in Figure 2 which has a zero-input duty
I nMOS I PMOS I I (pN* cycle of 2% after employing the expensive post-
1 1 0.751 I 0.756 I 0.10 I 4.0 fabrication trimming. The total current consumption of
2 0.68 0.65 0.18 7.5 the proposed prototype PWM is 20 pA which is only
3 0.88 0.65 0.25 10.5 0.5% of the full load current, thereby ensuring quiescent
4 0.(ix
__ 0.85
. .. 0.08 3.5 ~~

micropower operation. If realized in a low threshold

5 1 0.88 I 0.85 1 0.06 I 2.5 voltage process, the circuit consumes only lOpA at
* vDD=2.5v, RL=60W,Carrier Freq=40 H z . vDD=1.3v. This makes the proposed PWM suitable for
......................................... ~

micropower low voltage applications including hearing

aids.

5. CONCLUSIONS
..,
..~,._I ..^.,.
We have presented a novel self-tuning inverter-
comparator based on Master-Slave architecture for a
PWM. The measured duty cycle error at zero-input is
typically 0.5%. This is achieved without employing the
expensive post-fabrication trimming. The PWM is
realized by very simple circuit and can be readily
fabricated in a low-cost digital CMOS process. The
prototype IC met all design specifications, and is
suitable for micropower low-voltage applications
including hearing instruments.

Figure 5 DC transfer characteristics of the self-tuning
inverter-comparator due to process variations.
Comparing Tables 1 and 2, we note that the self-
tuning PWM has effectively self-tuned the DC bias of
the carrier to the inherent threshold of the comparator -
independent of the threshold voltage variations of the
nMOS and PMOS transistors. This significant
improvement will be better appreciated by comparing
the DC transfer characteristics of the inverter-
comparator in Figures 2 and 5. The worst case
simulated output static current in Table 2 is 1 0 5 p A
(VDD=2.5V), about 35 times better than the worst case
output static current given in Table 1.
The simulation and measurement results of the
self-tuning PWM for the remaining parameters are
tabulated in Table 3.
Table 3 Simulation and measurement results of the
self-tuning PWM (vDD=2.5v, RL=600L2,
Carrier Freq=40 kHz).
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Harmonic
Distortion

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