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Sitronix ST7065C
40CH Segment/Common Driver for Dot Matrix LCD
Functions: Features:
Dot matrix LCD driver with two 20 channel Display driving bias : static to 1/5
outputs Power supply for logic : 2.7V ~ 5.5V
Selectable function to use common/segment Power supply for LCD voltage (VDD~VEE) :
drivers simultaneously 3V ~ 11V
Bias voltage (V1 ~ V6) 64 Pin QFP package and bare chip available
Input/output signals
Input : Serial display data and control
pulse from controller IC
Output : 20 X 2 channels waveform for
LCD driving
Description:
ST7065C is a segment/common driver for dot parallel data and send out LCD driving
matrix type LCD display. It features 40 channels waveforms to the LCD panel. The ST7065C is
with 20 X 2 bits bi-directional shift registers, data designed for general-purpose LCD drivers. It can
latches, LCD drivers and logic control circuits. It drive both static and dynamic drive LCD. The LSI
is fabricated by high voltage CMOS process with can be used as segment/common driver.
low current consumption. The ST7065C has pin function compatibility with
The ST7065C can convert serial data received the KS0065B that allows the user easily to
from a LCD controller, such as ST7066U, into replace it with a ST7065C.
V1
V2 V5
SEGMENT DRIVER SEGMENT DRIVER
V3 V6
V4
VDD
VSS
VEE
DATA LATCH(20bits) DATA LATCH(20bits)
BIDIRECTIONAL BIDIRECTIONAL
SHIFTER(20bits) SHIFTER(20bits)
M
CL1 CONTOL
CL2
Pad Arrangement
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
49
30
50
29
51
28
52
27
53
26
54 (0,0)
25
55
24
56
23
57
Size : 2310x1830μm 22
58 Coordinate : center
Min. PAD Pitch : 120μm 21
G798E
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Package Dimensions
S S S S S S S S S S S
N N
3 3 3 3 3 3 3 3 3 3 4
C C
4 3 2 1 0 5 6 7 8 9 0
6 6 6 6 6 5 5 5 5 5 5 5 5
4 3 2 1 0 9 8 7 6 5 4 3 2
NC 1 51 V6
S29 2 50 V5
S28 3 49 V4
S27 4 48 V3
S26 5 47 V2
S25 6 46 V1
S24 7 45 FCS
S23 8 44 SHL2
S22 9 43 SHL1
S21 10 42 M
S20 11 41 NC
S19 12 40 DR2
S18 13 39 DL2
S17 14 38 DR1
S16 15 37 DL1
S15 16 36 VSS
S14 17 35 CL2
S13 18 34 CL1
S12 19 33 VEE
2 2 2 2 2 2 2 2 2 2 3 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2
S S S S S V S S S S S S
N
0 1 1 0 0 D 0 0 0 0 0 0
C
9 0 1 8 7 D 6 5 4 3 2 1
Pin Description:
Functional Description:
FCS
Output of LATCH
DATA
V2 V2
V4 V4
Channel1 Output
(S[1] ~ S[20]) V3 V3
V1 V1
V2
V2
V5 V5
Channel2 Output
(S[21] ~ S[40])
V6 V6
V1 V1
The output levels of channel1 and channel2 are decided by the combination of FCS,
M, and latched data. Refer to the following table:
D DL1
S[1] --- S[20] S[21]---S[40]
VDD
CL1 CL1
VSS
Bias_V1
Bias_V2
Bias_V3
Bias_V4
Bias_V5
D DL1 DR1
S[1] --- S[40]
CL1 CL1 DL2
M M ST7065C FCS
Controller SHL1
SHL2
Vcc(+5V) V1 V2 V3 V4 V5 V6
VSS
Bias_V1
Bias_V2
Bias_V3
Bias_V4
Bias_V5
One ST7065C used as a common driver and the other ST7065C as a segment
driver (FCS=0)
The ST7065C are used as common drivers, the FCS is set low and the signals (CL1,
CL2, M) from the controller are connected. V3&V5, V4&V6 are shorted in the
application circuit as shown in the following figure.
The other ST7065C are used as segment drivers, they will shift data on the falling
edge of CL2 and latch data on the falling edge of CL1. V3&V5, V4&V6 are shorted in
the application circuit as shown in the following figure.
Timing Characteristics
TWCKL
VIH
CL2
VIL
TWCKH
TR TF
TDH
TSU
Data in
(DL1, DL2)
(DR1, DR2)
TD
Data out
(DL1, DL2) VOH TSL
(DR1, DR2) VOL
TLS TLS
CL1
TWCKH
TR
TSU
D.C Characteristics:
Symbol Parameter Test Condition Min. Typ. Max. Unit Applicable pin
VDD Operating Voltage - 2.7 - 5.5 V -
VLCD Driver Supply Voltage VDD-VEE 3 - 11 V -
0.7
VIH Input High Voltage - - VDD V
VDD CL1,CL2,M,SHL1,S
0.3 HL2
VIL Input Low Voltage - 0 - V
VDD DL1,DL2,DR1,DR2
ILKG Input Leakage Current VIN = 0 ~ VDD -5 - 5 uA
VDD
VOH Output High Voltage IOH = -0.4mA - - V DL1,DL2,DR1,DR2
-0.4
V1~V6, S[1]~S[40]
VOL Output Low Voltage IOL = +0.4mA - - 0.4 V
IDD Operating Current FCL2 = 400KHZ - 100 300 uA VDD,VEE
IV Leakage Current VIN = VDD ~ VEE -10 - 10 uA V1 ~ V6
A.C Characteristics:
Test
Symbol Parameter Condition Min. Max. Unit Applicable pin
FCL Data Shift Frequency - - 400 KHZ CL2
TWCKH Clock High Level Width - 800 - ns CL1,CL2
TWCKL Clock Low Level Width - 800 - ns CL2
TSL Clock Set-up Time CL2 CL1 500 - ns CL1,CL2
TLS Clock Set-up Time CL1 CL2 500 - ns CL1,CL2
TR/TF Clock Rise/Fall Time - - 200 ns CL1,CL2
TSU Data Set-up Time - 300 - ns DL1,DL2,DR1,DR2
TDH Data Hold Time - 300 - ns DL1,DL2,DR1,DR2
TD Data Delay Time CL = 15 PF - 500 ns DL1,DL2,DR1,DR2
14/14
VEE VEE
V1 V2 V3 V4 V5 V6 V1 V2 V3 V4 V5 V6
ST7066U VCC
GND
CL2
CL1
M
V1
V2
V3
V4
ST7065C
V5
DB0-DB7
Regsister Regsister Regsister Regsister Regsister VR
Vcc(+5V) -V or GND
V1.4c
To MPU
Note:Regsister=2.2K~10K ohm
VR=10K~30Kohm