ElL 304 Lab report

Laboratory 2: Single-device amplifiers

Objective:
1. To determine the biasing state of the mosfet and calculate the RDmax for
saturation.
2. To characterize single-MOSFET amplifiers, namely, the common-
source, common-gate and common-drain amplifiers.

Apparatus Required:
 Bread Board
 Digital Oscilloscope
 CD4007 Integrated Circuit
 Cable and Probe
 Resistors
 Connecting Wires

Observations & Results:

Part 1: Resistive biasing

Circuit Diagram:
Breadboard Snapshot:

Observation Table:

Rd Vgs Vds (V) I (mA)

0 3.04 3.67 0.128
10000 3.04 2.63 0.122
22000 3.05 1.2 0.119
33000 3.08 0.19 0.115
39000 3.15 0.086 0.108
47000 3.39 0.081 0.98
51000 3.46 0.075 0.081

Results:
The value of current remains constant for lower values of Rd. It does
not change with increase in Rd. This implies that the device is in
saturation. The current remains almost constant till Rd is equal to
47kΩ. From 47kΩ onwards the current starts to decrease linearly
implying that the mosfet is in the linear region.
Part 2: Common source amplifier

Circuit Diagram:
RG1 100 kΩ
RG2 330 kΩ
RD 10 kΩ
RS 10 kΩ
C1 220 uF
C2 220 uF
RL 100 kΩ

Vgs 3V
Vds 2.54 V

Breadboard Snapshot:

Oscilloscope Snapshot:
Observation Table:
Frequency(Hz) Log(Frequency) Vin (mv) Vout (mv) Gain Gain (dB)
100 2 21.6 100 4.62963 13.31092
300 2.477121255 21.8 100.1 4.593976 13.24377
500 2.698970004 21.5 95.4 4.437209 12.9422
700 2.84509804 21.9 93.5 4.270588 12.60975
900 2.954242509 22.2 93.6 4.218391 12.50294
1000 3 22 91.8 4.170455 12.40367
3000 3.477121255 22.4 92.3 4.119565 12.29703
5000 3.698970004 22.6 91.6 4.053191 12.15594
7000 3.84509804 22.4 92 4.107527 12.27161
9000 3.954242509 22.6 92.1 4.074468 12.20142
10000 4 22.6 91.4 4.042553 12.13311
30000 4.477121255 22.8 88.6 3.884211 11.78606
50000 4.698970004 22.2 88.8 4 12.0412
70000 4.84509804 22.4 83.8 3.741935 11.46193
90000 4.954242509 22.8 76.6 3.357895 10.52134
100000 5 22.2 77.2 3.478261 10.82724
300000 5.477121255 20.2 56.6 2.80303 8.952556
500000 5.698970004 18.6 41.6 2.236364 6.990848
700000 5.84509804 18.4 33.9 1.842857 5.309833
900000 5.954242509 18 29.3 1.626866 4.227034
1000000 6 17.6 27.8 1.580645 3.976688
3000000 6.477121255 16.8 16.8 1 0

Graph:

Result:
The gain of the amplifier is around 4.6 at low frequencies and is
negative. The gain reduces in magnitude with increase in frequencies.
Part 3: Common gate amplifier

Circuit Diagram:
RG1 100 kΩ
RG2 330 kΩ
RD 10 kΩ
RS 10 kΩ
C1 220 uF
C2 220 uF
RL 100 kΩ

Vgs 3V
Vds 2.54 V

Breadboard Snapshot:

Oscilloscope Snapshot:
Observation Table:
Frequency(Hz) Log(Frequency) Vin (mv) Vout (mv) Gain Gain (dB)
100 2 71 616 8.676056 18.76645
300 2.477121255 72.7 611 8.4 18.48559
500 2.698970004 70.4 597 8.47619 18.56401
700 2.84509804 72.8 609 8.369231 18.45371
900 2.954242509 76.5 615 8.044118 18.10957
1000 3 74 608 8.212121 18.28911
3000 3.477121255 74.1 601 8.106061 18.1762
5000 3.698970004 87.4 724 8.282051 18.36276
7000 3.84509804 87.3 731 8.371795 18.45637
9000 3.954242509 88.5 733 8.278481 18.35901
10000 4 92.4 726 7.853659 17.90144
30000 4.477121255 90.6 630 6.954558 16.84539
50000 4.698970004 92.4 636 6.882353 16.75474
70000 4.84509804 93.7 548 5.847059 15.33875
90000 4.954242509 94.2 523 5.552941 14.89046
100000 5 95.2 478 5.023529 14.02018
300000 5.477121255 95.6 346 3.619512 11.173
500000 5.698970004 97.2 314 3.229268 10.18208
700000 5.84509804 92.6 243 2.625581 8.38451
900000 5.954242509 97 255 2.627848 8.392005
1000000 6 107 248 2.317647 7.300946
3000000 6.477121255 114.6 207 1.806977 5.139051

Graph:
Gain (dB)
20
18
16
14
Gain (dB)

12
10
8
6
4
2
0
0 1 2 3 4 5 6 7
Frequency (Log Scale)

Result:
The gain of the amplifier is around 8.67 at low frequencies and is
positive. The gain reduces in magnitude with increase in frequencies.
Part 4: Common drain amplifier

Circuit Diagram:

RG1 100 kΩ
RG2 330 kΩ
RS 10 kΩ
C1 220 uF
C2 220 uF
RL 100 kΩ

Vgs 3V
Vds 2.9 V

Breadboard Snapshot:

Oscilloscope Snapshot:
Observation Table:
Frequency(Hz) Log(Frequency) Vin (mv) Vout (mv) Gain Gain (dB)
100 2 82 40 0.487805 -6.23508
300 2.477121255 84 40.7 0.484848 -6.28788
500 2.698970004 84 43 0.512121 -5.81254
700 2.84509804 80 40 0.5 -6.0206
900 2.954242509 81 42.4 0.52381 -5.61653
1000 3 82 39.7 0.484375 -6.29637
3000 3.477121255 81 39.9 0.492063 -6.15958
5000 3.698970004 81 41.1 0.507937 -5.88381
7000 3.84509804 82 41 0.5 -6.0206
9000 3.954242509 84 43 0.512121 -5.81254
10000 4 85 41.4 0.486567 -6.25714
30000 4.477121255 83 39.6 0.476923 -6.43103
50000 4.698970004 88 42.5 0.482857 -6.32363
70000 4.84509804 85 40.3 0.474627 -6.47295
90000 4.954242509 85 42.9 0.504478 -5.94316
100000 5 83 41.9 0.504615 -5.94079
300000 5.477121255 80 41 0.512903 -5.79929
500000 5.698970004 77 37.8 0.491525 -6.16908
700000 5.84509804 84 38.2 0.454545 -6.84845
900000 5.954242509 86 38.2 0.444118 -7.05004
1000000 6 81 32.4 0.4 -7.9588
3000000 6.477121255 83 26 0.313846 -10.0657

Graph:

Results:
The gain of the amplifier is around 0.48 at low frequencies and is
positive. The gain reduces in magnitude with increase in frequencies.
The Gain reduces with increase in frequencies because of the presence
of parasitic capacitance associated with device. These amplifiers can be
represented as a negative feedback system with a pole in the closed
loop gain. Hence the gain of the amplifier reduces with the increase in
frequency.