Power/Ground and

Clock Routing

Somayyeh Koohi
Department of Computer Engineering
Sharif University of Technology
Adapted with modifications from lecture notes prepared by author
Topics

n Power/ground routing
n Clock routing
n Floorplanning tips
n Off-chip connections

Sharif University of Technology Modern VLSI Design: Chap7 2 of 33

Power distribution

n Must size wires to be able to handle current

v Requires designing topology of VDD/VSS networks
n Want to keep power network in metal
v Requires designing planar wiring (e.g. M1)
v So, use jumper where required
Ø Disadvantage: high resistance due to crossing diffusion

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Low-resistance jumper

We want to avoid this:

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Interdigitated power and ground lines

VDD

VSS

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Power tree design

n Each branch must be able to supply required

current to all of its subsidiary branches:
Ix = Σb ε x Ib
n Trees are interdigitated to supply both sides of
power supply

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Planar power/ground routing theorem

n Draw a dividing line through each cell such that all VDD
terminals are on one side and all VSS terminals on the other
n If floorplan places all cells with VDD on same side:
v Sufficient condition for planner wiring
v There exists a routing for both VDD and VSS which does not require
them to cross

VDD VSS
cell
VSS
VDD

Sharif University of Technology Modern VLSI Design: Chap7 7 of 33

 Planar routing theorem example
VDD VSS
B
VDD
VSS

C
VDD

VSS A VSS VDD

VDD

VSS
no connection
Sharif University of Technology Modern VLSI Design: Chap7 8 of 33
Power supply noise
n Ideal power supply: keep constant voltage while producing
varying current
n Variations in power supply voltage manifest themselves as
noise into the logic gates
n Power supply wiring resistance creates voltage variations with
current surges
v Transient current introduce power supply noise
n Voltage drops on power lines depend on dynamic behavior of
circuit

Sharif University of Technology Modern VLSI Design: Chap7 9 of 33

Tackling power supply noise
n Must measure current required by each block at
varying times
n May need to redesign power/ground network to
reduce resistance at high current loads
n Worst case: may have to move some activity to
another clock cycle to reduce peak current
v Distribute circuit activity temporally and physically

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Topics

n Power/ground routing
n Clock routing
n Floorplanning tips
n Off-chip connections

Sharif University of Technology Modern VLSI Design: Chap7 11 of 33

Clock distribution

n Goals:
v Deliver clock to all memory elements with
acceptable skew
v Deliver clock edges with acceptable sharpness

n Clocking network design is one of the greatest

challenges in the design of a large chip
v Use one metal layer for clock distribution network

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Clock distribution (example1)
n Wire capacitance becomes important for large chips:
vA 500λ x 2λ poly wire (2 µm process)
Ø C = 140 fF, R = 7.5 K
Ø RC time-constant = 1 ns (tr and tf ~ 2.2 ns)
v Therefore,only metal is used for distributing clock
v Even metal can be troublesome for long wires:
Ø A 1 cm x 3λ metal wire (2 µm process)
Ø C = 2.5 pF, R = 300
Ø RC time-constant = 0.75 ns (tr and tf ~ 1.7 ns)

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Clock delay varies with position

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Clock distribution tree
n Clocks are generally distributed via wiring trees
n Want to use low-resistance interconnect to minimize
delay
n Use multiple drivers to distribute driver requirements:
v Use optimal sizing principles to design buffers
n Clock lines can create significant crosstalk

Sharif University of Technology Modern VLSI Design: Chap7 15 of 33

Clock distribution (example)

n Consider a chip with 10K logic gates:

v Probably 1000 transistor gates are connected to the
clock
Ø Total capacitance = 5.4 pF (typical 2 µm process)
Ø Driving such capacitance at the same rate as one min-size
inverter drives another, requires a transistor 1000 times
wider than minimum size !
¨ So, use tree

Sharif University of Technology Modern VLSI Design: Chap7 16 of 33

H-tree
J Same clock skew at the corners
L Smaller clock skew at the center of the tree compared to its
corners
ü Solution: use buffer chains with even number of buffers

φ
Sharif University of Technology Modern VLSI Design: Chap7 17 of 33
Clock distribution tree example

Sharif University of Technology Modern VLSI Design: Chap7 18 of 33

Topics

n Power/ground routing
n Clock routing
n Floorplanning tips
n Off-chip connections

Sharif University of Technology Modern VLSI Design: Chap7 19 of 33

Floorplanning tips
n Develop a wiring plan
v Think about how layers will be used to distribute
important wires
n Sweep small components into larger blocks
vA floorplan with a single NAND gate in the middle will
be hard to work with
n Design wiring that looks simple
v If it looks complicated, it is complicated

Sharif University of Technology Modern VLSI Design: Chap7 20 of 33

Floorplanning tips (Cont’d)
n Design planar wiring
v Planarity is the essence of simplicity
v It isn’t always possible, but do it where feasible
Ø where it doesn’t introduce unacceptable delay
n Draw separate wiring plans for power and clocking
v These are important design tasks which should be tackled
early

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Topics

n Power/ground routing
n Clock routing
n Floorplanning tips
n Off-chip connections

Sharif University of Technology Modern VLSI Design: Chap7 22 of 33

Off-chip connections
n A package holds the chip
v Packages can introduce significant inductance
n Role of package body
v Physical/thermal support for chip
n Pads on the chip allow the wires on chip to be connected to the
package
v Pads are library components which require careful electrical design
v Wires connecting pad to the package introduce parasitic inductance

Sharif University of Technology Modern VLSI Design: Chap7 23 of 33

Package structure

n Cavity holds chip

n Leads in package connect to pads
v Provide substrate connection to chip
n Package types:
v DIP, PLCC, PGA, PQFP, BGA, …

Sharif University of Technology Modern VLSI Design: Chap7 24 of 33

Pin inductance
n Package pins have non-trivial inductance
v Introduce inductive noise (may appear as supply voltage drop)
v Voltage drop depending on logic family may lead to false logical result
Ø E.g. : pseudo-nMOS family
n Power and ground nets typically require many pins to supply
required current through the packaging inductance
v Increasing number of power supply pins reduces inductive noise (L
di/dt)

Sharif University of Technology Modern VLSI Design: Chap7 25 of 33

Pin inductance example

n Power circuit including pin

indutance:

v Voltage across pin inductance:

v vL = L diL / dt
v Current surge into chip causes inductive voltage drop:
Ø L = 0.5 nH
Ø iL = 1A (within 1 nsec)
Ø vL = 0.5 V

Sharif University of Technology Modern VLSI Design: Chap7 26 of 33

I/O architecture

n Pads are placed on top-layer metal to provide a

place to bond to the package
n Pads are typically placed around periphery of
chip
n Some advanced packaging systems bond
directly to package without bonding wire
v Some allow pads across entire chip surface

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Pad frame architecture

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Pad frame design
n Must supply power/ground to each pad as well as
chip core
v Separate power supply pins for pads and cores (if possible)
v Careful design in the case of common power supply pin
Ø How?
n Positions of pads around frame may be determined by
pinout requirements on package
n Want to distribute power/ground pins as evenly as
possible to minimize power distribution problems

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Input pads
n Main purpose is to provide electrostatic discharge (ESD)
protection
n Gate voltage of CMOS transistor is very sensitive due to its
thin oxide
v Can be permanently damaged by high voltage
n Static electricity in room is sufficient to damage CMOS ICs

n BJT is not as sensitive as CMOS transistors

v Since current of the Base terminal leads to voltage drop
Ø So, neuters ESD effect

Sharif University of Technology Modern VLSI Design: Chap7 30 of 33

Input pad circuits

n Resistor is used in series

with pad to limit current
caused by voltage spike

v May use parasitic bipolar transistors to drain away high voltages:

Ø One for positive pulses
Ø Another for negative pulses
v Must design layout to avoid latch-up

Sharif University of Technology Modern VLSI Design: Chap7 31 of 33

Output pad circuits

n Don’t need ESD protection,

transistor gates not connected to
pad
n Must be able to drive capacitive
load of pad + outside world

v May need voltage level shifting, etc. to be compatible with

other logic families

Sharif University of Technology Modern VLSI Design: Chap7 32 of 33

Three-state pad
n Combination input/output, controlled by mode input on chip
n Pad includes logic to disconnect output driver when pad is
used as input
n Must be protected against ESD

PAD

En
Din
Dout

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